1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ASM_X86_MSR_INDEX_H 3#define _ASM_X86_MSR_INDEX_H 4 5#include <linux/bits.h> 6 7/* 8 * CPU model specific register (MSR) numbers. 9 * 10 * Do not add new entries to this file unless the definitions are shared 11 * between multiple compilation units. 12 */ 13 14/* x86-64 specific MSRs */ 15#define MSR_EFER 0xc0000080 /* extended feature register */ 16#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 17#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 18#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 19#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 20#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 21#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 22#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 23#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 24 25/* EFER bits: */ 26#define _EFER_SCE 0 /* SYSCALL/SYSRET */ 27#define _EFER_LME 8 /* Long mode enable */ 28#define _EFER_LMA 10 /* Long mode active (read-only) */ 29#define _EFER_NX 11 /* No execute enable */ 30#define _EFER_SVME 12 /* Enable virtualization */ 31#define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 32#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 33 34#define EFER_SCE (1<<_EFER_SCE) 35#define EFER_LME (1<<_EFER_LME) 36#define EFER_LMA (1<<_EFER_LMA) 37#define EFER_NX (1<<_EFER_NX) 38#define EFER_SVME (1<<_EFER_SVME) 39#define EFER_LMSLE (1<<_EFER_LMSLE) 40#define EFER_FFXSR (1<<_EFER_FFXSR) 41 42/* Intel MSRs. Some also available on other CPUs */ 43 44#define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ 45#define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ 46#define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ 47#define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ 48#define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ 49#define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ 50 51#define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ 52#define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ 53 54#define MSR_PPIN_CTL 0x0000004e 55#define MSR_PPIN 0x0000004f 56 57#define MSR_IA32_PERFCTR0 0x000000c1 58#define MSR_IA32_PERFCTR1 0x000000c2 59#define MSR_FSB_FREQ 0x000000cd 60#define MSR_PLATFORM_INFO 0x000000ce 61#define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 62#define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) 63 64#define MSR_IA32_UMWAIT_CONTROL 0xe1 65#define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0) 66#define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1) 67/* 68 * The time field is bit[31:2], but representing a 32bit value with 69 * bit[1:0] zero. 70 */ 71#define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U) 72 73#define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 74#define NHM_C3_AUTO_DEMOTE (1UL << 25) 75#define NHM_C1_AUTO_DEMOTE (1UL << 26) 76#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 77#define SNB_C3_AUTO_UNDEMOTE (1UL << 27) 78#define SNB_C1_AUTO_UNDEMOTE (1UL << 28) 79 80#define MSR_MTRRcap 0x000000fe 81 82#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 83#define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ 84#define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ 85#define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ 86#define ARCH_CAP_SSB_NO BIT(4) /* 87 * Not susceptible to Speculative Store Bypass 88 * attack, so no Speculative Store Bypass 89 * control required. 90 */ 91#define ARCH_CAP_MDS_NO BIT(5) /* 92 * Not susceptible to 93 * Microarchitectural Data 94 * Sampling (MDS) vulnerabilities. 95 */ 96#define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /* 97 * The processor is not susceptible to a 98 * machine check error due to modifying the 99 * code page size along with either the 100 * physical address or cache type 101 * without TLB invalidation. 102 */ 103#define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */ 104#define ARCH_CAP_TAA_NO BIT(8) /* 105 * Not susceptible to 106 * TSX Async Abort (TAA) vulnerabilities. 107 */ 108 109#define MSR_IA32_FLUSH_CMD 0x0000010b 110#define L1D_FLUSH BIT(0) /* 111 * Writeback and invalidate the 112 * L1 data cache. 113 */ 114 115#define MSR_IA32_BBL_CR_CTL 0x00000119 116#define MSR_IA32_BBL_CR_CTL3 0x0000011e 117 118#define MSR_IA32_TSX_CTRL 0x00000122 119#define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ 120#define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ 121 122#define MSR_IA32_SYSENTER_CS 0x00000174 123#define MSR_IA32_SYSENTER_ESP 0x00000175 124#define MSR_IA32_SYSENTER_EIP 0x00000176 125 126#define MSR_IA32_MCG_CAP 0x00000179 127#define MSR_IA32_MCG_STATUS 0x0000017a 128#define MSR_IA32_MCG_CTL 0x0000017b 129#define MSR_IA32_MCG_EXT_CTL 0x000004d0 130 131#define MSR_OFFCORE_RSP_0 0x000001a6 132#define MSR_OFFCORE_RSP_1 0x000001a7 133#define MSR_TURBO_RATIO_LIMIT 0x000001ad 134#define MSR_TURBO_RATIO_LIMIT1 0x000001ae 135#define MSR_TURBO_RATIO_LIMIT2 0x000001af 136 137#define MSR_LBR_SELECT 0x000001c8 138#define MSR_LBR_TOS 0x000001c9 139#define MSR_LBR_NHM_FROM 0x00000680 140#define MSR_LBR_NHM_TO 0x000006c0 141#define MSR_LBR_CORE_FROM 0x00000040 142#define MSR_LBR_CORE_TO 0x00000060 143 144#define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 145#define LBR_INFO_MISPRED BIT_ULL(63) 146#define LBR_INFO_IN_TX BIT_ULL(62) 147#define LBR_INFO_ABORT BIT_ULL(61) 148#define LBR_INFO_CYCLES 0xffff 149 150#define MSR_IA32_PEBS_ENABLE 0x000003f1 151#define MSR_PEBS_DATA_CFG 0x000003f2 152#define MSR_IA32_DS_AREA 0x00000600 153#define MSR_IA32_PERF_CAPABILITIES 0x00000345 154#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 155 156#define MSR_IA32_RTIT_CTL 0x00000570 157#define RTIT_CTL_TRACEEN BIT(0) 158#define RTIT_CTL_CYCLEACC BIT(1) 159#define RTIT_CTL_OS BIT(2) 160#define RTIT_CTL_USR BIT(3) 161#define RTIT_CTL_PWR_EVT_EN BIT(4) 162#define RTIT_CTL_FUP_ON_PTW BIT(5) 163#define RTIT_CTL_FABRIC_EN BIT(6) 164#define RTIT_CTL_CR3EN BIT(7) 165#define RTIT_CTL_TOPA BIT(8) 166#define RTIT_CTL_MTC_EN BIT(9) 167#define RTIT_CTL_TSC_EN BIT(10) 168#define RTIT_CTL_DISRETC BIT(11) 169#define RTIT_CTL_PTW_EN BIT(12) 170#define RTIT_CTL_BRANCH_EN BIT(13) 171#define RTIT_CTL_MTC_RANGE_OFFSET 14 172#define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 173#define RTIT_CTL_CYC_THRESH_OFFSET 19 174#define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 175#define RTIT_CTL_PSB_FREQ_OFFSET 24 176#define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 177#define RTIT_CTL_ADDR0_OFFSET 32 178#define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) 179#define RTIT_CTL_ADDR1_OFFSET 36 180#define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) 181#define RTIT_CTL_ADDR2_OFFSET 40 182#define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) 183#define RTIT_CTL_ADDR3_OFFSET 44 184#define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) 185#define MSR_IA32_RTIT_STATUS 0x00000571 186#define RTIT_STATUS_FILTEREN BIT(0) 187#define RTIT_STATUS_CONTEXTEN BIT(1) 188#define RTIT_STATUS_TRIGGEREN BIT(2) 189#define RTIT_STATUS_BUFFOVF BIT(3) 190#define RTIT_STATUS_ERROR BIT(4) 191#define RTIT_STATUS_STOPPED BIT(5) 192#define RTIT_STATUS_BYTECNT_OFFSET 32 193#define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) 194#define MSR_IA32_RTIT_ADDR0_A 0x00000580 195#define MSR_IA32_RTIT_ADDR0_B 0x00000581 196#define MSR_IA32_RTIT_ADDR1_A 0x00000582 197#define MSR_IA32_RTIT_ADDR1_B 0x00000583 198#define MSR_IA32_RTIT_ADDR2_A 0x00000584 199#define MSR_IA32_RTIT_ADDR2_B 0x00000585 200#define MSR_IA32_RTIT_ADDR3_A 0x00000586 201#define MSR_IA32_RTIT_ADDR3_B 0x00000587 202#define MSR_IA32_RTIT_CR3_MATCH 0x00000572 203#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 204#define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 205 206#define MSR_MTRRfix64K_00000 0x00000250 207#define MSR_MTRRfix16K_80000 0x00000258 208#define MSR_MTRRfix16K_A0000 0x00000259 209#define MSR_MTRRfix4K_C0000 0x00000268 210#define MSR_MTRRfix4K_C8000 0x00000269 211#define MSR_MTRRfix4K_D0000 0x0000026a 212#define MSR_MTRRfix4K_D8000 0x0000026b 213#define MSR_MTRRfix4K_E0000 0x0000026c 214#define MSR_MTRRfix4K_E8000 0x0000026d 215#define MSR_MTRRfix4K_F0000 0x0000026e 216#define MSR_MTRRfix4K_F8000 0x0000026f 217#define MSR_MTRRdefType 0x000002ff 218 219#define MSR_IA32_CR_PAT 0x00000277 220 221#define MSR_IA32_DEBUGCTLMSR 0x000001d9 222#define MSR_IA32_LASTBRANCHFROMIP 0x000001db 223#define MSR_IA32_LASTBRANCHTOIP 0x000001dc 224#define MSR_IA32_LASTINTFROMIP 0x000001dd 225#define MSR_IA32_LASTINTTOIP 0x000001de 226 227/* DEBUGCTLMSR bits (others vary by model): */ 228#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 229#define DEBUGCTLMSR_BTF_SHIFT 1 230#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 231#define DEBUGCTLMSR_TR (1UL << 6) 232#define DEBUGCTLMSR_BTS (1UL << 7) 233#define DEBUGCTLMSR_BTINT (1UL << 8) 234#define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 235#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 236#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 237#define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12) 238#define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 239#define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) 240 241#define MSR_PEBS_FRONTEND 0x000003f7 242 243#define MSR_IA32_POWER_CTL 0x000001fc 244 245#define MSR_IA32_MC0_CTL 0x00000400 246#define MSR_IA32_MC0_STATUS 0x00000401 247#define MSR_IA32_MC0_ADDR 0x00000402 248#define MSR_IA32_MC0_MISC 0x00000403 249 250/* C-state Residency Counters */ 251#define MSR_PKG_C3_RESIDENCY 0x000003f8 252#define MSR_PKG_C6_RESIDENCY 0x000003f9 253#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa 254#define MSR_PKG_C7_RESIDENCY 0x000003fa 255#define MSR_CORE_C3_RESIDENCY 0x000003fc 256#define MSR_CORE_C6_RESIDENCY 0x000003fd 257#define MSR_CORE_C7_RESIDENCY 0x000003fe 258#define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 259#define MSR_PKG_C2_RESIDENCY 0x0000060d 260#define MSR_PKG_C8_RESIDENCY 0x00000630 261#define MSR_PKG_C9_RESIDENCY 0x00000631 262#define MSR_PKG_C10_RESIDENCY 0x00000632 263 264/* Interrupt Response Limit */ 265#define MSR_PKGC3_IRTL 0x0000060a 266#define MSR_PKGC6_IRTL 0x0000060b 267#define MSR_PKGC7_IRTL 0x0000060c 268#define MSR_PKGC8_IRTL 0x00000633 269#define MSR_PKGC9_IRTL 0x00000634 270#define MSR_PKGC10_IRTL 0x00000635 271 272/* Run Time Average Power Limiting (RAPL) Interface */ 273 274#define MSR_RAPL_POWER_UNIT 0x00000606 275 276#define MSR_PKG_POWER_LIMIT 0x00000610 277#define MSR_PKG_ENERGY_STATUS 0x00000611 278#define MSR_PKG_PERF_STATUS 0x00000613 279#define MSR_PKG_POWER_INFO 0x00000614 280 281#define MSR_DRAM_POWER_LIMIT 0x00000618 282#define MSR_DRAM_ENERGY_STATUS 0x00000619 283#define MSR_DRAM_PERF_STATUS 0x0000061b 284#define MSR_DRAM_POWER_INFO 0x0000061c 285 286#define MSR_PP0_POWER_LIMIT 0x00000638 287#define MSR_PP0_ENERGY_STATUS 0x00000639 288#define MSR_PP0_POLICY 0x0000063a 289#define MSR_PP0_PERF_STATUS 0x0000063b 290 291#define MSR_PP1_POWER_LIMIT 0x00000640 292#define MSR_PP1_ENERGY_STATUS 0x00000641 293#define MSR_PP1_POLICY 0x00000642 294 295/* Config TDP MSRs */ 296#define MSR_CONFIG_TDP_NOMINAL 0x00000648 297#define MSR_CONFIG_TDP_LEVEL_1 0x00000649 298#define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 299#define MSR_CONFIG_TDP_CONTROL 0x0000064B 300#define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 301 302#define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 303 304#define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 305#define MSR_PKG_ANY_CORE_C0_RES 0x00000659 306#define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 307#define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 308 309#define MSR_CORE_C1_RES 0x00000660 310#define MSR_MODULE_C6_RES_MS 0x00000664 311 312#define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 313#define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 314 315#define MSR_ATOM_CORE_RATIOS 0x0000066a 316#define MSR_ATOM_CORE_VIDS 0x0000066b 317#define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c 318#define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d 319 320 321#define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 322#define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 323#define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 324 325/* Hardware P state interface */ 326#define MSR_PPERF 0x0000064e 327#define MSR_PERF_LIMIT_REASONS 0x0000064f 328#define MSR_PM_ENABLE 0x00000770 329#define MSR_HWP_CAPABILITIES 0x00000771 330#define MSR_HWP_REQUEST_PKG 0x00000772 331#define MSR_HWP_INTERRUPT 0x00000773 332#define MSR_HWP_REQUEST 0x00000774 333#define MSR_HWP_STATUS 0x00000777 334 335/* CPUID.6.EAX */ 336#define HWP_BASE_BIT (1<<7) 337#define HWP_NOTIFICATIONS_BIT (1<<8) 338#define HWP_ACTIVITY_WINDOW_BIT (1<<9) 339#define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 340#define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 341 342/* IA32_HWP_CAPABILITIES */ 343#define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) 344#define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) 345#define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) 346#define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 347 348/* IA32_HWP_REQUEST */ 349#define HWP_MIN_PERF(x) (x & 0xff) 350#define HWP_MAX_PERF(x) ((x & 0xff) << 8) 351#define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 352#define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) 353#define HWP_EPP_PERFORMANCE 0x00 354#define HWP_EPP_BALANCE_PERFORMANCE 0x80 355#define HWP_EPP_BALANCE_POWERSAVE 0xC0 356#define HWP_EPP_POWERSAVE 0xFF 357#define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) 358#define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) 359 360/* IA32_HWP_STATUS */ 361#define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 362#define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 363 364/* IA32_HWP_INTERRUPT */ 365#define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 366#define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 367 368#define MSR_AMD64_MC0_MASK 0xc0010044 369 370#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 371#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 372#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 373#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 374 375#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 376 377/* These are consecutive and not in the normal 4er MCE bank block */ 378#define MSR_IA32_MC0_CTL2 0x00000280 379#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 380 381#define MSR_P6_PERFCTR0 0x000000c1 382#define MSR_P6_PERFCTR1 0x000000c2 383#define MSR_P6_EVNTSEL0 0x00000186 384#define MSR_P6_EVNTSEL1 0x00000187 385 386#define MSR_KNC_PERFCTR0 0x00000020 387#define MSR_KNC_PERFCTR1 0x00000021 388#define MSR_KNC_EVNTSEL0 0x00000028 389#define MSR_KNC_EVNTSEL1 0x00000029 390 391/* Alternative perfctr range with full access. */ 392#define MSR_IA32_PMC0 0x000004c1 393 394/* Auto-reload via MSR instead of DS area */ 395#define MSR_RELOAD_PMC0 0x000014c1 396#define MSR_RELOAD_FIXED_CTR0 0x00001309 397 398/* 399 * AMD64 MSRs. Not complete. See the architecture manual for a more 400 * complete list. 401 */ 402#define MSR_AMD64_PATCH_LEVEL 0x0000008b 403#define MSR_AMD64_TSC_RATIO 0xc0000104 404#define MSR_AMD64_NB_CFG 0xc001001f 405#define MSR_AMD64_CPUID_FN_1 0xc0011004 406#define MSR_AMD64_PATCH_LOADER 0xc0010020 407#define MSR_AMD_PERF_CTL 0xc0010062 408#define MSR_AMD_PERF_STATUS 0xc0010063 409#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 410#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 411#define MSR_AMD64_OSVW_STATUS 0xc0010141 412#define MSR_AMD64_LS_CFG 0xc0011020 413#define MSR_AMD64_DC_CFG 0xc0011022 414#define MSR_AMD64_BU_CFG2 0xc001102a 415#define MSR_AMD64_IBSFETCHCTL 0xc0011030 416#define MSR_AMD64_IBSFETCHLINAD 0xc0011031 417#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 418#define MSR_AMD64_IBSFETCH_REG_COUNT 3 419#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 420#define MSR_AMD64_IBSOPCTL 0xc0011033 421#define MSR_AMD64_IBSOPRIP 0xc0011034 422#define MSR_AMD64_IBSOPDATA 0xc0011035 423#define MSR_AMD64_IBSOPDATA2 0xc0011036 424#define MSR_AMD64_IBSOPDATA3 0xc0011037 425#define MSR_AMD64_IBSDCLINAD 0xc0011038 426#define MSR_AMD64_IBSDCPHYSAD 0xc0011039 427#define MSR_AMD64_IBSOP_REG_COUNT 7 428#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 429#define MSR_AMD64_IBSCTL 0xc001103a 430#define MSR_AMD64_IBSBRTARGET 0xc001103b 431#define MSR_AMD64_IBSOPDATA4 0xc001103d 432#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 433#define MSR_AMD64_SEV 0xc0010131 434#define MSR_AMD64_SEV_ENABLED_BIT 0 435#define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) 436 437#define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f 438 439/* Fam 17h MSRs */ 440#define MSR_F17H_IRPERF 0xc00000e9 441 442/* Fam 16h MSRs */ 443#define MSR_F16H_L2I_PERF_CTL 0xc0010230 444#define MSR_F16H_L2I_PERF_CTR 0xc0010231 445#define MSR_F16H_DR1_ADDR_MASK 0xc0011019 446#define MSR_F16H_DR2_ADDR_MASK 0xc001101a 447#define MSR_F16H_DR3_ADDR_MASK 0xc001101b 448#define MSR_F16H_DR0_ADDR_MASK 0xc0011027 449 450/* Fam 15h MSRs */ 451#define MSR_F15H_PERF_CTL 0xc0010200 452#define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL 453#define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) 454#define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) 455#define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) 456#define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) 457#define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) 458 459#define MSR_F15H_PERF_CTR 0xc0010201 460#define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR 461#define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) 462#define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) 463#define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) 464#define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) 465#define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) 466 467#define MSR_F15H_NB_PERF_CTL 0xc0010240 468#define MSR_F15H_NB_PERF_CTR 0xc0010241 469#define MSR_F15H_PTSC 0xc0010280 470#define MSR_F15H_IC_CFG 0xc0011021 471#define MSR_F15H_EX_CFG 0xc001102c 472 473/* Fam 10h MSRs */ 474#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 475#define FAM10H_MMIO_CONF_ENABLE (1<<0) 476#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 477#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 478#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 479#define FAM10H_MMIO_CONF_BASE_SHIFT 20 480#define MSR_FAM10H_NODE_ID 0xc001100c 481#define MSR_F10H_DECFG 0xc0011029 482#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1 483#define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT) 484 485/* K8 MSRs */ 486#define MSR_K8_TOP_MEM1 0xc001001a 487#define MSR_K8_TOP_MEM2 0xc001001d 488#define MSR_K8_SYSCFG 0xc0010010 489#define MSR_K8_SYSCFG_MEM_ENCRYPT_BIT 23 490#define MSR_K8_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_K8_SYSCFG_MEM_ENCRYPT_BIT) 491#define MSR_K8_INT_PENDING_MSG 0xc0010055 492/* C1E active bits in int pending message */ 493#define K8_INTP_C1E_ACTIVE_MASK 0x18000000 494#define MSR_K8_TSEG_ADDR 0xc0010112 495#define MSR_K8_TSEG_MASK 0xc0010113 496#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 497#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 498#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 499 500/* K7 MSRs */ 501#define MSR_K7_EVNTSEL0 0xc0010000 502#define MSR_K7_PERFCTR0 0xc0010004 503#define MSR_K7_EVNTSEL1 0xc0010001 504#define MSR_K7_PERFCTR1 0xc0010005 505#define MSR_K7_EVNTSEL2 0xc0010002 506#define MSR_K7_PERFCTR2 0xc0010006 507#define MSR_K7_EVNTSEL3 0xc0010003 508#define MSR_K7_PERFCTR3 0xc0010007 509#define MSR_K7_CLK_CTL 0xc001001b 510#define MSR_K7_HWCR 0xc0010015 511#define MSR_K7_HWCR_SMMLOCK_BIT 0 512#define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) 513#define MSR_K7_FID_VID_CTL 0xc0010041 514#define MSR_K7_FID_VID_STATUS 0xc0010042 515 516/* K6 MSRs */ 517#define MSR_K6_WHCR 0xc0000082 518#define MSR_K6_UWCCR 0xc0000085 519#define MSR_K6_EPMR 0xc0000086 520#define MSR_K6_PSOR 0xc0000087 521#define MSR_K6_PFIR 0xc0000088 522 523/* Centaur-Hauls/IDT defined MSRs. */ 524#define MSR_IDT_FCR1 0x00000107 525#define MSR_IDT_FCR2 0x00000108 526#define MSR_IDT_FCR3 0x00000109 527#define MSR_IDT_FCR4 0x0000010a 528 529#define MSR_IDT_MCR0 0x00000110 530#define MSR_IDT_MCR1 0x00000111 531#define MSR_IDT_MCR2 0x00000112 532#define MSR_IDT_MCR3 0x00000113 533#define MSR_IDT_MCR4 0x00000114 534#define MSR_IDT_MCR5 0x00000115 535#define MSR_IDT_MCR6 0x00000116 536#define MSR_IDT_MCR7 0x00000117 537#define MSR_IDT_MCR_CTRL 0x00000120 538 539/* VIA Cyrix defined MSRs*/ 540#define MSR_VIA_FCR 0x00001107 541#define MSR_VIA_LONGHAUL 0x0000110a 542#define MSR_VIA_RNG 0x0000110b 543#define MSR_VIA_BCR2 0x00001147 544 545/* Transmeta defined MSRs */ 546#define MSR_TMTA_LONGRUN_CTRL 0x80868010 547#define MSR_TMTA_LONGRUN_FLAGS 0x80868011 548#define MSR_TMTA_LRTI_READOUT 0x80868018 549#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 550 551/* Intel defined MSRs. */ 552#define MSR_IA32_P5_MC_ADDR 0x00000000 553#define MSR_IA32_P5_MC_TYPE 0x00000001 554#define MSR_IA32_TSC 0x00000010 555#define MSR_IA32_PLATFORM_ID 0x00000017 556#define MSR_IA32_EBL_CR_POWERON 0x0000002a 557#define MSR_EBC_FREQUENCY_ID 0x0000002c 558#define MSR_SMI_COUNT 0x00000034 559#define MSR_IA32_FEATURE_CONTROL 0x0000003a 560#define MSR_IA32_TSC_ADJUST 0x0000003b 561#define MSR_IA32_BNDCFGS 0x00000d90 562 563#define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 564 565#define MSR_IA32_XSS 0x00000da0 566 567#define FEATURE_CONTROL_LOCKED (1<<0) 568#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 569#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 570#define FEATURE_CONTROL_LMCE (1<<20) 571 572#define MSR_IA32_APICBASE 0x0000001b 573#define MSR_IA32_APICBASE_BSP (1<<8) 574#define MSR_IA32_APICBASE_ENABLE (1<<11) 575#define MSR_IA32_APICBASE_BASE (0xfffff<<12) 576 577#define MSR_IA32_TSCDEADLINE 0x000006e0 578 579#define MSR_IA32_UCODE_WRITE 0x00000079 580#define MSR_IA32_UCODE_REV 0x0000008b 581 582#define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 583#define MSR_IA32_SMBASE 0x0000009e 584 585#define MSR_IA32_PERF_STATUS 0x00000198 586#define MSR_IA32_PERF_CTL 0x00000199 587#define INTEL_PERF_CTL_MASK 0xffff 588 589#define MSR_IA32_MPERF 0x000000e7 590#define MSR_IA32_APERF 0x000000e8 591 592#define MSR_IA32_THERM_CONTROL 0x0000019a 593#define MSR_IA32_THERM_INTERRUPT 0x0000019b 594 595#define THERM_INT_HIGH_ENABLE (1 << 0) 596#define THERM_INT_LOW_ENABLE (1 << 1) 597#define THERM_INT_PLN_ENABLE (1 << 24) 598 599#define MSR_IA32_THERM_STATUS 0x0000019c 600 601#define THERM_STATUS_PROCHOT (1 << 0) 602#define THERM_STATUS_POWER_LIMIT (1 << 10) 603 604#define MSR_THERM2_CTL 0x0000019d 605 606#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 607 608#define MSR_IA32_MISC_ENABLE 0x000001a0 609 610#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 611 612#define MSR_MISC_FEATURE_CONTROL 0x000001a4 613#define MSR_MISC_PWR_MGMT 0x000001aa 614 615#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 616#define ENERGY_PERF_BIAS_PERFORMANCE 0 617#define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 618#define ENERGY_PERF_BIAS_NORMAL 6 619#define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 620#define ENERGY_PERF_BIAS_POWERSAVE 15 621 622#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 623 624#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 625#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 626 627#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 628 629#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 630#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 631#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 632 633/* Thermal Thresholds Support */ 634#define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 635#define THERM_SHIFT_THRESHOLD0 8 636#define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 637#define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 638#define THERM_SHIFT_THRESHOLD1 16 639#define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 640#define THERM_STATUS_THRESHOLD0 (1 << 6) 641#define THERM_LOG_THRESHOLD0 (1 << 7) 642#define THERM_STATUS_THRESHOLD1 (1 << 8) 643#define THERM_LOG_THRESHOLD1 (1 << 9) 644 645/* MISC_ENABLE bits: architectural */ 646#define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 647#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 648#define MSR_IA32_MISC_ENABLE_TCC_BIT 1 649#define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 650#define MSR_IA32_MISC_ENABLE_EMON_BIT 7 651#define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 652#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 653#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 654#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 655#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 656#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 657#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 658#define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 659#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 660#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 661#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 662#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 663#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 664#define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 665#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 666 667/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 668#define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 669#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 670#define MSR_IA32_MISC_ENABLE_TM1_BIT 3 671#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 672#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 673#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 674#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 675#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 676#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 677#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 678#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 679#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 680#define MSR_IA32_MISC_ENABLE_FERR_BIT 10 681#define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 682#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 683#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 684#define MSR_IA32_MISC_ENABLE_TM2_BIT 13 685#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 686#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 687#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 688#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 689#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 690#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 691#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 692#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 693#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 694#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 695#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 696#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 697#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 698 699/* MISC_FEATURES_ENABLES non-architectural features */ 700#define MSR_MISC_FEATURES_ENABLES 0x00000140 701 702#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 703#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) 704#define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 705 706#define MSR_IA32_TSC_DEADLINE 0x000006E0 707 708 709#define MSR_TSX_FORCE_ABORT 0x0000010F 710 711#define MSR_TFA_RTM_FORCE_ABORT_BIT 0 712#define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) 713 714/* P4/Xeon+ specific */ 715#define MSR_IA32_MCG_EAX 0x00000180 716#define MSR_IA32_MCG_EBX 0x00000181 717#define MSR_IA32_MCG_ECX 0x00000182 718#define MSR_IA32_MCG_EDX 0x00000183 719#define MSR_IA32_MCG_ESI 0x00000184 720#define MSR_IA32_MCG_EDI 0x00000185 721#define MSR_IA32_MCG_EBP 0x00000186 722#define MSR_IA32_MCG_ESP 0x00000187 723#define MSR_IA32_MCG_EFLAGS 0x00000188 724#define MSR_IA32_MCG_EIP 0x00000189 725#define MSR_IA32_MCG_RESERVED 0x0000018a 726 727/* Pentium IV performance counter MSRs */ 728#define MSR_P4_BPU_PERFCTR0 0x00000300 729#define MSR_P4_BPU_PERFCTR1 0x00000301 730#define MSR_P4_BPU_PERFCTR2 0x00000302 731#define MSR_P4_BPU_PERFCTR3 0x00000303 732#define MSR_P4_MS_PERFCTR0 0x00000304 733#define MSR_P4_MS_PERFCTR1 0x00000305 734#define MSR_P4_MS_PERFCTR2 0x00000306 735#define MSR_P4_MS_PERFCTR3 0x00000307 736#define MSR_P4_FLAME_PERFCTR0 0x00000308 737#define MSR_P4_FLAME_PERFCTR1 0x00000309 738#define MSR_P4_FLAME_PERFCTR2 0x0000030a 739#define MSR_P4_FLAME_PERFCTR3 0x0000030b 740#define MSR_P4_IQ_PERFCTR0 0x0000030c 741#define MSR_P4_IQ_PERFCTR1 0x0000030d 742#define MSR_P4_IQ_PERFCTR2 0x0000030e 743#define MSR_P4_IQ_PERFCTR3 0x0000030f 744#define MSR_P4_IQ_PERFCTR4 0x00000310 745#define MSR_P4_IQ_PERFCTR5 0x00000311 746#define MSR_P4_BPU_CCCR0 0x00000360 747#define MSR_P4_BPU_CCCR1 0x00000361 748#define MSR_P4_BPU_CCCR2 0x00000362 749#define MSR_P4_BPU_CCCR3 0x00000363 750#define MSR_P4_MS_CCCR0 0x00000364 751#define MSR_P4_MS_CCCR1 0x00000365 752#define MSR_P4_MS_CCCR2 0x00000366 753#define MSR_P4_MS_CCCR3 0x00000367 754#define MSR_P4_FLAME_CCCR0 0x00000368 755#define MSR_P4_FLAME_CCCR1 0x00000369 756#define MSR_P4_FLAME_CCCR2 0x0000036a 757#define MSR_P4_FLAME_CCCR3 0x0000036b 758#define MSR_P4_IQ_CCCR0 0x0000036c 759#define MSR_P4_IQ_CCCR1 0x0000036d 760#define MSR_P4_IQ_CCCR2 0x0000036e 761#define MSR_P4_IQ_CCCR3 0x0000036f 762#define MSR_P4_IQ_CCCR4 0x00000370 763#define MSR_P4_IQ_CCCR5 0x00000371 764#define MSR_P4_ALF_ESCR0 0x000003ca 765#define MSR_P4_ALF_ESCR1 0x000003cb 766#define MSR_P4_BPU_ESCR0 0x000003b2 767#define MSR_P4_BPU_ESCR1 0x000003b3 768#define MSR_P4_BSU_ESCR0 0x000003a0 769#define MSR_P4_BSU_ESCR1 0x000003a1 770#define MSR_P4_CRU_ESCR0 0x000003b8 771#define MSR_P4_CRU_ESCR1 0x000003b9 772#define MSR_P4_CRU_ESCR2 0x000003cc 773#define MSR_P4_CRU_ESCR3 0x000003cd 774#define MSR_P4_CRU_ESCR4 0x000003e0 775#define MSR_P4_CRU_ESCR5 0x000003e1 776#define MSR_P4_DAC_ESCR0 0x000003a8 777#define MSR_P4_DAC_ESCR1 0x000003a9 778#define MSR_P4_FIRM_ESCR0 0x000003a4 779#define MSR_P4_FIRM_ESCR1 0x000003a5 780#define MSR_P4_FLAME_ESCR0 0x000003a6 781#define MSR_P4_FLAME_ESCR1 0x000003a7 782#define MSR_P4_FSB_ESCR0 0x000003a2 783#define MSR_P4_FSB_ESCR1 0x000003a3 784#define MSR_P4_IQ_ESCR0 0x000003ba 785#define MSR_P4_IQ_ESCR1 0x000003bb 786#define MSR_P4_IS_ESCR0 0x000003b4 787#define MSR_P4_IS_ESCR1 0x000003b5 788#define MSR_P4_ITLB_ESCR0 0x000003b6 789#define MSR_P4_ITLB_ESCR1 0x000003b7 790#define MSR_P4_IX_ESCR0 0x000003c8 791#define MSR_P4_IX_ESCR1 0x000003c9 792#define MSR_P4_MOB_ESCR0 0x000003aa 793#define MSR_P4_MOB_ESCR1 0x000003ab 794#define MSR_P4_MS_ESCR0 0x000003c0 795#define MSR_P4_MS_ESCR1 0x000003c1 796#define MSR_P4_PMH_ESCR0 0x000003ac 797#define MSR_P4_PMH_ESCR1 0x000003ad 798#define MSR_P4_RAT_ESCR0 0x000003bc 799#define MSR_P4_RAT_ESCR1 0x000003bd 800#define MSR_P4_SAAT_ESCR0 0x000003ae 801#define MSR_P4_SAAT_ESCR1 0x000003af 802#define MSR_P4_SSU_ESCR0 0x000003be 803#define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 804 805#define MSR_P4_TBPU_ESCR0 0x000003c2 806#define MSR_P4_TBPU_ESCR1 0x000003c3 807#define MSR_P4_TC_ESCR0 0x000003c4 808#define MSR_P4_TC_ESCR1 0x000003c5 809#define MSR_P4_U2L_ESCR0 0x000003b0 810#define MSR_P4_U2L_ESCR1 0x000003b1 811 812#define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 813 814/* Intel Core-based CPU performance counters */ 815#define MSR_CORE_PERF_FIXED_CTR0 0x00000309 816#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 817#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 818#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 819#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 820#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 821#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 822 823/* PERF_GLOBAL_OVF_CTL bits */ 824#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55 825#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT) 826#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62 827#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT) 828#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63 829#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) 830 831/* Geode defined MSRs */ 832#define MSR_GEODE_BUSCONT_CONF0 0x00001900 833 834/* Intel VT MSRs */ 835#define MSR_IA32_VMX_BASIC 0x00000480 836#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 837#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 838#define MSR_IA32_VMX_EXIT_CTLS 0x00000483 839#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 840#define MSR_IA32_VMX_MISC 0x00000485 841#define MSR_IA32_VMX_CR0_FIXED0 0x00000486 842#define MSR_IA32_VMX_CR0_FIXED1 0x00000487 843#define MSR_IA32_VMX_CR4_FIXED0 0x00000488 844#define MSR_IA32_VMX_CR4_FIXED1 0x00000489 845#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 846#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 847#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 848#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 849#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 850#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 851#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 852#define MSR_IA32_VMX_VMFUNC 0x00000491 853 854/* VMX_BASIC bits and bitmasks */ 855#define VMX_BASIC_VMCS_SIZE_SHIFT 32 856#define VMX_BASIC_TRUE_CTLS (1ULL << 55) 857#define VMX_BASIC_64 0x0001000000000000LLU 858#define VMX_BASIC_MEM_TYPE_SHIFT 50 859#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 860#define VMX_BASIC_MEM_TYPE_WB 6LLU 861#define VMX_BASIC_INOUT 0x0040000000000000LLU 862 863/* MSR_IA32_VMX_MISC bits */ 864#define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) 865#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 866#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 867/* AMD-V MSRs */ 868 869#define MSR_VM_CR 0xc0010114 870#define MSR_VM_IGNNE 0xc0010115 871#define MSR_VM_HSAVE_PA 0xc0010117 872 873#endif /* _ASM_X86_MSR_INDEX_H */ 874