1
2config XTENSA
3 def_bool y
4 select ARCH_32BIT_OFF_T
5 select ARCH_HAS_BINFMT_FLAT if !MMU
6 select ARCH_HAS_SYNC_DMA_FOR_CPU
7 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
8 select ARCH_USE_QUEUED_RWLOCKS
9 select ARCH_USE_QUEUED_SPINLOCKS
10 select ARCH_WANT_FRAME_POINTERS
11 select ARCH_WANT_IPC_PARSE_VERSION
12 select BUILDTIME_EXTABLE_SORT
13 select CLONE_BACKWARDS
14 select COMMON_CLK
15 select DMA_REMAP if MMU
16 select GENERIC_ATOMIC64
17 select GENERIC_CLOCKEVENTS
18 select GENERIC_IRQ_SHOW
19 select GENERIC_PCI_IOMAP
20 select GENERIC_SCHED_CLOCK
21 select GENERIC_STRNCPY_FROM_USER if KASAN
22 select HAVE_ARCH_JUMP_LABEL
23 select HAVE_ARCH_KASAN if MMU
24 select HAVE_ARCH_TRACEHOOK
25 select HAVE_DEBUG_KMEMLEAK
26 select HAVE_DMA_CONTIGUOUS
27 select HAVE_EXIT_THREAD
28 select HAVE_FUNCTION_TRACER
29 select HAVE_FUTEX_CMPXCHG if !MMU
30 select HAVE_HW_BREAKPOINT if PERF_EVENTS
31 select HAVE_IRQ_TIME_ACCOUNTING
32 select HAVE_OPROFILE
33 select HAVE_PCI
34 select HAVE_PERF_EVENTS
35 select HAVE_STACKPROTECTOR
36 select HAVE_SYSCALL_TRACEPOINTS
37 select IRQ_DOMAIN
38 select MODULES_USE_ELF_RELA
39 select PERF_USE_VMALLOC
40 select VIRT_TO_BUS
41 help
42 Xtensa processors are 32-bit RISC machines designed by Tensilica
43 primarily for embedded systems. These processors are both
44 configurable and extensible. The Linux port to the Xtensa
45 architecture supports all processor configurations and extensions,
46 with reasonable minimum requirements. The Xtensa Linux project has
47 a home page at <http://www.linux-xtensa.org/>.
48
49config GENERIC_HWEIGHT
50 def_bool y
51
52config ARCH_HAS_ILOG2_U32
53 def_bool n
54
55config ARCH_HAS_ILOG2_U64
56 def_bool n
57
58config NO_IOPORT_MAP
59 def_bool n
60
61config HZ
62 int
63 default 100
64
65config LOCKDEP_SUPPORT
66 def_bool y
67
68config STACKTRACE_SUPPORT
69 def_bool y
70
71config TRACE_IRQFLAGS_SUPPORT
72 def_bool y
73
74config MMU
75 def_bool n
76
77config HAVE_XTENSA_GPIO32
78 def_bool n
79
80config KASAN_SHADOW_OFFSET
81 hex
82 default 0x6e400000
83
84menu "Processor type and features"
85
86choice
87 prompt "Xtensa Processor Configuration"
88 default XTENSA_VARIANT_FSF
89
90config XTENSA_VARIANT_FSF
91 bool "fsf - default (not generic) configuration"
92 select MMU
93
94config XTENSA_VARIANT_DC232B
95 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
96 select MMU
97 select HAVE_XTENSA_GPIO32
98 help
99 This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE).
100
101config XTENSA_VARIANT_DC233C
102 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
103 select MMU
104 select HAVE_XTENSA_GPIO32
105 help
106 This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE).
107
108config XTENSA_VARIANT_CUSTOM
109 bool "Custom Xtensa processor configuration"
110 select HAVE_XTENSA_GPIO32
111 help
112 Select this variant to use a custom Xtensa processor configuration.
113 You will be prompted for a processor variant CORENAME.
114endchoice
115
116config XTENSA_VARIANT_CUSTOM_NAME
117 string "Xtensa Processor Custom Core Variant Name"
118 depends on XTENSA_VARIANT_CUSTOM
119 help
120 Provide the name of a custom Xtensa processor variant.
121 This CORENAME selects arch/xtensa/variant/CORENAME.
122 Dont forget you have to select MMU if you have one.
123
124config XTENSA_VARIANT_NAME
125 string
126 default "dc232b" if XTENSA_VARIANT_DC232B
127 default "dc233c" if XTENSA_VARIANT_DC233C
128 default "fsf" if XTENSA_VARIANT_FSF
129 default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM
130
131config XTENSA_VARIANT_MMU
132 bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)"
133 depends on XTENSA_VARIANT_CUSTOM
134 default y
135 select MMU
136 help
137 Build a Conventional Kernel with full MMU support,
138 ie: it supports a TLB with auto-loading, page protection.
139
140config XTENSA_VARIANT_HAVE_PERF_EVENTS
141 bool "Core variant has Performance Monitor Module"
142 depends on XTENSA_VARIANT_CUSTOM
143 default n
144 help
145 Enable if core variant has Performance Monitor Module with
146 External Registers Interface.
147
148 If unsure, say N.
149
150config XTENSA_FAKE_NMI
151 bool "Treat PMM IRQ as NMI"
152 depends on XTENSA_VARIANT_HAVE_PERF_EVENTS
153 default n
154 help
155 If PMM IRQ is the only IRQ at EXCM level it is safe to
156 treat it as NMI, which improves accuracy of profiling.
157
158 If there are other interrupts at or above PMM IRQ priority level
159 but not above the EXCM level, PMM IRQ still may be treated as NMI,
160 but only if these IRQs are not used. There will be a build warning
161 saying that this is not safe, and a bugcheck if one of these IRQs
162 actually fire.
163
164 If unsure, say N.
165
166config XTENSA_UNALIGNED_USER
167 bool "Unaligned memory access in user space"
168 help
169 The Xtensa architecture currently does not handle unaligned
170 memory accesses in hardware but through an exception handler.
171 Per default, unaligned memory accesses are disabled in user space.
172
173 Say Y here to enable unaligned memory access in user space.
174
175config HAVE_SMP
176 bool "System Supports SMP (MX)"
177 depends on XTENSA_VARIANT_CUSTOM
178 select XTENSA_MX
179 help
180 This option is use to indicate that the system-on-a-chip (SOC)
181 supports Multiprocessing. Multiprocessor support implemented above
182 the CPU core definition and currently needs to be selected manually.
183
184 Multiprocessor support in implemented with external cache and
185 interrupt controllers.
186
187 The MX interrupt distributer adds Interprocessor Interrupts
188 and causes the IRQ numbers to be increased by 4 for devices
189 like the open cores ethernet driver and the serial interface.
190
191 You still have to select "Enable SMP" to enable SMP on this SOC.
192
193config SMP
194 bool "Enable Symmetric multi-processing support"
195 depends on HAVE_SMP
196 select GENERIC_SMP_IDLE_THREAD
197 help
198 Enabled SMP Software; allows more than one CPU/CORE
199 to be activated during startup.
200
201config NR_CPUS
202 depends on SMP
203 int "Maximum number of CPUs (2-32)"
204 range 2 32
205 default "4"
206
207config HOTPLUG_CPU
208 bool "Enable CPU hotplug support"
209 depends on SMP
210 help
211 Say Y here to allow turning CPUs off and on. CPUs can be
212 controlled through /sys/devices/system/cpu.
213
214 Say N if you want to disable CPU hotplug.
215
216config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
217 bool "Initialize Xtensa MMU inside the Linux kernel code"
218 depends on !XTENSA_VARIANT_FSF && !XTENSA_VARIANT_DC232B
219 default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM
220 help
221 Earlier version initialized the MMU in the exception vector
222 before jumping to _startup in head.S and had an advantage that
223 it was possible to place a software breakpoint at 'reset' and
224 then enter your normal kernel breakpoints once the MMU was mapped
225 to the kernel mappings (0XC0000000).
226
227 This unfortunately won't work for U-Boot and likely also wont
228 work for using KEXEC to have a hot kernel ready for doing a
229 KDUMP.
230
231 So now the MMU is initialized in head.S but it's necessary to
232 use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup.
233 xt-gdb can't place a Software Breakpoint in the 0XD region prior
234 to mapping the MMU and after mapping even if the area of low memory
235 was mapped gdb wouldn't remove the breakpoint on hitting it as the
236 PC wouldn't match. Since Hardware Breakpoints are recommended for
237 Linux configurations it seems reasonable to just assume they exist
238 and leave this older mechanism for unfortunate souls that choose
239 not to follow Tensilica's recommendation.
240
241 Selecting this will cause U-Boot to set the KERNEL Load and Entry
242 address at 0x00003000 instead of the mapped std of 0xD0003000.
243
244 If in doubt, say Y.
245
246config MEMMAP_CACHEATTR
247 hex "Cache attributes for the memory address space"
248 depends on !MMU
249 default 0x22222222
250 help
251 These cache attributes are set up for noMMU systems. Each hex digit
252 specifies cache attributes for the corresponding 512MB memory
253 region: bits 0..3 -- for addresses 0x00000000..0x1fffffff,
254 bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on.
255
256 Cache attribute values are specific for the MMU type.
257 For region protection MMUs:
258 1: WT cached,
259 2: cache bypass,
260 4: WB cached,
261 f: illegal.
262 For ful MMU:
263 bit 0: executable,
264 bit 1: writable,
265 bits 2..3:
266 0: cache bypass,
267 1: WB cache,
268 2: WT cache,
269 3: special (c and e are illegal, f is reserved).
270 For MPU:
271 0: illegal,
272 1: WB cache,
273 2: WB, no-write-allocate cache,
274 3: WT cache,
275 4: cache bypass.
276
277config KSEG_PADDR
278 hex "Physical address of the KSEG mapping"
279 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU
280 default 0x00000000
281 help
282 This is the physical address where KSEG is mapped. Please refer to
283 the chosen KSEG layout help for the required address alignment.
284 Unpacked kernel image (including vectors) must be located completely
285 within KSEG.
286 Physical memory below this address is not available to linux.
287
288 If unsure, leave the default value here.
289
290config KERNEL_LOAD_ADDRESS
291 hex "Kernel load address"
292 default 0x60003000 if !MMU
293 default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
294 default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
295 help
296 This is the address where the kernel is loaded.
297 It is virtual address for MMUv2 configurations and physical address
298 for all other configurations.
299
300 If unsure, leave the default value here.
301
302config VECTORS_OFFSET
303 hex "Kernel vectors offset"
304 default 0x00003000
305 help
306 This is the offset of the kernel image from the relocatable vectors
307 base.
308
309 If unsure, leave the default value here.
310
311choice
312 prompt "KSEG layout"
313 depends on MMU
314 default XTENSA_KSEG_MMU_V2
315
316config XTENSA_KSEG_MMU_V2
317 bool "MMUv2: 128MB cached + 128MB uncached"
318 help
319 MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting
320 at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000
321 without cache.
322 KSEG_PADDR must be aligned to 128MB.
323
324config XTENSA_KSEG_256M
325 bool "256MB cached + 256MB uncached"
326 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
327 help
328 TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000
329 with cache and to 0xc0000000 without cache.
330 KSEG_PADDR must be aligned to 256MB.
331
332config XTENSA_KSEG_512M
333 bool "512MB cached + 512MB uncached"
334 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
335 help
336 TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000
337 with cache and to 0xc0000000 without cache.
338 KSEG_PADDR must be aligned to 256MB.
339
340endchoice
341
342config HIGHMEM
343 bool "High Memory Support"
344 depends on MMU
345 help
346 Linux can use the full amount of RAM in the system by
347 default. However, the default MMUv2 setup only maps the
348 lowermost 128 MB of memory linearly to the areas starting
349 at 0xd0000000 (cached) and 0xd8000000 (uncached).
350 When there are more than 128 MB memory in the system not
351 all of it can be "permanently mapped" by the kernel.
352 The physical memory that's not permanently mapped is called
353 "high memory".
354
355 If you are compiling a kernel which will never run on a
356 machine with more than 128 MB total physical RAM, answer
357 N here.
358
359 If unsure, say Y.
360
361config FAST_SYSCALL_XTENSA
362 bool "Enable fast atomic syscalls"
363 default n
364 help
365 fast_syscall_xtensa is a syscall that can make atomic operations
366 on UP kernel when processor has no s32c1i support.
367
368 This syscall is deprecated. It may have issues when called with
369 invalid arguments. It is provided only for backwards compatibility.
370 Only enable it if your userspace software requires it.
371
372 If unsure, say N.
373
374config FAST_SYSCALL_SPILL_REGISTERS
375 bool "Enable spill registers syscall"
376 default n
377 help
378 fast_syscall_spill_registers is a syscall that spills all active
379 register windows of a calling userspace task onto its stack.
380
381 This syscall is deprecated. It may have issues when called with
382 invalid arguments. It is provided only for backwards compatibility.
383 Only enable it if your userspace software requires it.
384
385 If unsure, say N.
386
387config USER_ABI_CALL0
388 bool
389
390choice
391 prompt "Userspace ABI"
392 default USER_ABI_DEFAULT
393 help
394 Select supported userspace ABI.
395
396 If unsure, choose the default ABI.
397
398config USER_ABI_DEFAULT
399 bool "Default ABI only"
400 help
401 Assume default userspace ABI. For XEA2 cores it is windowed ABI.
402 call0 ABI binaries may be run on such kernel, but signal delivery
403 will not work correctly for them.
404
405config USER_ABI_CALL0_ONLY
406 bool "Call0 ABI only"
407 select USER_ABI_CALL0
408 help
409 Select this option to support only call0 ABI in userspace.
410 Windowed ABI binaries will crash with a segfault caused by
411 an illegal instruction exception on the first 'entry' opcode.
412
413 Choose this option if you're planning to run only user code
414 built with call0 ABI.
415
416config USER_ABI_CALL0_PROBE
417 bool "Support both windowed and call0 ABI by probing"
418 select USER_ABI_CALL0
419 help
420 Select this option to support both windowed and call0 userspace
421 ABIs. When enabled all processes are started with PS.WOE disabled
422 and a fast user exception handler for an illegal instruction is
423 used to turn on PS.WOE bit on the first 'entry' opcode executed by
424 the userspace.
425
426 This option should be enabled for the kernel that must support
427 both call0 and windowed ABIs in userspace at the same time.
428
429 Note that Xtensa ISA does not guarantee that entry opcode will
430 raise an illegal instruction exception on cores with XEA2 when
431 PS.WOE is disabled, check whether the target core supports it.
432
433endchoice
434
435endmenu
436
437config XTENSA_CALIBRATE_CCOUNT
438 def_bool n
439 help
440 On some platforms (XT2000, for example), the CPU clock rate can
441 vary. The frequency can be determined, however, by measuring
442 against a well known, fixed frequency, such as an UART oscillator.
443
444config SERIAL_CONSOLE
445 def_bool n
446
447menu "Platform options"
448
449choice
450 prompt "Xtensa System Type"
451 default XTENSA_PLATFORM_ISS
452
453config XTENSA_PLATFORM_ISS
454 bool "ISS"
455 select XTENSA_CALIBRATE_CCOUNT
456 select SERIAL_CONSOLE
457 help
458 ISS is an acronym for Tensilica's Instruction Set Simulator.
459
460config XTENSA_PLATFORM_XT2000
461 bool "XT2000"
462 select HAVE_IDE
463 help
464 XT2000 is the name of Tensilica's feature-rich emulation platform.
465 This hardware is capable of running a full Linux distribution.
466
467config XTENSA_PLATFORM_XTFPGA
468 bool "XTFPGA"
469 select ETHOC if ETHERNET
470 select PLATFORM_WANT_DEFAULT_MEM if !MMU
471 select SERIAL_CONSOLE
472 select XTENSA_CALIBRATE_CCOUNT
473 help
474 XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605).
475 This hardware is capable of running a full Linux distribution.
476
477endchoice
478
479config PLATFORM_NR_IRQS
480 int
481 default 3 if XTENSA_PLATFORM_XT2000
482 default 0
483
484config XTENSA_CPU_CLOCK
485 int "CPU clock rate [MHz]"
486 depends on !XTENSA_CALIBRATE_CCOUNT
487 default 16
488
489config GENERIC_CALIBRATE_DELAY
490 bool "Auto calibration of the BogoMIPS value"
491 help
492 The BogoMIPS value can easily be derived from the CPU frequency.
493
494config CMDLINE_BOOL
495 bool "Default bootloader kernel arguments"
496
497config CMDLINE
498 string "Initial kernel command string"
499 depends on CMDLINE_BOOL
500 default "console=ttyS0,38400 root=/dev/ram"
501 help
502 On some architectures (EBSA110 and CATS), there is currently no way
503 for the boot loader to pass arguments to the kernel. For these
504 architectures, you should supply some command-line options at build
505 time by entering them here. As a minimum, you should specify the
506 memory size and the root device (e.g., mem=64M root=/dev/nfs).
507
508config USE_OF
509 bool "Flattened Device Tree support"
510 select OF
511 select OF_EARLY_FLATTREE
512 help
513 Include support for flattened device tree machine descriptions.
514
515config BUILTIN_DTB_SOURCE
516 string "DTB to build into the kernel image"
517 depends on OF
518
519config PARSE_BOOTPARAM
520 bool "Parse bootparam block"
521 default y
522 help
523 Parse parameters passed to the kernel from the bootloader. It may
524 be disabled if the kernel is known to run without the bootloader.
525
526 If unsure, say Y.
527
528config BLK_DEV_SIMDISK
529 tristate "Host file-based simulated block device support"
530 default n
531 depends on XTENSA_PLATFORM_ISS && BLOCK
532 help
533 Create block devices that map to files in the host file system.
534 Device binding to host file may be changed at runtime via proc
535 interface provided the device is not in use.
536
537config BLK_DEV_SIMDISK_COUNT
538 int "Number of host file-based simulated block devices"
539 range 1 10
540 depends on BLK_DEV_SIMDISK
541 default 2
542 help
543 This is the default minimal number of created block devices.
544 Kernel/module parameter 'simdisk_count' may be used to change this
545 value at runtime. More file names (but no more than 10) may be
546 specified as parameters, simdisk_count grows accordingly.
547
548config SIMDISK0_FILENAME
549 string "Host filename for the first simulated device"
550 depends on BLK_DEV_SIMDISK = y
551 default ""
552 help
553 Attach a first simdisk to a host file. Conventionally, this file
554 contains a root file system.
555
556config SIMDISK1_FILENAME
557 string "Host filename for the second simulated device"
558 depends on BLK_DEV_SIMDISK = y && BLK_DEV_SIMDISK_COUNT != 1
559 default ""
560 help
561 Another simulated disk in a host file for a buildroot-independent
562 storage.
563
564config FORCE_MAX_ZONEORDER
565 int "Maximum zone order"
566 default "11"
567 help
568 The kernel memory allocator divides physically contiguous memory
569 blocks into "zones", where each zone is a power of two number of
570 pages. This option selects the largest power of two that the kernel
571 keeps in the memory allocator. If you need to allocate very large
572 blocks of physically contiguous memory, then you may need to
573 increase this value.
574
575 This config option is actually maximum order plus one. For example,
576 a value of 11 means that the largest free memory block is 2^10 pages.
577
578config PLATFORM_WANT_DEFAULT_MEM
579 def_bool n
580
581config DEFAULT_MEM_START
582 hex
583 prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM
584 default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM
585 default 0x00000000
586 help
587 This is the base address used for both PAGE_OFFSET and PHYS_OFFSET
588 in noMMU configurations.
589
590 If unsure, leave the default value here.
591
592config XTFPGA_LCD
593 bool "Enable XTFPGA LCD driver"
594 depends on XTENSA_PLATFORM_XTFPGA
595 default n
596 help
597 There's a 2x16 LCD on most of XTFPGA boards, kernel may output
598 progress messages there during bootup/shutdown. It may be useful
599 during board bringup.
600
601 If unsure, say N.
602
603config XTFPGA_LCD_BASE_ADDR
604 hex "XTFPGA LCD base address"
605 depends on XTFPGA_LCD
606 default "0x0d0c0000"
607 help
608 Base address of the LCD controller inside KIO region.
609 Different boards from XTFPGA family have LCD controller at different
610 addresses. Please consult prototyping user guide for your board for
611 the correct address. Wrong address here may lead to hardware lockup.
612
613config XTFPGA_LCD_8BIT_ACCESS
614 bool "Use 8-bit access to XTFPGA LCD"
615 depends on XTFPGA_LCD
616 default n
617 help
618 LCD may be connected with 4- or 8-bit interface, 8-bit access may
619 only be used with 8-bit interface. Please consult prototyping user
620 guide for your board for the correct interface width.
621
622endmenu
623
624menu "Power management options"
625
626source "kernel/power/Kconfig"
627
628endmenu
629
