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10#include <linux/bitops.h>
11#include <linux/interrupt.h>
12#include <linux/dmaengine.h>
13
14#include <linux/io-64-nonatomic-hi-lo.h>
15
16#include "internal.h"
17
18#define DW_DMA_MAX_NR_REQUESTS 16
19
20
21enum dw_dma_fc {
22 DW_DMA_FC_D_M2M,
23 DW_DMA_FC_D_M2P,
24 DW_DMA_FC_D_P2M,
25 DW_DMA_FC_D_P2P,
26 DW_DMA_FC_P_P2M,
27 DW_DMA_FC_SP_P2P,
28 DW_DMA_FC_P_M2P,
29 DW_DMA_FC_DP_P2P,
30};
31
32
33
34
35
36#define DW_REG(name) u32 name; u32 __pad_##name
37
38
39struct dw_dma_chan_regs {
40 DW_REG(SAR);
41 DW_REG(DAR);
42 DW_REG(LLP);
43 u32 CTL_LO;
44 u32 CTL_HI;
45 DW_REG(SSTAT);
46 DW_REG(DSTAT);
47 DW_REG(SSTATAR);
48 DW_REG(DSTATAR);
49 u32 CFG_LO;
50 u32 CFG_HI;
51 DW_REG(SGR);
52 DW_REG(DSR);
53};
54
55struct dw_dma_irq_regs {
56 DW_REG(XFER);
57 DW_REG(BLOCK);
58 DW_REG(SRC_TRAN);
59 DW_REG(DST_TRAN);
60 DW_REG(ERROR);
61};
62
63struct dw_dma_regs {
64
65 struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS];
66
67
68 struct dw_dma_irq_regs RAW;
69 struct dw_dma_irq_regs STATUS;
70 struct dw_dma_irq_regs MASK;
71 struct dw_dma_irq_regs CLEAR;
72
73 DW_REG(STATUS_INT);
74
75
76 DW_REG(REQ_SRC);
77 DW_REG(REQ_DST);
78 DW_REG(SGL_REQ_SRC);
79 DW_REG(SGL_REQ_DST);
80 DW_REG(LAST_SRC);
81 DW_REG(LAST_DST);
82
83
84 DW_REG(CFG);
85 DW_REG(CH_EN);
86 DW_REG(ID);
87 DW_REG(TEST);
88
89
90 DW_REG(CLASS_PRIORITY0);
91 DW_REG(CLASS_PRIORITY1);
92
93
94 u32 __reserved;
95
96
97 u32 DWC_PARAMS[DW_DMA_MAX_NR_CHANNELS];
98 u32 MULTI_BLK_TYPE;
99 u32 MAX_BLK_SIZE;
100
101
102 u32 DW_PARAMS;
103
104
105 u32 COMP_TYPE;
106 u32 COMP_VERSION;
107
108
109 DW_REG(FIFO_PARTITION0);
110 DW_REG(FIFO_PARTITION1);
111
112 DW_REG(SAI_ERR);
113 DW_REG(GLOBAL_CFG);
114};
115
116
117#define DW_PARAMS_NR_CHAN 8
118#define DW_PARAMS_NR_MASTER 11
119#define DW_PARAMS_DATA_WIDTH(n) (15 + 2 * (n))
120#define DW_PARAMS_DATA_WIDTH1 15
121#define DW_PARAMS_DATA_WIDTH2 17
122#define DW_PARAMS_DATA_WIDTH3 19
123#define DW_PARAMS_DATA_WIDTH4 21
124#define DW_PARAMS_EN 28
125
126
127#define DWC_PARAMS_MBLK_EN 11
128
129
130enum dw_dma_msize {
131 DW_DMA_MSIZE_1,
132 DW_DMA_MSIZE_4,
133 DW_DMA_MSIZE_8,
134 DW_DMA_MSIZE_16,
135 DW_DMA_MSIZE_32,
136 DW_DMA_MSIZE_64,
137 DW_DMA_MSIZE_128,
138 DW_DMA_MSIZE_256,
139};
140
141
142#define DWC_LLP_LMS(x) ((x) & 3)
143#define DWC_LLP_LOC(x) ((x) & ~3)
144
145
146#define DWC_CTLL_INT_EN (1 << 0)
147#define DWC_CTLL_DST_WIDTH(n) ((n)<<1)
148#define DWC_CTLL_SRC_WIDTH(n) ((n)<<4)
149#define DWC_CTLL_DST_INC (0<<7)
150#define DWC_CTLL_DST_DEC (1<<7)
151#define DWC_CTLL_DST_FIX (2<<7)
152#define DWC_CTLL_SRC_INC (0<<9)
153#define DWC_CTLL_SRC_DEC (1<<9)
154#define DWC_CTLL_SRC_FIX (2<<9)
155#define DWC_CTLL_DST_MSIZE(n) ((n)<<11)
156#define DWC_CTLL_SRC_MSIZE(n) ((n)<<14)
157#define DWC_CTLL_S_GATH_EN (1 << 17)
158#define DWC_CTLL_D_SCAT_EN (1 << 18)
159#define DWC_CTLL_FC(n) ((n) << 20)
160#define DWC_CTLL_FC_M2M (0 << 20)
161#define DWC_CTLL_FC_M2P (1 << 20)
162#define DWC_CTLL_FC_P2M (2 << 20)
163#define DWC_CTLL_FC_P2P (3 << 20)
164
165#define DWC_CTLL_DMS(n) ((n)<<23)
166#define DWC_CTLL_SMS(n) ((n)<<25)
167#define DWC_CTLL_LLP_D_EN (1 << 27)
168#define DWC_CTLL_LLP_S_EN (1 << 28)
169
170
171#define DWC_CTLH_BLOCK_TS_MASK GENMASK(11, 0)
172#define DWC_CTLH_BLOCK_TS(x) ((x) & DWC_CTLH_BLOCK_TS_MASK)
173#define DWC_CTLH_DONE (1 << 12)
174
175
176#define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5)
177#define DWC_CFGL_CH_PRIOR(x) ((x) << 5)
178#define DWC_CFGL_CH_SUSP (1 << 8)
179#define DWC_CFGL_FIFO_EMPTY (1 << 9)
180#define DWC_CFGL_HS_DST (1 << 10)
181#define DWC_CFGL_HS_SRC (1 << 11)
182#define DWC_CFGL_LOCK_CH_XFER (0 << 12)
183#define DWC_CFGL_LOCK_CH_BLOCK (1 << 12)
184#define DWC_CFGL_LOCK_CH_XACT (2 << 12)
185#define DWC_CFGL_LOCK_BUS_XFER (0 << 14)
186#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
187#define DWC_CFGL_LOCK_BUS_XACT (2 << 14)
188#define DWC_CFGL_LOCK_CH (1 << 15)
189#define DWC_CFGL_LOCK_BUS (1 << 16)
190#define DWC_CFGL_HS_DST_POL (1 << 18)
191#define DWC_CFGL_HS_SRC_POL (1 << 19)
192#define DWC_CFGL_MAX_BURST(x) ((x) << 20)
193#define DWC_CFGL_RELOAD_SAR (1 << 30)
194#define DWC_CFGL_RELOAD_DAR (1 << 31)
195
196
197#define DWC_CFGH_FCMODE (1 << 0)
198#define DWC_CFGH_FIFO_MODE (1 << 1)
199#define DWC_CFGH_PROTCTL(x) ((x) << 2)
200#define DWC_CFGH_PROTCTL_DATA (0 << 2)
201#define DWC_CFGH_PROTCTL_PRIV (1 << 2)
202#define DWC_CFGH_PROTCTL_BUFFER (2 << 2)
203#define DWC_CFGH_PROTCTL_CACHE (4 << 2)
204#define DWC_CFGH_DS_UPD_EN (1 << 5)
205#define DWC_CFGH_SS_UPD_EN (1 << 6)
206#define DWC_CFGH_SRC_PER(x) ((x) << 7)
207#define DWC_CFGH_DST_PER(x) ((x) << 11)
208
209
210#define DWC_SGR_SGI(x) ((x) << 0)
211#define DWC_SGR_SGC(x) ((x) << 20)
212
213
214#define DWC_DSR_DSI(x) ((x) << 0)
215#define DWC_DSR_DSC(x) ((x) << 20)
216
217
218#define DW_CFG_DMA_EN (1 << 0)
219
220
221
222
223enum idma32_msize {
224 IDMA32_MSIZE_1,
225 IDMA32_MSIZE_2,
226 IDMA32_MSIZE_4,
227 IDMA32_MSIZE_8,
228 IDMA32_MSIZE_16,
229 IDMA32_MSIZE_32,
230};
231
232
233#define IDMA32C_CTLH_BLOCK_TS_MASK GENMASK(16, 0)
234#define IDMA32C_CTLH_BLOCK_TS(x) ((x) & IDMA32C_CTLH_BLOCK_TS_MASK)
235#define IDMA32C_CTLH_DONE (1 << 17)
236
237
238#define IDMA32C_CFGL_DST_BURST_ALIGN (1 << 0)
239#define IDMA32C_CFGL_SRC_BURST_ALIGN (1 << 1)
240#define IDMA32C_CFGL_CH_DRAIN (1 << 10)
241#define IDMA32C_CFGL_DST_OPT_BL (1 << 20)
242#define IDMA32C_CFGL_SRC_OPT_BL (1 << 21)
243
244
245#define IDMA32C_CFGH_SRC_PER(x) ((x) << 0)
246#define IDMA32C_CFGH_DST_PER(x) ((x) << 4)
247#define IDMA32C_CFGH_RD_ISSUE_THD(x) ((x) << 8)
248#define IDMA32C_CFGH_RW_ISSUE_THD(x) ((x) << 18)
249#define IDMA32C_CFGH_SRC_PER_EXT(x) ((x) << 28)
250#define IDMA32C_CFGH_DST_PER_EXT(x) ((x) << 30)
251
252
253#define IDMA32C_FP_PSIZE_CH0(x) ((x) << 0)
254#define IDMA32C_FP_PSIZE_CH1(x) ((x) << 13)
255#define IDMA32C_FP_UPDATE (1 << 26)
256
257enum dw_dmac_flags {
258 DW_DMA_IS_CYCLIC = 0,
259 DW_DMA_IS_SOFT_LLP = 1,
260 DW_DMA_IS_PAUSED = 2,
261 DW_DMA_IS_INITIALIZED = 3,
262};
263
264struct dw_dma_chan {
265 struct dma_chan chan;
266 void __iomem *ch_regs;
267 u8 mask;
268 u8 priority;
269 enum dma_transfer_direction direction;
270
271
272 struct list_head *tx_node_active;
273
274 spinlock_t lock;
275
276
277 unsigned long flags;
278 struct list_head active_list;
279 struct list_head queue;
280
281 unsigned int descs_allocated;
282
283
284 unsigned int block_size;
285 bool nollp;
286
287
288 struct dw_dma_slave dws;
289
290
291 struct dma_slave_config dma_sconfig;
292};
293
294static inline struct dw_dma_chan_regs __iomem *
295__dwc_regs(struct dw_dma_chan *dwc)
296{
297 return dwc->ch_regs;
298}
299
300#define channel_readl(dwc, name) \
301 readl(&(__dwc_regs(dwc)->name))
302#define channel_writel(dwc, name, val) \
303 writel((val), &(__dwc_regs(dwc)->name))
304
305static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
306{
307 return container_of(chan, struct dw_dma_chan, chan);
308}
309
310struct dw_dma {
311 struct dma_device dma;
312 char name[20];
313 void __iomem *regs;
314 struct dma_pool *desc_pool;
315 struct tasklet_struct tasklet;
316
317
318 struct dw_dma_chan *chan;
319 u8 all_chan_mask;
320 u8 in_use;
321
322
323 void (*initialize_chan)(struct dw_dma_chan *dwc);
324 void (*suspend_chan)(struct dw_dma_chan *dwc, bool drain);
325 void (*resume_chan)(struct dw_dma_chan *dwc, bool drain);
326 u32 (*prepare_ctllo)(struct dw_dma_chan *dwc);
327 void (*encode_maxburst)(struct dw_dma_chan *dwc, u32 *maxburst);
328 u32 (*bytes2block)(struct dw_dma_chan *dwc, size_t bytes,
329 unsigned int width, size_t *len);
330 size_t (*block2bytes)(struct dw_dma_chan *dwc, u32 block, u32 width);
331
332
333 void (*set_device_name)(struct dw_dma *dw, int id);
334 void (*disable)(struct dw_dma *dw);
335 void (*enable)(struct dw_dma *dw);
336
337
338 struct dw_dma_platform_data *pdata;
339};
340
341static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
342{
343 return dw->regs;
344}
345
346#define dma_readl(dw, name) \
347 readl(&(__dw_regs(dw)->name))
348#define dma_writel(dw, name, val) \
349 writel((val), &(__dw_regs(dw)->name))
350
351#define idma32_readq(dw, name) \
352 hi_lo_readq(&(__dw_regs(dw)->name))
353#define idma32_writeq(dw, name, val) \
354 hi_lo_writeq((val), &(__dw_regs(dw)->name))
355
356#define channel_set_bit(dw, reg, mask) \
357 dma_writel(dw, reg, ((mask) << 8) | (mask))
358#define channel_clear_bit(dw, reg, mask) \
359 dma_writel(dw, reg, ((mask) << 8) | 0)
360
361static inline struct dw_dma *to_dw_dma(struct dma_device *ddev)
362{
363 return container_of(ddev, struct dw_dma, dma);
364}
365
366
367struct dw_lli {
368
369 __le32 sar;
370 __le32 dar;
371 __le32 llp;
372 __le32 ctllo;
373
374 __le32 ctlhi;
375
376
377
378 __le32 sstat;
379 __le32 dstat;
380};
381
382struct dw_desc {
383
384 struct dw_lli lli;
385
386#define lli_set(d, reg, v) ((d)->lli.reg |= cpu_to_le32(v))
387#define lli_clear(d, reg, v) ((d)->lli.reg &= ~cpu_to_le32(v))
388#define lli_read(d, reg) le32_to_cpu((d)->lli.reg)
389#define lli_write(d, reg, v) ((d)->lli.reg = cpu_to_le32(v))
390
391
392 struct list_head desc_node;
393 struct list_head tx_list;
394 struct dma_async_tx_descriptor txd;
395 size_t len;
396 size_t total_len;
397 u32 residue;
398};
399
400#define to_dw_desc(h) list_entry(h, struct dw_desc, desc_node)
401
402static inline struct dw_desc *
403txd_to_dw_desc(struct dma_async_tx_descriptor *txd)
404{
405 return container_of(txd, struct dw_desc, txd);
406}
407