linux/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
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   1/*
   2 * Copyright 2012-15 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 *  and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#include <linux/delay.h>
  27
  28#include "dc_bios_types.h"
  29#include "dce_stream_encoder.h"
  30#include "reg_helper.h"
  31#include "hw_shared.h"
  32
  33#define DC_LOGGER \
  34                enc110->base.ctx->logger
  35
  36
  37#define REG(reg)\
  38        (enc110->regs->reg)
  39
  40#undef FN
  41#define FN(reg_name, field_name) \
  42        enc110->se_shift->field_name, enc110->se_mask->field_name
  43
  44#define VBI_LINE_0 0
  45#define DP_BLANK_MAX_RETRY 20
  46#define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
  47
  48#ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK
  49        #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK       0x00000010L
  50        #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK         0x00000300L
  51        #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT     0x00000004
  52        #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT       0x00000008
  53#endif
  54
  55enum {
  56        DP_MST_UPDATE_MAX_RETRY = 50
  57};
  58
  59#define DCE110_SE(audio)\
  60        container_of(audio, struct dce110_stream_encoder, base)
  61
  62#define CTX \
  63        enc110->base.ctx
  64
  65static void dce110_update_generic_info_packet(
  66        struct dce110_stream_encoder *enc110,
  67        uint32_t packet_index,
  68        const struct dc_info_packet *info_packet)
  69{
  70        uint32_t regval;
  71        /* TODOFPGA Figure out a proper number for max_retries polling for lock
  72         * use 50 for now.
  73         */
  74        uint32_t max_retries = 50;
  75
  76        /*we need turn on clock before programming AFMT block*/
  77        if (REG(AFMT_CNTL))
  78                REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
  79
  80        if (REG(AFMT_VBI_PACKET_CONTROL1)) {
  81                if (packet_index >= 8)
  82                        ASSERT(0);
  83
  84                /* poll dig_update_lock is not locked -> asic internal signal
  85                 * assume otg master lock will unlock it
  86                 */
  87/*              REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
  88                                0, 10, max_retries);*/
  89
  90                /* check if HW reading GSP memory */
  91                REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
  92                                0, 10, max_retries);
  93
  94                /* HW does is not reading GSP memory not reading too long ->
  95                 * something wrong. clear GPS memory access and notify?
  96                 * hw SW is writing to GSP memory
  97                 */
  98                REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
  99        }
 100        /* choose which generic packet to use */
 101        {
 102                regval = REG_READ(AFMT_VBI_PACKET_CONTROL);
 103                REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
 104                                AFMT_GENERIC_INDEX, packet_index);
 105        }
 106
 107        /* write generic packet header
 108         * (4th byte is for GENERIC0 only) */
 109        {
 110                REG_SET_4(AFMT_GENERIC_HDR, 0,
 111                                AFMT_GENERIC_HB0, info_packet->hb0,
 112                                AFMT_GENERIC_HB1, info_packet->hb1,
 113                                AFMT_GENERIC_HB2, info_packet->hb2,
 114                                AFMT_GENERIC_HB3, info_packet->hb3);
 115        }
 116
 117        /* write generic packet contents
 118         * (we never use last 4 bytes)
 119         * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers */
 120        {
 121                const uint32_t *content =
 122                        (const uint32_t *) &info_packet->sb[0];
 123
 124                REG_WRITE(AFMT_GENERIC_0, *content++);
 125                REG_WRITE(AFMT_GENERIC_1, *content++);
 126                REG_WRITE(AFMT_GENERIC_2, *content++);
 127                REG_WRITE(AFMT_GENERIC_3, *content++);
 128                REG_WRITE(AFMT_GENERIC_4, *content++);
 129                REG_WRITE(AFMT_GENERIC_5, *content++);
 130                REG_WRITE(AFMT_GENERIC_6, *content++);
 131                REG_WRITE(AFMT_GENERIC_7, *content);
 132        }
 133
 134        if (!REG(AFMT_VBI_PACKET_CONTROL1)) {
 135                /* force double-buffered packet update */
 136                REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL,
 137                        AFMT_GENERIC0_UPDATE, (packet_index == 0),
 138                        AFMT_GENERIC2_UPDATE, (packet_index == 2));
 139        }
 140#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 141        if (REG(AFMT_VBI_PACKET_CONTROL1)) {
 142                switch (packet_index) {
 143                case 0:
 144                        REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 145                                        AFMT_GENERIC0_FRAME_UPDATE, 1);
 146                        break;
 147                case 1:
 148                        REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 149                                        AFMT_GENERIC1_FRAME_UPDATE, 1);
 150                        break;
 151                case 2:
 152                        REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 153                                        AFMT_GENERIC2_FRAME_UPDATE, 1);
 154                        break;
 155                case 3:
 156                        REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 157                                        AFMT_GENERIC3_FRAME_UPDATE, 1);
 158                        break;
 159                case 4:
 160                        REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 161                                        AFMT_GENERIC4_FRAME_UPDATE, 1);
 162                        break;
 163                case 5:
 164                        REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 165                                        AFMT_GENERIC5_FRAME_UPDATE, 1);
 166                        break;
 167                case 6:
 168                        REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 169                                        AFMT_GENERIC6_FRAME_UPDATE, 1);
 170                        break;
 171                case 7:
 172                        REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 173                                        AFMT_GENERIC7_FRAME_UPDATE, 1);
 174                        break;
 175                default:
 176                        break;
 177                }
 178        }
 179#endif
 180}
 181
 182static void dce110_update_hdmi_info_packet(
 183        struct dce110_stream_encoder *enc110,
 184        uint32_t packet_index,
 185        const struct dc_info_packet *info_packet)
 186{
 187        uint32_t cont, send, line;
 188
 189        if (info_packet->valid) {
 190                dce110_update_generic_info_packet(
 191                        enc110,
 192                        packet_index,
 193                        info_packet);
 194
 195                /* enable transmission of packet(s) -
 196                 * packet transmission begins on the next frame */
 197                cont = 1;
 198                /* send packet(s) every frame */
 199                send = 1;
 200                /* select line number to send packets on */
 201                line = 2;
 202        } else {
 203                cont = 0;
 204                send = 0;
 205                line = 0;
 206        }
 207
 208        /* choose which generic packet control to use */
 209        switch (packet_index) {
 210        case 0:
 211                REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
 212                                HDMI_GENERIC0_CONT, cont,
 213                                HDMI_GENERIC0_SEND, send,
 214                                HDMI_GENERIC0_LINE, line);
 215                break;
 216        case 1:
 217                REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
 218                                HDMI_GENERIC1_CONT, cont,
 219                                HDMI_GENERIC1_SEND, send,
 220                                HDMI_GENERIC1_LINE, line);
 221                break;
 222        case 2:
 223                REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
 224                                HDMI_GENERIC0_CONT, cont,
 225                                HDMI_GENERIC0_SEND, send,
 226                                HDMI_GENERIC0_LINE, line);
 227                break;
 228        case 3:
 229                REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
 230                                HDMI_GENERIC1_CONT, cont,
 231                                HDMI_GENERIC1_SEND, send,
 232                                HDMI_GENERIC1_LINE, line);
 233                break;
 234#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 235        case 4:
 236                if (REG(HDMI_GENERIC_PACKET_CONTROL2))
 237                        REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
 238                                        HDMI_GENERIC0_CONT, cont,
 239                                        HDMI_GENERIC0_SEND, send,
 240                                        HDMI_GENERIC0_LINE, line);
 241                break;
 242        case 5:
 243                if (REG(HDMI_GENERIC_PACKET_CONTROL2))
 244                        REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
 245                                        HDMI_GENERIC1_CONT, cont,
 246                                        HDMI_GENERIC1_SEND, send,
 247                                        HDMI_GENERIC1_LINE, line);
 248                break;
 249        case 6:
 250                if (REG(HDMI_GENERIC_PACKET_CONTROL3))
 251                        REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
 252                                        HDMI_GENERIC0_CONT, cont,
 253                                        HDMI_GENERIC0_SEND, send,
 254                                        HDMI_GENERIC0_LINE, line);
 255                break;
 256        case 7:
 257                if (REG(HDMI_GENERIC_PACKET_CONTROL3))
 258                        REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
 259                                        HDMI_GENERIC1_CONT, cont,
 260                                        HDMI_GENERIC1_SEND, send,
 261                                        HDMI_GENERIC1_LINE, line);
 262                break;
 263#endif
 264        default:
 265                /* invalid HW packet index */
 266                DC_LOG_WARNING(
 267                        "Invalid HW packet index: %s()\n",
 268                        __func__);
 269                return;
 270        }
 271}
 272
 273/* setup stream encoder in dp mode */
 274static void dce110_stream_encoder_dp_set_stream_attribute(
 275        struct stream_encoder *enc,
 276        struct dc_crtc_timing *crtc_timing,
 277        enum dc_color_space output_color_space,
 278        uint32_t enable_sdp_splitting)
 279{
 280#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 281        uint32_t h_active_start;
 282        uint32_t v_active_start;
 283        uint32_t misc0 = 0;
 284        uint32_t misc1 = 0;
 285        uint32_t h_blank;
 286        uint32_t h_back_porch;
 287        uint8_t synchronous_clock = 0; /* asynchronous mode */
 288        uint8_t colorimetry_bpc;
 289        uint8_t dynamic_range_rgb = 0; /*full range*/
 290        uint8_t dynamic_range_ycbcr = 1; /*bt709*/
 291#endif
 292
 293        struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 294        struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
 295        if (hw_crtc_timing.flags.INTERLACE) {
 296                /*the input timing is in VESA spec format with Interlace flag =1*/
 297                hw_crtc_timing.v_total /= 2;
 298                hw_crtc_timing.v_border_top /= 2;
 299                hw_crtc_timing.v_addressable /= 2;
 300                hw_crtc_timing.v_border_bottom /= 2;
 301                hw_crtc_timing.v_front_porch /= 2;
 302                hw_crtc_timing.v_sync_width /= 2;
 303        }
 304        /* set pixel encoding */
 305        switch (hw_crtc_timing.pixel_encoding) {
 306        case PIXEL_ENCODING_YCBCR422:
 307                REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 308                                DP_PIXEL_ENCODING_TYPE_YCBCR422);
 309                break;
 310        case PIXEL_ENCODING_YCBCR444:
 311                REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 312                                DP_PIXEL_ENCODING_TYPE_YCBCR444);
 313
 314                if (hw_crtc_timing.flags.Y_ONLY)
 315                        if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666)
 316                                /* HW testing only, no use case yet.
 317                                 * Color depth of Y-only could be
 318                                 * 8, 10, 12, 16 bits */
 319                                REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 320                                                DP_PIXEL_ENCODING_TYPE_Y_ONLY);
 321                /* Note: DP_MSA_MISC1 bit 7 is the indicator
 322                 * of Y-only mode.
 323                 * This bit is set in HW if register
 324                 * DP_PIXEL_ENCODING is programmed to 0x4 */
 325                break;
 326        case PIXEL_ENCODING_YCBCR420:
 327                REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 328                                DP_PIXEL_ENCODING_TYPE_YCBCR420);
 329                if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
 330                        REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
 331
 332#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 333                if (enc110->se_mask->DP_VID_N_MUL)
 334                        REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
 335#endif
 336                break;
 337        default:
 338                REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 339                                DP_PIXEL_ENCODING_TYPE_RGB444);
 340                break;
 341        }
 342
 343#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 344        if (REG(DP_MSA_MISC))
 345                misc1 = REG_READ(DP_MSA_MISC);
 346#endif
 347
 348        /* set color depth */
 349
 350        switch (hw_crtc_timing.display_color_depth) {
 351        case COLOR_DEPTH_666:
 352                REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 353                                0);
 354                break;
 355        case COLOR_DEPTH_888:
 356                REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 357                                DP_COMPONENT_PIXEL_DEPTH_8BPC);
 358                break;
 359        case COLOR_DEPTH_101010:
 360                REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 361                                DP_COMPONENT_PIXEL_DEPTH_10BPC);
 362
 363                break;
 364        case COLOR_DEPTH_121212:
 365                REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 366                                DP_COMPONENT_PIXEL_DEPTH_12BPC);
 367                break;
 368        default:
 369                REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 370                                DP_COMPONENT_PIXEL_DEPTH_6BPC);
 371                break;
 372        }
 373
 374        /* set dynamic range and YCbCr range */
 375
 376
 377#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 378        switch (hw_crtc_timing.display_color_depth) {
 379        case COLOR_DEPTH_666:
 380                colorimetry_bpc = 0;
 381                break;
 382        case COLOR_DEPTH_888:
 383                colorimetry_bpc = 1;
 384                break;
 385        case COLOR_DEPTH_101010:
 386                colorimetry_bpc = 2;
 387                break;
 388        case COLOR_DEPTH_121212:
 389                colorimetry_bpc = 3;
 390                break;
 391        default:
 392                colorimetry_bpc = 0;
 393                break;
 394        }
 395
 396        misc0 = misc0 | synchronous_clock;
 397        misc0 = colorimetry_bpc << 5;
 398
 399        if (REG(DP_MSA_TIMING_PARAM1)) {
 400                switch (output_color_space) {
 401                case COLOR_SPACE_SRGB:
 402                        misc0 = misc0 | 0x0;
 403                        misc1 = misc1 & ~0x80; /* bit7 = 0*/
 404                        dynamic_range_rgb = 0; /*full range*/
 405                        break;
 406                case COLOR_SPACE_SRGB_LIMITED:
 407                        misc0 = misc0 | 0x8; /* bit3=1 */
 408                        misc1 = misc1 & ~0x80; /* bit7 = 0*/
 409                        dynamic_range_rgb = 1; /*limited range*/
 410                        break;
 411                case COLOR_SPACE_YCBCR601:
 412                case COLOR_SPACE_YCBCR601_LIMITED:
 413                        misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
 414                        misc1 = misc1 & ~0x80; /* bit7 = 0*/
 415                        dynamic_range_ycbcr = 0; /*bt601*/
 416                        if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
 417                                misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
 418                        else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
 419                                misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
 420                        break;
 421                case COLOR_SPACE_YCBCR709:
 422                case COLOR_SPACE_YCBCR709_LIMITED:
 423                case COLOR_SPACE_YCBCR709_BLACK:
 424                        misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
 425                        misc1 = misc1 & ~0x80; /* bit7 = 0*/
 426                        dynamic_range_ycbcr = 1; /*bt709*/
 427                        if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
 428                                misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
 429                        else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
 430                                misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
 431                        break;
 432                case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
 433                        dynamic_range_rgb = 1; /*limited range*/
 434                        break;
 435                case COLOR_SPACE_2020_RGB_FULLRANGE:
 436                case COLOR_SPACE_2020_YCBCR:
 437                case COLOR_SPACE_XR_RGB:
 438                case COLOR_SPACE_MSREF_SCRGB:
 439                case COLOR_SPACE_ADOBERGB:
 440                case COLOR_SPACE_DCIP3:
 441                case COLOR_SPACE_XV_YCC_709:
 442                case COLOR_SPACE_XV_YCC_601:
 443                case COLOR_SPACE_DISPLAYNATIVE:
 444                case COLOR_SPACE_DOLBYVISION:
 445                case COLOR_SPACE_APPCTRL:
 446                case COLOR_SPACE_CUSTOMPOINTS:
 447                case COLOR_SPACE_UNKNOWN:
 448                        /* do nothing */
 449                        break;
 450                }
 451                if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE)
 452                        REG_UPDATE_2(
 453                                DP_PIXEL_FORMAT,
 454                                DP_DYN_RANGE, dynamic_range_rgb,
 455                                DP_YCBCR_RANGE, dynamic_range_ycbcr);
 456
 457#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 458                if (REG(DP_MSA_COLORIMETRY))
 459                        REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
 460
 461                if (REG(DP_MSA_MISC))
 462                        REG_WRITE(DP_MSA_MISC, misc1);   /* MSA_MISC1 */
 463
 464        /* dcn new register
 465         * dc_crtc_timing is vesa dmt struct. data from edid
 466         */
 467                if (REG(DP_MSA_TIMING_PARAM1))
 468                        REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
 469                                        DP_MSA_HTOTAL, hw_crtc_timing.h_total,
 470                                        DP_MSA_VTOTAL, hw_crtc_timing.v_total);
 471#endif
 472
 473                /* calcuate from vesa timing parameters
 474                 * h_active_start related to leading edge of sync
 475                 */
 476
 477                h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
 478                                hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
 479
 480                h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
 481                                hw_crtc_timing.h_sync_width;
 482
 483                /* start at begining of left border */
 484                h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
 485
 486
 487                v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -
 488                                hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
 489                                hw_crtc_timing.v_front_porch;
 490
 491
 492#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 493                /* start at begining of left border */
 494                if (REG(DP_MSA_TIMING_PARAM2))
 495                        REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
 496                                DP_MSA_HSTART, h_active_start,
 497                                DP_MSA_VSTART, v_active_start);
 498
 499                if (REG(DP_MSA_TIMING_PARAM3))
 500                        REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
 501                                        DP_MSA_HSYNCWIDTH,
 502                                        hw_crtc_timing.h_sync_width,
 503                                        DP_MSA_HSYNCPOLARITY,
 504                                        !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY,
 505                                        DP_MSA_VSYNCWIDTH,
 506                                        hw_crtc_timing.v_sync_width,
 507                                        DP_MSA_VSYNCPOLARITY,
 508                                        !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY);
 509
 510                /* HWDITH include border or overscan */
 511                if (REG(DP_MSA_TIMING_PARAM4))
 512                        REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
 513                                DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +
 514                                hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,
 515                                DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +
 516                                hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);
 517#endif
 518        }
 519#endif
 520}
 521
 522static void dce110_stream_encoder_set_stream_attribute_helper(
 523                struct dce110_stream_encoder *enc110,
 524                struct dc_crtc_timing *crtc_timing)
 525{
 526        if (enc110->regs->TMDS_CNTL) {
 527                switch (crtc_timing->pixel_encoding) {
 528                case PIXEL_ENCODING_YCBCR422:
 529                        REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1);
 530                        break;
 531                default:
 532                        REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0);
 533                        break;
 534                }
 535                REG_UPDATE(TMDS_CNTL, TMDS_COLOR_FORMAT, 0);
 536        } else if (enc110->regs->DIG_FE_CNTL) {
 537                switch (crtc_timing->pixel_encoding) {
 538                case PIXEL_ENCODING_YCBCR422:
 539                        REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
 540                        break;
 541                default:
 542                        REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
 543                        break;
 544                }
 545                REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
 546        }
 547
 548}
 549
 550/* setup stream encoder in hdmi mode */
 551static void dce110_stream_encoder_hdmi_set_stream_attribute(
 552        struct stream_encoder *enc,
 553        struct dc_crtc_timing *crtc_timing,
 554        int actual_pix_clk_khz,
 555        bool enable_audio)
 556{
 557        struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 558        struct bp_encoder_control cntl = {0};
 559
 560        cntl.action = ENCODER_CONTROL_SETUP;
 561        cntl.engine_id = enc110->base.id;
 562        cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 563        cntl.enable_dp_audio = enable_audio;
 564        cntl.pixel_clock = actual_pix_clk_khz;
 565        cntl.lanes_number = LANE_COUNT_FOUR;
 566
 567        if (enc110->base.bp->funcs->encoder_control(
 568                        enc110->base.bp, &cntl) != BP_RESULT_OK)
 569                return;
 570
 571        dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
 572
 573        /* setup HDMI engine */
 574        if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
 575                REG_UPDATE_3(HDMI_CONTROL,
 576                        HDMI_PACKET_GEN_VERSION, 1,
 577                        HDMI_KEEPOUT_MODE, 1,
 578                        HDMI_DEEP_COLOR_ENABLE, 0);
 579        } else if (enc110->regs->DIG_FE_CNTL) {
 580                REG_UPDATE_5(HDMI_CONTROL,
 581                        HDMI_PACKET_GEN_VERSION, 1,
 582                        HDMI_KEEPOUT_MODE, 1,
 583                        HDMI_DEEP_COLOR_ENABLE, 0,
 584                        HDMI_DATA_SCRAMBLE_EN, 0,
 585                        HDMI_CLOCK_CHANNEL_RATE, 0);
 586        }
 587
 588        switch (crtc_timing->display_color_depth) {
 589        case COLOR_DEPTH_888:
 590                REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
 591                break;
 592        case COLOR_DEPTH_101010:
 593                if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
 594                        REG_UPDATE_2(HDMI_CONTROL,
 595                                        HDMI_DEEP_COLOR_DEPTH, 1,
 596                                        HDMI_DEEP_COLOR_ENABLE, 0);
 597                } else {
 598                        REG_UPDATE_2(HDMI_CONTROL,
 599                                        HDMI_DEEP_COLOR_DEPTH, 1,
 600                                        HDMI_DEEP_COLOR_ENABLE, 1);
 601                        }
 602                break;
 603        case COLOR_DEPTH_121212:
 604                if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
 605                        REG_UPDATE_2(HDMI_CONTROL,
 606                                        HDMI_DEEP_COLOR_DEPTH, 2,
 607                                        HDMI_DEEP_COLOR_ENABLE, 0);
 608                } else {
 609                        REG_UPDATE_2(HDMI_CONTROL,
 610                                        HDMI_DEEP_COLOR_DEPTH, 2,
 611                                        HDMI_DEEP_COLOR_ENABLE, 1);
 612                        }
 613                break;
 614        case COLOR_DEPTH_161616:
 615                REG_UPDATE_2(HDMI_CONTROL,
 616                                HDMI_DEEP_COLOR_DEPTH, 3,
 617                                HDMI_DEEP_COLOR_ENABLE, 1);
 618                break;
 619        default:
 620                break;
 621        }
 622
 623        if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
 624                if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
 625                        /* enable HDMI data scrambler
 626                         * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
 627                         * Clock channel frequency is 1/4 of character rate.
 628                         */
 629                        REG_UPDATE_2(HDMI_CONTROL,
 630                                HDMI_DATA_SCRAMBLE_EN, 1,
 631                                HDMI_CLOCK_CHANNEL_RATE, 1);
 632                } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
 633
 634                        /* TODO: New feature for DCE11, still need to implement */
 635
 636                        /* enable HDMI data scrambler
 637                         * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
 638                         * Clock channel frequency is the same
 639                         * as character rate
 640                         */
 641                        REG_UPDATE_2(HDMI_CONTROL,
 642                                HDMI_DATA_SCRAMBLE_EN, 1,
 643                                HDMI_CLOCK_CHANNEL_RATE, 0);
 644                }
 645        }
 646
 647        REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
 648                HDMI_GC_CONT, 1,
 649                HDMI_GC_SEND, 1,
 650                HDMI_NULL_SEND, 1);
 651
 652        /* following belongs to audio */
 653        REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
 654
 655        REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
 656
 657        REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
 658                                VBI_LINE_0 + 2);
 659
 660        REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
 661
 662}
 663
 664/* setup stream encoder in dvi mode */
 665static void dce110_stream_encoder_dvi_set_stream_attribute(
 666        struct stream_encoder *enc,
 667        struct dc_crtc_timing *crtc_timing,
 668        bool is_dual_link)
 669{
 670        struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 671        struct bp_encoder_control cntl = {0};
 672
 673        cntl.action = ENCODER_CONTROL_SETUP;
 674        cntl.engine_id = enc110->base.id;
 675        cntl.signal = is_dual_link ?
 676                        SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
 677        cntl.enable_dp_audio = false;
 678        cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
 679        cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
 680
 681        if (enc110->base.bp->funcs->encoder_control(
 682                        enc110->base.bp, &cntl) != BP_RESULT_OK)
 683                return;
 684
 685        ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
 686        ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
 687        dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
 688}
 689
 690/* setup stream encoder in LVDS mode */
 691static void dce110_stream_encoder_lvds_set_stream_attribute(
 692        struct stream_encoder *enc,
 693        struct dc_crtc_timing *crtc_timing)
 694{
 695        struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 696        struct bp_encoder_control cntl = {0};
 697
 698        cntl.action = ENCODER_CONTROL_SETUP;
 699        cntl.engine_id = enc110->base.id;
 700        cntl.signal = SIGNAL_TYPE_LVDS;
 701        cntl.enable_dp_audio = false;
 702        cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
 703        cntl.lanes_number = LANE_COUNT_FOUR;
 704
 705        if (enc110->base.bp->funcs->encoder_control(
 706                        enc110->base.bp, &cntl) != BP_RESULT_OK)
 707                return;
 708
 709        ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
 710}
 711
 712static void dce110_stream_encoder_set_mst_bandwidth(
 713        struct stream_encoder *enc,
 714        struct fixed31_32 avg_time_slots_per_mtp)
 715{
 716        struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 717        uint32_t x = dc_fixpt_floor(
 718                avg_time_slots_per_mtp);
 719        uint32_t y = dc_fixpt_ceil(
 720                dc_fixpt_shl(
 721                        dc_fixpt_sub_int(
 722                                avg_time_slots_per_mtp,
 723                                x),
 724                        26));
 725
 726        {
 727                REG_SET_2(DP_MSE_RATE_CNTL, 0,
 728                        DP_MSE_RATE_X, x,
 729                        DP_MSE_RATE_Y, y);
 730        }
 731
 732        /* wait for update to be completed on the link */
 733        /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
 734        /* is reset to 0 (not pending) */
 735        REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
 736                        0,
 737                        10, DP_MST_UPDATE_MAX_RETRY);
 738}
 739
 740static void dce110_stream_encoder_update_hdmi_info_packets(
 741        struct stream_encoder *enc,
 742        const struct encoder_info_frame *info_frame)
 743{
 744        struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 745
 746        if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
 747                        enc110->se_mask->HDMI_AVI_INFO_SEND) {
 748
 749                if (info_frame->avi.valid) {
 750                        const uint32_t *content =
 751                                (const uint32_t *) &info_frame->avi.sb[0];
 752                        /*we need turn on clock before programming AFMT block*/
 753                        if (REG(AFMT_CNTL))
 754                                REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
 755
 756                        REG_WRITE(AFMT_AVI_INFO0, content[0]);
 757
 758                        REG_WRITE(AFMT_AVI_INFO1, content[1]);
 759
 760                        REG_WRITE(AFMT_AVI_INFO2, content[2]);
 761
 762                        REG_WRITE(AFMT_AVI_INFO3, content[3]);
 763
 764                        REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION,
 765                                                info_frame->avi.hb1);
 766
 767                        REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
 768                                        HDMI_AVI_INFO_SEND, 1,
 769                                        HDMI_AVI_INFO_CONT, 1);
 770
 771                        REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE,
 772                                                        VBI_LINE_0 + 2);
 773
 774                } else {
 775                        REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
 776                                HDMI_AVI_INFO_SEND, 0,
 777                                HDMI_AVI_INFO_CONT, 0);
 778                }
 779        }
 780
 781        if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
 782                        enc110->se_mask->HDMI_AVI_INFO_SEND) {
 783                dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor);
 784                dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut);
 785                dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd);
 786                dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd);
 787        }
 788
 789#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 790        if (enc110->se_mask->HDMI_DB_DISABLE) {
 791                /* for bring up, disable dp double  TODO */
 792                if (REG(HDMI_DB_CONTROL))
 793                        REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
 794
 795                dce110_update_hdmi_info_packet(enc110, 0, &info_frame->avi);
 796                dce110_update_hdmi_info_packet(enc110, 1, &info_frame->vendor);
 797                dce110_update_hdmi_info_packet(enc110, 2, &info_frame->gamut);
 798                dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd);
 799                dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd);
 800        }
 801#endif
 802}
 803
 804static void dce110_stream_encoder_stop_hdmi_info_packets(
 805        struct stream_encoder *enc)
 806{
 807        struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 808
 809        /* stop generic packets 0 & 1 on HDMI */
 810        REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
 811                HDMI_GENERIC1_CONT, 0,
 812                HDMI_GENERIC1_LINE, 0,
 813                HDMI_GENERIC1_SEND, 0,
 814                HDMI_GENERIC0_CONT, 0,
 815                HDMI_GENERIC0_LINE, 0,
 816                HDMI_GENERIC0_SEND, 0);
 817
 818        /* stop generic packets 2 & 3 on HDMI */
 819        REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
 820                HDMI_GENERIC0_CONT, 0,
 821                HDMI_GENERIC0_LINE, 0,
 822                HDMI_GENERIC0_SEND, 0,
 823                HDMI_GENERIC1_CONT, 0,
 824                HDMI_GENERIC1_LINE, 0,
 825                HDMI_GENERIC1_SEND, 0);
 826
 827#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 828        /* stop generic packets 2 & 3 on HDMI */
 829        if (REG(HDMI_GENERIC_PACKET_CONTROL2))
 830                REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
 831                        HDMI_GENERIC0_CONT, 0,
 832                        HDMI_GENERIC0_LINE, 0,
 833                        HDMI_GENERIC0_SEND, 0,
 834                        HDMI_GENERIC1_CONT, 0,
 835                        HDMI_GENERIC1_LINE, 0,
 836                        HDMI_GENERIC1_SEND, 0);
 837
 838        if (REG(HDMI_GENERIC_PACKET_CONTROL3))
 839                REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
 840                        HDMI_GENERIC0_CONT, 0,
 841                        HDMI_GENERIC0_LINE, 0,
 842                        HDMI_GENERIC0_SEND, 0,
 843                        HDMI_GENERIC1_CONT, 0,
 844                        HDMI_GENERIC1_LINE, 0,
 845                        HDMI_GENERIC1_SEND, 0);
 846#endif
 847}
 848
 849static void dce110_stream_encoder_update_dp_info_packets(
 850        struct stream_encoder *enc,
 851        const struct encoder_info_frame *info_frame)
 852{
 853        struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 854        uint32_t value = 0;
 855
 856        if (info_frame->vsc.valid)
 857                dce110_update_generic_info_packet(
 858                                        enc110,
 859                                        0,  /* packetIndex */
 860                                        &info_frame->vsc);
 861
 862        if (info_frame->spd.valid)
 863                dce110_update_generic_info_packet(
 864                                enc110,
 865                                2,  /* packetIndex */
 866                                &info_frame->spd);
 867
 868        if (info_frame->hdrsmd.valid)
 869                dce110_update_generic_info_packet(
 870                                enc110,
 871                                3,  /* packetIndex */
 872                                &info_frame->hdrsmd);
 873
 874        /* enable/disable transmission of packet(s).
 875        *  If enabled, packet transmission begins on the next frame
 876        */
 877        REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
 878        REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
 879        REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
 880
 881        /* This bit is the master enable bit.
 882        * When enabling secondary stream engine,
 883        * this master bit must also be set.
 884        * This register shared with audio info frame.
 885        * Therefore we need to enable master bit
 886        * if at least on of the fields is not 0
 887        */
 888        value = REG_READ(DP_SEC_CNTL);
 889        if (value)
 890                REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
 891}
 892
 893static void dce110_stream_encoder_stop_dp_info_packets(
 894        struct stream_encoder *enc)
 895{
 896        /* stop generic packets on DP */
 897        struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 898        uint32_t value = 0;
 899
 900        if (enc110->se_mask->DP_SEC_AVI_ENABLE) {
 901                REG_SET_7(DP_SEC_CNTL, 0,
 902                        DP_SEC_GSP0_ENABLE, 0,
 903                        DP_SEC_GSP1_ENABLE, 0,
 904                        DP_SEC_GSP2_ENABLE, 0,
 905                        DP_SEC_GSP3_ENABLE, 0,
 906                        DP_SEC_AVI_ENABLE, 0,
 907                        DP_SEC_MPG_ENABLE, 0,
 908                        DP_SEC_STREAM_ENABLE, 0);
 909        }
 910
 911        /* this register shared with audio info frame.
 912         * therefore we need to keep master enabled
 913         * if at least one of the fields is not 0 */
 914        value = REG_READ(DP_SEC_CNTL);
 915        if (value)
 916                REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
 917
 918}
 919
 920static void dce110_stream_encoder_dp_blank(
 921        struct stream_encoder *enc)
 922{
 923        struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 924        uint32_t  reg1 = 0;
 925        uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
 926
 927        /* Note: For CZ, we are changing driver default to disable
 928         * stream deferred to next VBLANK. If results are positive, we
 929         * will make the same change to all DCE versions. There are a
 930         * handful of panels that cannot handle disable stream at
 931         * HBLANK and will result in a white line flash across the
 932         * screen on stream disable. */
 933        REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1);
 934        if ((reg1 & 0x1) == 0)
 935                /*stream not enabled*/
 936                return;
 937        /* Specify the video stream disable point
 938         * (2 = start of the next vertical blank) */
 939        REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
 940        /* Larger delay to wait until VBLANK - use max retry of
 941         * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
 942         * a little more because we may not trust delay accuracy.
 943         */
 944        max_retries = DP_BLANK_MAX_RETRY * 150;
 945
 946        /* disable DP stream */
 947        REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
 948
 949        /* the encoder stops sending the video stream
 950         * at the start of the vertical blanking.
 951         * Poll for DP_VID_STREAM_STATUS == 0
 952         */
 953
 954        REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
 955                        0,
 956                        10, max_retries);
 957
 958        /* Tell the DP encoder to ignore timing from CRTC, must be done after
 959         * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
 960         * complete, stream status will be stuck in video stream enabled state,
 961         * i.e. DP_VID_STREAM_STATUS stuck at 1.
 962         */
 963
 964        REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
 965}
 966
 967/* output video stream to link encoder */
 968static void dce110_stream_encoder_dp_unblank(
 969        struct stream_encoder *enc,
 970        const struct encoder_unblank_param *param)
 971{
 972        struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 973
 974        if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
 975                uint32_t n_vid = 0x8000;
 976                uint32_t m_vid;
 977
 978                /* M / N = Fstream / Flink
 979                * m_vid / n_vid = pixel rate / link rate
 980                */
 981
 982                uint64_t m_vid_l = n_vid;
 983
 984                m_vid_l *= param->timing.pix_clk_100hz / 10;
 985                m_vid_l = div_u64(m_vid_l,
 986                        param->link_settings.link_rate
 987                                * LINK_RATE_REF_FREQ_IN_KHZ);
 988
 989                m_vid = (uint32_t) m_vid_l;
 990
 991                /* enable auto measurement */
 992
 993                REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
 994
 995                /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
 996                 * therefore program initial value for Mvid and Nvid
 997                 */
 998
 999                REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
1000
1001                REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
1002
1003                REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);
1004        }
1005
1006        /* set DIG_START to 0x1 to resync FIFO */
1007
1008        REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
1009
1010        /* switch DP encoder to CRTC data */
1011
1012        REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
1013
1014        /* wait 100us for DIG/DP logic to prime
1015        * (i.e. a few video lines)
1016        */
1017        udelay(100);
1018
1019        /* the hardware would start sending video at the start of the next DP
1020        * frame (i.e. rising edge of the vblank).
1021        * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
1022        * register has no effect on enable transition! HW always guarantees
1023        * VID_STREAM enable at start of next frame, and this is not
1024        * programmable
1025        */
1026
1027        REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
1028}
1029
1030static void dce110_stream_encoder_set_avmute(
1031        struct stream_encoder *enc,
1032        bool enable)
1033{
1034        struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1035        unsigned int value = enable ? 1 : 0;
1036
1037        REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
1038}
1039
1040
1041static void dce110_reset_hdmi_stream_attribute(
1042        struct stream_encoder *enc)
1043{
1044        struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1045        if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN)
1046                REG_UPDATE_5(HDMI_CONTROL,
1047                        HDMI_PACKET_GEN_VERSION, 1,
1048                        HDMI_KEEPOUT_MODE, 1,
1049                        HDMI_DEEP_COLOR_ENABLE, 0,
1050                        HDMI_DATA_SCRAMBLE_EN, 0,
1051                        HDMI_CLOCK_CHANNEL_RATE, 0);
1052        else
1053                REG_UPDATE_3(HDMI_CONTROL,
1054                        HDMI_PACKET_GEN_VERSION, 1,
1055                        HDMI_KEEPOUT_MODE, 1,
1056                        HDMI_DEEP_COLOR_ENABLE, 0);
1057}
1058
1059#define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
1060#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
1061
1062#include "include/audio_types.h"
1063
1064/**
1065* speakersToChannels
1066*
1067* @brief
1068*  translate speakers to channels
1069*
1070*  FL  - Front Left
1071*  FR  - Front Right
1072*  RL  - Rear Left
1073*  RR  - Rear Right
1074*  RC  - Rear Center
1075*  FC  - Front Center
1076*  FLC - Front Left Center
1077*  FRC - Front Right Center
1078*  RLC - Rear Left Center
1079*  RRC - Rear Right Center
1080*  LFE - Low Freq Effect
1081*
1082*               FC
1083*          FLC      FRC
1084*    FL                    FR
1085*
1086*                    LFE
1087*              ()
1088*
1089*
1090*    RL                    RR
1091*          RLC      RRC
1092*               RC
1093*
1094*             ch  8   7   6   5   4   3   2   1
1095* 0b00000011      -   -   -   -   -   -   FR  FL
1096* 0b00000111      -   -   -   -   -   LFE FR  FL
1097* 0b00001011      -   -   -   -   FC  -   FR  FL
1098* 0b00001111      -   -   -   -   FC  LFE FR  FL
1099* 0b00010011      -   -   -   RC  -   -   FR  FL
1100* 0b00010111      -   -   -   RC  -   LFE FR  FL
1101* 0b00011011      -   -   -   RC  FC  -   FR  FL
1102* 0b00011111      -   -   -   RC  FC  LFE FR  FL
1103* 0b00110011      -   -   RR  RL  -   -   FR  FL
1104* 0b00110111      -   -   RR  RL  -   LFE FR  FL
1105* 0b00111011      -   -   RR  RL  FC  -   FR  FL
1106* 0b00111111      -   -   RR  RL  FC  LFE FR  FL
1107* 0b01110011      -   RC  RR  RL  -   -   FR  FL
1108* 0b01110111      -   RC  RR  RL  -   LFE FR  FL
1109* 0b01111011      -   RC  RR  RL  FC  -   FR  FL
1110* 0b01111111      -   RC  RR  RL  FC  LFE FR  FL
1111* 0b11110011      RRC RLC RR  RL  -   -   FR  FL
1112* 0b11110111      RRC RLC RR  RL  -   LFE FR  FL
1113* 0b11111011      RRC RLC RR  RL  FC  -   FR  FL
1114* 0b11111111      RRC RLC RR  RL  FC  LFE FR  FL
1115* 0b11000011      FRC FLC -   -   -   -   FR  FL
1116* 0b11000111      FRC FLC -   -   -   LFE FR  FL
1117* 0b11001011      FRC FLC -   -   FC  -   FR  FL
1118* 0b11001111      FRC FLC -   -   FC  LFE FR  FL
1119* 0b11010011      FRC FLC -   RC  -   -   FR  FL
1120* 0b11010111      FRC FLC -   RC  -   LFE FR  FL
1121* 0b11011011      FRC FLC -   RC  FC  -   FR  FL
1122* 0b11011111      FRC FLC -   RC  FC  LFE FR  FL
1123* 0b11110011      FRC FLC RR  RL  -   -   FR  FL
1124* 0b11110111      FRC FLC RR  RL  -   LFE FR  FL
1125* 0b11111011      FRC FLC RR  RL  FC  -   FR  FL
1126* 0b11111111      FRC FLC RR  RL  FC  LFE FR  FL
1127*
1128* @param
1129*  speakers - speaker information as it comes from CEA audio block
1130*/
1131/* translate speakers to channels */
1132
1133union audio_cea_channels {
1134        uint8_t all;
1135        struct audio_cea_channels_bits {
1136                uint32_t FL:1;
1137                uint32_t FR:1;
1138                uint32_t LFE:1;
1139                uint32_t FC:1;
1140                uint32_t RL_RC:1;
1141                uint32_t RR:1;
1142                uint32_t RC_RLC_FLC:1;
1143                uint32_t RRC_FRC:1;
1144        } channels;
1145};
1146
1147/* 25.2MHz/1.001*/
1148/* 25.2MHz/1.001*/
1149/* 25.2MHz*/
1150/* 27MHz */
1151/* 27MHz*1.001*/
1152/* 27MHz*1.001*/
1153/* 54MHz*/
1154/* 54MHz*1.001*/
1155/* 74.25MHz/1.001*/
1156/* 74.25MHz*/
1157/* 148.5MHz/1.001*/
1158/* 148.5MHz*/
1159
1160static const struct audio_clock_info audio_clock_info_table[16] = {
1161        {2517, 4576, 28125, 7007, 31250, 6864, 28125},
1162        {2518, 4576, 28125, 7007, 31250, 6864, 28125},
1163        {2520, 4096, 25200, 6272, 28000, 6144, 25200},
1164        {2700, 4096, 27000, 6272, 30000, 6144, 27000},
1165        {2702, 4096, 27027, 6272, 30030, 6144, 27027},
1166        {2703, 4096, 27027, 6272, 30030, 6144, 27027},
1167        {5400, 4096, 54000, 6272, 60000, 6144, 54000},
1168        {5405, 4096, 54054, 6272, 60060, 6144, 54054},
1169        {7417, 11648, 210937, 17836, 234375, 11648, 140625},
1170        {7425, 4096, 74250, 6272, 82500, 6144, 74250},
1171        {14835, 11648, 421875, 8918, 234375, 5824, 140625},
1172        {14850, 4096, 148500, 6272, 165000, 6144, 148500},
1173        {29670, 5824, 421875, 4459, 234375, 5824, 281250},
1174        {29700, 3072, 222750, 4704, 247500, 5120, 247500},
1175        {59340, 5824, 843750, 8918, 937500, 5824, 562500},
1176        {59400, 3072, 445500, 9408, 990000, 6144, 594000}
1177};
1178
1179static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
1180        {2517,  9152,  84375,  7007,  48875,  9152,  56250},
1181        {2518,  9152,  84375,  7007,  48875,  9152,  56250},
1182        {2520,  4096,  37800,  6272,  42000,  6144,  37800},
1183        {2700,  4096,  40500,  6272,  45000,  6144,  40500},
1184        {2702,  8192,  81081,  6272,  45045,  8192,  54054},
1185        {2703,  8192,  81081,  6272,  45045,  8192,  54054},
1186        {5400,  4096,  81000,  6272,  90000,  6144,  81000},
1187        {5405,  4096,  81081,  6272,  90090,  6144,  81081},
1188        {7417, 11648, 316406, 17836, 351562, 11648, 210937},
1189        {7425, 4096, 111375,  6272, 123750,  6144, 111375},
1190        {14835, 11648, 632812, 17836, 703125, 11648, 421875},
1191        {14850, 4096, 222750,  6272, 247500,  6144, 222750},
1192        {29670, 5824, 632812,  8918, 703125,  5824, 421875},
1193        {29700, 4096, 445500,  4704, 371250,  5120, 371250}
1194};
1195
1196static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
1197        {2517,  4576,  56250,  7007,  62500,  6864,  56250},
1198        {2518,  4576,  56250,  7007,  62500,  6864,  56250},
1199        {2520,  4096,  50400,  6272,  56000,  6144,  50400},
1200        {2700,  4096,  54000,  6272,  60000,  6144,  54000},
1201        {2702,  4096,  54054,  6267,  60060,  8192,  54054},
1202        {2703,  4096,  54054,  6272,  60060,  8192,  54054},
1203        {5400,  4096, 108000,  6272, 120000,  6144, 108000},
1204        {5405,  4096, 108108,  6272, 120120,  6144, 108108},
1205        {7417, 11648, 421875, 17836, 468750, 11648, 281250},
1206        {7425,  4096, 148500,  6272, 165000,  6144, 148500},
1207        {14835, 11648, 843750,  8918, 468750, 11648, 281250},
1208        {14850, 4096, 297000,  6272, 330000,  6144, 297000},
1209        {29670, 5824, 843750,  4459, 468750,  5824, 562500},
1210        {29700, 3072, 445500,  4704, 495000,  5120, 495000}
1211
1212
1213};
1214
1215static union audio_cea_channels speakers_to_channels(
1216        struct audio_speaker_flags speaker_flags)
1217{
1218        union audio_cea_channels cea_channels = {0};
1219
1220        /* these are one to one */
1221        cea_channels.channels.FL = speaker_flags.FL_FR;
1222        cea_channels.channels.FR = speaker_flags.FL_FR;
1223        cea_channels.channels.LFE = speaker_flags.LFE;
1224        cea_channels.channels.FC = speaker_flags.FC;
1225
1226        /* if Rear Left and Right exist move RC speaker to channel 7
1227         * otherwise to channel 5
1228         */
1229        if (speaker_flags.RL_RR) {
1230                cea_channels.channels.RL_RC = speaker_flags.RL_RR;
1231                cea_channels.channels.RR = speaker_flags.RL_RR;
1232                cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
1233        } else {
1234                cea_channels.channels.RL_RC = speaker_flags.RC;
1235        }
1236
1237        /* FRONT Left Right Center and REAR Left Right Center are exclusive */
1238        if (speaker_flags.FLC_FRC) {
1239                cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
1240                cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
1241        } else {
1242                cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
1243                cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
1244        }
1245
1246        return cea_channels;
1247}
1248
1249static uint32_t calc_max_audio_packets_per_line(
1250        const struct audio_crtc_info *crtc_info)
1251{
1252        uint32_t max_packets_per_line;
1253
1254        max_packets_per_line =
1255                crtc_info->h_total - crtc_info->h_active;
1256
1257        if (crtc_info->pixel_repetition)
1258                max_packets_per_line *= crtc_info->pixel_repetition;
1259
1260        /* for other hdmi features */
1261        max_packets_per_line -= 58;
1262        /* for Control Period */
1263        max_packets_per_line -= 16;
1264        /* Number of Audio Packets per Line */
1265        max_packets_per_line /= 32;
1266
1267        return max_packets_per_line;
1268}
1269
1270static void get_audio_clock_info(
1271        enum dc_color_depth color_depth,
1272        uint32_t crtc_pixel_clock_100Hz,
1273        uint32_t actual_pixel_clock_100Hz,
1274        struct audio_clock_info *audio_clock_info)
1275{
1276        const struct audio_clock_info *clock_info;
1277        uint32_t index;
1278        uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100;
1279        uint32_t audio_array_size;
1280
1281        switch (color_depth) {
1282        case COLOR_DEPTH_161616:
1283                clock_info = audio_clock_info_table_48bpc;
1284                audio_array_size = ARRAY_SIZE(
1285                                audio_clock_info_table_48bpc);
1286                break;
1287        case COLOR_DEPTH_121212:
1288                clock_info = audio_clock_info_table_36bpc;
1289                audio_array_size = ARRAY_SIZE(
1290                                audio_clock_info_table_36bpc);
1291                break;
1292        default:
1293                clock_info = audio_clock_info_table;
1294                audio_array_size = ARRAY_SIZE(
1295                                audio_clock_info_table);
1296                break;
1297        }
1298
1299        if (clock_info != NULL) {
1300                /* search for exact pixel clock in table */
1301                for (index = 0; index < audio_array_size; index++) {
1302                        if (clock_info[index].pixel_clock_in_10khz >
1303                                crtc_pixel_clock_in_10khz)
1304                                break;  /* not match */
1305                        else if (clock_info[index].pixel_clock_in_10khz ==
1306                                        crtc_pixel_clock_in_10khz) {
1307                                /* match found */
1308                                *audio_clock_info = clock_info[index];
1309                                return;
1310                        }
1311                }
1312        }
1313
1314        /* not found */
1315        if (actual_pixel_clock_100Hz == 0)
1316                actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz;
1317
1318        /* See HDMI spec  the table entry under
1319         *  pixel clock of "Other". */
1320        audio_clock_info->pixel_clock_in_10khz =
1321                        actual_pixel_clock_100Hz / 100;
1322        audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10;
1323        audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10;
1324        audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10;
1325
1326        audio_clock_info->n_32khz = 4096;
1327        audio_clock_info->n_44khz = 6272;
1328        audio_clock_info->n_48khz = 6144;
1329}
1330
1331static void dce110_se_audio_setup(
1332        struct stream_encoder *enc,
1333        unsigned int az_inst,
1334        struct audio_info *audio_info)
1335{
1336        struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1337
1338        uint32_t speakers = 0;
1339        uint32_t channels = 0;
1340
1341        ASSERT(audio_info);
1342        if (audio_info == NULL)
1343                /* This should not happen.it does so we don't get BSOD*/
1344                return;
1345
1346        speakers = audio_info->flags.info.ALLSPEAKERS;
1347        channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
1348
1349        /* setup the audio stream source select (audio -> dig mapping) */
1350        REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
1351
1352        /* Channel allocation */
1353        REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
1354}
1355
1356static void dce110_se_setup_hdmi_audio(
1357        struct stream_encoder *enc,
1358        const struct audio_crtc_info *crtc_info)
1359{
1360        struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1361
1362        struct audio_clock_info audio_clock_info = {0};
1363        uint32_t max_packets_per_line;
1364
1365        /* For now still do calculation, although this field is ignored when
1366        above HDMI_PACKET_GEN_VERSION set to 1 */
1367        max_packets_per_line = calc_max_audio_packets_per_line(crtc_info);
1368
1369        /* HDMI_AUDIO_PACKET_CONTROL */
1370        REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL,
1371                        HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line,
1372                        HDMI_AUDIO_DELAY_EN, 1);
1373
1374        /* AFMT_AUDIO_PACKET_CONTROL */
1375        REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1376
1377        /* AFMT_AUDIO_PACKET_CONTROL2 */
1378        REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1379                        AFMT_AUDIO_LAYOUT_OVRD, 0,
1380                        AFMT_60958_OSF_OVRD, 0);
1381
1382        /* HDMI_ACR_PACKET_CONTROL */
1383        REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
1384                        HDMI_ACR_AUTO_SEND, 1,
1385                        HDMI_ACR_SOURCE, 0,
1386                        HDMI_ACR_AUDIO_PRIORITY, 0);
1387
1388        /* Program audio clock sample/regeneration parameters */
1389        get_audio_clock_info(crtc_info->color_depth,
1390                             crtc_info->requested_pixel_clock_100Hz,
1391                             crtc_info->calculated_pixel_clock_100Hz,
1392                             &audio_clock_info);
1393        DC_LOG_HW_AUDIO(
1394                        "\n%s:Input::requested_pixel_clock_100Hz = %d"  \
1395                        "calculated_pixel_clock_100Hz = %d \n", __func__,       \
1396                        crtc_info->requested_pixel_clock_100Hz,         \
1397                        crtc_info->calculated_pixel_clock_100Hz);
1398
1399        /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
1400        REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
1401
1402        /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
1403        REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
1404
1405        /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
1406        REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
1407
1408        /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
1409        REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
1410
1411        /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
1412        REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
1413
1414        /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
1415        REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
1416
1417        /* Video driver cannot know in advance which sample rate will
1418           be used by HD Audio driver
1419           HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
1420           programmed below in interruppt callback */
1421
1422        /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
1423        AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1424        REG_UPDATE_2(AFMT_60958_0,
1425                        AFMT_60958_CS_CHANNEL_NUMBER_L, 1,
1426                        AFMT_60958_CS_CLOCK_ACCURACY, 0);
1427
1428        /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
1429        REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1430
1431        /*AFMT_60958_2 now keep this settings until
1432         *  Programming guide comes out*/
1433        REG_UPDATE_6(AFMT_60958_2,
1434                        AFMT_60958_CS_CHANNEL_NUMBER_2, 3,
1435                        AFMT_60958_CS_CHANNEL_NUMBER_3, 4,
1436                        AFMT_60958_CS_CHANNEL_NUMBER_4, 5,
1437                        AFMT_60958_CS_CHANNEL_NUMBER_5, 6,
1438                        AFMT_60958_CS_CHANNEL_NUMBER_6, 7,
1439                        AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1440}
1441
1442static void dce110_se_setup_dp_audio(
1443        struct stream_encoder *enc)
1444{
1445        struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1446
1447        /* --- DP Audio packet configurations --- */
1448
1449        /* ATP Configuration */
1450        REG_SET(DP_SEC_AUD_N, 0,
1451                        DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
1452
1453        /* Async/auto-calc timestamp mode */
1454        REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
1455                        DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
1456
1457        /* --- The following are the registers
1458         *  copied from the SetupHDMI --- */
1459
1460        /* AFMT_AUDIO_PACKET_CONTROL */
1461        REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1462
1463        /* AFMT_AUDIO_PACKET_CONTROL2 */
1464        /* Program the ATP and AIP next */
1465        REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1466                        AFMT_AUDIO_LAYOUT_OVRD, 0,
1467                        AFMT_60958_OSF_OVRD, 0);
1468
1469        /* AFMT_INFOFRAME_CONTROL0 */
1470        REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1471
1472        /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1473        REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
1474}
1475
1476static void dce110_se_enable_audio_clock(
1477        struct stream_encoder *enc,
1478        bool enable)
1479{
1480        struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1481
1482        if (REG(AFMT_CNTL) == 0)
1483                return;   /* DCE8/10 does not have this register */
1484
1485        REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
1486
1487        /* wait for AFMT clock to turn on,
1488         * expectation: this should complete in 1-2 reads
1489         *
1490         * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
1491         *
1492         * TODO: wait for clock_on does not work well. May need HW
1493         * program sequence. But audio seems work normally even without wait
1494         * for clock_on status change
1495         */
1496}
1497
1498static void dce110_se_enable_dp_audio(
1499        struct stream_encoder *enc)
1500{
1501        struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1502
1503        /* Enable Audio packets */
1504        REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1505
1506        /* Program the ATP and AIP next */
1507        REG_UPDATE_2(DP_SEC_CNTL,
1508                        DP_SEC_ATP_ENABLE, 1,
1509                        DP_SEC_AIP_ENABLE, 1);
1510
1511        /* Program STREAM_ENABLE after all the other enables. */
1512        REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1513}
1514
1515static void dce110_se_disable_dp_audio(
1516        struct stream_encoder *enc)
1517{
1518        struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1519        uint32_t value = 0;
1520
1521        /* Disable Audio packets */
1522        REG_UPDATE_5(DP_SEC_CNTL,
1523                        DP_SEC_ASP_ENABLE, 0,
1524                        DP_SEC_ATP_ENABLE, 0,
1525                        DP_SEC_AIP_ENABLE, 0,
1526                        DP_SEC_ACM_ENABLE, 0,
1527                        DP_SEC_STREAM_ENABLE, 0);
1528
1529        /* This register shared with encoder info frame. Therefore we need to
1530        keep master enabled if at least on of the fields is not 0 */
1531        value = REG_READ(DP_SEC_CNTL);
1532        if (value != 0)
1533                REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1534
1535}
1536
1537void dce110_se_audio_mute_control(
1538        struct stream_encoder *enc,
1539        bool mute)
1540{
1541        struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1542
1543        REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
1544}
1545
1546void dce110_se_dp_audio_setup(
1547        struct stream_encoder *enc,
1548        unsigned int az_inst,
1549        struct audio_info *info)
1550{
1551        dce110_se_audio_setup(enc, az_inst, info);
1552}
1553
1554void dce110_se_dp_audio_enable(
1555        struct stream_encoder *enc)
1556{
1557        dce110_se_enable_audio_clock(enc, true);
1558        dce110_se_setup_dp_audio(enc);
1559        dce110_se_enable_dp_audio(enc);
1560}
1561
1562void dce110_se_dp_audio_disable(
1563        struct stream_encoder *enc)
1564{
1565        dce110_se_disable_dp_audio(enc);
1566        dce110_se_enable_audio_clock(enc, false);
1567}
1568
1569void dce110_se_hdmi_audio_setup(
1570        struct stream_encoder *enc,
1571        unsigned int az_inst,
1572        struct audio_info *info,
1573        struct audio_crtc_info *audio_crtc_info)
1574{
1575        dce110_se_enable_audio_clock(enc, true);
1576        dce110_se_setup_hdmi_audio(enc, audio_crtc_info);
1577        dce110_se_audio_setup(enc, az_inst, info);
1578}
1579
1580void dce110_se_hdmi_audio_disable(
1581        struct stream_encoder *enc)
1582{
1583        dce110_se_enable_audio_clock(enc, false);
1584}
1585
1586
1587static void setup_stereo_sync(
1588        struct stream_encoder *enc,
1589        int tg_inst, bool enable)
1590{
1591        struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1592        REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1593        REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
1594}
1595
1596static void dig_connect_to_otg(
1597        struct stream_encoder *enc,
1598        int tg_inst)
1599{
1600        struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1601
1602        REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
1603}
1604
1605static unsigned int dig_source_otg(
1606        struct stream_encoder *enc)
1607{
1608        uint32_t tg_inst = 0;
1609        struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1610
1611        REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
1612
1613        return tg_inst;
1614}
1615
1616static const struct stream_encoder_funcs dce110_str_enc_funcs = {
1617        .dp_set_stream_attribute =
1618                dce110_stream_encoder_dp_set_stream_attribute,
1619        .hdmi_set_stream_attribute =
1620                dce110_stream_encoder_hdmi_set_stream_attribute,
1621        .dvi_set_stream_attribute =
1622                dce110_stream_encoder_dvi_set_stream_attribute,
1623        .lvds_set_stream_attribute =
1624                dce110_stream_encoder_lvds_set_stream_attribute,
1625        .set_mst_bandwidth =
1626                dce110_stream_encoder_set_mst_bandwidth,
1627        .update_hdmi_info_packets =
1628                dce110_stream_encoder_update_hdmi_info_packets,
1629        .stop_hdmi_info_packets =
1630                dce110_stream_encoder_stop_hdmi_info_packets,
1631        .update_dp_info_packets =
1632                dce110_stream_encoder_update_dp_info_packets,
1633        .stop_dp_info_packets =
1634                dce110_stream_encoder_stop_dp_info_packets,
1635        .dp_blank =
1636                dce110_stream_encoder_dp_blank,
1637        .dp_unblank =
1638                dce110_stream_encoder_dp_unblank,
1639        .audio_mute_control = dce110_se_audio_mute_control,
1640
1641        .dp_audio_setup = dce110_se_dp_audio_setup,
1642        .dp_audio_enable = dce110_se_dp_audio_enable,
1643        .dp_audio_disable = dce110_se_dp_audio_disable,
1644
1645        .hdmi_audio_setup = dce110_se_hdmi_audio_setup,
1646        .hdmi_audio_disable = dce110_se_hdmi_audio_disable,
1647        .setup_stereo_sync  = setup_stereo_sync,
1648        .set_avmute = dce110_stream_encoder_set_avmute,
1649        .dig_connect_to_otg  = dig_connect_to_otg,
1650        .hdmi_reset_stream_attribute = dce110_reset_hdmi_stream_attribute,
1651        .dig_source_otg = dig_source_otg,
1652};
1653
1654void dce110_stream_encoder_construct(
1655        struct dce110_stream_encoder *enc110,
1656        struct dc_context *ctx,
1657        struct dc_bios *bp,
1658        enum engine_id eng_id,
1659        const struct dce110_stream_enc_registers *regs,
1660        const struct dce_stream_encoder_shift *se_shift,
1661        const struct dce_stream_encoder_mask *se_mask)
1662{
1663        enc110->base.funcs = &dce110_str_enc_funcs;
1664        enc110->base.ctx = ctx;
1665        enc110->base.id = eng_id;
1666        enc110->base.bp = bp;
1667        enc110->regs = regs;
1668        enc110->se_shift = se_shift;
1669        enc110->se_mask = se_mask;
1670}
1671