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26#include <linux/delay.h>
27
28#include "dc_bios_types.h"
29#include "dce_stream_encoder.h"
30#include "reg_helper.h"
31#include "hw_shared.h"
32
33#define DC_LOGGER \
34 enc110->base.ctx->logger
35
36
37#define REG(reg)\
38 (enc110->regs->reg)
39
40#undef FN
41#define FN(reg_name, field_name) \
42 enc110->se_shift->field_name, enc110->se_mask->field_name
43
44#define VBI_LINE_0 0
45#define DP_BLANK_MAX_RETRY 20
46#define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
47
48#ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK
49 #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x00000010L
50 #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x00000300L
51 #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x00000004
52 #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x00000008
53#endif
54
55enum {
56 DP_MST_UPDATE_MAX_RETRY = 50
57};
58
59#define DCE110_SE(audio)\
60 container_of(audio, struct dce110_stream_encoder, base)
61
62#define CTX \
63 enc110->base.ctx
64
65static void dce110_update_generic_info_packet(
66 struct dce110_stream_encoder *enc110,
67 uint32_t packet_index,
68 const struct dc_info_packet *info_packet)
69{
70 uint32_t regval;
71
72
73
74 uint32_t max_retries = 50;
75
76
77 if (REG(AFMT_CNTL))
78 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
79
80 if (REG(AFMT_VBI_PACKET_CONTROL1)) {
81 if (packet_index >= 8)
82 ASSERT(0);
83
84
85
86
87
88
89
90
91 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
92 0, 10, max_retries);
93
94
95
96
97
98 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
99 }
100
101 {
102 regval = REG_READ(AFMT_VBI_PACKET_CONTROL);
103 REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
104 AFMT_GENERIC_INDEX, packet_index);
105 }
106
107
108
109 {
110 REG_SET_4(AFMT_GENERIC_HDR, 0,
111 AFMT_GENERIC_HB0, info_packet->hb0,
112 AFMT_GENERIC_HB1, info_packet->hb1,
113 AFMT_GENERIC_HB2, info_packet->hb2,
114 AFMT_GENERIC_HB3, info_packet->hb3);
115 }
116
117
118
119
120 {
121 const uint32_t *content =
122 (const uint32_t *) &info_packet->sb[0];
123
124 REG_WRITE(AFMT_GENERIC_0, *content++);
125 REG_WRITE(AFMT_GENERIC_1, *content++);
126 REG_WRITE(AFMT_GENERIC_2, *content++);
127 REG_WRITE(AFMT_GENERIC_3, *content++);
128 REG_WRITE(AFMT_GENERIC_4, *content++);
129 REG_WRITE(AFMT_GENERIC_5, *content++);
130 REG_WRITE(AFMT_GENERIC_6, *content++);
131 REG_WRITE(AFMT_GENERIC_7, *content);
132 }
133
134 if (!REG(AFMT_VBI_PACKET_CONTROL1)) {
135
136 REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL,
137 AFMT_GENERIC0_UPDATE, (packet_index == 0),
138 AFMT_GENERIC2_UPDATE, (packet_index == 2));
139 }
140#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
141 if (REG(AFMT_VBI_PACKET_CONTROL1)) {
142 switch (packet_index) {
143 case 0:
144 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
145 AFMT_GENERIC0_FRAME_UPDATE, 1);
146 break;
147 case 1:
148 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
149 AFMT_GENERIC1_FRAME_UPDATE, 1);
150 break;
151 case 2:
152 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
153 AFMT_GENERIC2_FRAME_UPDATE, 1);
154 break;
155 case 3:
156 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
157 AFMT_GENERIC3_FRAME_UPDATE, 1);
158 break;
159 case 4:
160 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
161 AFMT_GENERIC4_FRAME_UPDATE, 1);
162 break;
163 case 5:
164 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
165 AFMT_GENERIC5_FRAME_UPDATE, 1);
166 break;
167 case 6:
168 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
169 AFMT_GENERIC6_FRAME_UPDATE, 1);
170 break;
171 case 7:
172 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
173 AFMT_GENERIC7_FRAME_UPDATE, 1);
174 break;
175 default:
176 break;
177 }
178 }
179#endif
180}
181
182static void dce110_update_hdmi_info_packet(
183 struct dce110_stream_encoder *enc110,
184 uint32_t packet_index,
185 const struct dc_info_packet *info_packet)
186{
187 uint32_t cont, send, line;
188
189 if (info_packet->valid) {
190 dce110_update_generic_info_packet(
191 enc110,
192 packet_index,
193 info_packet);
194
195
196
197 cont = 1;
198
199 send = 1;
200
201 line = 2;
202 } else {
203 cont = 0;
204 send = 0;
205 line = 0;
206 }
207
208
209 switch (packet_index) {
210 case 0:
211 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
212 HDMI_GENERIC0_CONT, cont,
213 HDMI_GENERIC0_SEND, send,
214 HDMI_GENERIC0_LINE, line);
215 break;
216 case 1:
217 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
218 HDMI_GENERIC1_CONT, cont,
219 HDMI_GENERIC1_SEND, send,
220 HDMI_GENERIC1_LINE, line);
221 break;
222 case 2:
223 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
224 HDMI_GENERIC0_CONT, cont,
225 HDMI_GENERIC0_SEND, send,
226 HDMI_GENERIC0_LINE, line);
227 break;
228 case 3:
229 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
230 HDMI_GENERIC1_CONT, cont,
231 HDMI_GENERIC1_SEND, send,
232 HDMI_GENERIC1_LINE, line);
233 break;
234#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
235 case 4:
236 if (REG(HDMI_GENERIC_PACKET_CONTROL2))
237 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
238 HDMI_GENERIC0_CONT, cont,
239 HDMI_GENERIC0_SEND, send,
240 HDMI_GENERIC0_LINE, line);
241 break;
242 case 5:
243 if (REG(HDMI_GENERIC_PACKET_CONTROL2))
244 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
245 HDMI_GENERIC1_CONT, cont,
246 HDMI_GENERIC1_SEND, send,
247 HDMI_GENERIC1_LINE, line);
248 break;
249 case 6:
250 if (REG(HDMI_GENERIC_PACKET_CONTROL3))
251 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
252 HDMI_GENERIC0_CONT, cont,
253 HDMI_GENERIC0_SEND, send,
254 HDMI_GENERIC0_LINE, line);
255 break;
256 case 7:
257 if (REG(HDMI_GENERIC_PACKET_CONTROL3))
258 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
259 HDMI_GENERIC1_CONT, cont,
260 HDMI_GENERIC1_SEND, send,
261 HDMI_GENERIC1_LINE, line);
262 break;
263#endif
264 default:
265
266 DC_LOG_WARNING(
267 "Invalid HW packet index: %s()\n",
268 __func__);
269 return;
270 }
271}
272
273
274static void dce110_stream_encoder_dp_set_stream_attribute(
275 struct stream_encoder *enc,
276 struct dc_crtc_timing *crtc_timing,
277 enum dc_color_space output_color_space,
278 uint32_t enable_sdp_splitting)
279{
280#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
281 uint32_t h_active_start;
282 uint32_t v_active_start;
283 uint32_t misc0 = 0;
284 uint32_t misc1 = 0;
285 uint32_t h_blank;
286 uint32_t h_back_porch;
287 uint8_t synchronous_clock = 0;
288 uint8_t colorimetry_bpc;
289 uint8_t dynamic_range_rgb = 0;
290 uint8_t dynamic_range_ycbcr = 1;
291#endif
292
293 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
294 struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
295 if (hw_crtc_timing.flags.INTERLACE) {
296
297 hw_crtc_timing.v_total /= 2;
298 hw_crtc_timing.v_border_top /= 2;
299 hw_crtc_timing.v_addressable /= 2;
300 hw_crtc_timing.v_border_bottom /= 2;
301 hw_crtc_timing.v_front_porch /= 2;
302 hw_crtc_timing.v_sync_width /= 2;
303 }
304
305 switch (hw_crtc_timing.pixel_encoding) {
306 case PIXEL_ENCODING_YCBCR422:
307 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
308 DP_PIXEL_ENCODING_TYPE_YCBCR422);
309 break;
310 case PIXEL_ENCODING_YCBCR444:
311 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
312 DP_PIXEL_ENCODING_TYPE_YCBCR444);
313
314 if (hw_crtc_timing.flags.Y_ONLY)
315 if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666)
316
317
318
319 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
320 DP_PIXEL_ENCODING_TYPE_Y_ONLY);
321
322
323
324
325 break;
326 case PIXEL_ENCODING_YCBCR420:
327 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
328 DP_PIXEL_ENCODING_TYPE_YCBCR420);
329 if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
330 REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
331
332#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
333 if (enc110->se_mask->DP_VID_N_MUL)
334 REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
335#endif
336 break;
337 default:
338 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
339 DP_PIXEL_ENCODING_TYPE_RGB444);
340 break;
341 }
342
343#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
344 if (REG(DP_MSA_MISC))
345 misc1 = REG_READ(DP_MSA_MISC);
346#endif
347
348
349
350 switch (hw_crtc_timing.display_color_depth) {
351 case COLOR_DEPTH_666:
352 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
353 0);
354 break;
355 case COLOR_DEPTH_888:
356 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
357 DP_COMPONENT_PIXEL_DEPTH_8BPC);
358 break;
359 case COLOR_DEPTH_101010:
360 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
361 DP_COMPONENT_PIXEL_DEPTH_10BPC);
362
363 break;
364 case COLOR_DEPTH_121212:
365 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
366 DP_COMPONENT_PIXEL_DEPTH_12BPC);
367 break;
368 default:
369 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
370 DP_COMPONENT_PIXEL_DEPTH_6BPC);
371 break;
372 }
373
374
375
376
377#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
378 switch (hw_crtc_timing.display_color_depth) {
379 case COLOR_DEPTH_666:
380 colorimetry_bpc = 0;
381 break;
382 case COLOR_DEPTH_888:
383 colorimetry_bpc = 1;
384 break;
385 case COLOR_DEPTH_101010:
386 colorimetry_bpc = 2;
387 break;
388 case COLOR_DEPTH_121212:
389 colorimetry_bpc = 3;
390 break;
391 default:
392 colorimetry_bpc = 0;
393 break;
394 }
395
396 misc0 = misc0 | synchronous_clock;
397 misc0 = colorimetry_bpc << 5;
398
399 if (REG(DP_MSA_TIMING_PARAM1)) {
400 switch (output_color_space) {
401 case COLOR_SPACE_SRGB:
402 misc0 = misc0 | 0x0;
403 misc1 = misc1 & ~0x80;
404 dynamic_range_rgb = 0;
405 break;
406 case COLOR_SPACE_SRGB_LIMITED:
407 misc0 = misc0 | 0x8;
408 misc1 = misc1 & ~0x80;
409 dynamic_range_rgb = 1;
410 break;
411 case COLOR_SPACE_YCBCR601:
412 case COLOR_SPACE_YCBCR601_LIMITED:
413 misc0 = misc0 | 0x8;
414 misc1 = misc1 & ~0x80;
415 dynamic_range_ycbcr = 0;
416 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
417 misc0 = misc0 | 0x2;
418 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
419 misc0 = misc0 | 0x4;
420 break;
421 case COLOR_SPACE_YCBCR709:
422 case COLOR_SPACE_YCBCR709_LIMITED:
423 case COLOR_SPACE_YCBCR709_BLACK:
424 misc0 = misc0 | 0x18;
425 misc1 = misc1 & ~0x80;
426 dynamic_range_ycbcr = 1;
427 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
428 misc0 = misc0 | 0x2;
429 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
430 misc0 = misc0 | 0x4;
431 break;
432 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
433 dynamic_range_rgb = 1;
434 break;
435 case COLOR_SPACE_2020_RGB_FULLRANGE:
436 case COLOR_SPACE_2020_YCBCR:
437 case COLOR_SPACE_XR_RGB:
438 case COLOR_SPACE_MSREF_SCRGB:
439 case COLOR_SPACE_ADOBERGB:
440 case COLOR_SPACE_DCIP3:
441 case COLOR_SPACE_XV_YCC_709:
442 case COLOR_SPACE_XV_YCC_601:
443 case COLOR_SPACE_DISPLAYNATIVE:
444 case COLOR_SPACE_DOLBYVISION:
445 case COLOR_SPACE_APPCTRL:
446 case COLOR_SPACE_CUSTOMPOINTS:
447 case COLOR_SPACE_UNKNOWN:
448
449 break;
450 }
451 if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE)
452 REG_UPDATE_2(
453 DP_PIXEL_FORMAT,
454 DP_DYN_RANGE, dynamic_range_rgb,
455 DP_YCBCR_RANGE, dynamic_range_ycbcr);
456
457#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
458 if (REG(DP_MSA_COLORIMETRY))
459 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
460
461 if (REG(DP_MSA_MISC))
462 REG_WRITE(DP_MSA_MISC, misc1);
463
464
465
466
467 if (REG(DP_MSA_TIMING_PARAM1))
468 REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
469 DP_MSA_HTOTAL, hw_crtc_timing.h_total,
470 DP_MSA_VTOTAL, hw_crtc_timing.v_total);
471#endif
472
473
474
475
476
477 h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
478 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
479
480 h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
481 hw_crtc_timing.h_sync_width;
482
483
484 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
485
486
487 v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -
488 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
489 hw_crtc_timing.v_front_porch;
490
491
492#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
493
494 if (REG(DP_MSA_TIMING_PARAM2))
495 REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
496 DP_MSA_HSTART, h_active_start,
497 DP_MSA_VSTART, v_active_start);
498
499 if (REG(DP_MSA_TIMING_PARAM3))
500 REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
501 DP_MSA_HSYNCWIDTH,
502 hw_crtc_timing.h_sync_width,
503 DP_MSA_HSYNCPOLARITY,
504 !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY,
505 DP_MSA_VSYNCWIDTH,
506 hw_crtc_timing.v_sync_width,
507 DP_MSA_VSYNCPOLARITY,
508 !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY);
509
510
511 if (REG(DP_MSA_TIMING_PARAM4))
512 REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
513 DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +
514 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,
515 DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +
516 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);
517#endif
518 }
519#endif
520}
521
522static void dce110_stream_encoder_set_stream_attribute_helper(
523 struct dce110_stream_encoder *enc110,
524 struct dc_crtc_timing *crtc_timing)
525{
526 if (enc110->regs->TMDS_CNTL) {
527 switch (crtc_timing->pixel_encoding) {
528 case PIXEL_ENCODING_YCBCR422:
529 REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1);
530 break;
531 default:
532 REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0);
533 break;
534 }
535 REG_UPDATE(TMDS_CNTL, TMDS_COLOR_FORMAT, 0);
536 } else if (enc110->regs->DIG_FE_CNTL) {
537 switch (crtc_timing->pixel_encoding) {
538 case PIXEL_ENCODING_YCBCR422:
539 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
540 break;
541 default:
542 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
543 break;
544 }
545 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
546 }
547
548}
549
550
551static void dce110_stream_encoder_hdmi_set_stream_attribute(
552 struct stream_encoder *enc,
553 struct dc_crtc_timing *crtc_timing,
554 int actual_pix_clk_khz,
555 bool enable_audio)
556{
557 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
558 struct bp_encoder_control cntl = {0};
559
560 cntl.action = ENCODER_CONTROL_SETUP;
561 cntl.engine_id = enc110->base.id;
562 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
563 cntl.enable_dp_audio = enable_audio;
564 cntl.pixel_clock = actual_pix_clk_khz;
565 cntl.lanes_number = LANE_COUNT_FOUR;
566
567 if (enc110->base.bp->funcs->encoder_control(
568 enc110->base.bp, &cntl) != BP_RESULT_OK)
569 return;
570
571 dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
572
573
574 if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
575 REG_UPDATE_3(HDMI_CONTROL,
576 HDMI_PACKET_GEN_VERSION, 1,
577 HDMI_KEEPOUT_MODE, 1,
578 HDMI_DEEP_COLOR_ENABLE, 0);
579 } else if (enc110->regs->DIG_FE_CNTL) {
580 REG_UPDATE_5(HDMI_CONTROL,
581 HDMI_PACKET_GEN_VERSION, 1,
582 HDMI_KEEPOUT_MODE, 1,
583 HDMI_DEEP_COLOR_ENABLE, 0,
584 HDMI_DATA_SCRAMBLE_EN, 0,
585 HDMI_CLOCK_CHANNEL_RATE, 0);
586 }
587
588 switch (crtc_timing->display_color_depth) {
589 case COLOR_DEPTH_888:
590 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
591 break;
592 case COLOR_DEPTH_101010:
593 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
594 REG_UPDATE_2(HDMI_CONTROL,
595 HDMI_DEEP_COLOR_DEPTH, 1,
596 HDMI_DEEP_COLOR_ENABLE, 0);
597 } else {
598 REG_UPDATE_2(HDMI_CONTROL,
599 HDMI_DEEP_COLOR_DEPTH, 1,
600 HDMI_DEEP_COLOR_ENABLE, 1);
601 }
602 break;
603 case COLOR_DEPTH_121212:
604 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
605 REG_UPDATE_2(HDMI_CONTROL,
606 HDMI_DEEP_COLOR_DEPTH, 2,
607 HDMI_DEEP_COLOR_ENABLE, 0);
608 } else {
609 REG_UPDATE_2(HDMI_CONTROL,
610 HDMI_DEEP_COLOR_DEPTH, 2,
611 HDMI_DEEP_COLOR_ENABLE, 1);
612 }
613 break;
614 case COLOR_DEPTH_161616:
615 REG_UPDATE_2(HDMI_CONTROL,
616 HDMI_DEEP_COLOR_DEPTH, 3,
617 HDMI_DEEP_COLOR_ENABLE, 1);
618 break;
619 default:
620 break;
621 }
622
623 if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
624 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
625
626
627
628
629 REG_UPDATE_2(HDMI_CONTROL,
630 HDMI_DATA_SCRAMBLE_EN, 1,
631 HDMI_CLOCK_CHANNEL_RATE, 1);
632 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
633
634
635
636
637
638
639
640
641 REG_UPDATE_2(HDMI_CONTROL,
642 HDMI_DATA_SCRAMBLE_EN, 1,
643 HDMI_CLOCK_CHANNEL_RATE, 0);
644 }
645 }
646
647 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
648 HDMI_GC_CONT, 1,
649 HDMI_GC_SEND, 1,
650 HDMI_NULL_SEND, 1);
651
652
653 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
654
655 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
656
657 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
658 VBI_LINE_0 + 2);
659
660 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
661
662}
663
664
665static void dce110_stream_encoder_dvi_set_stream_attribute(
666 struct stream_encoder *enc,
667 struct dc_crtc_timing *crtc_timing,
668 bool is_dual_link)
669{
670 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
671 struct bp_encoder_control cntl = {0};
672
673 cntl.action = ENCODER_CONTROL_SETUP;
674 cntl.engine_id = enc110->base.id;
675 cntl.signal = is_dual_link ?
676 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
677 cntl.enable_dp_audio = false;
678 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
679 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
680
681 if (enc110->base.bp->funcs->encoder_control(
682 enc110->base.bp, &cntl) != BP_RESULT_OK)
683 return;
684
685 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
686 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
687 dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
688}
689
690
691static void dce110_stream_encoder_lvds_set_stream_attribute(
692 struct stream_encoder *enc,
693 struct dc_crtc_timing *crtc_timing)
694{
695 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
696 struct bp_encoder_control cntl = {0};
697
698 cntl.action = ENCODER_CONTROL_SETUP;
699 cntl.engine_id = enc110->base.id;
700 cntl.signal = SIGNAL_TYPE_LVDS;
701 cntl.enable_dp_audio = false;
702 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
703 cntl.lanes_number = LANE_COUNT_FOUR;
704
705 if (enc110->base.bp->funcs->encoder_control(
706 enc110->base.bp, &cntl) != BP_RESULT_OK)
707 return;
708
709 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
710}
711
712static void dce110_stream_encoder_set_mst_bandwidth(
713 struct stream_encoder *enc,
714 struct fixed31_32 avg_time_slots_per_mtp)
715{
716 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
717 uint32_t x = dc_fixpt_floor(
718 avg_time_slots_per_mtp);
719 uint32_t y = dc_fixpt_ceil(
720 dc_fixpt_shl(
721 dc_fixpt_sub_int(
722 avg_time_slots_per_mtp,
723 x),
724 26));
725
726 {
727 REG_SET_2(DP_MSE_RATE_CNTL, 0,
728 DP_MSE_RATE_X, x,
729 DP_MSE_RATE_Y, y);
730 }
731
732
733
734
735 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
736 0,
737 10, DP_MST_UPDATE_MAX_RETRY);
738}
739
740static void dce110_stream_encoder_update_hdmi_info_packets(
741 struct stream_encoder *enc,
742 const struct encoder_info_frame *info_frame)
743{
744 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
745
746 if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
747 enc110->se_mask->HDMI_AVI_INFO_SEND) {
748
749 if (info_frame->avi.valid) {
750 const uint32_t *content =
751 (const uint32_t *) &info_frame->avi.sb[0];
752
753 if (REG(AFMT_CNTL))
754 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
755
756 REG_WRITE(AFMT_AVI_INFO0, content[0]);
757
758 REG_WRITE(AFMT_AVI_INFO1, content[1]);
759
760 REG_WRITE(AFMT_AVI_INFO2, content[2]);
761
762 REG_WRITE(AFMT_AVI_INFO3, content[3]);
763
764 REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION,
765 info_frame->avi.hb1);
766
767 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
768 HDMI_AVI_INFO_SEND, 1,
769 HDMI_AVI_INFO_CONT, 1);
770
771 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE,
772 VBI_LINE_0 + 2);
773
774 } else {
775 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
776 HDMI_AVI_INFO_SEND, 0,
777 HDMI_AVI_INFO_CONT, 0);
778 }
779 }
780
781 if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
782 enc110->se_mask->HDMI_AVI_INFO_SEND) {
783 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor);
784 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut);
785 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd);
786 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd);
787 }
788
789#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
790 if (enc110->se_mask->HDMI_DB_DISABLE) {
791
792 if (REG(HDMI_DB_CONTROL))
793 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
794
795 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->avi);
796 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->vendor);
797 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->gamut);
798 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd);
799 dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd);
800 }
801#endif
802}
803
804static void dce110_stream_encoder_stop_hdmi_info_packets(
805 struct stream_encoder *enc)
806{
807 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
808
809
810 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
811 HDMI_GENERIC1_CONT, 0,
812 HDMI_GENERIC1_LINE, 0,
813 HDMI_GENERIC1_SEND, 0,
814 HDMI_GENERIC0_CONT, 0,
815 HDMI_GENERIC0_LINE, 0,
816 HDMI_GENERIC0_SEND, 0);
817
818
819 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
820 HDMI_GENERIC0_CONT, 0,
821 HDMI_GENERIC0_LINE, 0,
822 HDMI_GENERIC0_SEND, 0,
823 HDMI_GENERIC1_CONT, 0,
824 HDMI_GENERIC1_LINE, 0,
825 HDMI_GENERIC1_SEND, 0);
826
827#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
828
829 if (REG(HDMI_GENERIC_PACKET_CONTROL2))
830 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
831 HDMI_GENERIC0_CONT, 0,
832 HDMI_GENERIC0_LINE, 0,
833 HDMI_GENERIC0_SEND, 0,
834 HDMI_GENERIC1_CONT, 0,
835 HDMI_GENERIC1_LINE, 0,
836 HDMI_GENERIC1_SEND, 0);
837
838 if (REG(HDMI_GENERIC_PACKET_CONTROL3))
839 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
840 HDMI_GENERIC0_CONT, 0,
841 HDMI_GENERIC0_LINE, 0,
842 HDMI_GENERIC0_SEND, 0,
843 HDMI_GENERIC1_CONT, 0,
844 HDMI_GENERIC1_LINE, 0,
845 HDMI_GENERIC1_SEND, 0);
846#endif
847}
848
849static void dce110_stream_encoder_update_dp_info_packets(
850 struct stream_encoder *enc,
851 const struct encoder_info_frame *info_frame)
852{
853 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
854 uint32_t value = 0;
855
856 if (info_frame->vsc.valid)
857 dce110_update_generic_info_packet(
858 enc110,
859 0,
860 &info_frame->vsc);
861
862 if (info_frame->spd.valid)
863 dce110_update_generic_info_packet(
864 enc110,
865 2,
866 &info_frame->spd);
867
868 if (info_frame->hdrsmd.valid)
869 dce110_update_generic_info_packet(
870 enc110,
871 3,
872 &info_frame->hdrsmd);
873
874
875
876
877 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
878 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
879 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
880
881
882
883
884
885
886
887
888 value = REG_READ(DP_SEC_CNTL);
889 if (value)
890 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
891}
892
893static void dce110_stream_encoder_stop_dp_info_packets(
894 struct stream_encoder *enc)
895{
896
897 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
898 uint32_t value = 0;
899
900 if (enc110->se_mask->DP_SEC_AVI_ENABLE) {
901 REG_SET_7(DP_SEC_CNTL, 0,
902 DP_SEC_GSP0_ENABLE, 0,
903 DP_SEC_GSP1_ENABLE, 0,
904 DP_SEC_GSP2_ENABLE, 0,
905 DP_SEC_GSP3_ENABLE, 0,
906 DP_SEC_AVI_ENABLE, 0,
907 DP_SEC_MPG_ENABLE, 0,
908 DP_SEC_STREAM_ENABLE, 0);
909 }
910
911
912
913
914 value = REG_READ(DP_SEC_CNTL);
915 if (value)
916 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
917
918}
919
920static void dce110_stream_encoder_dp_blank(
921 struct stream_encoder *enc)
922{
923 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
924 uint32_t reg1 = 0;
925 uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
926
927
928
929
930
931
932
933 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1);
934 if ((reg1 & 0x1) == 0)
935
936 return;
937
938
939 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
940
941
942
943
944 max_retries = DP_BLANK_MAX_RETRY * 150;
945
946
947 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
948
949
950
951
952
953
954 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
955 0,
956 10, max_retries);
957
958
959
960
961
962
963
964 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
965}
966
967
968static void dce110_stream_encoder_dp_unblank(
969 struct stream_encoder *enc,
970 const struct encoder_unblank_param *param)
971{
972 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
973
974 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
975 uint32_t n_vid = 0x8000;
976 uint32_t m_vid;
977
978
979
980
981
982 uint64_t m_vid_l = n_vid;
983
984 m_vid_l *= param->timing.pix_clk_100hz / 10;
985 m_vid_l = div_u64(m_vid_l,
986 param->link_settings.link_rate
987 * LINK_RATE_REF_FREQ_IN_KHZ);
988
989 m_vid = (uint32_t) m_vid_l;
990
991
992
993 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
994
995
996
997
998
999 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
1000
1001 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
1002
1003 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);
1004 }
1005
1006
1007
1008 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
1009
1010
1011
1012 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
1013
1014
1015
1016
1017 udelay(100);
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
1028}
1029
1030static void dce110_stream_encoder_set_avmute(
1031 struct stream_encoder *enc,
1032 bool enable)
1033{
1034 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1035 unsigned int value = enable ? 1 : 0;
1036
1037 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
1038}
1039
1040
1041static void dce110_reset_hdmi_stream_attribute(
1042 struct stream_encoder *enc)
1043{
1044 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1045 if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN)
1046 REG_UPDATE_5(HDMI_CONTROL,
1047 HDMI_PACKET_GEN_VERSION, 1,
1048 HDMI_KEEPOUT_MODE, 1,
1049 HDMI_DEEP_COLOR_ENABLE, 0,
1050 HDMI_DATA_SCRAMBLE_EN, 0,
1051 HDMI_CLOCK_CHANNEL_RATE, 0);
1052 else
1053 REG_UPDATE_3(HDMI_CONTROL,
1054 HDMI_PACKET_GEN_VERSION, 1,
1055 HDMI_KEEPOUT_MODE, 1,
1056 HDMI_DEEP_COLOR_ENABLE, 0);
1057}
1058
1059#define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
1060#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
1061
1062#include "include/audio_types.h"
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
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1085
1086
1087
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1092
1093
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1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
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1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133union audio_cea_channels {
1134 uint8_t all;
1135 struct audio_cea_channels_bits {
1136 uint32_t FL:1;
1137 uint32_t FR:1;
1138 uint32_t LFE:1;
1139 uint32_t FC:1;
1140 uint32_t RL_RC:1;
1141 uint32_t RR:1;
1142 uint32_t RC_RLC_FLC:1;
1143 uint32_t RRC_FRC:1;
1144 } channels;
1145};
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160static const struct audio_clock_info audio_clock_info_table[16] = {
1161 {2517, 4576, 28125, 7007, 31250, 6864, 28125},
1162 {2518, 4576, 28125, 7007, 31250, 6864, 28125},
1163 {2520, 4096, 25200, 6272, 28000, 6144, 25200},
1164 {2700, 4096, 27000, 6272, 30000, 6144, 27000},
1165 {2702, 4096, 27027, 6272, 30030, 6144, 27027},
1166 {2703, 4096, 27027, 6272, 30030, 6144, 27027},
1167 {5400, 4096, 54000, 6272, 60000, 6144, 54000},
1168 {5405, 4096, 54054, 6272, 60060, 6144, 54054},
1169 {7417, 11648, 210937, 17836, 234375, 11648, 140625},
1170 {7425, 4096, 74250, 6272, 82500, 6144, 74250},
1171 {14835, 11648, 421875, 8918, 234375, 5824, 140625},
1172 {14850, 4096, 148500, 6272, 165000, 6144, 148500},
1173 {29670, 5824, 421875, 4459, 234375, 5824, 281250},
1174 {29700, 3072, 222750, 4704, 247500, 5120, 247500},
1175 {59340, 5824, 843750, 8918, 937500, 5824, 562500},
1176 {59400, 3072, 445500, 9408, 990000, 6144, 594000}
1177};
1178
1179static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
1180 {2517, 9152, 84375, 7007, 48875, 9152, 56250},
1181 {2518, 9152, 84375, 7007, 48875, 9152, 56250},
1182 {2520, 4096, 37800, 6272, 42000, 6144, 37800},
1183 {2700, 4096, 40500, 6272, 45000, 6144, 40500},
1184 {2702, 8192, 81081, 6272, 45045, 8192, 54054},
1185 {2703, 8192, 81081, 6272, 45045, 8192, 54054},
1186 {5400, 4096, 81000, 6272, 90000, 6144, 81000},
1187 {5405, 4096, 81081, 6272, 90090, 6144, 81081},
1188 {7417, 11648, 316406, 17836, 351562, 11648, 210937},
1189 {7425, 4096, 111375, 6272, 123750, 6144, 111375},
1190 {14835, 11648, 632812, 17836, 703125, 11648, 421875},
1191 {14850, 4096, 222750, 6272, 247500, 6144, 222750},
1192 {29670, 5824, 632812, 8918, 703125, 5824, 421875},
1193 {29700, 4096, 445500, 4704, 371250, 5120, 371250}
1194};
1195
1196static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
1197 {2517, 4576, 56250, 7007, 62500, 6864, 56250},
1198 {2518, 4576, 56250, 7007, 62500, 6864, 56250},
1199 {2520, 4096, 50400, 6272, 56000, 6144, 50400},
1200 {2700, 4096, 54000, 6272, 60000, 6144, 54000},
1201 {2702, 4096, 54054, 6267, 60060, 8192, 54054},
1202 {2703, 4096, 54054, 6272, 60060, 8192, 54054},
1203 {5400, 4096, 108000, 6272, 120000, 6144, 108000},
1204 {5405, 4096, 108108, 6272, 120120, 6144, 108108},
1205 {7417, 11648, 421875, 17836, 468750, 11648, 281250},
1206 {7425, 4096, 148500, 6272, 165000, 6144, 148500},
1207 {14835, 11648, 843750, 8918, 468750, 11648, 281250},
1208 {14850, 4096, 297000, 6272, 330000, 6144, 297000},
1209 {29670, 5824, 843750, 4459, 468750, 5824, 562500},
1210 {29700, 3072, 445500, 4704, 495000, 5120, 495000}
1211
1212
1213};
1214
1215static union audio_cea_channels speakers_to_channels(
1216 struct audio_speaker_flags speaker_flags)
1217{
1218 union audio_cea_channels cea_channels = {0};
1219
1220
1221 cea_channels.channels.FL = speaker_flags.FL_FR;
1222 cea_channels.channels.FR = speaker_flags.FL_FR;
1223 cea_channels.channels.LFE = speaker_flags.LFE;
1224 cea_channels.channels.FC = speaker_flags.FC;
1225
1226
1227
1228
1229 if (speaker_flags.RL_RR) {
1230 cea_channels.channels.RL_RC = speaker_flags.RL_RR;
1231 cea_channels.channels.RR = speaker_flags.RL_RR;
1232 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
1233 } else {
1234 cea_channels.channels.RL_RC = speaker_flags.RC;
1235 }
1236
1237
1238 if (speaker_flags.FLC_FRC) {
1239 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
1240 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
1241 } else {
1242 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
1243 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
1244 }
1245
1246 return cea_channels;
1247}
1248
1249static uint32_t calc_max_audio_packets_per_line(
1250 const struct audio_crtc_info *crtc_info)
1251{
1252 uint32_t max_packets_per_line;
1253
1254 max_packets_per_line =
1255 crtc_info->h_total - crtc_info->h_active;
1256
1257 if (crtc_info->pixel_repetition)
1258 max_packets_per_line *= crtc_info->pixel_repetition;
1259
1260
1261 max_packets_per_line -= 58;
1262
1263 max_packets_per_line -= 16;
1264
1265 max_packets_per_line /= 32;
1266
1267 return max_packets_per_line;
1268}
1269
1270static void get_audio_clock_info(
1271 enum dc_color_depth color_depth,
1272 uint32_t crtc_pixel_clock_100Hz,
1273 uint32_t actual_pixel_clock_100Hz,
1274 struct audio_clock_info *audio_clock_info)
1275{
1276 const struct audio_clock_info *clock_info;
1277 uint32_t index;
1278 uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100;
1279 uint32_t audio_array_size;
1280
1281 switch (color_depth) {
1282 case COLOR_DEPTH_161616:
1283 clock_info = audio_clock_info_table_48bpc;
1284 audio_array_size = ARRAY_SIZE(
1285 audio_clock_info_table_48bpc);
1286 break;
1287 case COLOR_DEPTH_121212:
1288 clock_info = audio_clock_info_table_36bpc;
1289 audio_array_size = ARRAY_SIZE(
1290 audio_clock_info_table_36bpc);
1291 break;
1292 default:
1293 clock_info = audio_clock_info_table;
1294 audio_array_size = ARRAY_SIZE(
1295 audio_clock_info_table);
1296 break;
1297 }
1298
1299 if (clock_info != NULL) {
1300
1301 for (index = 0; index < audio_array_size; index++) {
1302 if (clock_info[index].pixel_clock_in_10khz >
1303 crtc_pixel_clock_in_10khz)
1304 break;
1305 else if (clock_info[index].pixel_clock_in_10khz ==
1306 crtc_pixel_clock_in_10khz) {
1307
1308 *audio_clock_info = clock_info[index];
1309 return;
1310 }
1311 }
1312 }
1313
1314
1315 if (actual_pixel_clock_100Hz == 0)
1316 actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz;
1317
1318
1319
1320 audio_clock_info->pixel_clock_in_10khz =
1321 actual_pixel_clock_100Hz / 100;
1322 audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10;
1323 audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10;
1324 audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10;
1325
1326 audio_clock_info->n_32khz = 4096;
1327 audio_clock_info->n_44khz = 6272;
1328 audio_clock_info->n_48khz = 6144;
1329}
1330
1331static void dce110_se_audio_setup(
1332 struct stream_encoder *enc,
1333 unsigned int az_inst,
1334 struct audio_info *audio_info)
1335{
1336 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1337
1338 uint32_t speakers = 0;
1339 uint32_t channels = 0;
1340
1341 ASSERT(audio_info);
1342 if (audio_info == NULL)
1343
1344 return;
1345
1346 speakers = audio_info->flags.info.ALLSPEAKERS;
1347 channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
1348
1349
1350 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
1351
1352
1353 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
1354}
1355
1356static void dce110_se_setup_hdmi_audio(
1357 struct stream_encoder *enc,
1358 const struct audio_crtc_info *crtc_info)
1359{
1360 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1361
1362 struct audio_clock_info audio_clock_info = {0};
1363 uint32_t max_packets_per_line;
1364
1365
1366
1367 max_packets_per_line = calc_max_audio_packets_per_line(crtc_info);
1368
1369
1370 REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL,
1371 HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line,
1372 HDMI_AUDIO_DELAY_EN, 1);
1373
1374
1375 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1376
1377
1378 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1379 AFMT_AUDIO_LAYOUT_OVRD, 0,
1380 AFMT_60958_OSF_OVRD, 0);
1381
1382
1383 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
1384 HDMI_ACR_AUTO_SEND, 1,
1385 HDMI_ACR_SOURCE, 0,
1386 HDMI_ACR_AUDIO_PRIORITY, 0);
1387
1388
1389 get_audio_clock_info(crtc_info->color_depth,
1390 crtc_info->requested_pixel_clock_100Hz,
1391 crtc_info->calculated_pixel_clock_100Hz,
1392 &audio_clock_info);
1393 DC_LOG_HW_AUDIO(
1394 "\n%s:Input::requested_pixel_clock_100Hz = %d" \
1395 "calculated_pixel_clock_100Hz = %d \n", __func__, \
1396 crtc_info->requested_pixel_clock_100Hz, \
1397 crtc_info->calculated_pixel_clock_100Hz);
1398
1399
1400 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
1401
1402
1403 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
1404
1405
1406 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
1407
1408
1409 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
1410
1411
1412 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
1413
1414
1415 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
1416
1417
1418
1419
1420
1421
1422
1423
1424 REG_UPDATE_2(AFMT_60958_0,
1425 AFMT_60958_CS_CHANNEL_NUMBER_L, 1,
1426 AFMT_60958_CS_CLOCK_ACCURACY, 0);
1427
1428
1429 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1430
1431
1432
1433 REG_UPDATE_6(AFMT_60958_2,
1434 AFMT_60958_CS_CHANNEL_NUMBER_2, 3,
1435 AFMT_60958_CS_CHANNEL_NUMBER_3, 4,
1436 AFMT_60958_CS_CHANNEL_NUMBER_4, 5,
1437 AFMT_60958_CS_CHANNEL_NUMBER_5, 6,
1438 AFMT_60958_CS_CHANNEL_NUMBER_6, 7,
1439 AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1440}
1441
1442static void dce110_se_setup_dp_audio(
1443 struct stream_encoder *enc)
1444{
1445 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1446
1447
1448
1449
1450 REG_SET(DP_SEC_AUD_N, 0,
1451 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
1452
1453
1454 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
1455 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
1456
1457
1458
1459
1460
1461 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1462
1463
1464
1465 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1466 AFMT_AUDIO_LAYOUT_OVRD, 0,
1467 AFMT_60958_OSF_OVRD, 0);
1468
1469
1470 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1471
1472
1473 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
1474}
1475
1476static void dce110_se_enable_audio_clock(
1477 struct stream_encoder *enc,
1478 bool enable)
1479{
1480 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1481
1482 if (REG(AFMT_CNTL) == 0)
1483 return;
1484
1485 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496}
1497
1498static void dce110_se_enable_dp_audio(
1499 struct stream_encoder *enc)
1500{
1501 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1502
1503
1504 REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1505
1506
1507 REG_UPDATE_2(DP_SEC_CNTL,
1508 DP_SEC_ATP_ENABLE, 1,
1509 DP_SEC_AIP_ENABLE, 1);
1510
1511
1512 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1513}
1514
1515static void dce110_se_disable_dp_audio(
1516 struct stream_encoder *enc)
1517{
1518 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1519 uint32_t value = 0;
1520
1521
1522 REG_UPDATE_5(DP_SEC_CNTL,
1523 DP_SEC_ASP_ENABLE, 0,
1524 DP_SEC_ATP_ENABLE, 0,
1525 DP_SEC_AIP_ENABLE, 0,
1526 DP_SEC_ACM_ENABLE, 0,
1527 DP_SEC_STREAM_ENABLE, 0);
1528
1529
1530
1531 value = REG_READ(DP_SEC_CNTL);
1532 if (value != 0)
1533 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1534
1535}
1536
1537void dce110_se_audio_mute_control(
1538 struct stream_encoder *enc,
1539 bool mute)
1540{
1541 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1542
1543 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
1544}
1545
1546void dce110_se_dp_audio_setup(
1547 struct stream_encoder *enc,
1548 unsigned int az_inst,
1549 struct audio_info *info)
1550{
1551 dce110_se_audio_setup(enc, az_inst, info);
1552}
1553
1554void dce110_se_dp_audio_enable(
1555 struct stream_encoder *enc)
1556{
1557 dce110_se_enable_audio_clock(enc, true);
1558 dce110_se_setup_dp_audio(enc);
1559 dce110_se_enable_dp_audio(enc);
1560}
1561
1562void dce110_se_dp_audio_disable(
1563 struct stream_encoder *enc)
1564{
1565 dce110_se_disable_dp_audio(enc);
1566 dce110_se_enable_audio_clock(enc, false);
1567}
1568
1569void dce110_se_hdmi_audio_setup(
1570 struct stream_encoder *enc,
1571 unsigned int az_inst,
1572 struct audio_info *info,
1573 struct audio_crtc_info *audio_crtc_info)
1574{
1575 dce110_se_enable_audio_clock(enc, true);
1576 dce110_se_setup_hdmi_audio(enc, audio_crtc_info);
1577 dce110_se_audio_setup(enc, az_inst, info);
1578}
1579
1580void dce110_se_hdmi_audio_disable(
1581 struct stream_encoder *enc)
1582{
1583 dce110_se_enable_audio_clock(enc, false);
1584}
1585
1586
1587static void setup_stereo_sync(
1588 struct stream_encoder *enc,
1589 int tg_inst, bool enable)
1590{
1591 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1592 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1593 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
1594}
1595
1596static void dig_connect_to_otg(
1597 struct stream_encoder *enc,
1598 int tg_inst)
1599{
1600 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1601
1602 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
1603}
1604
1605static unsigned int dig_source_otg(
1606 struct stream_encoder *enc)
1607{
1608 uint32_t tg_inst = 0;
1609 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1610
1611 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
1612
1613 return tg_inst;
1614}
1615
1616static const struct stream_encoder_funcs dce110_str_enc_funcs = {
1617 .dp_set_stream_attribute =
1618 dce110_stream_encoder_dp_set_stream_attribute,
1619 .hdmi_set_stream_attribute =
1620 dce110_stream_encoder_hdmi_set_stream_attribute,
1621 .dvi_set_stream_attribute =
1622 dce110_stream_encoder_dvi_set_stream_attribute,
1623 .lvds_set_stream_attribute =
1624 dce110_stream_encoder_lvds_set_stream_attribute,
1625 .set_mst_bandwidth =
1626 dce110_stream_encoder_set_mst_bandwidth,
1627 .update_hdmi_info_packets =
1628 dce110_stream_encoder_update_hdmi_info_packets,
1629 .stop_hdmi_info_packets =
1630 dce110_stream_encoder_stop_hdmi_info_packets,
1631 .update_dp_info_packets =
1632 dce110_stream_encoder_update_dp_info_packets,
1633 .stop_dp_info_packets =
1634 dce110_stream_encoder_stop_dp_info_packets,
1635 .dp_blank =
1636 dce110_stream_encoder_dp_blank,
1637 .dp_unblank =
1638 dce110_stream_encoder_dp_unblank,
1639 .audio_mute_control = dce110_se_audio_mute_control,
1640
1641 .dp_audio_setup = dce110_se_dp_audio_setup,
1642 .dp_audio_enable = dce110_se_dp_audio_enable,
1643 .dp_audio_disable = dce110_se_dp_audio_disable,
1644
1645 .hdmi_audio_setup = dce110_se_hdmi_audio_setup,
1646 .hdmi_audio_disable = dce110_se_hdmi_audio_disable,
1647 .setup_stereo_sync = setup_stereo_sync,
1648 .set_avmute = dce110_stream_encoder_set_avmute,
1649 .dig_connect_to_otg = dig_connect_to_otg,
1650 .hdmi_reset_stream_attribute = dce110_reset_hdmi_stream_attribute,
1651 .dig_source_otg = dig_source_otg,
1652};
1653
1654void dce110_stream_encoder_construct(
1655 struct dce110_stream_encoder *enc110,
1656 struct dc_context *ctx,
1657 struct dc_bios *bp,
1658 enum engine_id eng_id,
1659 const struct dce110_stream_enc_registers *regs,
1660 const struct dce_stream_encoder_shift *se_shift,
1661 const struct dce_stream_encoder_mask *se_mask)
1662{
1663 enc110->base.funcs = &dce110_str_enc_funcs;
1664 enc110->base.ctx = ctx;
1665 enc110->base.id = eng_id;
1666 enc110->base.bp = bp;
1667 enc110->regs = regs;
1668 enc110->se_shift = se_shift;
1669 enc110->se_mask = se_mask;
1670}
1671
