/*
 * Copyright © 2006-2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *      Eric Anholt <eric@anholt.net>
 */

#include <linux/i2c.h>
#include <linux/input.h>
#include <linux/intel-iommu.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/dma-resv.h>
#include <linux/slab.h>
#include <linux/vgaarb.h>

#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_atomic_uapi.h>
#include <drm/drm_dp_helper.h>
#include <drm/drm_edid.h>
#include <drm/drm_fourcc.h>
#include <drm/drm_plane_helper.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_rect.h>
#include <drm/i915_drm.h>

#include "display/intel_crt.h"
#include "display/intel_ddi.h"
#include "display/intel_dp.h"
#include "display/intel_dsi.h"
#include "display/intel_dvo.h"
#include "display/intel_gmbus.h"
#include "display/intel_hdmi.h"
#include "display/intel_lvds.h"
#include "display/intel_sdvo.h"
#include "display/intel_tv.h"
#include "display/intel_vdsc.h"

#include "i915_drv.h"
#include "i915_trace.h"
#include "intel_acpi.h"
#include "intel_atomic.h"
#include "intel_atomic_plane.h"
#include "intel_bw.h"
#include "intel_cdclk.h"
#include "intel_color.h"
#include "intel_display_types.h"
#include "intel_fbc.h"
#include "intel_fbdev.h"
#include "intel_fifo_underrun.h"
#include "intel_frontbuffer.h"
#include "intel_hdcp.h"
#include "intel_hotplug.h"
#include "intel_overlay.h"
#include "intel_pipe_crc.h"
#include "intel_pm.h"
#include "intel_psr.h"
#include "intel_quirks.h"
#include "intel_sideband.h"
#include "intel_sprite.h"
#include "intel_tc.h"

/* Primary plane formats for gen <= 3 */
static const u32 i8xx_primary_formats[] = {
        DRM_FORMAT_C8,
        DRM_FORMAT_RGB565,
        DRM_FORMAT_XRGB1555,
        DRM_FORMAT_XRGB8888,
};

/* Primary plane formats for gen >= 4 */
static const u32 i965_primary_formats[] = {
        DRM_FORMAT_C8,
        DRM_FORMAT_RGB565,
        DRM_FORMAT_XRGB8888,
        DRM_FORMAT_XBGR8888,
        DRM_FORMAT_XRGB2101010,
        DRM_FORMAT_XBGR2101010,
};

static const u64 i9xx_format_modifiers[] = {
        I915_FORMAT_MOD_X_TILED,
        DRM_FORMAT_MOD_LINEAR,
        DRM_FORMAT_MOD_INVALID
};

/* Cursor formats */
static const u32 intel_cursor_formats[] = {
        DRM_FORMAT_ARGB8888,
};

static const u64 cursor_format_modifiers[] = {
        DRM_FORMAT_MOD_LINEAR,
        DRM_FORMAT_MOD_INVALID
};

static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
                                struct intel_crtc_state *pipe_config);
static void ironlake_pch_clock_get(struct intel_crtc *crtc,
                                   struct intel_crtc_state *pipe_config);

static int intel_framebuffer_init(struct intel_framebuffer *ifb,
                                  struct drm_i915_gem_object *obj,
                                  struct drm_mode_fb_cmd2 *mode_cmd);
static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
                                         const struct intel_link_m_n *m_n,
                                         const struct intel_link_m_n *m2_n2);
static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state);
static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state);
static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
static void vlv_prepare_pll(struct intel_crtc *crtc,
                            const struct intel_crtc_state *pipe_config);
static void chv_prepare_pll(struct intel_crtc *crtc,
                            const struct intel_crtc_state *pipe_config);
static void intel_begin_crtc_commit(struct intel_atomic_state *, struct intel_crtc *);
static void intel_finish_crtc_commit(struct intel_atomic_state *, struct intel_crtc *);
static void intel_crtc_init_scalers(struct intel_crtc *crtc,
                                    struct intel_crtc_state *crtc_state);
static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state);
static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
static void intel_modeset_setup_hw_state(struct drm_device *dev,
                                         struct drm_modeset_acquire_ctx *ctx);
static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);

struct intel_limit {
        struct {
                int min, max;
        } dot, vco, n, m, m1, m2, p, p1;

        struct {
                int dot_limit;
                int p2_slow, p2_fast;
        } p2;
};

/* returns HPLL frequency in kHz */
int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
{
        int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };

        /* Obtain SKU information */
        hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
                CCK_FUSE_HPLL_FREQ_MASK;

        return vco_freq[hpll_freq] * 1000;
}

int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
                      const char *name, u32 reg, int ref_freq)
{
        u32 val;
        int divider;

        val = vlv_cck_read(dev_priv, reg);
        divider = val & CCK_FREQUENCY_VALUES;

        WARN((val & CCK_FREQUENCY_STATUS) !=
             (divider << CCK_FREQUENCY_STATUS_SHIFT),
             "%s change in progress\n", name);

        return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
}

int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
                           const char *name, u32 reg)
{
        int hpll;

        vlv_cck_get(dev_priv);

        if (dev_priv->hpll_freq == 0)
                dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);

        hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);

        vlv_cck_put(dev_priv);

        return hpll;
}

static void intel_update_czclk(struct drm_i915_private *dev_priv)
{
        if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
                return;

        dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
                                                      CCK_CZ_CLOCK_CONTROL);

        DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
}

static inline u32 /* units of 100MHz */
intel_fdi_link_freq(struct drm_i915_private *dev_priv,
                    const struct intel_crtc_state *pipe_config)
{
        if (HAS_DDI(dev_priv))
                return pipe_config->port_clock; /* SPLL */
        else
                return dev_priv->fdi_pll_freq;
}

static const struct intel_limit intel_limits_i8xx_dac = {
        .dot = { .min = 25000, .max = 350000 },
        .vco = { .min = 908000, .max = 1512000 },
        .n = { .min = 2, .max = 16 },
        .m = { .min = 96, .max = 140 },
        .m1 = { .min = 18, .max = 26 },
        .m2 = { .min = 6, .max = 16 },
        .p = { .min = 4, .max = 128 },
        .p1 = { .min = 2, .max = 33 },
        .p2 = { .dot_limit = 165000,
                .p2_slow = 4, .p2_fast = 2 },
};

static const struct intel_limit intel_limits_i8xx_dvo = {
        .dot = { .min = 25000, .max = 350000 },
        .vco = { .min = 908000, .max = 1512000 },
        .n = { .min = 2, .max = 16 },
        .m = { .min = 96, .max = 140 },
        .m1 = { .min = 18, .max = 26 },
        .m2 = { .min = 6, .max = 16 },
        .p = { .min = 4, .max = 128 },
        .p1 = { .min = 2, .max = 33 },
        .p2 = { .dot_limit = 165000,
                .p2_slow = 4, .p2_fast = 4 },
};

static const struct intel_limit intel_limits_i8xx_lvds = {
        .dot = { .min = 25000, .max = 350000 },
        .vco = { .min = 908000, .max = 1512000 },
        .n = { .min = 2, .max = 16 },
        .m = { .min = 96, .max = 140 },
        .m1 = { .min = 18, .max = 26 },
        .m2 = { .min = 6, .max = 16 },
        .p = { .min = 4, .max = 128 },
        .p1 = { .min = 1, .max = 6 },
        .p2 = { .dot_limit = 165000,
                .p2_slow = 14, .p2_fast = 7 },
};

static const struct intel_limit intel_limits_i9xx_sdvo = {
        .dot = { .min = 20000, .max = 400000 },
        .vco = { .min = 1400000, .max = 2800000 },
        .n = { .min = 1, .max = 6 },
        .m = { .min = 70, .max = 120 },
        .m1 = { .min = 8, .max = 18 },
        .m2 = { .min = 3, .max = 7 },
        .p = { .min = 5, .max = 80 },
        .p1 = { .min = 1, .max = 8 },
        .p2 = { .dot_limit = 200000,
                .p2_slow = 10, .p2_fast = 5 },
};

static const struct intel_limit intel_limits_i9xx_lvds = {
        .dot = { .min = 20000, .max = 400000 },
        .vco = { .min = 1400000, .max = 2800000 },
        .n = { .min = 1, .max = 6 },
        .m = { .min = 70, .max = 120 },
        .m1 = { .min = 8, .max = 18 },
        .m2 = { .min = 3, .max = 7 },
        .p = { .min = 7, .max = 98 },
        .p1 = { .min = 1, .max = 8 },
        .p2 = { .dot_limit = 112000,
                .p2_slow = 14, .p2_fast = 7 },
};


static const struct intel_limit intel_limits_g4x_sdvo = {
        .dot = { .min = 25000, .max = 270000 },
        .vco = { .min = 1750000, .max = 3500000},
        .n = { .min = 1, .max = 4 },
        .m = { .min = 104, .max = 138 },
        .m1 = { .min = 17, .max = 23 },
        .m2 = { .min = 5, .max = 11 },
        .p = { .min = 10, .max = 30 },
        .p1 = { .min = 1, .max = 3},
        .p2 = { .dot_limit = 270000,
                .p2_slow = 10,
                .p2_fast = 10
        },
};

static const struct intel_limit intel_limits_g4x_hdmi = {
        .dot = { .min = 22000, .max = 400000 },
        .vco = { .min = 1750000, .max = 3500000},
        .n = { .min = 1, .max = 4 },
        .m = { .min = 104, .max = 138 },
        .m1 = { .min = 16, .max = 23 },
        .m2 = { .min = 5, .max = 11 },
        .p = { .min = 5, .max = 80 },
        .p1 = { .min = 1, .max = 8},
        .p2 = { .dot_limit = 165000,
                .p2_slow = 10, .p2_fast = 5 },
};

static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
        .dot = { .min = 20000, .max = 115000 },
        .vco = { .min = 1750000, .max = 3500000 },
        .n = { .min = 1, .max = 3 },
        .m = { .min = 104, .max = 138 },
        .m1 = { .min = 17, .max = 23 },
        .m2 = { .min = 5, .max = 11 },
        .p = { .min = 28, .max = 112 },
        .p1 = { .min = 2, .max = 8 },
        .p2 = { .dot_limit = 0,
                .p2_slow = 14, .p2_fast = 14
        },
};

static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
        .dot = { .min = 80000, .max = 224000 },
        .vco = { .min = 1750000, .max = 3500000 },
        .n = { .min = 1, .max = 3 },
        .m = { .min = 104, .max = 138 },
        .m1 = { .min = 17, .max = 23 },
        .m2 = { .min = 5, .max = 11 },
        .p = { .min = 14, .max = 42 },
        .p1 = { .min = 2, .max = 6 },
        .p2 = { .dot_limit = 0,
                .p2_slow = 7, .p2_fast = 7
        },
};

static const struct intel_limit intel_limits_pineview_sdvo = {
        .dot = { .min = 20000, .max = 400000},
        .vco = { .min = 1700000, .max = 3500000 },
        /* Pineview's Ncounter is a ring counter */
        .n = { .min = 3, .max = 6 },
        .m = { .min = 2, .max = 256 },
        /* Pineview only has one combined m divider, which we treat as m2. */
        .m1 = { .min = 0, .max = 0 },
        .m2 = { .min = 0, .max = 254 },
        .p = { .min = 5, .max = 80 },
        .p1 = { .min = 1, .max = 8 },
        .p2 = { .dot_limit = 200000,
                .p2_slow = 10, .p2_fast = 5 },
};

static const struct intel_limit intel_limits_pineview_lvds = {
        .dot = { .min = 20000, .max = 400000 },
        .vco = { .min = 1700000, .max = 3500000 },
        .n = { .min = 3, .max = 6 },
        .m = { .min = 2, .max = 256 },
        .m1 = { .min = 0, .max = 0 },
        .m2 = { .min = 0, .max = 254 },
        .p = { .min = 7, .max = 112 },
        .p1 = { .min = 1, .max = 8 },
        .p2 = { .dot_limit = 112000,
                .p2_slow = 14, .p2_fast = 14 },
};

/* Ironlake / Sandybridge
 *
 * We calculate clock using (register_value + 2) for N/M1/M2, so here
 * the range value for them is (actual_value - 2).
 */
static const struct intel_limit intel_limits_ironlake_dac = {
        .dot = { .min = 25000, .max = 350000 },
        .vco = { .min = 1760000, .max = 3510000 },
        .n = { .min = 1, .max = 5 },
        .m = { .min = 79, .max = 127 },
        .m1 = { .min = 12, .max = 22 },
        .m2 = { .min = 5, .max = 9 },
        .p = { .min = 5, .max = 80 },
        .p1 = { .min = 1, .max = 8 },
        .p2 = { .dot_limit = 225000,
                .p2_slow = 10, .p2_fast = 5 },
};

static const struct intel_limit intel_limits_ironlake_single_lvds = {
        .dot = { .min = 25000, .max = 350000 },
        .vco = { .min = 1760000, .max = 3510000 },
        .n = { .min = 1, .max = 3 },
        .m = { .min = 79, .max = 118 },
        .m1 = { .min = 12, .max = 22 },
        .m2 = { .min = 5, .max = 9 },
        .p = { .min = 28, .max = 112 },
        .p1 = { .min = 2, .max = 8 },
        .p2 = { .dot_limit = 225000,
                .p2_slow = 14, .p2_fast = 14 },
};

static const struct intel_limit intel_limits_ironlake_dual_lvds = {
        .dot = { .min = 25000, .max = 350000 },
        .vco = { .min = 1760000, .max = 3510000 },
        .n = { .min = 1, .max = 3 },
        .m = { .min = 79, .max = 127 },
        .m1 = { .min = 12, .max = 22 },
        .m2 = { .min = 5, .max = 9 },
        .p = { .min = 14, .max = 56 },
        .p1 = { .min = 2, .max = 8 },
        .p2 = { .dot_limit = 225000,
                .p2_slow = 7, .p2_fast = 7 },
};

/* LVDS 100mhz refclk limits. */
static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
        .dot = { .min = 25000, .max = 350000 },
        .vco = { .min = 1760000, .max = 3510000 },
        .n = { .min = 1, .max = 2 },
        .m = { .min = 79, .max = 126 },
        .m1 = { .min = 12, .max = 22 },
        .m2 = { .min = 5, .max = 9 },
        .p = { .min = 28, .max = 112 },
        .p1 = { .min = 2, .max = 8 },
        .p2 = { .dot_limit = 225000,
                .p2_slow = 14, .p2_fast = 14 },
};

static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
        .dot = { .min = 25000, .max = 350000 },
        .vco = { .min = 1760000, .max = 3510000 },
        .n = { .min = 1, .max = 3 },
        .m = { .min = 79, .max = 126 },
        .m1 = { .min = 12, .max = 22 },
        .m2 = { .min = 5, .max = 9 },
        .p = { .min = 14, .max = 42 },
        .p1 = { .min = 2, .max = 6 },
        .p2 = { .dot_limit = 225000,
                .p2_slow = 7, .p2_fast = 7 },
};

static const struct intel_limit intel_limits_vlv = {
         /*
          * These are the data rate limits (measured in fast clocks)
          * since those are the strictest limits we have. The fast
          * clock and actual rate limits are more relaxed, so checking
          * them would make no difference.
          */
        .dot = { .min = 25000 * 5, .max = 270000 * 5 },
        .vco = { .min = 4000000, .max = 6000000 },
        .n = { .min = 1, .max = 7 },
        .m1 = { .min = 2, .max = 3 },
        .m2 = { .min = 11, .max = 156 },
        .p1 = { .min = 2, .max = 3 },
        .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
};

static const struct intel_limit intel_limits_chv = {
        /*
         * These are the data rate limits (measured in fast clocks)
         * since those are the strictest limits we have.  The fast
         * clock and actual rate limits are more relaxed, so checking
         * them would make no difference.
         */
        .dot = { .min = 25000 * 5, .max = 540000 * 5},
        .vco = { .min = 4800000, .max = 6480000 },
        .n = { .min = 1, .max = 1 },
        .m1 = { .min = 2, .max = 2 },
        .m2 = { .min = 24 << 22, .max = 175 << 22 },
        .p1 = { .min = 2, .max = 4 },
        .p2 = { .p2_slow = 1, .p2_fast = 14 },
};

static const struct intel_limit intel_limits_bxt = {
        /* FIXME: find real dot limits */
        .dot = { .min = 0, .max = INT_MAX },
        .vco = { .min = 4800000, .max = 6700000 },
        .n = { .min = 1, .max = 1 },
        .m1 = { .min = 2, .max = 2 },
        /* FIXME: find real m2 limits */
        .m2 = { .min = 2 << 22, .max = 255 << 22 },
        .p1 = { .min = 2, .max = 4 },
        .p2 = { .p2_slow = 1, .p2_fast = 20 },
};

/* WA Display #0827: Gen9:all */
static void
skl_wa_827(struct drm_i915_private *dev_priv, int pipe, bool enable)
{
        if (enable)
                I915_WRITE(CLKGATE_DIS_PSL(pipe),
                           I915_READ(CLKGATE_DIS_PSL(pipe)) |
                           DUPS1_GATING_DIS | DUPS2_GATING_DIS);
        else
                I915_WRITE(CLKGATE_DIS_PSL(pipe),
                           I915_READ(CLKGATE_DIS_PSL(pipe)) &
                           ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
}

/* Wa_2006604312:icl */
static void
icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
                       bool enable)
{
        if (enable)
                I915_WRITE(CLKGATE_DIS_PSL(pipe),
                           I915_READ(CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
        else
                I915_WRITE(CLKGATE_DIS_PSL(pipe),
                           I915_READ(CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
}

static bool
needs_modeset(const struct intel_crtc_state *state)
{
        return drm_atomic_crtc_needs_modeset(&state->base);
}

/*
 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 * The helpers' return value is the rate of the clock that is fed to the
 * display engine's pipe which can be the above fast dot clock rate or a
 * divided-down version of it.
 */
/* m1 is reserved as 0 in Pineview, n is a ring counter */
static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
{
        clock->m = clock->m2 + 2;
        clock->p = clock->p1 * clock->p2;
        if (WARN_ON(clock->n == 0 || clock->p == 0))
                return 0;
        clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
        clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);

        return clock->dot;
}

static u32 i9xx_dpll_compute_m(struct dpll *dpll)
{
        return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
}

static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
{
        clock->m = i9xx_dpll_compute_m(clock);
        clock->p = clock->p1 * clock->p2;
        if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
                return 0;
        clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
        clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);

        return clock->dot;
}

static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
{
        clock->m = clock->m1 * clock->m2;
        clock->p = clock->p1 * clock->p2;
        if (WARN_ON(clock->n == 0 || clock->p == 0))
                return 0;
        clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
        clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);

        return clock->dot / 5;
}

int chv_calc_dpll_params(int refclk, struct dpll *clock)
{
        clock->m = clock->m1 * clock->m2;
        clock->p = clock->p1 * clock->p2;
        if (WARN_ON(clock->n == 0 || clock->p == 0))
                return 0;
        clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
                                           clock->n << 22);
        clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);

        return clock->dot / 5;
}

#define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)

/*
 * Returns whether the given set of divisors are valid for a given refclk with
 * the given connectors.
 */
static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
                               const struct intel_limit *limit,
                               const struct dpll *clock)
{
        if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
                INTELPllInvalid("n out of range\n");
        if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
                INTELPllInvalid("p1 out of range\n");
        if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
                INTELPllInvalid("m2 out of range\n");
        if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
                INTELPllInvalid("m1 out of range\n");

        if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
            !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
                if (clock->m1 <= clock->m2)
                        INTELPllInvalid("m1 <= m2\n");

        if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
            !IS_GEN9_LP(dev_priv)) {
                if (clock->p < limit->p.min || limit->p.max < clock->p)
                        INTELPllInvalid("p out of range\n");
                if (clock->m < limit->m.min || limit->m.max < clock->m)
                        INTELPllInvalid("m out of range\n");
        }

        if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
                INTELPllInvalid("vco out of range\n");
        /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
         * connector, etc., rather than just a single range.
         */
        if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
                INTELPllInvalid("dot out of range\n");

        return true;
}

static int
i9xx_select_p2_div(const struct intel_limit *limit,
                   const struct intel_crtc_state *crtc_state,
                   int target)
{
        struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);

        if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
                /*
                 * For LVDS just rely on its current settings for dual-channel.
                 * We haven't figured out how to reliably set up different
                 * single/dual channel state, if we even can.
                 */
                if (intel_is_dual_link_lvds(dev_priv))
                        return limit->p2.p2_fast;
                else
                        return limit->p2.p2_slow;
        } else {
                if (target < limit->p2.dot_limit)
                        return limit->p2.p2_slow;
                else
                        return limit->p2.p2_fast;
        }
}

/*
 * Returns a set of divisors for the desired target clock with the given
 * refclk, or FALSE.  The returned values represent the clock equation:
 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 *
 * Target and reference clocks are specified in kHz.
 *
 * If match_clock is provided, then best_clock P divider must match the P
 * divider from @match_clock used for LVDS downclocking.
 */
static bool
i9xx_find_best_dpll(const struct intel_limit *limit,
                    struct intel_crtc_state *crtc_state,
                    int target, int refclk, struct dpll *match_clock,
                    struct dpll *best_clock)
{
        struct drm_device *dev = crtc_state->base.crtc->dev;
        struct dpll clock;
        int err = target;

        memset(best_clock, 0, sizeof(*best_clock));

        clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);

        for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
             clock.m1++) {
                for (clock.m2 = limit->m2.min;
                     clock.m2 <= limit->m2.max; clock.m2++) {
                        if (clock.m2 >= clock.m1)
                                break;
                        for (clock.n = limit->n.min;
                             clock.n <= limit->n.max; clock.n++) {
                                for (clock.p1 = limit->p1.min;
                                        clock.p1 <= limit->p1.max; clock.p1++) {
                                        int this_err;

                                        i9xx_calc_dpll_params(refclk, &clock);
                                        if (!intel_PLL_is_valid(to_i915(dev),
                                                                limit,
                                                                &clock))
                                                continue;
                                        if (match_clock &&
                                            clock.p != match_clock->p)
                                                continue;

                                        this_err = abs(clock.dot - target);
                                        if (this_err < err) {
                                                *best_clock = clock;
                                                err = this_err;
                                        }
                                }
                        }
                }
        }

        return (err != target);
}

/*
 * Returns a set of divisors for the desired target clock with the given
 * refclk, or FALSE.  The returned values represent the clock equation:
 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 *
 * Target and reference clocks are specified in kHz.
 *
 * If match_clock is provided, then best_clock P divider must match the P
 * divider from @match_clock used for LVDS downclocking.
 */
static bool
pnv_find_best_dpll(const struct intel_limit *limit,
                   struct intel_crtc_state *crtc_state,
                   int target, int refclk, struct dpll *match_clock,
                   struct dpll *best_clock)
{
        struct drm_device *dev = crtc_state->base.crtc->dev;
        struct dpll clock;
        int err = target;

        memset(best_clock, 0, sizeof(*best_clock));

        clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);

        for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
             clock.m1++) {
                for (clock.m2 = limit->m2.min;
                     clock.m2 <= limit->m2.max; clock.m2++) {
                        for (clock.n = limit->n.min;
                             clock.n <= limit->n.max; clock.n++) {
                                for (clock.p1 = limit->p1.min;
                                        clock.p1 <= limit->p1.max; clock.p1++) {
                                        int this_err;

                                        pnv_calc_dpll_params(refclk, &clock);
                                        if (!intel_PLL_is_valid(to_i915(dev),
                                                                limit,
                                                                &clock))
                                                continue;
                                        if (match_clock &&
                                            clock.p != match_clock->p)
                                                continue;

                                        this_err = abs(clock.dot - target);
                                        if (this_err < err) {
                                                *best_clock = clock;
                                                err = this_err;
                                        }
                                }
                        }
                }
        }

        return (err != target);
}

/*
 * Returns a set of divisors for the desired target clock with the given
 * refclk, or FALSE.  The returned values represent the clock equation:
 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 *
 * Target and reference clocks are specified in kHz.
 *
 * If match_clock is provided, then best_clock P divider must match the P
 * divider from @match_clock used for LVDS downclocking.
 */
static bool
g4x_find_best_dpll(const struct intel_limit *limit,
                   struct intel_crtc_state *crtc_state,
                   int target, int refclk, struct dpll *match_clock,
                   struct dpll *best_clock)
{
        struct drm_device *dev = crtc_state->base.crtc->dev;
        struct dpll clock;
        int max_n;
        bool found = false;
        /* approximately equals target * 0.00585 */
        int err_most = (target >> 8) + (target >> 9);

        memset(best_clock, 0, sizeof(*best_clock));

        clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);

        max_n = limit->n.max;
        /* based on hardware requirement, prefer smaller n to precision */
        for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
                /* based on hardware requirement, prefere larger m1,m2 */
                for (clock.m1 = limit->m1.max;
                     clock.m1 >= limit->m1.min; clock.m1--) {
                        for (clock.m2 = limit->m2.max;
                             clock.m2 >= limit->m2.min; clock.m2--) {
                                for (clock.p1 = limit->p1.max;
                                     clock.p1 >= limit->p1.min; clock.p1--) {
                                        int this_err;

                                        i9xx_calc_dpll_params(refclk, &clock);
                                        if (!intel_PLL_is_valid(to_i915(dev),
                                                                limit,
                                                                &clock))
                                                continue;

                                        this_err = abs(clock.dot - target);
                                        if (this_err < err_most) {
                                                *best_clock = clock;
                                                err_most = this_err;
                                                max_n = clock.n;
                                                found = true;
                                        }
                                }
                        }
                }
        }
        return found;
}

/*
 * Check if the calculated PLL configuration is more optimal compared to the
 * best configuration and error found so far. Return the calculated error.
 */
static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
                               const struct dpll *calculated_clock,
                               const struct dpll *best_clock,
                               unsigned int best_error_ppm,
                               unsigned int *error_ppm)
{
        /*
         * For CHV ignore the error and consider only the P value.
         * Prefer a bigger P value based on HW requirements.
         */
        if (IS_CHERRYVIEW(to_i915(dev))) {
                *error_ppm = 0;

                return calculated_clock->p > best_clock->p;
        }

        if (WARN_ON_ONCE(!target_freq))
                return false;

        *error_ppm = div_u64(1000000ULL *
                                abs(target_freq - calculated_clock->dot),
                             target_freq);
        /*
         * Prefer a better P value over a better (smaller) error if the error
         * is small. Ensure this preference for future configurations too by
         * setting the error to 0.
         */
        if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
                *error_ppm = 0;

                return true;
        }

        return *error_ppm + 10 < best_error_ppm;
}

/*
 * Returns a set of divisors for the desired target clock with the given
 * refclk, or FALSE.  The returned values represent the clock equation:
 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 */
static bool
vlv_find_best_dpll(const struct intel_limit *limit,
                   struct intel_crtc_state *crtc_state,
                   int target, int refclk, struct dpll *match_clock,
                   struct dpll *best_clock)
{
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
        struct drm_device *dev = crtc->base.dev;
        struct dpll clock;
        unsigned int bestppm = 1000000;
        /* min update 19.2 MHz */
        int max_n = min(limit->n.max, refclk / 19200);
        bool found = false;

        target *= 5; /* fast clock */

        memset(best_clock, 0, sizeof(*best_clock));

        /* based on hardware requirement, prefer smaller n to precision */
        for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
                for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
                        for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
                             clock.p2 -= clock.p2 > 10 ? 2 : 1) {
                                clock.p = clock.p1 * clock.p2;
                                /* based on hardware requirement, prefer bigger m1,m2 values */
                                for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
                                        unsigned int ppm;

                                        clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
                                                                     refclk * clock.m1);

                                        vlv_calc_dpll_params(refclk, &clock);

                                        if (!intel_PLL_is_valid(to_i915(dev),
                                                                limit,
                                                                &clock))
                                                continue;

                                        if (!vlv_PLL_is_optimal(dev, target,
                                                                &clock,
                                                                best_clock,
                                                                bestppm, &ppm))
                                                continue;

                                        *best_clock = clock;
                                        bestppm = ppm;
                                        found = true;
                                }
                        }
                }
        }

        return found;
}

/*
 * Returns a set of divisors for the desired target clock with the given
 * refclk, or FALSE.  The returned values represent the clock equation:
 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 */
static bool
chv_find_best_dpll(const struct intel_limit *limit,
                   struct intel_crtc_state *crtc_state,
                   int target, int refclk, struct dpll *match_clock,
                   struct dpll *best_clock)
{
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
        struct drm_device *dev = crtc->base.dev;
        unsigned int best_error_ppm;
        struct dpll clock;
        u64 m2;
        int found = false;

        memset(best_clock, 0, sizeof(*best_clock));
        best_error_ppm = 1000000;

        /*
         * Based on hardware doc, the n always set to 1, and m1 always
         * set to 2.  If requires to support 200Mhz refclk, we need to
         * revisit this because n may not 1 anymore.
         */
        clock.n = 1, clock.m1 = 2;
        target *= 5;    /* fast clock */

        for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
                for (clock.p2 = limit->p2.p2_fast;
                                clock.p2 >= limit->p2.p2_slow;
                                clock.p2 -= clock.p2 > 10 ? 2 : 1) {
                        unsigned int error_ppm;

                        clock.p = clock.p1 * clock.p2;

                        m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
                                                   refclk * clock.m1);

                        if (m2 > INT_MAX/clock.m1)
                                continue;

                        clock.m2 = m2;

                        chv_calc_dpll_params(refclk, &clock);

                        if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
                                continue;

                        if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
                                                best_error_ppm, &error_ppm))
                                continue;

                        *best_clock = clock;
                        best_error_ppm = error_ppm;
                        found = true;
                }
        }

        return found;
}

bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
                        struct dpll *best_clock)
{
        int refclk = 100000;
        const struct intel_limit *limit = &intel_limits_bxt;

        return chv_find_best_dpll(limit, crtc_state,
                                  crtc_state->port_clock, refclk,
                                  NULL, best_clock);
}

bool intel_crtc_active(struct intel_crtc *crtc)
{
        /* Be paranoid as we can arrive here with only partial
         * state retrieved from the hardware during setup.
         *
         * We can ditch the adjusted_mode.crtc_clock check as soon
         * as Haswell has gained clock readout/fastboot support.
         *
         * We can ditch the crtc->primary->state->fb check as soon as we can
         * properly reconstruct framebuffers.
         *
         * FIXME: The intel_crtc->active here should be switched to
         * crtc->state->active once we have proper CRTC states wired up
         * for atomic.
         */
        return crtc->active && crtc->base.primary->state->fb &&
                crtc->config->base.adjusted_mode.crtc_clock;
}

enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
                                             enum pipe pipe)
{
        struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);

        return crtc->config->cpu_transcoder;
}

static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
                                    enum pipe pipe)
{
        i915_reg_t reg = PIPEDSL(pipe);
        u32 line1, line2;
        u32 line_mask;

        if (IS_GEN(dev_priv, 2))
                line_mask = DSL_LINEMASK_GEN2;
        else
                line_mask = DSL_LINEMASK_GEN3;

        line1 = I915_READ(reg) & line_mask;
        msleep(5);
        line2 = I915_READ(reg) & line_mask;

        return line1 != line2;
}

static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
{
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum pipe pipe = crtc->pipe;

        /* Wait for the display line to settle/start moving */
        if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
                DRM_ERROR("pipe %c scanline %s wait timed out\n",
                          pipe_name(pipe), onoff(state));
}

static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
{
        wait_for_pipe_scanline_moving(crtc, false);
}

static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
{
        wait_for_pipe_scanline_moving(crtc, true);
}

static void
intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
{
        struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

        if (INTEL_GEN(dev_priv) >= 4) {
                enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
                i915_reg_t reg = PIPECONF(cpu_transcoder);

                /* Wait for the Pipe State to go off */
                if (intel_de_wait_for_clear(dev_priv, reg,
                                            I965_PIPECONF_ACTIVE, 100))
                        WARN(1, "pipe_off wait timed out\n");
        } else {
                intel_wait_for_pipe_scanline_stopped(crtc);
        }
}

/* Only for pre-ILK configs */
void assert_pll(struct drm_i915_private *dev_priv,
                enum pipe pipe, bool state)
{
        u32 val;
        bool cur_state;

        val = I915_READ(DPLL(pipe));
        cur_state = !!(val & DPLL_VCO_ENABLE);
        I915_STATE_WARN(cur_state != state,
             "PLL state assertion failure (expected %s, current %s)\n",
                        onoff(state), onoff(cur_state));
}

/* XXX: the dsi pll is shared between MIPI DSI ports */
void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
{
        u32 val;
        bool cur_state;

        vlv_cck_get(dev_priv);
        val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
        vlv_cck_put(dev_priv);

        cur_state = val & DSI_PLL_VCO_EN;
        I915_STATE_WARN(cur_state != state,
             "DSI PLL state assertion failure (expected %s, current %s)\n",
                        onoff(state), onoff(cur_state));
}

static void assert_fdi_tx(struct drm_i915_private *dev_priv,
                          enum pipe pipe, bool state)
{
        bool cur_state;
        enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
                                                                      pipe);

        if (HAS_DDI(dev_priv)) {
                /* DDI does not have a specific FDI_TX register */
                u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
                cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
        } else {
                u32 val = I915_READ(FDI_TX_CTL(pipe));
                cur_state = !!(val & FDI_TX_ENABLE);
        }
        I915_STATE_WARN(cur_state != state,
             "FDI TX state assertion failure (expected %s, current %s)\n",
                        onoff(state), onoff(cur_state));
}
#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)

static void assert_fdi_rx(struct drm_i915_private *dev_priv,
                          enum pipe pipe, bool state)
{
        u32 val;
        bool cur_state;

        val = I915_READ(FDI_RX_CTL(pipe));
        cur_state = !!(val & FDI_RX_ENABLE);
        I915_STATE_WARN(cur_state != state,
             "FDI RX state assertion failure (expected %s, current %s)\n",
                        onoff(state), onoff(cur_state));
}
#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)

static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
                                      enum pipe pipe)
{
        u32 val;

        /* ILK FDI PLL is always enabled */
        if (IS_GEN(dev_priv, 5))
                return;

        /* On Haswell, DDI ports are responsible for the FDI PLL setup */
        if (HAS_DDI(dev_priv))
                return;

        val = I915_READ(FDI_TX_CTL(pipe));
        I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
}

void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
                       enum pipe pipe, bool state)
{
        u32 val;
        bool cur_state;

        val = I915_READ(FDI_RX_CTL(pipe));
        cur_state = !!(val & FDI_RX_PLL_ENABLE);
        I915_STATE_WARN(cur_state != state,
             "FDI RX PLL assertion failure (expected %s, current %s)\n",
                        onoff(state), onoff(cur_state));
}

void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
{
        i915_reg_t pp_reg;
        u32 val;
        enum pipe panel_pipe = INVALID_PIPE;
        bool locked = true;

        if (WARN_ON(HAS_DDI(dev_priv)))
                return;

        if (HAS_PCH_SPLIT(dev_priv)) {
                u32 port_sel;

                pp_reg = PP_CONTROL(0);
                port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;

                switch (port_sel) {
                case PANEL_PORT_SELECT_LVDS:
                        intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
                        break;
                case PANEL_PORT_SELECT_DPA:
                        intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
                        break;
                case PANEL_PORT_SELECT_DPC:
                        intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
                        break;
                case PANEL_PORT_SELECT_DPD:
                        intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
                        break;
                default:
                        MISSING_CASE(port_sel);
                        break;
                }
        } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
                /* presumably write lock depends on pipe, not port select */
                pp_reg = PP_CONTROL(pipe);
                panel_pipe = pipe;
        } else {
                u32 port_sel;

                pp_reg = PP_CONTROL(0);
                port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;

                WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS);
                intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
        }

        val = I915_READ(pp_reg);
        if (!(val & PANEL_POWER_ON) ||
            ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
                locked = false;

        I915_STATE_WARN(panel_pipe == pipe && locked,
             "panel assertion failure, pipe %c regs locked\n",
             pipe_name(pipe));
}

void assert_pipe(struct drm_i915_private *dev_priv,
                 enum pipe pipe, bool state)
{
        bool cur_state;
        enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
                                                                      pipe);
        enum intel_display_power_domain power_domain;
        intel_wakeref_t wakeref;

        /* we keep both pipes enabled on 830 */
        if (IS_I830(dev_priv))
                state = true;

        power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
        wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
        if (wakeref) {
                u32 val = I915_READ(PIPECONF(cpu_transcoder));
                cur_state = !!(val & PIPECONF_ENABLE);

                intel_display_power_put(dev_priv, power_domain, wakeref);
        } else {
                cur_state = false;
        }

        I915_STATE_WARN(cur_state != state,
             "pipe %c assertion failure (expected %s, current %s)\n",
                        pipe_name(pipe), onoff(state), onoff(cur_state));
}

static void assert_plane(struct intel_plane *plane, bool state)
{
        enum pipe pipe;
        bool cur_state;

        cur_state = plane->get_hw_state(plane, &pipe);

        I915_STATE_WARN(cur_state != state,
                        "%s assertion failure (expected %s, current %s)\n",
                        plane->base.name, onoff(state), onoff(cur_state));
}

#define assert_plane_enabled(p) assert_plane(p, true)
#define assert_plane_disabled(p) assert_plane(p, false)

static void assert_planes_disabled(struct intel_crtc *crtc)
{
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        struct intel_plane *plane;

        for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
                assert_plane_disabled(plane);
}

static void assert_vblank_disabled(struct drm_crtc *crtc)
{
        if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
                drm_crtc_vblank_put(crtc);
}

void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
                                    enum pipe pipe)
{
        u32 val;
        bool enabled;

        val = I915_READ(PCH_TRANSCONF(pipe));
        enabled = !!(val & TRANS_ENABLE);
        I915_STATE_WARN(enabled,
             "transcoder assertion failed, should be off on pipe %c but is still active\n",
             pipe_name(pipe));
}

static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
                                   enum pipe pipe, enum port port,
                                   i915_reg_t dp_reg)
{
        enum pipe port_pipe;
        bool state;

        state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);

        I915_STATE_WARN(state && port_pipe == pipe,
                        "PCH DP %c enabled on transcoder %c, should be disabled\n",
                        port_name(port), pipe_name(pipe));

        I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
                        "IBX PCH DP %c still using transcoder B\n",
                        port_name(port));
}

static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
                                     enum pipe pipe, enum port port,
                                     i915_reg_t hdmi_reg)
{
        enum pipe port_pipe;
        bool state;

        state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);

        I915_STATE_WARN(state && port_pipe == pipe,
                        "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
                        port_name(port), pipe_name(pipe));

        I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
                        "IBX PCH HDMI %c still using transcoder B\n",
                        port_name(port));
}

static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
                                      enum pipe pipe)
{
        enum pipe port_pipe;

        assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
        assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
        assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);

        I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
                        port_pipe == pipe,
                        "PCH VGA enabled on transcoder %c, should be disabled\n",
                        pipe_name(pipe));

        I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
                        port_pipe == pipe,
                        "PCH LVDS enabled on transcoder %c, should be disabled\n",
                        pipe_name(pipe));

        /* PCH SDVOB multiplex with HDMIB */
        assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
        assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
        assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
}

static void _vlv_enable_pll(struct intel_crtc *crtc,
                            const struct intel_crtc_state *pipe_config)
{
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum pipe pipe = crtc->pipe;

        I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
        POSTING_READ(DPLL(pipe));
        udelay(150);

        if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
                DRM_ERROR("DPLL %d failed to lock\n", pipe);
}

static void vlv_enable_pll(struct intel_crtc *crtc,
                           const struct intel_crtc_state *pipe_config)
{
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum pipe pipe = crtc->pipe;

        assert_pipe_disabled(dev_priv, pipe);

        /* PLL is protected by panel, make sure we can write it */
        assert_panel_unlocked(dev_priv, pipe);

        if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
                _vlv_enable_pll(crtc, pipe_config);

        I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
        POSTING_READ(DPLL_MD(pipe));
}


static void _chv_enable_pll(struct intel_crtc *crtc,
                            const struct intel_crtc_state *pipe_config)
{
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum pipe pipe = crtc->pipe;
        enum dpio_channel port = vlv_pipe_to_channel(pipe);
        u32 tmp;

        vlv_dpio_get(dev_priv);

        /* Enable back the 10bit clock to display controller */
        tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
        tmp |= DPIO_DCLKP_EN;
        vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);

        vlv_dpio_put(dev_priv);

        /*
         * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
         */
        udelay(1);

        /* Enable PLL */
        I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);

        /* Check PLL is locked */
        if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
                DRM_ERROR("PLL %d failed to lock\n", pipe);
}

static void chv_enable_pll(struct intel_crtc *crtc,
                           const struct intel_crtc_state *pipe_config)
{
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum pipe pipe = crtc->pipe;

        assert_pipe_disabled(dev_priv, pipe);

        /* PLL is protected by panel, make sure we can write it */
        assert_panel_unlocked(dev_priv, pipe);

        if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
                _chv_enable_pll(crtc, pipe_config);

        if (pipe != PIPE_A) {
                /*
                 * WaPixelRepeatModeFixForC0:chv
                 *
                 * DPLLCMD is AWOL. Use chicken bits to propagate
                 * the value from DPLLBMD to either pipe B or C.
                 */
                I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
                I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
                I915_WRITE(CBR4_VLV, 0);
                dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;

                /*
                 * DPLLB VGA mode also seems to cause problems.
                 * We should always have it disabled.
                 */
                WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
        } else {
                I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
                POSTING_READ(DPLL_MD(pipe));
        }
}

static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
{
        if (IS_I830(dev_priv))
                return false;

        return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
}

static void i9xx_enable_pll(struct intel_crtc *crtc,
                            const struct intel_crtc_state *crtc_state)
{
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        i915_reg_t reg = DPLL(crtc->pipe);
        u32 dpll = crtc_state->dpll_hw_state.dpll;
        int i;

        assert_pipe_disabled(dev_priv, crtc->pipe);

        /* PLL is protected by panel, make sure we can write it */
        if (i9xx_has_pps(dev_priv))
                assert_panel_unlocked(dev_priv, crtc->pipe);

        /*
         * Apparently we need to have VGA mode enabled prior to changing
         * the P1/P2 dividers. Otherwise the DPLL will keep using the old
         * dividers, even though the register value does change.
         */
        I915_WRITE(reg, dpll & ~DPLL_VGA_MODE_DIS);
        I915_WRITE(reg, dpll);

        /* Wait for the clocks to stabilize. */
        POSTING_READ(reg);
        udelay(150);

        if (INTEL_GEN(dev_priv) >= 4) {
                I915_WRITE(DPLL_MD(crtc->pipe),
                           crtc_state->dpll_hw_state.dpll_md);
        } else {
                /* The pixel multiplier can only be updated once the
                 * DPLL is enabled and the clocks are stable.
                 *
                 * So write it again.
                 */
                I915_WRITE(reg, dpll);
        }

        /* We do this three times for luck */
        for (i = 0; i < 3; i++) {
                I915_WRITE(reg, dpll);
                POSTING_READ(reg);
                udelay(150); /* wait for warmup */
        }
}

static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
{
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum pipe pipe = crtc->pipe;

        /* Don't disable pipe or pipe PLLs if needed */
        if (IS_I830(dev_priv))
                return;

        /* Make sure the pipe isn't still relying on us */
        assert_pipe_disabled(dev_priv, pipe);

        I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
        POSTING_READ(DPLL(pipe));
}

static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
{
        u32 val;

        /* Make sure the pipe isn't still relying on us */
        assert_pipe_disabled(dev_priv, pipe);

        val = DPLL_INTEGRATED_REF_CLK_VLV |
                DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
        if (pipe != PIPE_A)
                val |= DPLL_INTEGRATED_CRI_CLK_VLV;

        I915_WRITE(DPLL(pipe), val);
        POSTING_READ(DPLL(pipe));
}

static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
{
        enum dpio_channel port = vlv_pipe_to_channel(pipe);
        u32 val;

        /* Make sure the pipe isn't still relying on us */
        assert_pipe_disabled(dev_priv, pipe);

        val = DPLL_SSC_REF_CLK_CHV |
                DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
        if (pipe != PIPE_A)
                val |= DPLL_INTEGRATED_CRI_CLK_VLV;

        I915_WRITE(DPLL(pipe), val);
        POSTING_READ(DPLL(pipe));

        vlv_dpio_get(dev_priv);

        /* Disable 10bit clock to display controller */
        val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
        val &= ~DPIO_DCLKP_EN;
        vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);

        vlv_dpio_put(dev_priv);
}

void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
                         struct intel_digital_port *dport,
                         unsigned int expected_mask)
{
        u32 port_mask;
        i915_reg_t dpll_reg;

        switch (dport->base.port) {
        case PORT_B:
                port_mask = DPLL_PORTB_READY_MASK;
                dpll_reg = DPLL(0);
                break;
        case PORT_C:
                port_mask = DPLL_PORTC_READY_MASK;
                dpll_reg = DPLL(0);
                expected_mask <<= 4;
                break;
        case PORT_D:
                port_mask = DPLL_PORTD_READY_MASK;
                dpll_reg = DPIO_PHY_STATUS;
                break;
        default:
                BUG();
        }

        if (intel_de_wait_for_register(dev_priv, dpll_reg,
                                       port_mask, expected_mask, 1000))
                WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
                     port_name(dport->base.port),
                     I915_READ(dpll_reg) & port_mask, expected_mask);
}

static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
{
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum pipe pipe = crtc->pipe;
        i915_reg_t reg;
        u32 val, pipeconf_val;

        /* Make sure PCH DPLL is enabled */
        assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);

        /* FDI must be feeding us bits for PCH ports */
        assert_fdi_tx_enabled(dev_priv, pipe);
        assert_fdi_rx_enabled(dev_priv, pipe);

        if (HAS_PCH_CPT(dev_priv)) {
                /* Workaround: Set the timing override bit before enabling the
                 * pch transcoder. */
                reg = TRANS_CHICKEN2(pipe);
                val = I915_READ(reg);
                val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
                I915_WRITE(reg, val);
        }

        reg = PCH_TRANSCONF(pipe);
        val = I915_READ(reg);
        pipeconf_val = I915_READ(PIPECONF(pipe));

        if (HAS_PCH_IBX(dev_priv)) {
                /*
                 * Make the BPC in transcoder be consistent with
                 * that in pipeconf reg. For HDMI we must use 8bpc
                 * here for both 8bpc and 12bpc.
                 */
                val &= ~PIPECONF_BPC_MASK;
                if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
                        val |= PIPECONF_8BPC;
                else
                        val |= pipeconf_val & PIPECONF_BPC_MASK;
        }

        val &= ~TRANS_INTERLACE_MASK;
        if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
                if (HAS_PCH_IBX(dev_priv) &&
                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
                        val |= TRANS_LEGACY_INTERLACED_ILK;
                else
                        val |= TRANS_INTERLACED;
        } else {
                val |= TRANS_PROGRESSIVE;
        }

        I915_WRITE(reg, val | TRANS_ENABLE);
        if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
                DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
}

static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
                                      enum transcoder cpu_transcoder)
{
        u32 val, pipeconf_val;

        /* FDI must be feeding us bits for PCH ports */
        assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
        assert_fdi_rx_enabled(dev_priv, PIPE_A);

        /* Workaround: set timing override bit. */
        val = I915_READ(TRANS_CHICKEN2(PIPE_A));
        val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
        I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);

        val = TRANS_ENABLE;
        pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));

        if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
            PIPECONF_INTERLACED_ILK)
                val |= TRANS_INTERLACED;
        else
                val |= TRANS_PROGRESSIVE;

        I915_WRITE(LPT_TRANSCONF, val);
        if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
                                  TRANS_STATE_ENABLE, 100))
                DRM_ERROR("Failed to enable PCH transcoder\n");
}

static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
                                            enum pipe pipe)
{
        i915_reg_t reg;
        u32 val;

        /* FDI relies on the transcoder */
        assert_fdi_tx_disabled(dev_priv, pipe);
        assert_fdi_rx_disabled(dev_priv, pipe);

        /* Ports must be off as well */
        assert_pch_ports_disabled(dev_priv, pipe);

        reg = PCH_TRANSCONF(pipe);
        val = I915_READ(reg);
        val &= ~TRANS_ENABLE;
        I915_WRITE(reg, val);
        /* wait for PCH transcoder off, transcoder state */
        if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
                DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));

        if (HAS_PCH_CPT(dev_priv)) {
                /* Workaround: Clear the timing override chicken bit again. */
                reg = TRANS_CHICKEN2(pipe);
                val = I915_READ(reg);
                val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
                I915_WRITE(reg, val);
        }
}

void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
{
        u32 val;

        val = I915_READ(LPT_TRANSCONF);
        val &= ~TRANS_ENABLE;
        I915_WRITE(LPT_TRANSCONF, val);
        /* wait for PCH transcoder off, transcoder state */
        if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
                                    TRANS_STATE_ENABLE, 50))
                DRM_ERROR("Failed to disable PCH transcoder\n");

        /* Workaround: clear timing override bit. */
        val = I915_READ(TRANS_CHICKEN2(PIPE_A));
        val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
        I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
}

enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
{
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

        if (HAS_PCH_LPT(dev_priv))
                return PIPE_A;
        else
                return crtc->pipe;
}

static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
{
        struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);

        /*
         * On i965gm the hardware frame counter reads
         * zero when the TV encoder is enabled :(
         */
        if (IS_I965GM(dev_priv) &&
            (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
                return 0;

        if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
                return 0xffffffff; /* full 32 bit counter */
        else if (INTEL_GEN(dev_priv) >= 3)
                return 0xffffff; /* only 24 bits of frame count */
        else
                return 0; /* Gen2 doesn't have a hardware frame counter */
}

static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
{
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);

        drm_crtc_set_max_vblank_count(&crtc->base,
                                      intel_crtc_max_vblank_count(crtc_state));
        drm_crtc_vblank_on(&crtc->base);
}

static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
{
        struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
        enum pipe pipe = crtc->pipe;
        i915_reg_t reg;
        u32 val;

        DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));

        assert_planes_disabled(crtc);

        /*
         * A pipe without a PLL won't actually be able to drive bits from
         * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
         * need the check.
         */
        if (HAS_GMCH(dev_priv)) {
                if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
                        assert_dsi_pll_enabled(dev_priv);
                else
                        assert_pll_enabled(dev_priv, pipe);
        } else {
                if (new_crtc_state->has_pch_encoder) {
                        /* if driving the PCH, we need FDI enabled */
                        assert_fdi_rx_pll_enabled(dev_priv,
                                                  intel_crtc_pch_transcoder(crtc));
                        assert_fdi_tx_pll_enabled(dev_priv,
                                                  (enum pipe) cpu_transcoder);
                }
                /* FIXME: assert CPU port conditions for SNB+ */
        }

        trace_intel_pipe_enable(crtc);

        reg = PIPECONF(cpu_transcoder);
        val = I915_READ(reg);
        if (val & PIPECONF_ENABLE) {
                /* we keep both pipes enabled on 830 */
                WARN_ON(!IS_I830(dev_priv));
                return;
        }

        I915_WRITE(reg, val | PIPECONF_ENABLE);
        POSTING_READ(reg);

        /*
         * Until the pipe starts PIPEDSL reads will return a stale value,
         * which causes an apparent vblank timestamp jump when PIPEDSL
         * resets to its proper value. That also messes up the frame count
         * when it's derived from the timestamps. So let's wait for the
         * pipe to start properly before we call drm_crtc_vblank_on()
         */
        if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
                intel_wait_for_pipe_scanline_moving(crtc);
}

static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
{
        struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
        enum pipe pipe = crtc->pipe;
        i915_reg_t reg;
        u32 val;

        DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));

        /*
         * Make sure planes won't keep trying to pump pixels to us,
         * or we might hang the display.
         */
        assert_planes_disabled(crtc);

        trace_intel_pipe_disable(crtc);

        reg = PIPECONF(cpu_transcoder);
        val = I915_READ(reg);
        if ((val & PIPECONF_ENABLE) == 0)
                return;

        /*
         * Double wide has implications for planes
         * so best keep it disabled when not needed.
         */
        if (old_crtc_state->double_wide)
                val &= ~PIPECONF_DOUBLE_WIDE;

        /* Don't disable pipe or pipe PLLs if needed */
        if (!IS_I830(dev_priv))
                val &= ~PIPECONF_ENABLE;

        I915_WRITE(reg, val);
        if ((val & PIPECONF_ENABLE) == 0)
                intel_wait_for_pipe_off(old_crtc_state);
}

static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
{
        return IS_GEN(dev_priv, 2) ? 2048 : 4096;
}

static unsigned int
intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
{
        struct drm_i915_private *dev_priv = to_i915(fb->dev);
        unsigned int cpp = fb->format->cpp[color_plane];

        switch (fb->modifier) {
        case DRM_FORMAT_MOD_LINEAR:
                return intel_tile_size(dev_priv);
        case I915_FORMAT_MOD_X_TILED:
                if (IS_GEN(dev_priv, 2))
                        return 128;
                else
                        return 512;
        case I915_FORMAT_MOD_Y_TILED_CCS:
                if (color_plane == 1)
                        return 128;
                /* fall through */
        case I915_FORMAT_MOD_Y_TILED:
                if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
                        return 128;
                else
                        return 512;
        case I915_FORMAT_MOD_Yf_TILED_CCS:
                if (color_plane == 1)
                        return 128;
                /* fall through */
        case I915_FORMAT_MOD_Yf_TILED:
                switch (cpp) {
                case 1:
                        return 64;
                case 2:
                case 4:
                        return 128;
                case 8:
                case 16:
                        return 256;
                default:
                        MISSING_CASE(cpp);
                        return cpp;
                }
                break;
        default:
                MISSING_CASE(fb->modifier);
                return cpp;
        }
}

static unsigned int
intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
{
        return intel_tile_size(to_i915(fb->dev)) /
                intel_tile_width_bytes(fb, color_plane);
}

/* Return the tile dimensions in pixel units */
static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
                            unsigned int *tile_width,
                            unsigned int *tile_height)
{
        unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
        unsigned int cpp = fb->format->cpp[color_plane];

        *tile_width = tile_width_bytes / cpp;
        *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
}

unsigned int
intel_fb_align_height(const struct drm_framebuffer *fb,
                      int color_plane, unsigned int height)
{
        unsigned int tile_height = intel_tile_height(fb, color_plane);

        return ALIGN(height, tile_height);
}

unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
{
        unsigned int size = 0;
        int i;

        for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
                size += rot_info->plane[i].width * rot_info->plane[i].height;

        return size;
}

unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
{
        unsigned int size = 0;
        int i;

        for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
                size += rem_info->plane[i].width * rem_info->plane[i].height;

        return size;
}

static void
intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
                        const struct drm_framebuffer *fb,
                        unsigned int rotation)
{
        view->type = I915_GGTT_VIEW_NORMAL;
        if (drm_rotation_90_or_270(rotation)) {

                view->type = I915_GGTT_VIEW_ROTATED;
                view->rotated = to_intel_framebuffer(fb)->rot_info;
        }
}

static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
{
        if (IS_I830(dev_priv))
                return 16 * 1024;
        else if (IS_I85X(dev_priv))
                return 256;
        else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
                return 32;
        else
                return 4 * 1024;
}

static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
{
        if (INTEL_GEN(dev_priv) >= 9)
                return 256 * 1024;
        else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
                 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
                return 128 * 1024;
        else if (INTEL_GEN(dev_priv) >= 4)
                return 4 * 1024;
        else
                return 0;
}

static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
                                         int color_plane)
{
        struct drm_i915_private *dev_priv = to_i915(fb->dev);

        /* AUX_DIST needs only 4K alignment */
        if (color_plane == 1)
                return 4096;

        switch (fb->modifier) {
        case DRM_FORMAT_MOD_LINEAR:
                return intel_linear_alignment(dev_priv);
        case I915_FORMAT_MOD_X_TILED:
                if (INTEL_GEN(dev_priv) >= 9)
                        return 256 * 1024;
                return 0;
        case I915_FORMAT_MOD_Y_TILED_CCS:
        case I915_FORMAT_MOD_Yf_TILED_CCS:
        case I915_FORMAT_MOD_Y_TILED:
        case I915_FORMAT_MOD_Yf_TILED:
                return 1 * 1024 * 1024;
        default:
                MISSING_CASE(fb->modifier);
                return 0;
        }
}

static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
{
        struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
        struct drm_i915_private *dev_priv = to_i915(plane->base.dev);

        return INTEL_GEN(dev_priv) < 4 ||
                (plane->has_fbc &&
                 plane_state->view.type == I915_GGTT_VIEW_NORMAL);
}

struct i915_vma *
intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
                           const struct i915_ggtt_view *view,
                           bool uses_fence,
                           unsigned long *out_flags)
{
        struct drm_device *dev = fb->dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
        struct drm_i915_gem_object *obj = intel_fb_obj(fb);
        intel_wakeref_t wakeref;
        struct i915_vma *vma;
        unsigned int pinctl;
        u32 alignment;

        WARN_ON(!mutex_is_locked(&dev->struct_mutex));

        alignment = intel_surf_alignment(fb, 0);

        /* Note that the w/a also requires 64 PTE of padding following the
         * bo. We currently fill all unused PTE with the shadow page and so
         * we should always have valid PTE following the scanout preventing
         * the VT-d warning.
         */
        if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
                alignment = 256 * 1024;

        /*
         * Global gtt pte registers are special registers which actually forward
         * writes to a chunk of system memory. Which means that there is no risk
         * that the register values disappear as soon as we call
         * intel_runtime_pm_put(), so it is correct to wrap only the
         * pin/unpin/fence and not more.
         */
        wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
        i915_gem_object_lock(obj);

        atomic_inc(&dev_priv->gpu_error.pending_fb_pin);

        pinctl = 0;

        /* Valleyview is definitely limited to scanning out the first
         * 512MiB. Lets presume this behaviour was inherited from the
         * g4x display engine and that all earlier gen are similarly
         * limited. Testing suggests that it is a little more
         * complicated than this. For example, Cherryview appears quite
         * happy to scanout from anywhere within its global aperture.
         */
        if (HAS_GMCH(dev_priv))
                pinctl |= PIN_MAPPABLE;

        vma = i915_gem_object_pin_to_display_plane(obj,
                                                   alignment, view, pinctl);
        if (IS_ERR(vma))
                goto err;

        if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
                int ret;

                /* Install a fence for tiled scan-out. Pre-i965 always needs a
                 * fence, whereas 965+ only requires a fence if using
                 * framebuffer compression.  For simplicity, we always, when
                 * possible, install a fence as the cost is not that onerous.
                 *
                 * If we fail to fence the tiled scanout, then either the
                 * modeset will reject the change (which is highly unlikely as
                 * the affected systems, all but one, do not have unmappable
                 * space) or we will not be able to enable full powersaving
                 * techniques (also likely not to apply due to various limits
                 * FBC and the like impose on the size of the buffer, which
                 * presumably we violated anyway with this unmappable buffer).
                 * Anyway, it is presumably better to stumble onwards with
                 * something and try to run the system in a "less than optimal"
                 * mode that matches the user configuration.
                 */
                ret = i915_vma_pin_fence(vma);
                if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
                        i915_gem_object_unpin_from_display_plane(vma);
                        vma = ERR_PTR(ret);
                        goto err;
                }

                if (ret == 0 && vma->fence)
                        *out_flags |= PLANE_HAS_FENCE;
        }

        i915_vma_get(vma);
err:
        atomic_dec(&dev_priv->gpu_error.pending_fb_pin);

        i915_gem_object_unlock(obj);
        intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
        return vma;
}

void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
{
        lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);

        i915_gem_object_lock(vma->obj);
        if (flags & PLANE_HAS_FENCE)
                i915_vma_unpin_fence(vma);
        i915_gem_object_unpin_from_display_plane(vma);
        i915_gem_object_unlock(vma->obj);

        i915_vma_put(vma);
}

static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
                          unsigned int rotation)
{
        if (drm_rotation_90_or_270(rotation))
                return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
        else
                return fb->pitches[color_plane];
}

/*
 * Convert the x/y offsets into a linear offset.
 * Only valid with 0/180 degree rotation, which is fine since linear
 * offset is only used with linear buffers on pre-hsw and tiled buffers
 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
 */
u32 intel_fb_xy_to_linear(int x, int y,
                          const struct intel_plane_state *state,
                          int color_plane)
{
        const struct drm_framebuffer *fb = state->base.fb;
        unsigned int cpp = fb->format->cpp[color_plane];
        unsigned int pitch = state->color_plane[color_plane].stride;

        return y * pitch + x * cpp;
}

/*
 * Add the x/y offsets derived from fb->offsets[] to the user
 * specified plane src x/y offsets. The resulting x/y offsets
 * specify the start of scanout from the beginning of the gtt mapping.
 */
void intel_add_fb_offsets(int *x, int *y,
                          const struct intel_plane_state *state,
                          int color_plane)

{
        *x += state->color_plane[color_plane].x;
        *y += state->color_plane[color_plane].y;
}

static u32 intel_adjust_tile_offset(int *x, int *y,
                                    unsigned int tile_width,
                                    unsigned int tile_height,
                                    unsigned int tile_size,
                                    unsigned int pitch_tiles,
                                    u32 old_offset,
                                    u32 new_offset)
{
        unsigned int pitch_pixels = pitch_tiles * tile_width;
        unsigned int tiles;

        WARN_ON(old_offset & (tile_size - 1));
        WARN_ON(new_offset & (tile_size - 1));
        WARN_ON(new_offset > old_offset);

        tiles = (old_offset - new_offset) / tile_size;

        *y += tiles / pitch_tiles * tile_height;
        *x += tiles % pitch_tiles * tile_width;

        /* minimize x in case it got needlessly big */
        *y += *x / pitch_pixels * tile_height;
        *x %= pitch_pixels;

        return new_offset;
}

static bool is_surface_linear(u64 modifier, int color_plane)
{
        return modifier == DRM_FORMAT_MOD_LINEAR;
}

static u32 intel_adjust_aligned_offset(int *x, int *y,
                                       const struct drm_framebuffer *fb,
                                       int color_plane,
                                       unsigned int rotation,
                                       unsigned int pitch,
                                       u32 old_offset, u32 new_offset)
{
        struct drm_i915_private *dev_priv = to_i915(fb->dev);
        unsigned int cpp = fb->format->cpp[color_plane];

        WARN_ON(new_offset > old_offset);

        if (!is_surface_linear(fb->modifier, color_plane)) {
                unsigned int tile_size, tile_width, tile_height;
                unsigned int pitch_tiles;

                tile_size = intel_tile_size(dev_priv);
                intel_tile_dims(fb, color_plane, &tile_width, &tile_height);

                if (drm_rotation_90_or_270(rotation)) {
                        pitch_tiles = pitch / tile_height;
                        swap(tile_width, tile_height);
                } else {
                        pitch_tiles = pitch / (tile_width * cpp);
                }

                intel_adjust_tile_offset(x, y, tile_width, tile_height,
                                         tile_size, pitch_tiles,
                                         old_offset, new_offset);
        } else {
                old_offset += *y * pitch + *x * cpp;

                *y = (old_offset - new_offset) / pitch;
                *x = ((old_offset - new_offset) - *y * pitch) / cpp;
        }

        return new_offset;
}

/*
 * Adjust the tile offset by moving the difference into
 * the x/y offsets.
 */
static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
                                             const struct intel_plane_state *state,
                                             int color_plane,
                                             u32 old_offset, u32 new_offset)
{
        return intel_adjust_aligned_offset(x, y, state->base.fb, color_plane,
                                           state->base.rotation,
                                           state->color_plane[color_plane].stride,
                                           old_offset, new_offset);
}

/*
 * Computes the aligned offset to the base tile and adjusts
 * x, y. bytes per pixel is assumed to be a power-of-two.
 *
 * In the 90/270 rotated case, x and y are assumed
 * to be already rotated to match the rotated GTT view, and
 * pitch is the tile_height aligned framebuffer height.
 *
 * This function is used when computing the derived information
 * under intel_framebuffer, so using any of that information
 * here is not allowed. Anything under drm_framebuffer can be
 * used. This is why the user has to pass in the pitch since it
 * is specified in the rotated orientation.
 */
static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
                                        int *x, int *y,
                                        const struct drm_framebuffer *fb,
                                        int color_plane,
                                        unsigned int pitch,
                                        unsigned int rotation,
                                        u32 alignment)
{
        unsigned int cpp = fb->format->cpp[color_plane];
        u32 offset, offset_aligned;

        if (alignment)
                alignment--;

        if (!is_surface_linear(fb->modifier, color_plane)) {
                unsigned int tile_size, tile_width, tile_height;
                unsigned int tile_rows, tiles, pitch_tiles;

                tile_size = intel_tile_size(dev_priv);
                intel_tile_dims(fb, color_plane, &tile_width, &tile_height);

                if (drm_rotation_90_or_270(rotation)) {
                        pitch_tiles = pitch / tile_height;
                        swap(tile_width, tile_height);
                } else {
                        pitch_tiles = pitch / (tile_width * cpp);
                }

                tile_rows = *y / tile_height;
                *y %= tile_height;

                tiles = *x / tile_width;
                *x %= tile_width;

                offset = (tile_rows * pitch_tiles + tiles) * tile_size;
                offset_aligned = offset & ~alignment;

                intel_adjust_tile_offset(x, y, tile_width, tile_height,
                                         tile_size, pitch_tiles,
                                         offset, offset_aligned);
        } else {
                offset = *y * pitch + *x * cpp;
                offset_aligned = offset & ~alignment;

                *y = (offset & alignment) / pitch;
                *x = ((offset & alignment) - *y * pitch) / cpp;
        }

        return offset_aligned;
}

static u32 intel_plane_compute_aligned_offset(int *x, int *y,
                                              const struct intel_plane_state *state,
                                              int color_plane)
{
        struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
        struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
        const struct drm_framebuffer *fb = state->base.fb;
        unsigned int rotation = state->base.rotation;
        int pitch = state->color_plane[color_plane].stride;
        u32 alignment;

        if (intel_plane->id == PLANE_CURSOR)
                alignment = intel_cursor_alignment(dev_priv);
        else
                alignment = intel_surf_alignment(fb, color_plane);

        return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
                                            pitch, rotation, alignment);
}

/* Convert the fb->offset[] into x/y offsets */
static int intel_fb_offset_to_xy(int *x, int *y,
                                 const struct drm_framebuffer *fb,
                                 int color_plane)
{
        struct drm_i915_private *dev_priv = to_i915(fb->dev);
        unsigned int height;

        if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
            fb->offsets[color_plane] % intel_tile_size(dev_priv)) {
                DRM_DEBUG_KMS("Misaligned offset 0x%08x for color plane %d\n",
                              fb->offsets[color_plane], color_plane);
                return -EINVAL;
        }

        height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
        height = ALIGN(height, intel_tile_height(fb, color_plane));

        /* Catch potential overflows early */
        if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
                            fb->offsets[color_plane])) {
                DRM_DEBUG_KMS("Bad offset 0x%08x or pitch %d for color plane %d\n",
                              fb->offsets[color_plane], fb->pitches[color_plane],
                              color_plane);
                return -ERANGE;
        }

        *x = 0;
        *y = 0;

        intel_adjust_aligned_offset(x, y,
                                    fb, color_plane, DRM_MODE_ROTATE_0,
                                    fb->pitches[color_plane],
                                    fb->offsets[color_plane], 0);

        return 0;
}

static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
{
        switch (fb_modifier) {
        case I915_FORMAT_MOD_X_TILED:
                return I915_TILING_X;
        case I915_FORMAT_MOD_Y_TILED:
        case I915_FORMAT_MOD_Y_TILED_CCS:
                return I915_TILING_Y;
        default:
                return I915_TILING_NONE;
        }
}

/*
 * From the Sky Lake PRM:
 * "The Color Control Surface (CCS) contains the compression status of
 *  the cache-line pairs. The compression state of the cache-line pair
 *  is specified by 2 bits in the CCS. Each CCS cache-line represents
 *  an area on the main surface of 16 x16 sets of 128 byte Y-tiled
 *  cache-line-pairs. CCS is always Y tiled."
 *
 * Since cache line pairs refers to horizontally adjacent cache lines,
 * each cache line in the CCS corresponds to an area of 32x16 cache
 * lines on the main surface. Since each pixel is 4 bytes, this gives
 * us a ratio of one byte in the CCS for each 8x16 pixels in the
 * main surface.
 */
static const struct drm_format_info ccs_formats[] = {
        { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
          .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
        { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
          .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
        { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
          .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
        { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
          .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
};

static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],
                   int num_formats, u32 format)
{
        int i;

        for (i = 0; i < num_formats; i++) {
                if (formats[i].format == format)
                        return &formats[i];
        }

        return NULL;
}

static const struct drm_format_info *
intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
{
        switch (cmd->modifier[0]) {
        case I915_FORMAT_MOD_Y_TILED_CCS:
        case I915_FORMAT_MOD_Yf_TILED_CCS:
                return lookup_format_info(ccs_formats,
                                          ARRAY_SIZE(ccs_formats),
                                          cmd->pixel_format);
        default:
                return NULL;
        }
}

bool is_ccs_modifier(u64 modifier)
{
        return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
               modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}

u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
                              u32 pixel_format, u64 modifier)
{
        struct intel_crtc *crtc;
        struct intel_plane *plane;

        /*
         * We assume the primary plane for pipe A has
         * the highest stride limits of them all.
         */
        crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
        if (!crtc)
                return 0;

        plane = to_intel_plane(crtc->base.primary);

        return plane->max_stride(plane, pixel_format, modifier,
                                 DRM_MODE_ROTATE_0);
}

static
u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
                        u32 pixel_format, u64 modifier)
{
        /*
         * Arbitrary limit for gen4+ chosen to match the
         * render engine max stride.
         *
         * The new CCS hash mode makes remapping impossible
         */
        if (!is_ccs_modifier(modifier)) {
                if (INTEL_GEN(dev_priv) >= 7)
                        return 256*1024;
                else if (INTEL_GEN(dev_priv) >= 4)
                        return 128*1024;
        }

        return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
}

static u32
intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
{
        struct drm_i915_private *dev_priv = to_i915(fb->dev);

        if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
                u32 max_stride = intel_plane_fb_max_stride(dev_priv,
                                                           fb->format->format,
                                                           fb->modifier);

                /*
                 * To make remapping with linear generally feasible
                 * we need the stride to be page aligned.
                 */
                if (fb->pitches[color_plane] > max_stride)
                        return intel_tile_size(dev_priv);
                else
                        return 64;
        } else {
                return intel_tile_width_bytes(fb, color_plane);
        }
}

bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
{
        struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
        struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
        const struct drm_framebuffer *fb = plane_state->base.fb;
        int i;

        /* We don't want to deal with remapping with cursors */
        if (plane->id == PLANE_CURSOR)
                return false;

        /*
         * The display engine limits already match/exceed the
         * render engine limits, so not much point in remapping.
         * Would also need to deal with the fence POT alignment
         * and gen2 2KiB GTT tile size.
         */
        if (INTEL_GEN(dev_priv) < 4)
                return false;

        /*
         * The new CCS hash mode isn't compatible with remapping as
         * the virtual address of the pages affects the compressed data.
         */
        if (is_ccs_modifier(fb->modifier))
                return false;

        /* Linear needs a page aligned stride for remapping */
        if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
                unsigned int alignment = intel_tile_size(dev_priv) - 1;

                for (i = 0; i < fb->format->num_planes; i++) {
                        if (fb->pitches[i] & alignment)
                                return false;
                }
        }

        return true;
}

static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
{
        struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
        const struct drm_framebuffer *fb = plane_state->base.fb;
        unsigned int rotation = plane_state->base.rotation;
        u32 stride, max_stride;

        /*
         * No remapping for invisible planes since we don't have
         * an actual source viewport to remap.
         */
        if (!plane_state->base.visible)
                return false;

        if (!intel_plane_can_remap(plane_state))
                return false;

        /*
         * FIXME: aux plane limits on gen9+ are
         * unclear in Bspec, for now no checking.
         */
        stride = intel_fb_pitch(fb, 0, rotation);
        max_stride = plane->max_stride(plane, fb->format->format,
                                       fb->modifier, rotation);

        return stride > max_stride;
}

static int
intel_fill_fb_info(struct drm_i915_private *dev_priv,
                   struct drm_framebuffer *fb)
{
        struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
        struct intel_rotation_info *rot_info = &intel_fb->rot_info;
        struct drm_i915_gem_object *obj = intel_fb_obj(fb);
        u32 gtt_offset_rotated = 0;
        unsigned int max_size = 0;
        int i, num_planes = fb->format->num_planes;
        unsigned int tile_size = intel_tile_size(dev_priv);

        for (i = 0; i < num_planes; i++) {
                unsigned int width, height;
                unsigned int cpp, size;
                u32 offset;
                int x, y;
                int ret;

                cpp = fb->format->cpp[i];
                width = drm_framebuffer_plane_width(fb->width, fb, i);
                height = drm_framebuffer_plane_height(fb->height, fb, i);

                ret = intel_fb_offset_to_xy(&x, &y, fb, i);
                if (ret) {
                        DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
                                      i, fb->offsets[i]);
                        return ret;
                }

                if (is_ccs_modifier(fb->modifier) && i == 1) {
                        int hsub = fb->format->hsub;
                        int vsub = fb->format->vsub;
                        int tile_width, tile_height;
                        int main_x, main_y;
                        int ccs_x, ccs_y;

                        intel_tile_dims(fb, i, &tile_width, &tile_height);
                        tile_width *= hsub;
                        tile_height *= vsub;

                        ccs_x = (x * hsub) % tile_width;
                        ccs_y = (y * vsub) % tile_height;
                        main_x = intel_fb->normal[0].x % tile_width;
                        main_y = intel_fb->normal[0].y % tile_height;

                        /*
                         * CCS doesn't have its own x/y offset register, so the intra CCS tile
                         * x/y offsets must match between CCS and the main surface.
                         */
                        if (main_x != ccs_x || main_y != ccs_y) {
                                DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
                                              main_x, main_y,
                                              ccs_x, ccs_y,
                                              intel_fb->normal[0].x,
                                              intel_fb->normal[0].y,
                                              x, y);
                                return -EINVAL;
                        }
                }

                /*
                 * The fence (if used) is aligned to the start of the object
                 * so having the framebuffer wrap around across the edge of the
                 * fenced region doesn't really work. We have no API to configure
                 * the fence start offset within the object (nor could we probably
                 * on gen2/3). So it's just easier if we just require that the
                 * fb layout agrees with the fence layout. We already check that the
                 * fb stride matches the fence stride elsewhere.
                 */
                if (i == 0 && i915_gem_object_is_tiled(obj) &&
                    (x + width) * cpp > fb->pitches[i]) {
                        DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
                                      i, fb->offsets[i]);
                        return -EINVAL;
                }

                /*
                 * First pixel of the framebuffer from
                 * the start of the normal gtt mapping.
                 */
                intel_fb->normal[i].x = x;
                intel_fb->normal[i].y = y;

                offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
                                                      fb->pitches[i],
                                                      DRM_MODE_ROTATE_0,
                                                      tile_size);
                offset /= tile_size;

                if (!is_surface_linear(fb->modifier, i)) {
                        unsigned int tile_width, tile_height;
                        unsigned int pitch_tiles;
                        struct drm_rect r;

                        intel_tile_dims(fb, i, &tile_width, &tile_height);

                        rot_info->plane[i].offset = offset;
                        rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
                        rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
                        rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);

                        intel_fb->rotated[i].pitch =
                                rot_info->plane[i].height * tile_height;

                        /* how many tiles does this plane need */
                        size = rot_info->plane[i].stride * rot_info->plane[i].height;
                        /*
                         * If the plane isn't horizontally tile aligned,
                         * we need one more tile.
                         */
                        if (x != 0)
                                size++;

                        /* rotate the x/y offsets to match the GTT view */
                        r.x1 = x;
                        r.y1 = y;
                        r.x2 = x + width;
                        r.y2 = y + height;
                        drm_rect_rotate(&r,
                                        rot_info->plane[i].width * tile_width,
                                        rot_info->plane[i].height * tile_height,
                                        DRM_MODE_ROTATE_270);
                        x = r.x1;
                        y = r.y1;

                        /* rotate the tile dimensions to match the GTT view */
                        pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
                        swap(tile_width, tile_height);

                        /*
                         * We only keep the x/y offsets, so push all of the
                         * gtt offset into the x/y offsets.
                         */
                        intel_adjust_tile_offset(&x, &y,
                                                 tile_width, tile_height,
                                                 tile_size, pitch_tiles,
                                                 gtt_offset_rotated * tile_size, 0);

                        gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;

                        /*
                         * First pixel of the framebuffer from
                         * the start of the rotated gtt mapping.
                         */
                        intel_fb->rotated[i].x = x;
                        intel_fb->rotated[i].y = y;
                } else {
                        size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
                                            x * cpp, tile_size);
                }

                /* how many tiles in total needed in the bo */
                max_size = max(max_size, offset + size);
        }

        if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
                DRM_DEBUG_KMS("fb too big for bo (need %llu bytes, have %zu bytes)\n",
                              mul_u32_u32(max_size, tile_size), obj->base.size);
                return -EINVAL;
        }

        return 0;
}

static void
intel_plane_remap_gtt(struct intel_plane_state *plane_state)
{
        struct drm_i915_private *dev_priv =
                to_i915(plane_state->base.plane->dev);
        struct drm_framebuffer *fb = plane_state->base.fb;
        struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
        struct intel_rotation_info *info = &plane_state->view.rotated;
        unsigned int rotation = plane_state->base.rotation;
        int i, num_planes = fb->format->num_planes;
        unsigned int tile_size = intel_tile_size(dev_priv);
        unsigned int src_x, src_y;
        unsigned int src_w, src_h;
        u32 gtt_offset = 0;

        memset(&plane_state->view, 0, sizeof(plane_state->view));
        plane_state->view.type = drm_rotation_90_or_270(rotation) ?
                I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;

        src_x = plane_state->base.src.x1 >> 16;
        src_y = plane_state->base.src.y1 >> 16;
        src_w = drm_rect_width(&plane_state->base.src) >> 16;
        src_h = drm_rect_height(&plane_state->base.src) >> 16;

        WARN_ON(is_ccs_modifier(fb->modifier));

        /* Make src coordinates relative to the viewport */
        drm_rect_translate(&plane_state->base.src,
                           -(src_x << 16), -(src_y << 16));

        /* Rotate src coordinates to match rotated GTT view */
        if (drm_rotation_90_or_270(rotation))
                drm_rect_rotate(&plane_state->base.src,
                                src_w << 16, src_h << 16,
                                DRM_MODE_ROTATE_270);

        for (i = 0; i < num_planes; i++) {
                unsigned int hsub = i ? fb->format->hsub : 1;
                unsigned int vsub = i ? fb->format->vsub : 1;
                unsigned int cpp = fb->format->cpp[i];
                unsigned int tile_width, tile_height;
                unsigned int width, height;
                unsigned int pitch_tiles;
                unsigned int x, y;
                u32 offset;

                intel_tile_dims(fb, i, &tile_width, &tile_height);

                x = src_x / hsub;
                y = src_y / vsub;
                width = src_w / hsub;
                height = src_h / vsub;

                /*
                 * First pixel of the src viewport from the
                 * start of the normal gtt mapping.
                 */
                x += intel_fb->normal[i].x;
                y += intel_fb->normal[i].y;

                offset = intel_compute_aligned_offset(dev_priv, &x, &y,
                                                      fb, i, fb->pitches[i],
                                                      DRM_MODE_ROTATE_0, tile_size);
                offset /= tile_size;

                info->plane[i].offset = offset;
                info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
                                                     tile_width * cpp);
                info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
                info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);

                if (drm_rotation_90_or_270(rotation)) {
                        struct drm_rect r;

                        /* rotate the x/y offsets to match the GTT view */
                        r.x1 = x;
                        r.y1 = y;
                        r.x2 = x + width;
                        r.y2 = y + height;
                        drm_rect_rotate(&r,
                                        info->plane[i].width * tile_width,
                                        info->plane[i].height * tile_height,
                                        DRM_MODE_ROTATE_270);
                        x = r.x1;
                        y = r.y1;

                        pitch_tiles = info->plane[i].height;
                        plane_state->color_plane[i].stride = pitch_tiles * tile_height;

                        /* rotate the tile dimensions to match the GTT view */
                        swap(tile_width, tile_height);
                } else {
                        pitch_tiles = info->plane[i].width;
                        plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
                }

                /*
                 * We only keep the x/y offsets, so push all of the
                 * gtt offset into the x/y offsets.
                 */
                intel_adjust_tile_offset(&x, &y,
                                         tile_width, tile_height,
                                         tile_size, pitch_tiles,
                                         gtt_offset * tile_size, 0);

                gtt_offset += info->plane[i].width * info->plane[i].height;

                plane_state->color_plane[i].offset = 0;
                plane_state->color_plane[i].x = x;
                plane_state->color_plane[i].y = y;
        }
}

static int
intel_plane_compute_gtt(struct intel_plane_state *plane_state)
{
        const struct intel_framebuffer *fb =
                to_intel_framebuffer(plane_state->base.fb);
        unsigned int rotation = plane_state->base.rotation;
        int i, num_planes;

        if (!fb)
                return 0;

        num_planes = fb->base.format->num_planes;

        if (intel_plane_needs_remap(plane_state)) {
                intel_plane_remap_gtt(plane_state);

                /*
                 * Sometimes even remapping can't overcome
                 * the stride limitations :( Can happen with
                 * big plane sizes and suitably misaligned
                 * offsets.
                 */
                return intel_plane_check_stride(plane_state);
        }

        intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);

        for (i = 0; i < num_planes; i++) {
                plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
                plane_state->color_plane[i].offset = 0;

                if (drm_rotation_90_or_270(rotation)) {
                        plane_state->color_plane[i].x = fb->rotated[i].x;
                        plane_state->color_plane[i].y = fb->rotated[i].y;
                } else {
                        plane_state->color_plane[i].x = fb->normal[i].x;
                        plane_state->color_plane[i].y = fb->normal[i].y;
                }
        }

        /* Rotate src coordinates to match rotated GTT view */
        if (drm_rotation_90_or_270(rotation))
                drm_rect_rotate(&plane_state->base.src,
                                fb->base.width << 16, fb->base.height << 16,
                                DRM_MODE_ROTATE_270);

        return intel_plane_check_stride(plane_state);
}

static int i9xx_format_to_fourcc(int format)
{
        switch (format) {
        case DISPPLANE_8BPP:
                return DRM_FORMAT_C8;
        case DISPPLANE_BGRX555:
                return DRM_FORMAT_XRGB1555;
        case DISPPLANE_BGRX565:
                return DRM_FORMAT_RGB565;
        default:
        case DISPPLANE_BGRX888:
                return DRM_FORMAT_XRGB8888;
        case DISPPLANE_RGBX888:
                return DRM_FORMAT_XBGR8888;
        case DISPPLANE_BGRX101010:
                return DRM_FORMAT_XRGB2101010;
        case DISPPLANE_RGBX101010:
                return DRM_FORMAT_XBGR2101010;
        }
}

int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
{
        switch (format) {
        case PLANE_CTL_FORMAT_RGB_565:
                return DRM_FORMAT_RGB565;
        case PLANE_CTL_FORMAT_NV12:
                return DRM_FORMAT_NV12;
        case PLANE_CTL_FORMAT_P010:
                return DRM_FORMAT_P010;
        case PLANE_CTL_FORMAT_P012:
                return DRM_FORMAT_P012;
        case PLANE_CTL_FORMAT_P016:
                return DRM_FORMAT_P016;
        case PLANE_CTL_FORMAT_Y210:
                return DRM_FORMAT_Y210;
        case PLANE_CTL_FORMAT_Y212:
                return DRM_FORMAT_Y212;
        case PLANE_CTL_FORMAT_Y216:
                return DRM_FORMAT_Y216;
        case PLANE_CTL_FORMAT_Y410:
                return DRM_FORMAT_XVYU2101010;
        case PLANE_CTL_FORMAT_Y412:
                return DRM_FORMAT_XVYU12_16161616;
        case PLANE_CTL_FORMAT_Y416:
                return DRM_FORMAT_XVYU16161616;
        default: