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39#ifndef __BNXT_QPLIB_RCFW_H__
40#define __BNXT_QPLIB_RCFW_H__
41
42#define RCFW_CMDQ_TRIG_VAL 1
43#define RCFW_COMM_PCI_BAR_REGION 0
44#define RCFW_COMM_CONS_PCI_BAR_REGION 2
45#define RCFW_COMM_BASE_OFFSET 0x600
46#define RCFW_PF_COMM_PROD_OFFSET 0xc
47#define RCFW_VF_COMM_PROD_OFFSET 0xc
48#define RCFW_COMM_TRIG_OFFSET 0x100
49#define RCFW_COMM_SIZE 0x104
50
51#define RCFW_DBR_PCI_BAR_REGION 2
52#define RCFW_DBR_BASE_PAGE_SHIFT 12
53
54#define RCFW_CMD_PREP(req, CMD, cmd_flags) \
55 do { \
56 memset(&(req), 0, sizeof((req))); \
57 (req).opcode = CMDQ_BASE_OPCODE_##CMD; \
58 (req).cmd_size = sizeof((req)); \
59 (req).flags = cpu_to_le16(cmd_flags); \
60 } while (0)
61
62#define RCFW_CMD_WAIT_TIME_MS 20000
63
64
65struct bnxt_qplib_cmdqe {
66 u8 data[16];
67};
68
69
70#define BNXT_QPLIB_CMDQE_MAX_CNT_256 256
71#define BNXT_QPLIB_CMDQE_MAX_CNT_8192 8192
72#define BNXT_QPLIB_CMDQE_UNITS sizeof(struct bnxt_qplib_cmdqe)
73#define BNXT_QPLIB_CMDQE_BYTES(depth) ((depth) * BNXT_QPLIB_CMDQE_UNITS)
74
75static inline u32 bnxt_qplib_cmdqe_npages(u32 depth)
76{
77 u32 npages;
78
79 npages = BNXT_QPLIB_CMDQE_BYTES(depth) / PAGE_SIZE;
80 if (BNXT_QPLIB_CMDQE_BYTES(depth) % PAGE_SIZE)
81 npages++;
82 return npages;
83}
84
85static inline u32 bnxt_qplib_cmdqe_page_size(u32 depth)
86{
87 return (bnxt_qplib_cmdqe_npages(depth) * PAGE_SIZE);
88}
89
90static inline u32 bnxt_qplib_cmdqe_cnt_per_pg(u32 depth)
91{
92 return (bnxt_qplib_cmdqe_page_size(depth) /
93 BNXT_QPLIB_CMDQE_UNITS);
94}
95
96
97static inline void bnxt_qplib_set_cmd_slots(struct cmdq_base *req)
98{
99 req->cmd_size = (req->cmd_size + BNXT_QPLIB_CMDQE_UNITS - 1) /
100 BNXT_QPLIB_CMDQE_UNITS;
101}
102
103#define MAX_CMDQ_IDX(depth) ((depth) - 1)
104
105static inline u32 bnxt_qplib_max_cmdq_idx_per_pg(u32 depth)
106{
107 return (bnxt_qplib_cmdqe_cnt_per_pg(depth) - 1);
108}
109
110#define RCFW_MAX_COOKIE_VALUE 0x7FFF
111#define RCFW_CMD_IS_BLOCKING 0x8000
112#define RCFW_BLOCKED_CMD_WAIT_COUNT 0x4E20
113
114#define HWRM_VERSION_RCFW_CMDQ_DEPTH_CHECK 0x1000900020011ULL
115
116static inline u32 get_cmdq_pg(u32 val, u32 depth)
117{
118 return (val & ~(bnxt_qplib_max_cmdq_idx_per_pg(depth))) /
119 (bnxt_qplib_cmdqe_cnt_per_pg(depth));
120}
121
122static inline u32 get_cmdq_idx(u32 val, u32 depth)
123{
124 return val & (bnxt_qplib_max_cmdq_idx_per_pg(depth));
125}
126
127
128struct bnxt_qplib_crsbe {
129 u8 data[1024];
130};
131
132
133
134#define BNXT_QPLIB_CREQE_MAX_CNT (64 * 1024)
135#define BNXT_QPLIB_CREQE_UNITS 16
136#define BNXT_QPLIB_CREQE_CNT_PER_PG (PAGE_SIZE / BNXT_QPLIB_CREQE_UNITS)
137
138#define MAX_CREQ_IDX (BNXT_QPLIB_CREQE_MAX_CNT - 1)
139#define MAX_CREQ_IDX_PER_PG (BNXT_QPLIB_CREQE_CNT_PER_PG - 1)
140
141static inline u32 get_creq_pg(u32 val)
142{
143 return (val & ~MAX_CREQ_IDX_PER_PG) / BNXT_QPLIB_CREQE_CNT_PER_PG;
144}
145
146static inline u32 get_creq_idx(u32 val)
147{
148 return val & MAX_CREQ_IDX_PER_PG;
149}
150
151#define BNXT_QPLIB_CREQE_PER_PG (PAGE_SIZE / sizeof(struct creq_base))
152
153#define CREQ_CMP_VALID(hdr, raw_cons, cp_bit) \
154 (!!((hdr)->v & CREQ_BASE_V) == \
155 !((raw_cons) & (cp_bit)))
156
157#define CREQ_DB_KEY_CP (0x2 << CMPL_DOORBELL_KEY_SFT)
158#define CREQ_DB_IDX_VALID CMPL_DOORBELL_IDX_VALID
159#define CREQ_DB_IRQ_DIS CMPL_DOORBELL_MASK
160#define CREQ_DB_CP_FLAGS_REARM (CREQ_DB_KEY_CP | \
161 CREQ_DB_IDX_VALID)
162#define CREQ_DB_CP_FLAGS (CREQ_DB_KEY_CP | \
163 CREQ_DB_IDX_VALID | \
164 CREQ_DB_IRQ_DIS)
165
166static inline void bnxt_qplib_ring_creq_db64(void __iomem *db, u32 index,
167 u32 xid, bool arm)
168{
169 u64 val = 0;
170
171 val = xid & DBC_DBC_XID_MASK;
172 val |= DBC_DBC_PATH_ROCE;
173 val |= arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ;
174 val <<= 32;
175 val |= index & DBC_DBC_INDEX_MASK;
176
177 writeq(val, db);
178}
179
180static inline void bnxt_qplib_ring_creq_db_rearm(void __iomem *db, u32 raw_cons,
181 u32 max_elements, u32 xid,
182 bool gen_p5)
183{
184 u32 index = raw_cons & (max_elements - 1);
185
186 if (gen_p5)
187 bnxt_qplib_ring_creq_db64(db, index, xid, true);
188 else
189 writel(CREQ_DB_CP_FLAGS_REARM | (index & DBC_DBC32_XID_MASK),
190 db);
191}
192
193static inline void bnxt_qplib_ring_creq_db(void __iomem *db, u32 raw_cons,
194 u32 max_elements, u32 xid,
195 bool gen_p5)
196{
197 u32 index = raw_cons & (max_elements - 1);
198
199 if (gen_p5)
200 bnxt_qplib_ring_creq_db64(db, index, xid, true);
201 else
202 writel(CREQ_DB_CP_FLAGS | (index & DBC_DBC32_XID_MASK),
203 db);
204}
205
206#define CREQ_ENTRY_POLL_BUDGET 0x100
207
208
209
210struct bnxt_qplib_crsq {
211 struct creq_qp_event *resp;
212 u32 req_size;
213};
214
215struct bnxt_qplib_rcfw_sbuf {
216 void *sb;
217 dma_addr_t dma_addr;
218 u32 size;
219};
220
221struct bnxt_qplib_qp_node {
222 u32 qp_id;
223 void *qp_handle;
224};
225
226#define BNXT_QPLIB_OOS_COUNT_MASK 0xFFFFFFFF
227
228
229struct bnxt_qplib_rcfw {
230 struct pci_dev *pdev;
231 struct bnxt_qplib_res *res;
232 int vector;
233 struct tasklet_struct worker;
234 bool requested;
235 unsigned long *cmdq_bitmap;
236 u32 bmap_size;
237 unsigned long flags;
238#define FIRMWARE_INITIALIZED_FLAG 0
239#define FIRMWARE_FIRST_FLAG 31
240#define FIRMWARE_TIMED_OUT 3
241 wait_queue_head_t waitq;
242 int (*aeq_handler)(struct bnxt_qplib_rcfw *,
243 void *, void *);
244 u32 seq_num;
245
246
247 void __iomem *cmdq_bar_reg_iomem;
248 u16 cmdq_bar_reg;
249 u16 cmdq_bar_reg_prod_off;
250 u16 cmdq_bar_reg_trig_off;
251 u16 creq_ring_id;
252 u16 creq_bar_reg;
253 void __iomem *creq_bar_reg_iomem;
254
255
256 struct bnxt_qplib_hwq creq;
257 u64 creq_qp_event_processed;
258 u64 creq_func_event_processed;
259
260
261 struct bnxt_qplib_hwq cmdq;
262 struct bnxt_qplib_crsq *crsqe_tbl;
263 int qp_tbl_size;
264 struct bnxt_qplib_qp_node *qp_tbl;
265 u64 oos_prev;
266 u32 init_oos_stats;
267 u32 cmdq_depth;
268};
269
270void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);
271int bnxt_qplib_alloc_rcfw_channel(struct pci_dev *pdev,
272 struct bnxt_qplib_rcfw *rcfw,
273 struct bnxt_qplib_ctx *ctx,
274 int qp_tbl_sz);
275void bnxt_qplib_rcfw_stop_irq(struct bnxt_qplib_rcfw *rcfw, bool kill);
276void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);
277int bnxt_qplib_rcfw_start_irq(struct bnxt_qplib_rcfw *rcfw, int msix_vector,
278 bool need_init);
279int bnxt_qplib_enable_rcfw_channel(struct pci_dev *pdev,
280 struct bnxt_qplib_rcfw *rcfw,
281 int msix_vector,
282 int cp_bar_reg_off, int virt_fn,
283 int (*aeq_handler)(struct bnxt_qplib_rcfw *,
284 void *aeqe, void *obj));
285
286struct bnxt_qplib_rcfw_sbuf *bnxt_qplib_rcfw_alloc_sbuf(
287 struct bnxt_qplib_rcfw *rcfw,
288 u32 size);
289void bnxt_qplib_rcfw_free_sbuf(struct bnxt_qplib_rcfw *rcfw,
290 struct bnxt_qplib_rcfw_sbuf *sbuf);
291int bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw,
292 struct cmdq_base *req, struct creq_base *resp,
293 void *sbuf, u8 is_block);
294
295int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw);
296int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw,
297 struct bnxt_qplib_ctx *ctx, int is_virtfn);
298void bnxt_qplib_mark_qp_error(void *qp_handle);
299#endif
300
