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9#ifndef __SDHCI_HW_H
10#define __SDHCI_HW_H
11
12#include <linux/scatterlist.h>
13#include <linux/compiler.h>
14#include <linux/types.h>
15#include <linux/io.h>
16#include <linux/leds.h>
17#include <linux/interrupt.h>
18
19#include <linux/mmc/host.h>
20
21
22
23
24
25#define SDHCI_DMA_ADDRESS 0x00
26#define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS
27#define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS
28
29#define SDHCI_BLOCK_SIZE 0x04
30#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
31
32#define SDHCI_BLOCK_COUNT 0x06
33
34#define SDHCI_ARGUMENT 0x08
35
36#define SDHCI_TRANSFER_MODE 0x0C
37#define SDHCI_TRNS_DMA 0x01
38#define SDHCI_TRNS_BLK_CNT_EN 0x02
39#define SDHCI_TRNS_AUTO_CMD12 0x04
40#define SDHCI_TRNS_AUTO_CMD23 0x08
41#define SDHCI_TRNS_AUTO_SEL 0x0C
42#define SDHCI_TRNS_READ 0x10
43#define SDHCI_TRNS_MULTI 0x20
44
45#define SDHCI_COMMAND 0x0E
46#define SDHCI_CMD_RESP_MASK 0x03
47#define SDHCI_CMD_CRC 0x08
48#define SDHCI_CMD_INDEX 0x10
49#define SDHCI_CMD_DATA 0x20
50#define SDHCI_CMD_ABORTCMD 0xC0
51
52#define SDHCI_CMD_RESP_NONE 0x00
53#define SDHCI_CMD_RESP_LONG 0x01
54#define SDHCI_CMD_RESP_SHORT 0x02
55#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
56
57#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
58#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
59
60#define SDHCI_RESPONSE 0x10
61
62#define SDHCI_BUFFER 0x20
63
64#define SDHCI_PRESENT_STATE 0x24
65#define SDHCI_CMD_INHIBIT 0x00000001
66#define SDHCI_DATA_INHIBIT 0x00000002
67#define SDHCI_DOING_WRITE 0x00000100
68#define SDHCI_DOING_READ 0x00000200
69#define SDHCI_SPACE_AVAILABLE 0x00000400
70#define SDHCI_DATA_AVAILABLE 0x00000800
71#define SDHCI_CARD_PRESENT 0x00010000
72#define SDHCI_CARD_PRES_SHIFT 16
73#define SDHCI_CD_STABLE 0x00020000
74#define SDHCI_CD_LVL 0x00040000
75#define SDHCI_CD_LVL_SHIFT 18
76#define SDHCI_WRITE_PROTECT 0x00080000
77#define SDHCI_DATA_LVL_MASK 0x00F00000
78#define SDHCI_DATA_LVL_SHIFT 20
79#define SDHCI_DATA_0_LVL_MASK 0x00100000
80#define SDHCI_CMD_LVL 0x01000000
81
82#define SDHCI_HOST_CONTROL 0x28
83#define SDHCI_CTRL_LED 0x01
84#define SDHCI_CTRL_4BITBUS 0x02
85#define SDHCI_CTRL_HISPD 0x04
86#define SDHCI_CTRL_DMA_MASK 0x18
87#define SDHCI_CTRL_SDMA 0x00
88#define SDHCI_CTRL_ADMA1 0x08
89#define SDHCI_CTRL_ADMA32 0x10
90#define SDHCI_CTRL_ADMA64 0x18
91#define SDHCI_CTRL_ADMA3 0x18
92#define SDHCI_CTRL_8BITBUS 0x20
93#define SDHCI_CTRL_CDTEST_INS 0x40
94#define SDHCI_CTRL_CDTEST_EN 0x80
95
96#define SDHCI_POWER_CONTROL 0x29
97#define SDHCI_POWER_ON 0x01
98#define SDHCI_POWER_180 0x0A
99#define SDHCI_POWER_300 0x0C
100#define SDHCI_POWER_330 0x0E
101
102#define SDHCI_BLOCK_GAP_CONTROL 0x2A
103
104#define SDHCI_WAKE_UP_CONTROL 0x2B
105#define SDHCI_WAKE_ON_INT 0x01
106#define SDHCI_WAKE_ON_INSERT 0x02
107#define SDHCI_WAKE_ON_REMOVE 0x04
108
109#define SDHCI_CLOCK_CONTROL 0x2C
110#define SDHCI_DIVIDER_SHIFT 8
111#define SDHCI_DIVIDER_HI_SHIFT 6
112#define SDHCI_DIV_MASK 0xFF
113#define SDHCI_DIV_MASK_LEN 8
114#define SDHCI_DIV_HI_MASK 0x300
115#define SDHCI_PROG_CLOCK_MODE 0x0020
116#define SDHCI_CLOCK_CARD_EN 0x0004
117#define SDHCI_CLOCK_PLL_EN 0x0008
118#define SDHCI_CLOCK_INT_STABLE 0x0002
119#define SDHCI_CLOCK_INT_EN 0x0001
120
121#define SDHCI_TIMEOUT_CONTROL 0x2E
122
123#define SDHCI_SOFTWARE_RESET 0x2F
124#define SDHCI_RESET_ALL 0x01
125#define SDHCI_RESET_CMD 0x02
126#define SDHCI_RESET_DATA 0x04
127
128#define SDHCI_INT_STATUS 0x30
129#define SDHCI_INT_ENABLE 0x34
130#define SDHCI_SIGNAL_ENABLE 0x38
131#define SDHCI_INT_RESPONSE 0x00000001
132#define SDHCI_INT_DATA_END 0x00000002
133#define SDHCI_INT_BLK_GAP 0x00000004
134#define SDHCI_INT_DMA_END 0x00000008
135#define SDHCI_INT_SPACE_AVAIL 0x00000010
136#define SDHCI_INT_DATA_AVAIL 0x00000020
137#define SDHCI_INT_CARD_INSERT 0x00000040
138#define SDHCI_INT_CARD_REMOVE 0x00000080
139#define SDHCI_INT_CARD_INT 0x00000100
140#define SDHCI_INT_RETUNE 0x00001000
141#define SDHCI_INT_CQE 0x00004000
142#define SDHCI_INT_ERROR 0x00008000
143#define SDHCI_INT_TIMEOUT 0x00010000
144#define SDHCI_INT_CRC 0x00020000
145#define SDHCI_INT_END_BIT 0x00040000
146#define SDHCI_INT_INDEX 0x00080000
147#define SDHCI_INT_DATA_TIMEOUT 0x00100000
148#define SDHCI_INT_DATA_CRC 0x00200000
149#define SDHCI_INT_DATA_END_BIT 0x00400000
150#define SDHCI_INT_BUS_POWER 0x00800000
151#define SDHCI_INT_AUTO_CMD_ERR 0x01000000
152#define SDHCI_INT_ADMA_ERROR 0x02000000
153
154#define SDHCI_INT_NORMAL_MASK 0x00007FFF
155#define SDHCI_INT_ERROR_MASK 0xFFFF8000
156
157#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
158 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \
159 SDHCI_INT_AUTO_CMD_ERR)
160#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
161 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
162 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
163 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \
164 SDHCI_INT_BLK_GAP)
165#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
166
167#define SDHCI_CQE_INT_ERR_MASK ( \
168 SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | \
169 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | \
170 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)
171
172#define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE)
173
174#define SDHCI_AUTO_CMD_STATUS 0x3C
175#define SDHCI_AUTO_CMD_TIMEOUT 0x00000002
176#define SDHCI_AUTO_CMD_CRC 0x00000004
177#define SDHCI_AUTO_CMD_END_BIT 0x00000008
178#define SDHCI_AUTO_CMD_INDEX 0x00000010
179
180#define SDHCI_HOST_CONTROL2 0x3E
181#define SDHCI_CTRL_UHS_MASK 0x0007
182#define SDHCI_CTRL_UHS_SDR12 0x0000
183#define SDHCI_CTRL_UHS_SDR25 0x0001
184#define SDHCI_CTRL_UHS_SDR50 0x0002
185#define SDHCI_CTRL_UHS_SDR104 0x0003
186#define SDHCI_CTRL_UHS_DDR50 0x0004
187#define SDHCI_CTRL_HS400 0x0005
188#define SDHCI_CTRL_VDD_180 0x0008
189#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
190#define SDHCI_CTRL_DRV_TYPE_B 0x0000
191#define SDHCI_CTRL_DRV_TYPE_A 0x0010
192#define SDHCI_CTRL_DRV_TYPE_C 0x0020
193#define SDHCI_CTRL_DRV_TYPE_D 0x0030
194#define SDHCI_CTRL_EXEC_TUNING 0x0040
195#define SDHCI_CTRL_TUNED_CLK 0x0080
196#define SDHCI_CMD23_ENABLE 0x0800
197#define SDHCI_CTRL_V4_MODE 0x1000
198#define SDHCI_CTRL_64BIT_ADDR 0x2000
199#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
200
201#define SDHCI_CAPABILITIES 0x40
202#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
203#define SDHCI_TIMEOUT_CLK_SHIFT 0
204#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
205#define SDHCI_CLOCK_BASE_MASK 0x00003F00
206#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
207#define SDHCI_CLOCK_BASE_SHIFT 8
208#define SDHCI_MAX_BLOCK_MASK 0x00030000
209#define SDHCI_MAX_BLOCK_SHIFT 16
210#define SDHCI_CAN_DO_8BIT 0x00040000
211#define SDHCI_CAN_DO_ADMA2 0x00080000
212#define SDHCI_CAN_DO_ADMA1 0x00100000
213#define SDHCI_CAN_DO_HISPD 0x00200000
214#define SDHCI_CAN_DO_SDMA 0x00400000
215#define SDHCI_CAN_DO_SUSPEND 0x00800000
216#define SDHCI_CAN_VDD_330 0x01000000
217#define SDHCI_CAN_VDD_300 0x02000000
218#define SDHCI_CAN_VDD_180 0x04000000
219#define SDHCI_CAN_64BIT_V4 0x08000000
220#define SDHCI_CAN_64BIT 0x10000000
221
222#define SDHCI_SUPPORT_SDR50 0x00000001
223#define SDHCI_SUPPORT_SDR104 0x00000002
224#define SDHCI_SUPPORT_DDR50 0x00000004
225#define SDHCI_DRIVER_TYPE_A 0x00000010
226#define SDHCI_DRIVER_TYPE_C 0x00000020
227#define SDHCI_DRIVER_TYPE_D 0x00000040
228#define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00
229#define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8
230#define SDHCI_USE_SDR50_TUNING 0x00002000
231#define SDHCI_RETUNING_MODE_MASK 0x0000C000
232#define SDHCI_RETUNING_MODE_SHIFT 14
233#define SDHCI_CLOCK_MUL_MASK 0x00FF0000
234#define SDHCI_CLOCK_MUL_SHIFT 16
235#define SDHCI_CAN_DO_ADMA3 0x08000000
236#define SDHCI_SUPPORT_HS400 0x80000000
237
238#define SDHCI_CAPABILITIES_1 0x44
239
240#define SDHCI_MAX_CURRENT 0x48
241#define SDHCI_MAX_CURRENT_LIMIT 0xFF
242#define SDHCI_MAX_CURRENT_330_MASK 0x0000FF
243#define SDHCI_MAX_CURRENT_330_SHIFT 0
244#define SDHCI_MAX_CURRENT_300_MASK 0x00FF00
245#define SDHCI_MAX_CURRENT_300_SHIFT 8
246#define SDHCI_MAX_CURRENT_180_MASK 0xFF0000
247#define SDHCI_MAX_CURRENT_180_SHIFT 16
248#define SDHCI_MAX_CURRENT_MULTIPLIER 4
249
250
251
252#define SDHCI_SET_ACMD12_ERROR 0x50
253#define SDHCI_SET_INT_ERROR 0x52
254
255#define SDHCI_ADMA_ERROR 0x54
256
257
258
259#define SDHCI_ADMA_ADDRESS 0x58
260#define SDHCI_ADMA_ADDRESS_HI 0x5C
261
262
263
264#define SDHCI_PRESET_FOR_SDR12 0x66
265#define SDHCI_PRESET_FOR_SDR25 0x68
266#define SDHCI_PRESET_FOR_SDR50 0x6A
267#define SDHCI_PRESET_FOR_SDR104 0x6C
268#define SDHCI_PRESET_FOR_DDR50 0x6E
269#define SDHCI_PRESET_FOR_HS400 0x74
270#define SDHCI_PRESET_DRV_MASK 0xC000
271#define SDHCI_PRESET_DRV_SHIFT 14
272#define SDHCI_PRESET_CLKGEN_SEL_MASK 0x400
273#define SDHCI_PRESET_CLKGEN_SEL_SHIFT 10
274#define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF
275#define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0
276
277#define SDHCI_SLOT_INT_STATUS 0xFC
278
279#define SDHCI_HOST_VERSION 0xFE
280#define SDHCI_VENDOR_VER_MASK 0xFF00
281#define SDHCI_VENDOR_VER_SHIFT 8
282#define SDHCI_SPEC_VER_MASK 0x00FF
283#define SDHCI_SPEC_VER_SHIFT 0
284#define SDHCI_SPEC_100 0
285#define SDHCI_SPEC_200 1
286#define SDHCI_SPEC_300 2
287#define SDHCI_SPEC_400 3
288#define SDHCI_SPEC_410 4
289#define SDHCI_SPEC_420 5
290
291
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293
294
295#define SDHCI_MAX_DIV_SPEC_200 256
296#define SDHCI_MAX_DIV_SPEC_300 2046
297
298
299
300
301#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
302#define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
303
304
305#define SDHCI_ADMA2_32_DESC_SZ 8
306
307
308struct sdhci_adma2_32_desc {
309 __le16 cmd;
310 __le16 len;
311 __le32 addr;
312} __packed __aligned(4);
313
314
315#define SDHCI_ADMA2_ALIGN 4
316#define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1)
317
318
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320
321
322
323#define SDHCI_ADMA2_DESC_ALIGN 8
324
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331
332#define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12)
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336
337
338struct sdhci_adma2_64_desc {
339 __le16 cmd;
340 __le16 len;
341 __le32 addr_lo;
342 __le32 addr_hi;
343} __packed __aligned(4);
344
345#define ADMA2_TRAN_VALID 0x21
346#define ADMA2_NOP_END_VALID 0x3
347#define ADMA2_END 0x2
348
349
350
351
352
353#define SDHCI_MAX_SEGS 128
354
355
356#define SDHCI_MAX_MRQS 2
357
358
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361
362
363
364#define MMC_CMD_TRANSFER_TIME (10 * NSEC_PER_MSEC)
365
366enum sdhci_cookie {
367 COOKIE_UNMAPPED,
368 COOKIE_PRE_MAPPED,
369 COOKIE_MAPPED,
370};
371
372struct sdhci_host {
373
374 const char *hw_name;
375
376 unsigned int quirks;
377
378
379#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
380
381#define SDHCI_QUIRK_FORCE_DMA (1<<1)
382
383#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
384
385#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
386
387#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
388
389#define SDHCI_QUIRK_BROKEN_DMA (1<<5)
390
391#define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
392
393#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
394
395#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)
396
397#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)
398
399#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)
400
401#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)
402
403#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
404
405#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13)
406
407#define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14)
408
409#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
410
411#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
412
413#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)
414
415#define SDHCI_QUIRK_NO_LED (1<<19)
416
417#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)
418
419#define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21)
420
421#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)
422
423#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)
424
425#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24)
426
427#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25)
428
429#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26)
430
431#define SDHCI_QUIRK_MISSING_CAPS (1<<27)
432
433#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28)
434
435#define SDHCI_QUIRK_NO_HISPD_BIT (1<<29)
436
437#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30)
438
439#define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31)
440
441 unsigned int quirks2;
442
443#define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0)
444#define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1)
445
446#define SDHCI_QUIRK2_NO_1_8_V (1<<2)
447#define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3)
448#define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4)
449
450#define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5)
451
452#define SDHCI_QUIRK2_BROKEN_HS200 (1<<6)
453
454#define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7)
455
456#define SDHCI_QUIRK2_STOP_WITH_TC (1<<8)
457
458#define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9)
459
460#define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10)
461
462#define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11)
463
464#define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12)
465
466#define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13)
467
468#define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14)
469
470#define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15)
471
472#define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16)
473
474
475
476
477#define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17)
478
479
480
481
482
483
484#define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18)
485
486 int irq;
487 void __iomem *ioaddr;
488 char *bounce_buffer;
489 dma_addr_t bounce_addr;
490 unsigned int bounce_buffer_size;
491
492 const struct sdhci_ops *ops;
493
494
495 struct mmc_host *mmc;
496 struct mmc_host_ops mmc_host_ops;
497 u64 dma_mask;
498
499#if IS_ENABLED(CONFIG_LEDS_CLASS)
500 struct led_classdev led;
501 char led_name[32];
502#endif
503
504 spinlock_t lock;
505
506 int flags;
507#define SDHCI_USE_SDMA (1<<0)
508#define SDHCI_USE_ADMA (1<<1)
509#define SDHCI_REQ_USE_DMA (1<<2)
510#define SDHCI_DEVICE_DEAD (1<<3)
511#define SDHCI_SDR50_NEEDS_TUNING (1<<4)
512#define SDHCI_AUTO_CMD12 (1<<6)
513#define SDHCI_AUTO_CMD23 (1<<7)
514#define SDHCI_PV_ENABLED (1<<8)
515#define SDHCI_USE_64_BIT_DMA (1<<12)
516#define SDHCI_HS400_TUNING (1<<13)
517#define SDHCI_SIGNALING_330 (1<<14)
518#define SDHCI_SIGNALING_180 (1<<15)
519#define SDHCI_SIGNALING_120 (1<<16)
520
521 unsigned int version;
522
523 unsigned int max_clk;
524 unsigned int timeout_clk;
525 unsigned int clk_mul;
526
527 unsigned int clock;
528 u8 pwr;
529
530 bool runtime_suspended;
531 bool bus_on;
532 bool preset_enabled;
533 bool pending_reset;
534 bool irq_wake_enabled;
535 bool v4_mode;
536
537 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS];
538 struct mmc_command *cmd;
539 struct mmc_command *data_cmd;
540 struct mmc_data *data;
541 unsigned int data_early:1;
542
543 struct sg_mapping_iter sg_miter;
544 unsigned int blocks;
545
546 int sg_count;
547
548 void *adma_table;
549 void *align_buffer;
550
551 size_t adma_table_sz;
552 size_t align_buffer_sz;
553
554 dma_addr_t adma_addr;
555 dma_addr_t align_addr;
556
557 unsigned int desc_sz;
558
559 struct workqueue_struct *complete_wq;
560 struct work_struct complete_work;
561
562 struct timer_list timer;
563 struct timer_list data_timer;
564
565 u32 caps;
566 u32 caps1;
567 bool read_caps;
568
569 unsigned int ocr_avail_sdio;
570 unsigned int ocr_avail_sd;
571 unsigned int ocr_avail_mmc;
572 u32 ocr_mask;
573
574 unsigned timing;
575
576 u32 thread_isr;
577
578
579 u32 ier;
580
581 bool cqe_on;
582 u32 cqe_ier;
583 u32 cqe_err_ier;
584
585 wait_queue_head_t buf_ready_int;
586 unsigned int tuning_done;
587
588 unsigned int tuning_count;
589 unsigned int tuning_mode;
590 unsigned int tuning_err;
591#define SDHCI_TUNING_MODE_1 0
592#define SDHCI_TUNING_MODE_2 1
593#define SDHCI_TUNING_MODE_3 2
594
595 int tuning_delay;
596 int tuning_loop_count;
597
598
599 u32 sdma_boundary;
600
601
602 u32 adma_table_cnt;
603
604 u64 data_timeout;
605
606 unsigned long private[0] ____cacheline_aligned;
607};
608
609struct sdhci_ops {
610#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
611 u32 (*read_l)(struct sdhci_host *host, int reg);
612 u16 (*read_w)(struct sdhci_host *host, int reg);
613 u8 (*read_b)(struct sdhci_host *host, int reg);
614 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
615 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
616 void (*write_b)(struct sdhci_host *host, u8 val, int reg);
617#endif
618
619 void (*set_clock)(struct sdhci_host *host, unsigned int clock);
620 void (*set_power)(struct sdhci_host *host, unsigned char mode,
621 unsigned short vdd);
622
623 u32 (*irq)(struct sdhci_host *host, u32 intmask);
624
625 int (*set_dma_mask)(struct sdhci_host *host);
626 int (*enable_dma)(struct sdhci_host *host);
627 unsigned int (*get_max_clock)(struct sdhci_host *host);
628 unsigned int (*get_min_clock)(struct sdhci_host *host);
629
630 unsigned int (*get_timeout_clock)(struct sdhci_host *host);
631 unsigned int (*get_max_timeout_count)(struct sdhci_host *host);
632 void (*set_timeout)(struct sdhci_host *host,
633 struct mmc_command *cmd);
634 void (*set_bus_width)(struct sdhci_host *host, int width);
635 void (*platform_send_init_74_clocks)(struct sdhci_host *host,
636 u8 power_mode);
637 unsigned int (*get_ro)(struct sdhci_host *host);
638 void (*reset)(struct sdhci_host *host, u8 mask);
639 int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
640 void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
641 void (*hw_reset)(struct sdhci_host *host);
642 void (*adma_workaround)(struct sdhci_host *host, u32 intmask);
643 void (*card_event)(struct sdhci_host *host);
644 void (*voltage_switch)(struct sdhci_host *host);
645 void (*adma_write_desc)(struct sdhci_host *host, void **desc,
646 dma_addr_t addr, int len, unsigned int cmd);
647};
648
649#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
650
651static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
652{
653 if (unlikely(host->ops->write_l))
654 host->ops->write_l(host, val, reg);
655 else
656 writel(val, host->ioaddr + reg);
657}
658
659static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
660{
661 if (unlikely(host->ops->write_w))
662 host->ops->write_w(host, val, reg);
663 else
664 writew(val, host->ioaddr + reg);
665}
666
667static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
668{
669 if (unlikely(host->ops->write_b))
670 host->ops->write_b(host, val, reg);
671 else
672 writeb(val, host->ioaddr + reg);
673}
674
675static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
676{
677 if (unlikely(host->ops->read_l))
678 return host->ops->read_l(host, reg);
679 else
680 return readl(host->ioaddr + reg);
681}
682
683static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
684{
685 if (unlikely(host->ops->read_w))
686 return host->ops->read_w(host, reg);
687 else
688 return readw(host->ioaddr + reg);
689}
690
691static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
692{
693 if (unlikely(host->ops->read_b))
694 return host->ops->read_b(host, reg);
695 else
696 return readb(host->ioaddr + reg);
697}
698
699#else
700
701static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
702{
703 writel(val, host->ioaddr + reg);
704}
705
706static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
707{
708 writew(val, host->ioaddr + reg);
709}
710
711static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
712{
713 writeb(val, host->ioaddr + reg);
714}
715
716static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
717{
718 return readl(host->ioaddr + reg);
719}
720
721static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
722{
723 return readw(host->ioaddr + reg);
724}
725
726static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
727{
728 return readb(host->ioaddr + reg);
729}
730
731#endif
732
733struct sdhci_host *sdhci_alloc_host(struct device *dev, size_t priv_size);
734void sdhci_free_host(struct sdhci_host *host);
735
736static inline void *sdhci_priv(struct sdhci_host *host)
737{
738 return host->private;
739}
740
741void sdhci_card_detect(struct sdhci_host *host);
742void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
743 const u32 *caps, const u32 *caps1);
744int sdhci_setup_host(struct sdhci_host *host);
745void sdhci_cleanup_host(struct sdhci_host *host);
746int __sdhci_add_host(struct sdhci_host *host);
747int sdhci_add_host(struct sdhci_host *host);
748void sdhci_remove_host(struct sdhci_host *host, int dead);
749void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd);
750
751static inline void sdhci_read_caps(struct sdhci_host *host)
752{
753 __sdhci_read_caps(host, NULL, NULL, NULL);
754}
755
756u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
757 unsigned int *actual_clock);
758void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
759void sdhci_enable_clk(struct sdhci_host *host, u16 clk);
760void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
761 unsigned short vdd);
762void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
763 unsigned short vdd);
764void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq);
765void sdhci_set_bus_width(struct sdhci_host *host, int width);
766void sdhci_reset(struct sdhci_host *host, u8 mask);
767void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
768int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
769void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
770int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
771 struct mmc_ios *ios);
772void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable);
773void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
774 dma_addr_t addr, int len, unsigned int cmd);
775
776#ifdef CONFIG_PM
777int sdhci_suspend_host(struct sdhci_host *host);
778int sdhci_resume_host(struct sdhci_host *host);
779int sdhci_runtime_suspend_host(struct sdhci_host *host);
780int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset);
781#endif
782
783void sdhci_cqe_enable(struct mmc_host *mmc);
784void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery);
785bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
786 int *data_error);
787
788void sdhci_dumpregs(struct sdhci_host *host);
789void sdhci_enable_v4_mode(struct sdhci_host *host);
790
791void sdhci_start_tuning(struct sdhci_host *host);
792void sdhci_end_tuning(struct sdhci_host *host);
793void sdhci_reset_tuning(struct sdhci_host *host);
794void sdhci_send_tuning(struct sdhci_host *host, u32 opcode);
795void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode);
796
797#endif
798