1
2
3
4
5
6
7
8#include <linux/clk.h>
9#include <linux/clk-provider.h>
10#include <linux/device.h>
11#include <linux/ethtool.h>
12#include <linux/io.h>
13#include <linux/ioport.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/of_net.h>
17#include <linux/mfd/syscon.h>
18#include <linux/platform_device.h>
19#include <linux/stmmac.h>
20
21#include "stmmac_platform.h"
22
23#define PRG_ETH0 0x0
24
25#define PRG_ETH0_RGMII_MODE BIT(0)
26
27#define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0)
28#define PRG_ETH0_EXT_RGMII_MODE 1
29#define PRG_ETH0_EXT_RMII_MODE 4
30
31
32#define PRG_ETH0_CLK_M250_SEL_SHIFT 4
33#define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4)
34
35#define PRG_ETH0_TXDLY_SHIFT 5
36#define PRG_ETH0_TXDLY_MASK GENMASK(6, 5)
37
38
39#define PRG_ETH0_CLK_M250_DIV_SHIFT 7
40#define PRG_ETH0_CLK_M250_DIV_WIDTH 3
41
42#define PRG_ETH0_RGMII_TX_CLK_EN 10
43
44#define PRG_ETH0_INVERTED_RMII_CLK BIT(11)
45#define PRG_ETH0_TX_AND_PHY_REF_CLK BIT(12)
46
47#define MUX_CLK_NUM_PARENTS 2
48
49struct meson8b_dwmac;
50
51struct meson8b_dwmac_data {
52 int (*set_phy_mode)(struct meson8b_dwmac *dwmac);
53};
54
55struct meson8b_dwmac {
56 struct device *dev;
57 void __iomem *regs;
58
59 const struct meson8b_dwmac_data *data;
60 phy_interface_t phy_mode;
61 struct clk *rgmii_tx_clk;
62 u32 tx_delay_ns;
63};
64
65struct meson8b_dwmac_clk_configs {
66 struct clk_mux m250_mux;
67 struct clk_divider m250_div;
68 struct clk_fixed_factor fixed_div2;
69 struct clk_gate rgmii_tx_en;
70};
71
72static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg,
73 u32 mask, u32 value)
74{
75 u32 data;
76
77 data = readl(dwmac->regs + reg);
78 data &= ~mask;
79 data |= (value & mask);
80
81 writel(data, dwmac->regs + reg);
82}
83
84static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac,
85 const char *name_suffix,
86 const char **parent_names,
87 int num_parents,
88 const struct clk_ops *ops,
89 struct clk_hw *hw)
90{
91 struct clk_init_data init;
92 char clk_name[32];
93
94 snprintf(clk_name, sizeof(clk_name), "%s#%s", dev_name(dwmac->dev),
95 name_suffix);
96
97 init.name = clk_name;
98 init.ops = ops;
99 init.flags = CLK_SET_RATE_PARENT;
100 init.parent_names = parent_names;
101 init.num_parents = num_parents;
102
103 hw->init = &init;
104
105 return devm_clk_register(dwmac->dev, hw);
106}
107
108static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac)
109{
110 int i, ret;
111 struct clk *clk;
112 struct device *dev = dwmac->dev;
113 const char *parent_name, *mux_parent_names[MUX_CLK_NUM_PARENTS];
114 struct meson8b_dwmac_clk_configs *clk_configs;
115
116 clk_configs = devm_kzalloc(dev, sizeof(*clk_configs), GFP_KERNEL);
117 if (!clk_configs)
118 return -ENOMEM;
119
120
121 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
122 char name[16];
123
124 snprintf(name, sizeof(name), "clkin%d", i);
125 clk = devm_clk_get(dev, name);
126 if (IS_ERR(clk)) {
127 ret = PTR_ERR(clk);
128 if (ret != -EPROBE_DEFER)
129 dev_err(dev, "Missing clock %s\n", name);
130 return ret;
131 }
132
133 mux_parent_names[i] = __clk_get_name(clk);
134 }
135
136 clk_configs->m250_mux.reg = dwmac->regs + PRG_ETH0;
137 clk_configs->m250_mux.shift = PRG_ETH0_CLK_M250_SEL_SHIFT;
138 clk_configs->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_MASK;
139 clk = meson8b_dwmac_register_clk(dwmac, "m250_sel", mux_parent_names,
140 MUX_CLK_NUM_PARENTS, &clk_mux_ops,
141 &clk_configs->m250_mux.hw);
142 if (WARN_ON(IS_ERR(clk)))
143 return PTR_ERR(clk);
144
145 parent_name = __clk_get_name(clk);
146 clk_configs->m250_div.reg = dwmac->regs + PRG_ETH0;
147 clk_configs->m250_div.shift = PRG_ETH0_CLK_M250_DIV_SHIFT;
148 clk_configs->m250_div.width = PRG_ETH0_CLK_M250_DIV_WIDTH;
149 clk_configs->m250_div.flags = CLK_DIVIDER_ONE_BASED |
150 CLK_DIVIDER_ALLOW_ZERO |
151 CLK_DIVIDER_ROUND_CLOSEST;
152 clk = meson8b_dwmac_register_clk(dwmac, "m250_div", &parent_name, 1,
153 &clk_divider_ops,
154 &clk_configs->m250_div.hw);
155 if (WARN_ON(IS_ERR(clk)))
156 return PTR_ERR(clk);
157
158 parent_name = __clk_get_name(clk);
159 clk_configs->fixed_div2.mult = 1;
160 clk_configs->fixed_div2.div = 2;
161 clk = meson8b_dwmac_register_clk(dwmac, "fixed_div2", &parent_name, 1,
162 &clk_fixed_factor_ops,
163 &clk_configs->fixed_div2.hw);
164 if (WARN_ON(IS_ERR(clk)))
165 return PTR_ERR(clk);
166
167 parent_name = __clk_get_name(clk);
168 clk_configs->rgmii_tx_en.reg = dwmac->regs + PRG_ETH0;
169 clk_configs->rgmii_tx_en.bit_idx = PRG_ETH0_RGMII_TX_CLK_EN;
170 clk = meson8b_dwmac_register_clk(dwmac, "rgmii_tx_en", &parent_name, 1,
171 &clk_gate_ops,
172 &clk_configs->rgmii_tx_en.hw);
173 if (WARN_ON(IS_ERR(clk)))
174 return PTR_ERR(clk);
175
176 dwmac->rgmii_tx_clk = clk;
177
178 return 0;
179}
180
181static int meson8b_set_phy_mode(struct meson8b_dwmac *dwmac)
182{
183 switch (dwmac->phy_mode) {
184 case PHY_INTERFACE_MODE_RGMII:
185 case PHY_INTERFACE_MODE_RGMII_RXID:
186 case PHY_INTERFACE_MODE_RGMII_ID:
187 case PHY_INTERFACE_MODE_RGMII_TXID:
188
189 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
190 PRG_ETH0_RGMII_MODE,
191 PRG_ETH0_RGMII_MODE);
192 break;
193 case PHY_INTERFACE_MODE_RMII:
194
195 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
196 PRG_ETH0_RGMII_MODE, 0);
197 break;
198 default:
199 dev_err(dwmac->dev, "fail to set phy-mode %s\n",
200 phy_modes(dwmac->phy_mode));
201 return -EINVAL;
202 }
203
204 return 0;
205}
206
207static int meson_axg_set_phy_mode(struct meson8b_dwmac *dwmac)
208{
209 switch (dwmac->phy_mode) {
210 case PHY_INTERFACE_MODE_RGMII:
211 case PHY_INTERFACE_MODE_RGMII_RXID:
212 case PHY_INTERFACE_MODE_RGMII_ID:
213 case PHY_INTERFACE_MODE_RGMII_TXID:
214
215 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
216 PRG_ETH0_EXT_PHY_MODE_MASK,
217 PRG_ETH0_EXT_RGMII_MODE);
218 break;
219 case PHY_INTERFACE_MODE_RMII:
220
221 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
222 PRG_ETH0_EXT_PHY_MODE_MASK,
223 PRG_ETH0_EXT_RMII_MODE);
224 break;
225 default:
226 dev_err(dwmac->dev, "fail to set phy-mode %s\n",
227 phy_modes(dwmac->phy_mode));
228 return -EINVAL;
229 }
230
231 return 0;
232}
233
234static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
235{
236 int ret;
237 u8 tx_dly_val = 0;
238
239 switch (dwmac->phy_mode) {
240 case PHY_INTERFACE_MODE_RGMII:
241 case PHY_INTERFACE_MODE_RGMII_RXID:
242
243
244
245
246 tx_dly_val = dwmac->tx_delay_ns >> 1;
247
248
249 case PHY_INTERFACE_MODE_RGMII_ID:
250 case PHY_INTERFACE_MODE_RGMII_TXID:
251
252 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
253 PRG_ETH0_INVERTED_RMII_CLK, 0);
254
255 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK,
256 tx_dly_val << PRG_ETH0_TXDLY_SHIFT);
257
258
259
260
261
262
263 ret = clk_set_rate(dwmac->rgmii_tx_clk, 125 * 1000 * 1000);
264 if (ret) {
265 dev_err(dwmac->dev,
266 "failed to set RGMII TX clock\n");
267 return ret;
268 }
269
270 ret = clk_prepare_enable(dwmac->rgmii_tx_clk);
271 if (ret) {
272 dev_err(dwmac->dev,
273 "failed to enable the RGMII TX clock\n");
274 return ret;
275 }
276
277 devm_add_action_or_reset(dwmac->dev,
278 (void(*)(void *))clk_disable_unprepare,
279 dwmac->rgmii_tx_clk);
280 break;
281
282 case PHY_INTERFACE_MODE_RMII:
283
284 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
285 PRG_ETH0_INVERTED_RMII_CLK,
286 PRG_ETH0_INVERTED_RMII_CLK);
287
288
289 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK,
290 0);
291
292 break;
293
294 default:
295 dev_err(dwmac->dev, "unsupported phy-mode %s\n",
296 phy_modes(dwmac->phy_mode));
297 return -EINVAL;
298 }
299
300
301 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TX_AND_PHY_REF_CLK,
302 PRG_ETH0_TX_AND_PHY_REF_CLK);
303
304 return 0;
305}
306
307static int meson8b_dwmac_probe(struct platform_device *pdev)
308{
309 struct plat_stmmacenet_data *plat_dat;
310 struct stmmac_resources stmmac_res;
311 struct meson8b_dwmac *dwmac;
312 int ret;
313
314 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
315 if (ret)
316 return ret;
317
318 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
319 if (IS_ERR(plat_dat))
320 return PTR_ERR(plat_dat);
321
322 dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
323 if (!dwmac) {
324 ret = -ENOMEM;
325 goto err_remove_config_dt;
326 }
327
328 dwmac->data = (const struct meson8b_dwmac_data *)
329 of_device_get_match_data(&pdev->dev);
330 if (!dwmac->data) {
331 ret = -EINVAL;
332 goto err_remove_config_dt;
333 }
334 dwmac->regs = devm_platform_ioremap_resource(pdev, 1);
335 if (IS_ERR(dwmac->regs)) {
336 ret = PTR_ERR(dwmac->regs);
337 goto err_remove_config_dt;
338 }
339
340 dwmac->dev = &pdev->dev;
341 dwmac->phy_mode = of_get_phy_mode(pdev->dev.of_node);
342 if ((int)dwmac->phy_mode < 0) {
343 dev_err(&pdev->dev, "missing phy-mode property\n");
344 ret = -EINVAL;
345 goto err_remove_config_dt;
346 }
347
348
349 if (of_property_read_u32(pdev->dev.of_node, "amlogic,tx-delay-ns",
350 &dwmac->tx_delay_ns))
351 dwmac->tx_delay_ns = 2;
352
353 ret = meson8b_init_rgmii_tx_clk(dwmac);
354 if (ret)
355 goto err_remove_config_dt;
356
357 ret = dwmac->data->set_phy_mode(dwmac);
358 if (ret)
359 goto err_remove_config_dt;
360
361 ret = meson8b_init_prg_eth(dwmac);
362 if (ret)
363 goto err_remove_config_dt;
364
365 plat_dat->bsp_priv = dwmac;
366
367 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
368 if (ret)
369 goto err_remove_config_dt;
370
371 return 0;
372
373err_remove_config_dt:
374 stmmac_remove_config_dt(pdev, plat_dat);
375
376 return ret;
377}
378
379static const struct meson8b_dwmac_data meson8b_dwmac_data = {
380 .set_phy_mode = meson8b_set_phy_mode,
381};
382
383static const struct meson8b_dwmac_data meson_axg_dwmac_data = {
384 .set_phy_mode = meson_axg_set_phy_mode,
385};
386
387static const struct of_device_id meson8b_dwmac_match[] = {
388 {
389 .compatible = "amlogic,meson8b-dwmac",
390 .data = &meson8b_dwmac_data,
391 },
392 {
393 .compatible = "amlogic,meson8m2-dwmac",
394 .data = &meson8b_dwmac_data,
395 },
396 {
397 .compatible = "amlogic,meson-gxbb-dwmac",
398 .data = &meson8b_dwmac_data,
399 },
400 {
401 .compatible = "amlogic,meson-axg-dwmac",
402 .data = &meson_axg_dwmac_data,
403 },
404 { }
405};
406MODULE_DEVICE_TABLE(of, meson8b_dwmac_match);
407
408static struct platform_driver meson8b_dwmac_driver = {
409 .probe = meson8b_dwmac_probe,
410 .remove = stmmac_pltfr_remove,
411 .driver = {
412 .name = "meson8b-dwmac",
413 .pm = &stmmac_pltfr_pm_ops,
414 .of_match_table = meson8b_dwmac_match,
415 },
416};
417module_platform_driver(meson8b_dwmac_driver);
418
419MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
420MODULE_DESCRIPTION("Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer");
421MODULE_LICENSE("GPL v2");
422
