linux/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
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   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/**
   3 * dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
   4 *
   5 * Copyright (C) 2014 Chen-Zhi (Roger Chen)
   6 *
   7 * Chen-Zhi (Roger Chen)  <roger.chen@rock-chips.com>
   8 */
   9
  10#include <linux/stmmac.h>
  11#include <linux/bitops.h>
  12#include <linux/clk.h>
  13#include <linux/phy.h>
  14#include <linux/of_net.h>
  15#include <linux/gpio.h>
  16#include <linux/module.h>
  17#include <linux/of_gpio.h>
  18#include <linux/of_device.h>
  19#include <linux/platform_device.h>
  20#include <linux/regulator/consumer.h>
  21#include <linux/delay.h>
  22#include <linux/mfd/syscon.h>
  23#include <linux/regmap.h>
  24#include <linux/pm_runtime.h>
  25
  26#include "stmmac_platform.h"
  27
  28struct rk_priv_data;
  29struct rk_gmac_ops {
  30        void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
  31                             int tx_delay, int rx_delay);
  32        void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
  33        void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
  34        void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
  35        void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);
  36};
  37
  38struct rk_priv_data {
  39        struct platform_device *pdev;
  40        int phy_iface;
  41        struct regulator *regulator;
  42        bool suspended;
  43        const struct rk_gmac_ops *ops;
  44
  45        bool clk_enabled;
  46        bool clock_input;
  47        bool integrated_phy;
  48
  49        struct clk *clk_mac;
  50        struct clk *gmac_clkin;
  51        struct clk *mac_clk_rx;
  52        struct clk *mac_clk_tx;
  53        struct clk *clk_mac_ref;
  54        struct clk *clk_mac_refout;
  55        struct clk *clk_mac_speed;
  56        struct clk *aclk_mac;
  57        struct clk *pclk_mac;
  58        struct clk *clk_phy;
  59
  60        struct reset_control *phy_reset;
  61
  62        int tx_delay;
  63        int rx_delay;
  64
  65        struct regmap *grf;
  66};
  67
  68#define HIWORD_UPDATE(val, mask, shift) \
  69                ((val) << (shift) | (mask) << ((shift) + 16))
  70
  71#define GRF_BIT(nr)     (BIT(nr) | BIT(nr+16))
  72#define GRF_CLR_BIT(nr) (BIT(nr+16))
  73
  74#define DELAY_ENABLE(soc, tx, rx) \
  75        (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
  76         ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
  77
  78#define PX30_GRF_GMAC_CON1              0x0904
  79
  80/* PX30_GRF_GMAC_CON1 */
  81#define PX30_GMAC_PHY_INTF_SEL_RMII     (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
  82                                         GRF_BIT(6))
  83#define PX30_GMAC_SPEED_10M             GRF_CLR_BIT(2)
  84#define PX30_GMAC_SPEED_100M            GRF_BIT(2)
  85
  86static void px30_set_to_rmii(struct rk_priv_data *bsp_priv)
  87{
  88        struct device *dev = &bsp_priv->pdev->dev;
  89
  90        if (IS_ERR(bsp_priv->grf)) {
  91                dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
  92                return;
  93        }
  94
  95        regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
  96                     PX30_GMAC_PHY_INTF_SEL_RMII);
  97}
  98
  99static void px30_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 100{
 101        struct device *dev = &bsp_priv->pdev->dev;
 102        int ret;
 103
 104        if (IS_ERR(bsp_priv->clk_mac_speed)) {
 105                dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__);
 106                return;
 107        }
 108
 109        if (speed == 10) {
 110                regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
 111                             PX30_GMAC_SPEED_10M);
 112
 113                ret = clk_set_rate(bsp_priv->clk_mac_speed, 2500000);
 114                if (ret)
 115                        dev_err(dev, "%s: set clk_mac_speed rate 2500000 failed: %d\n",
 116                                __func__, ret);
 117        } else if (speed == 100) {
 118                regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
 119                             PX30_GMAC_SPEED_100M);
 120
 121                ret = clk_set_rate(bsp_priv->clk_mac_speed, 25000000);
 122                if (ret)
 123                        dev_err(dev, "%s: set clk_mac_speed rate 25000000 failed: %d\n",
 124                                __func__, ret);
 125
 126        } else {
 127                dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 128        }
 129}
 130
 131static const struct rk_gmac_ops px30_ops = {
 132        .set_to_rmii = px30_set_to_rmii,
 133        .set_rmii_speed = px30_set_rmii_speed,
 134};
 135
 136#define RK3128_GRF_MAC_CON0     0x0168
 137#define RK3128_GRF_MAC_CON1     0x016c
 138
 139/* RK3128_GRF_MAC_CON0 */
 140#define RK3128_GMAC_TXCLK_DLY_ENABLE   GRF_BIT(14)
 141#define RK3128_GMAC_TXCLK_DLY_DISABLE  GRF_CLR_BIT(14)
 142#define RK3128_GMAC_RXCLK_DLY_ENABLE   GRF_BIT(15)
 143#define RK3128_GMAC_RXCLK_DLY_DISABLE  GRF_CLR_BIT(15)
 144#define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
 145#define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
 146
 147/* RK3128_GRF_MAC_CON1 */
 148#define RK3128_GMAC_PHY_INTF_SEL_RGMII  \
 149                (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8))
 150#define RK3128_GMAC_PHY_INTF_SEL_RMII   \
 151                (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8))
 152#define RK3128_GMAC_FLOW_CTRL          GRF_BIT(9)
 153#define RK3128_GMAC_FLOW_CTRL_CLR      GRF_CLR_BIT(9)
 154#define RK3128_GMAC_SPEED_10M          GRF_CLR_BIT(10)
 155#define RK3128_GMAC_SPEED_100M         GRF_BIT(10)
 156#define RK3128_GMAC_RMII_CLK_25M       GRF_BIT(11)
 157#define RK3128_GMAC_RMII_CLK_2_5M      GRF_CLR_BIT(11)
 158#define RK3128_GMAC_CLK_125M           (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
 159#define RK3128_GMAC_CLK_25M            (GRF_BIT(12) | GRF_BIT(13))
 160#define RK3128_GMAC_CLK_2_5M           (GRF_CLR_BIT(12) | GRF_BIT(13))
 161#define RK3128_GMAC_RMII_MODE          GRF_BIT(14)
 162#define RK3128_GMAC_RMII_MODE_CLR      GRF_CLR_BIT(14)
 163
 164static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
 165                                int tx_delay, int rx_delay)
 166{
 167        struct device *dev = &bsp_priv->pdev->dev;
 168
 169        if (IS_ERR(bsp_priv->grf)) {
 170                dev_err(dev, "Missing rockchip,grf property\n");
 171                return;
 172        }
 173
 174        regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 175                     RK3128_GMAC_PHY_INTF_SEL_RGMII |
 176                     RK3128_GMAC_RMII_MODE_CLR);
 177        regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0,
 178                     DELAY_ENABLE(RK3128, tx_delay, rx_delay) |
 179                     RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) |
 180                     RK3128_GMAC_CLK_TX_DL_CFG(tx_delay));
 181}
 182
 183static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
 184{
 185        struct device *dev = &bsp_priv->pdev->dev;
 186
 187        if (IS_ERR(bsp_priv->grf)) {
 188                dev_err(dev, "Missing rockchip,grf property\n");
 189                return;
 190        }
 191
 192        regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 193                     RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE);
 194}
 195
 196static void rk3128_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 197{
 198        struct device *dev = &bsp_priv->pdev->dev;
 199
 200        if (IS_ERR(bsp_priv->grf)) {
 201                dev_err(dev, "Missing rockchip,grf property\n");
 202                return;
 203        }
 204
 205        if (speed == 10)
 206                regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 207                             RK3128_GMAC_CLK_2_5M);
 208        else if (speed == 100)
 209                regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 210                             RK3128_GMAC_CLK_25M);
 211        else if (speed == 1000)
 212                regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 213                             RK3128_GMAC_CLK_125M);
 214        else
 215                dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 216}
 217
 218static void rk3128_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 219{
 220        struct device *dev = &bsp_priv->pdev->dev;
 221
 222        if (IS_ERR(bsp_priv->grf)) {
 223                dev_err(dev, "Missing rockchip,grf property\n");
 224                return;
 225        }
 226
 227        if (speed == 10) {
 228                regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 229                             RK3128_GMAC_RMII_CLK_2_5M |
 230                             RK3128_GMAC_SPEED_10M);
 231        } else if (speed == 100) {
 232                regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 233                             RK3128_GMAC_RMII_CLK_25M |
 234                             RK3128_GMAC_SPEED_100M);
 235        } else {
 236                dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 237        }
 238}
 239
 240static const struct rk_gmac_ops rk3128_ops = {
 241        .set_to_rgmii = rk3128_set_to_rgmii,
 242        .set_to_rmii = rk3128_set_to_rmii,
 243        .set_rgmii_speed = rk3128_set_rgmii_speed,
 244        .set_rmii_speed = rk3128_set_rmii_speed,
 245};
 246
 247#define RK3228_GRF_MAC_CON0     0x0900
 248#define RK3228_GRF_MAC_CON1     0x0904
 249
 250#define RK3228_GRF_CON_MUX      0x50
 251
 252/* RK3228_GRF_MAC_CON0 */
 253#define RK3228_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 7)
 254#define RK3228_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 255
 256/* RK3228_GRF_MAC_CON1 */
 257#define RK3228_GMAC_PHY_INTF_SEL_RGMII  \
 258                (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
 259#define RK3228_GMAC_PHY_INTF_SEL_RMII   \
 260                (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
 261#define RK3228_GMAC_FLOW_CTRL           GRF_BIT(3)
 262#define RK3228_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(3)
 263#define RK3228_GMAC_SPEED_10M           GRF_CLR_BIT(2)
 264#define RK3228_GMAC_SPEED_100M          GRF_BIT(2)
 265#define RK3228_GMAC_RMII_CLK_25M        GRF_BIT(7)
 266#define RK3228_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(7)
 267#define RK3228_GMAC_CLK_125M            (GRF_CLR_BIT(8) | GRF_CLR_BIT(9))
 268#define RK3228_GMAC_CLK_25M             (GRF_BIT(8) | GRF_BIT(9))
 269#define RK3228_GMAC_CLK_2_5M            (GRF_CLR_BIT(8) | GRF_BIT(9))
 270#define RK3228_GMAC_RMII_MODE           GRF_BIT(10)
 271#define RK3228_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(10)
 272#define RK3228_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(0)
 273#define RK3228_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(0)
 274#define RK3228_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(1)
 275#define RK3228_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(1)
 276
 277/* RK3228_GRF_COM_MUX */
 278#define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY  GRF_BIT(15)
 279
 280static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
 281                                int tx_delay, int rx_delay)
 282{
 283        struct device *dev = &bsp_priv->pdev->dev;
 284
 285        if (IS_ERR(bsp_priv->grf)) {
 286                dev_err(dev, "Missing rockchip,grf property\n");
 287                return;
 288        }
 289
 290        regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 291                     RK3228_GMAC_PHY_INTF_SEL_RGMII |
 292                     RK3228_GMAC_RMII_MODE_CLR |
 293                     DELAY_ENABLE(RK3228, tx_delay, rx_delay));
 294
 295        regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
 296                     RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) |
 297                     RK3228_GMAC_CLK_TX_DL_CFG(tx_delay));
 298}
 299
 300static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
 301{
 302        struct device *dev = &bsp_priv->pdev->dev;
 303
 304        if (IS_ERR(bsp_priv->grf)) {
 305                dev_err(dev, "Missing rockchip,grf property\n");
 306                return;
 307        }
 308
 309        regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 310                     RK3228_GMAC_PHY_INTF_SEL_RMII |
 311                     RK3228_GMAC_RMII_MODE);
 312
 313        /* set MAC to RMII mode */
 314        regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
 315}
 316
 317static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 318{
 319        struct device *dev = &bsp_priv->pdev->dev;
 320
 321        if (IS_ERR(bsp_priv->grf)) {
 322                dev_err(dev, "Missing rockchip,grf property\n");
 323                return;
 324        }
 325
 326        if (speed == 10)
 327                regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 328                             RK3228_GMAC_CLK_2_5M);
 329        else if (speed == 100)
 330                regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 331                             RK3228_GMAC_CLK_25M);
 332        else if (speed == 1000)
 333                regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 334                             RK3228_GMAC_CLK_125M);
 335        else
 336                dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 337}
 338
 339static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 340{
 341        struct device *dev = &bsp_priv->pdev->dev;
 342
 343        if (IS_ERR(bsp_priv->grf)) {
 344                dev_err(dev, "Missing rockchip,grf property\n");
 345                return;
 346        }
 347
 348        if (speed == 10)
 349                regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 350                             RK3228_GMAC_RMII_CLK_2_5M |
 351                             RK3228_GMAC_SPEED_10M);
 352        else if (speed == 100)
 353                regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 354                             RK3228_GMAC_RMII_CLK_25M |
 355                             RK3228_GMAC_SPEED_100M);
 356        else
 357                dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 358}
 359
 360static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
 361{
 362        regmap_write(priv->grf, RK3228_GRF_CON_MUX,
 363                     RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
 364}
 365
 366static const struct rk_gmac_ops rk3228_ops = {
 367        .set_to_rgmii = rk3228_set_to_rgmii,
 368        .set_to_rmii = rk3228_set_to_rmii,
 369        .set_rgmii_speed = rk3228_set_rgmii_speed,
 370        .set_rmii_speed = rk3228_set_rmii_speed,
 371        .integrated_phy_powerup =  rk3228_integrated_phy_powerup,
 372};
 373
 374#define RK3288_GRF_SOC_CON1     0x0248
 375#define RK3288_GRF_SOC_CON3     0x0250
 376
 377/*RK3288_GRF_SOC_CON1*/
 378#define RK3288_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(6) | GRF_CLR_BIT(7) | \
 379                                         GRF_CLR_BIT(8))
 380#define RK3288_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \
 381                                         GRF_BIT(8))
 382#define RK3288_GMAC_FLOW_CTRL           GRF_BIT(9)
 383#define RK3288_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(9)
 384#define RK3288_GMAC_SPEED_10M           GRF_CLR_BIT(10)
 385#define RK3288_GMAC_SPEED_100M          GRF_BIT(10)
 386#define RK3288_GMAC_RMII_CLK_25M        GRF_BIT(11)
 387#define RK3288_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(11)
 388#define RK3288_GMAC_CLK_125M            (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
 389#define RK3288_GMAC_CLK_25M             (GRF_BIT(12) | GRF_BIT(13))
 390#define RK3288_GMAC_CLK_2_5M            (GRF_CLR_BIT(12) | GRF_BIT(13))
 391#define RK3288_GMAC_RMII_MODE           GRF_BIT(14)
 392#define RK3288_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(14)
 393
 394/*RK3288_GRF_SOC_CON3*/
 395#define RK3288_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(14)
 396#define RK3288_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(14)
 397#define RK3288_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 398#define RK3288_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 399#define RK3288_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 7)
 400#define RK3288_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 401
 402static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
 403                                int tx_delay, int rx_delay)
 404{
 405        struct device *dev = &bsp_priv->pdev->dev;
 406
 407        if (IS_ERR(bsp_priv->grf)) {
 408                dev_err(dev, "Missing rockchip,grf property\n");
 409                return;
 410        }
 411
 412        regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 413                     RK3288_GMAC_PHY_INTF_SEL_RGMII |
 414                     RK3288_GMAC_RMII_MODE_CLR);
 415        regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
 416                     DELAY_ENABLE(RK3288, tx_delay, rx_delay) |
 417                     RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) |
 418                     RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
 419}
 420
 421static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
 422{
 423        struct device *dev = &bsp_priv->pdev->dev;
 424
 425        if (IS_ERR(bsp_priv->grf)) {
 426                dev_err(dev, "Missing rockchip,grf property\n");
 427                return;
 428        }
 429
 430        regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 431                     RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE);
 432}
 433
 434static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 435{
 436        struct device *dev = &bsp_priv->pdev->dev;
 437
 438        if (IS_ERR(bsp_priv->grf)) {
 439                dev_err(dev, "Missing rockchip,grf property\n");
 440                return;
 441        }
 442
 443        if (speed == 10)
 444                regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 445                             RK3288_GMAC_CLK_2_5M);
 446        else if (speed == 100)
 447                regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 448                             RK3288_GMAC_CLK_25M);
 449        else if (speed == 1000)
 450                regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 451                             RK3288_GMAC_CLK_125M);
 452        else
 453                dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 454}
 455
 456static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 457{
 458        struct device *dev = &bsp_priv->pdev->dev;
 459
 460        if (IS_ERR(bsp_priv->grf)) {
 461                dev_err(dev, "Missing rockchip,grf property\n");
 462                return;
 463        }
 464
 465        if (speed == 10) {
 466                regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 467                             RK3288_GMAC_RMII_CLK_2_5M |
 468                             RK3288_GMAC_SPEED_10M);
 469        } else if (speed == 100) {
 470                regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 471                             RK3288_GMAC_RMII_CLK_25M |
 472                             RK3288_GMAC_SPEED_100M);
 473        } else {
 474                dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 475        }
 476}
 477
 478static const struct rk_gmac_ops rk3288_ops = {
 479        .set_to_rgmii = rk3288_set_to_rgmii,
 480        .set_to_rmii = rk3288_set_to_rmii,
 481        .set_rgmii_speed = rk3288_set_rgmii_speed,
 482        .set_rmii_speed = rk3288_set_rmii_speed,
 483};
 484
 485#define RK3328_GRF_MAC_CON0     0x0900
 486#define RK3328_GRF_MAC_CON1     0x0904
 487#define RK3328_GRF_MAC_CON2     0x0908
 488#define RK3328_GRF_MACPHY_CON1  0xb04
 489
 490/* RK3328_GRF_MAC_CON0 */
 491#define RK3328_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 7)
 492#define RK3328_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 493
 494/* RK3328_GRF_MAC_CON1 */
 495#define RK3328_GMAC_PHY_INTF_SEL_RGMII  \
 496                (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
 497#define RK3328_GMAC_PHY_INTF_SEL_RMII   \
 498                (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
 499#define RK3328_GMAC_FLOW_CTRL           GRF_BIT(3)
 500#define RK3328_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(3)
 501#define RK3328_GMAC_SPEED_10M           GRF_CLR_BIT(2)
 502#define RK3328_GMAC_SPEED_100M          GRF_BIT(2)
 503#define RK3328_GMAC_RMII_CLK_25M        GRF_BIT(7)
 504#define RK3328_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(7)
 505#define RK3328_GMAC_CLK_125M            (GRF_CLR_BIT(11) | GRF_CLR_BIT(12))
 506#define RK3328_GMAC_CLK_25M             (GRF_BIT(11) | GRF_BIT(12))
 507#define RK3328_GMAC_CLK_2_5M            (GRF_CLR_BIT(11) | GRF_BIT(12))
 508#define RK3328_GMAC_RMII_MODE           GRF_BIT(9)
 509#define RK3328_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(9)
 510#define RK3328_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(0)
 511#define RK3328_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(0)
 512#define RK3328_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(1)
 513#define RK3328_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(0)
 514
 515/* RK3328_GRF_MACPHY_CON1 */
 516#define RK3328_MACPHY_RMII_MODE         GRF_BIT(9)
 517
 518static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
 519                                int tx_delay, int rx_delay)
 520{
 521        struct device *dev = &bsp_priv->pdev->dev;
 522
 523        if (IS_ERR(bsp_priv->grf)) {
 524                dev_err(dev, "Missing rockchip,grf property\n");
 525                return;
 526        }
 527
 528        regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 529                     RK3328_GMAC_PHY_INTF_SEL_RGMII |
 530                     RK3328_GMAC_RMII_MODE_CLR |
 531                     RK3328_GMAC_RXCLK_DLY_ENABLE |
 532                     RK3328_GMAC_TXCLK_DLY_ENABLE);
 533
 534        regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0,
 535                     RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) |
 536                     RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
 537}
 538
 539static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
 540{
 541        struct device *dev = &bsp_priv->pdev->dev;
 542        unsigned int reg;
 543
 544        if (IS_ERR(bsp_priv->grf)) {
 545                dev_err(dev, "Missing rockchip,grf property\n");
 546                return;
 547        }
 548
 549        reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
 550                  RK3328_GRF_MAC_CON1;
 551
 552        regmap_write(bsp_priv->grf, reg,
 553                     RK3328_GMAC_PHY_INTF_SEL_RMII |
 554                     RK3328_GMAC_RMII_MODE);
 555}
 556
 557static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 558{
 559        struct device *dev = &bsp_priv->pdev->dev;
 560
 561        if (IS_ERR(bsp_priv->grf)) {
 562                dev_err(dev, "Missing rockchip,grf property\n");
 563                return;
 564        }
 565
 566        if (speed == 10)
 567                regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 568                             RK3328_GMAC_CLK_2_5M);
 569        else if (speed == 100)
 570                regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 571                             RK3328_GMAC_CLK_25M);
 572        else if (speed == 1000)
 573                regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 574                             RK3328_GMAC_CLK_125M);
 575        else
 576                dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 577}
 578
 579static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 580{
 581        struct device *dev = &bsp_priv->pdev->dev;
 582        unsigned int reg;
 583
 584        if (IS_ERR(bsp_priv->grf)) {
 585                dev_err(dev, "Missing rockchip,grf property\n");
 586                return;
 587        }
 588
 589        reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
 590                  RK3328_GRF_MAC_CON1;
 591
 592        if (speed == 10)
 593                regmap_write(bsp_priv->grf, reg,
 594                             RK3328_GMAC_RMII_CLK_2_5M |
 595                             RK3328_GMAC_SPEED_10M);
 596        else if (speed == 100)
 597                regmap_write(bsp_priv->grf, reg,
 598                             RK3328_GMAC_RMII_CLK_25M |
 599                             RK3328_GMAC_SPEED_100M);
 600        else
 601                dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 602}
 603
 604static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
 605{
 606        regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
 607                     RK3328_MACPHY_RMII_MODE);
 608}
 609
 610static const struct rk_gmac_ops rk3328_ops = {
 611        .set_to_rgmii = rk3328_set_to_rgmii,
 612        .set_to_rmii = rk3328_set_to_rmii,
 613        .set_rgmii_speed = rk3328_set_rgmii_speed,
 614        .set_rmii_speed = rk3328_set_rmii_speed,
 615        .integrated_phy_powerup =  rk3328_integrated_phy_powerup,
 616};
 617
 618#define RK3366_GRF_SOC_CON6     0x0418
 619#define RK3366_GRF_SOC_CON7     0x041c
 620
 621/* RK3366_GRF_SOC_CON6 */
 622#define RK3366_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
 623                                         GRF_CLR_BIT(11))
 624#define RK3366_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
 625                                         GRF_BIT(11))
 626#define RK3366_GMAC_FLOW_CTRL           GRF_BIT(8)
 627#define RK3366_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(8)
 628#define RK3366_GMAC_SPEED_10M           GRF_CLR_BIT(7)
 629#define RK3366_GMAC_SPEED_100M          GRF_BIT(7)
 630#define RK3366_GMAC_RMII_CLK_25M        GRF_BIT(3)
 631#define RK3366_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(3)
 632#define RK3366_GMAC_CLK_125M            (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
 633#define RK3366_GMAC_CLK_25M             (GRF_BIT(4) | GRF_BIT(5))
 634#define RK3366_GMAC_CLK_2_5M            (GRF_CLR_BIT(4) | GRF_BIT(5))
 635#define RK3366_GMAC_RMII_MODE           GRF_BIT(6)
 636#define RK3366_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(6)
 637
 638/* RK3366_GRF_SOC_CON7 */
 639#define RK3366_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
 640#define RK3366_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
 641#define RK3366_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 642#define RK3366_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 643#define RK3366_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
 644#define RK3366_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 645
 646static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
 647                                int tx_delay, int rx_delay)
 648{
 649        struct device *dev = &bsp_priv->pdev->dev;
 650
 651        if (IS_ERR(bsp_priv->grf)) {
 652                dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 653                return;
 654        }
 655
 656        regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 657                     RK3366_GMAC_PHY_INTF_SEL_RGMII |
 658                     RK3366_GMAC_RMII_MODE_CLR);
 659        regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
 660                     DELAY_ENABLE(RK3366, tx_delay, rx_delay) |
 661                     RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |
 662                     RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
 663}
 664
 665static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
 666{
 667        struct device *dev = &bsp_priv->pdev->dev;
 668
 669        if (IS_ERR(bsp_priv->grf)) {
 670                dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 671                return;
 672        }
 673
 674        regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 675                     RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE);
 676}
 677
 678static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 679{
 680        struct device *dev = &bsp_priv->pdev->dev;
 681
 682        if (IS_ERR(bsp_priv->grf)) {
 683                dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 684                return;
 685        }
 686
 687        if (speed == 10)
 688                regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 689                             RK3366_GMAC_CLK_2_5M);
 690        else if (speed == 100)
 691                regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 692                             RK3366_GMAC_CLK_25M);
 693        else if (speed == 1000)
 694                regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 695                             RK3366_GMAC_CLK_125M);
 696        else
 697                dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 698}
 699
 700static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 701{
 702        struct device *dev = &bsp_priv->pdev->dev;
 703
 704        if (IS_ERR(bsp_priv->grf)) {
 705                dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 706                return;
 707        }
 708
 709        if (speed == 10) {
 710                regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 711                             RK3366_GMAC_RMII_CLK_2_5M |
 712                             RK3366_GMAC_SPEED_10M);
 713        } else if (speed == 100) {
 714                regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 715                             RK3366_GMAC_RMII_CLK_25M |
 716                             RK3366_GMAC_SPEED_100M);
 717        } else {
 718                dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 719        }
 720}
 721
 722static const struct rk_gmac_ops rk3366_ops = {
 723        .set_to_rgmii = rk3366_set_to_rgmii,
 724        .set_to_rmii = rk3366_set_to_rmii,
 725        .set_rgmii_speed = rk3366_set_rgmii_speed,
 726        .set_rmii_speed = rk3366_set_rmii_speed,
 727};
 728
 729#define RK3368_GRF_SOC_CON15    0x043c
 730#define RK3368_GRF_SOC_CON16    0x0440
 731
 732/* RK3368_GRF_SOC_CON15 */
 733#define RK3368_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
 734                                         GRF_CLR_BIT(11))
 735#define RK3368_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
 736                                         GRF_BIT(11))
 737#define RK3368_GMAC_FLOW_CTRL           GRF_BIT(8)
 738#define RK3368_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(8)
 739#define RK3368_GMAC_SPEED_10M           GRF_CLR_BIT(7)
 740#define RK3368_GMAC_SPEED_100M          GRF_BIT(7)
 741#define RK3368_GMAC_RMII_CLK_25M        GRF_BIT(3)
 742#define RK3368_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(3)
 743#define RK3368_GMAC_CLK_125M            (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
 744#define RK3368_GMAC_CLK_25M             (GRF_BIT(4) | GRF_BIT(5))
 745#define RK3368_GMAC_CLK_2_5M            (GRF_CLR_BIT(4) | GRF_BIT(5))
 746#define RK3368_GMAC_RMII_MODE           GRF_BIT(6)
 747#define RK3368_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(6)
 748
 749/* RK3368_GRF_SOC_CON16 */
 750#define RK3368_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
 751#define RK3368_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
 752#define RK3368_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 753#define RK3368_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 754#define RK3368_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
 755#define RK3368_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 756
 757static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
 758                                int tx_delay, int rx_delay)
 759{
 760        struct device *dev = &bsp_priv->pdev->dev;
 761
 762        if (IS_ERR(bsp_priv->grf)) {
 763                dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 764                return;
 765        }
 766
 767        regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 768                     RK3368_GMAC_PHY_INTF_SEL_RGMII |
 769                     RK3368_GMAC_RMII_MODE_CLR);
 770        regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
 771                     DELAY_ENABLE(RK3368, tx_delay, rx_delay) |
 772                     RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
 773                     RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
 774}
 775
 776static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
 777{
 778        struct device *dev = &bsp_priv->pdev->dev;
 779
 780        if (IS_ERR(bsp_priv->grf)) {
 781                dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 782                return;
 783        }
 784
 785        regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 786                     RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE);
 787}
 788
 789static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 790{
 791        struct device *dev = &bsp_priv->pdev->dev;
 792
 793        if (IS_ERR(bsp_priv->grf)) {
 794                dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 795                return;
 796        }
 797
 798        if (speed == 10)
 799                regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 800                             RK3368_GMAC_CLK_2_5M);
 801        else if (speed == 100)
 802                regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 803                             RK3368_GMAC_CLK_25M);
 804        else if (speed == 1000)
 805                regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 806                             RK3368_GMAC_CLK_125M);
 807        else
 808                dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 809}
 810
 811static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 812{
 813        struct device *dev = &bsp_priv->pdev->dev;
 814
 815        if (IS_ERR(bsp_priv->grf)) {
 816                dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 817                return;
 818        }
 819
 820        if (speed == 10) {
 821                regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 822                             RK3368_GMAC_RMII_CLK_2_5M |
 823                             RK3368_GMAC_SPEED_10M);
 824        } else if (speed == 100) {
 825                regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 826                             RK3368_GMAC_RMII_CLK_25M |
 827                             RK3368_GMAC_SPEED_100M);
 828        } else {
 829                dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 830        }
 831}
 832
 833static const struct rk_gmac_ops rk3368_ops = {
 834        .set_to_rgmii = rk3368_set_to_rgmii,
 835        .set_to_rmii = rk3368_set_to_rmii,
 836        .set_rgmii_speed = rk3368_set_rgmii_speed,
 837        .set_rmii_speed = rk3368_set_rmii_speed,
 838};
 839
 840#define RK3399_GRF_SOC_CON5     0xc214
 841#define RK3399_GRF_SOC_CON6     0xc218
 842
 843/* RK3399_GRF_SOC_CON5 */
 844#define RK3399_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
 845                                         GRF_CLR_BIT(11))
 846#define RK3399_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
 847                                         GRF_BIT(11))
 848#define RK3399_GMAC_FLOW_CTRL           GRF_BIT(8)
 849#define RK3399_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(8)
 850#define RK3399_GMAC_SPEED_10M           GRF_CLR_BIT(7)
 851#define RK3399_GMAC_SPEED_100M          GRF_BIT(7)
 852#define RK3399_GMAC_RMII_CLK_25M        GRF_BIT(3)
 853#define RK3399_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(3)
 854#define RK3399_GMAC_CLK_125M            (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
 855#define RK3399_GMAC_CLK_25M             (GRF_BIT(4) | GRF_BIT(5))
 856#define RK3399_GMAC_CLK_2_5M            (GRF_CLR_BIT(4) | GRF_BIT(5))
 857#define RK3399_GMAC_RMII_MODE           GRF_BIT(6)
 858#define RK3399_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(6)
 859
 860/* RK3399_GRF_SOC_CON6 */
 861#define RK3399_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
 862#define RK3399_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
 863#define RK3399_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 864#define RK3399_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 865#define RK3399_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
 866#define RK3399_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 867
 868static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
 869                                int tx_delay, int rx_delay)
 870{
 871        struct device *dev = &bsp_priv->pdev->dev;
 872
 873        if (IS_ERR(bsp_priv->grf)) {
 874                dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 875                return;
 876        }
 877
 878        regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 879                     RK3399_GMAC_PHY_INTF_SEL_RGMII |
 880                     RK3399_GMAC_RMII_MODE_CLR);
 881        regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
 882                     DELAY_ENABLE(RK3399, tx_delay, rx_delay) |
 883                     RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) |
 884                     RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
 885}
 886
 887static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
 888{
 889        struct device *dev = &bsp_priv->pdev->dev;
 890
 891        if (IS_ERR(bsp_priv->grf)) {
 892                dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 893                return;
 894        }
 895
 896        regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 897                     RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE);
 898}
 899
 900static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 901{
 902        struct device *dev = &bsp_priv->pdev->dev;
 903
 904        if (IS_ERR(bsp_priv->grf)) {
 905                dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 906                return;
 907        }
 908
 909        if (speed == 10)
 910                regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 911                             RK3399_GMAC_CLK_2_5M);
 912        else if (speed == 100)
 913                regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 914                             RK3399_GMAC_CLK_25M);
 915        else if (speed == 1000)
 916                regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 917                             RK3399_GMAC_CLK_125M);
 918        else
 919                dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 920}
 921
 922static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 923{
 924        struct device *dev = &bsp_priv->pdev->dev;
 925
 926        if (IS_ERR(bsp_priv->grf)) {
 927                dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 928                return;
 929        }
 930
 931        if (speed == 10) {
 932                regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 933                             RK3399_GMAC_RMII_CLK_2_5M |
 934                             RK3399_GMAC_SPEED_10M);
 935        } else if (speed == 100) {
 936                regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 937                             RK3399_GMAC_RMII_CLK_25M |
 938                             RK3399_GMAC_SPEED_100M);
 939        } else {
 940                dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 941        }
 942}
 943
 944static const struct rk_gmac_ops rk3399_ops = {
 945        .set_to_rgmii = rk3399_set_to_rgmii,
 946        .set_to_rmii = rk3399_set_to_rmii,
 947        .set_rgmii_speed = rk3399_set_rgmii_speed,
 948        .set_rmii_speed = rk3399_set_rmii_speed,
 949};
 950
 951#define RV1108_GRF_GMAC_CON0            0X0900
 952
 953/* RV1108_GRF_GMAC_CON0 */
 954#define RV1108_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
 955                                        GRF_BIT(6))
 956#define RV1108_GMAC_FLOW_CTRL           GRF_BIT(3)
 957#define RV1108_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(3)
 958#define RV1108_GMAC_SPEED_10M           GRF_CLR_BIT(2)
 959#define RV1108_GMAC_SPEED_100M          GRF_BIT(2)
 960#define RV1108_GMAC_RMII_CLK_25M        GRF_BIT(7)
 961#define RV1108_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(7)
 962
 963static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
 964{
 965        struct device *dev = &bsp_priv->pdev->dev;
 966
 967        if (IS_ERR(bsp_priv->grf)) {
 968                dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 969                return;
 970        }
 971
 972        regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
 973                     RV1108_GMAC_PHY_INTF_SEL_RMII);
 974}
 975
 976static void rv1108_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 977{
 978        struct device *dev = &bsp_priv->pdev->dev;
 979
 980        if (IS_ERR(bsp_priv->grf)) {
 981                dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 982                return;
 983        }
 984
 985        if (speed == 10) {
 986                regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
 987                             RV1108_GMAC_RMII_CLK_2_5M |
 988                             RV1108_GMAC_SPEED_10M);
 989        } else if (speed == 100) {
 990                regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
 991                             RV1108_GMAC_RMII_CLK_25M |
 992                             RV1108_GMAC_SPEED_100M);
 993        } else {
 994                dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 995        }
 996}
 997
 998static const struct rk_gmac_ops rv1108_ops = {
 999        .set_to_rmii = rv1108_set_to_rmii,
1000        .set_rmii_speed = rv1108_set_rmii_speed,
1001};
1002
1003#define RK_GRF_MACPHY_CON0              0xb00
1004#define RK_GRF_MACPHY_CON1              0xb04
1005#define RK_GRF_MACPHY_CON2              0xb08
1006#define RK_GRF_MACPHY_CON3              0xb0c
1007
1008#define RK_MACPHY_ENABLE                GRF_BIT(0)
1009#define RK_MACPHY_DISABLE               GRF_CLR_BIT(0)
1010#define RK_MACPHY_CFG_CLK_50M           GRF_BIT(14)
1011#define RK_GMAC2PHY_RMII_MODE           (GRF_BIT(6) | GRF_CLR_BIT(7))
1012#define RK_GRF_CON2_MACPHY_ID           HIWORD_UPDATE(0x1234, 0xffff, 0)
1013#define RK_GRF_CON3_MACPHY_ID           HIWORD_UPDATE(0x35, 0x3f, 0)
1014
1015static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)
1016{
1017        if (priv->ops->integrated_phy_powerup)
1018                priv->ops->integrated_phy_powerup(priv);
1019
1020        regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
1021        regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
1022
1023        regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
1024        regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
1025
1026        if (priv->phy_reset) {
1027                /* PHY needs to be disabled before trying to reset it */
1028                regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1029                if (priv->phy_reset)
1030                        reset_control_assert(priv->phy_reset);
1031                usleep_range(10, 20);
1032                if (priv->phy_reset)
1033                        reset_control_deassert(priv->phy_reset);
1034                usleep_range(10, 20);
1035                regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
1036                msleep(30);
1037        }
1038}
1039
1040static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)
1041{
1042        regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1043        if (priv->phy_reset)
1044                reset_control_assert(priv->phy_reset);
1045}
1046
1047static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
1048{
1049        struct rk_priv_data *bsp_priv = plat->bsp_priv;
1050        struct device *dev = &bsp_priv->pdev->dev;
1051        int ret;
1052
1053        bsp_priv->clk_enabled = false;
1054
1055        bsp_priv->mac_clk_rx = devm_clk_get(dev, "mac_clk_rx");
1056        if (IS_ERR(bsp_priv->mac_clk_rx))
1057                dev_err(dev, "cannot get clock %s\n",
1058                        "mac_clk_rx");
1059
1060        bsp_priv->mac_clk_tx = devm_clk_get(dev, "mac_clk_tx");
1061        if (IS_ERR(bsp_priv->mac_clk_tx))
1062                dev_err(dev, "cannot get clock %s\n",
1063                        "mac_clk_tx");
1064
1065        bsp_priv->aclk_mac = devm_clk_get(dev, "aclk_mac");
1066        if (IS_ERR(bsp_priv->aclk_mac))
1067                dev_err(dev, "cannot get clock %s\n",
1068                        "aclk_mac");
1069
1070        bsp_priv->pclk_mac = devm_clk_get(dev, "pclk_mac");
1071        if (IS_ERR(bsp_priv->pclk_mac))
1072                dev_err(dev, "cannot get clock %s\n",
1073                        "pclk_mac");
1074
1075        bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth");
1076        if (IS_ERR(bsp_priv->clk_mac))
1077                dev_err(dev, "cannot get clock %s\n",
1078                        "stmmaceth");
1079
1080        if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
1081                bsp_priv->clk_mac_ref = devm_clk_get(dev, "clk_mac_ref");
1082                if (IS_ERR(bsp_priv->clk_mac_ref))
1083                        dev_err(dev, "cannot get clock %s\n",
1084                                "clk_mac_ref");
1085
1086                if (!bsp_priv->clock_input) {
1087                        bsp_priv->clk_mac_refout =
1088                                devm_clk_get(dev, "clk_mac_refout");
1089                        if (IS_ERR(bsp_priv->clk_mac_refout))
1090                                dev_err(dev, "cannot get clock %s\n",
1091                                        "clk_mac_refout");
1092                }
1093        }
1094
1095        bsp_priv->clk_mac_speed = devm_clk_get(dev, "clk_mac_speed");
1096        if (IS_ERR(bsp_priv->clk_mac_speed))
1097                dev_err(dev, "cannot get clock %s\n", "clk_mac_speed");
1098
1099        if (bsp_priv->clock_input) {
1100                dev_info(dev, "clock input from PHY\n");
1101        } else {
1102                if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1103                        clk_set_rate(bsp_priv->clk_mac, 50000000);
1104        }
1105
1106        if (plat->phy_node && bsp_priv->integrated_phy) {
1107                bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0);
1108                if (IS_ERR(bsp_priv->clk_phy)) {
1109                        ret = PTR_ERR(bsp_priv->clk_phy);
1110                        dev_err(dev, "Cannot get PHY clock: %d\n", ret);
1111                        return -EINVAL;
1112                }
1113                clk_set_rate(bsp_priv->clk_phy, 50000000);
1114        }
1115
1116        return 0;
1117}
1118
1119static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
1120{
1121        int phy_iface = bsp_priv->phy_iface;
1122
1123        if (enable) {
1124                if (!bsp_priv->clk_enabled) {
1125                        if (phy_iface == PHY_INTERFACE_MODE_RMII) {
1126                                if (!IS_ERR(bsp_priv->mac_clk_rx))
1127                                        clk_prepare_enable(
1128                                                bsp_priv->mac_clk_rx);
1129
1130                                if (!IS_ERR(bsp_priv->clk_mac_ref))
1131                                        clk_prepare_enable(
1132                                                bsp_priv->clk_mac_ref);
1133
1134                                if (!IS_ERR(bsp_priv->clk_mac_refout))
1135                                        clk_prepare_enable(
1136                                                bsp_priv->clk_mac_refout);
1137                        }
1138
1139                        if (!IS_ERR(bsp_priv->clk_phy))
1140                                clk_prepare_enable(bsp_priv->clk_phy);
1141
1142                        if (!IS_ERR(bsp_priv->aclk_mac))
1143                                clk_prepare_enable(bsp_priv->aclk_mac);
1144
1145                        if (!IS_ERR(bsp_priv->pclk_mac))
1146                                clk_prepare_enable(bsp_priv->pclk_mac);
1147
1148                        if (!IS_ERR(bsp_priv->mac_clk_tx))
1149                                clk_prepare_enable(bsp_priv->mac_clk_tx);
1150
1151                        if (!IS_ERR(bsp_priv->clk_mac_speed))
1152                                clk_prepare_enable(bsp_priv->clk_mac_speed);
1153
1154                        /**
1155                         * if (!IS_ERR(bsp_priv->clk_mac))
1156                         *      clk_prepare_enable(bsp_priv->clk_mac);
1157                         */
1158                        mdelay(5);
1159                        bsp_priv->clk_enabled = true;
1160                }
1161        } else {
1162                if (bsp_priv->clk_enabled) {
1163                        if (phy_iface == PHY_INTERFACE_MODE_RMII) {
1164                                clk_disable_unprepare(bsp_priv->mac_clk_rx);
1165
1166                                clk_disable_unprepare(bsp_priv->clk_mac_ref);
1167
1168                                clk_disable_unprepare(bsp_priv->clk_mac_refout);
1169                        }
1170
1171                        clk_disable_unprepare(bsp_priv->clk_phy);
1172
1173                        clk_disable_unprepare(bsp_priv->aclk_mac);
1174
1175                        clk_disable_unprepare(bsp_priv->pclk_mac);
1176
1177                        clk_disable_unprepare(bsp_priv->mac_clk_tx);
1178
1179                        clk_disable_unprepare(bsp_priv->clk_mac_speed);
1180                        /**
1181                         * if (!IS_ERR(bsp_priv->clk_mac))
1182                         *      clk_disable_unprepare(bsp_priv->clk_mac);
1183                         */
1184                        bsp_priv->clk_enabled = false;
1185                }
1186        }
1187
1188        return 0;
1189}
1190
1191static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
1192{
1193        struct regulator *ldo = bsp_priv->regulator;
1194        int ret;
1195        struct device *dev = &bsp_priv->pdev->dev;
1196
1197        if (!ldo)
1198                return 0;
1199
1200        if (enable) {
1201                ret = regulator_enable(ldo);
1202                if (ret)
1203                        dev_err(dev, "fail to enable phy-supply\n");
1204        } else {
1205                ret = regulator_disable(ldo);
1206                if (ret)
1207                        dev_err(dev, "fail to disable phy-supply\n");
1208        }
1209
1210        return 0;
1211}
1212
1213static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
1214                                          struct plat_stmmacenet_data *plat,
1215                                          const struct rk_gmac_ops *ops)
1216{
1217        struct rk_priv_data *bsp_priv;
1218        struct device *dev = &pdev->dev;
1219        int ret;
1220        const char *strings = NULL;
1221        int value;
1222
1223        bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL);
1224        if (!bsp_priv)
1225                return ERR_PTR(-ENOMEM);
1226
1227        bsp_priv->phy_iface = of_get_phy_mode(dev->of_node);
1228        bsp_priv->ops = ops;
1229
1230        bsp_priv->regulator = devm_regulator_get_optional(dev, "phy");
1231        if (IS_ERR(bsp_priv->regulator)) {
1232                if (PTR_ERR(bsp_priv->regulator) == -EPROBE_DEFER) {
1233                        dev_err(dev, "phy regulator is not available yet, deferred probing\n");
1234                        return ERR_PTR(-EPROBE_DEFER);
1235                }
1236                dev_err(dev, "no regulator found\n");
1237                bsp_priv->regulator = NULL;
1238        }
1239
1240        ret = of_property_read_string(dev->of_node, "clock_in_out", &strings);
1241        if (ret) {
1242                dev_err(dev, "Can not read property: clock_in_out.\n");
1243                bsp_priv->clock_input = true;
1244        } else {
1245                dev_info(dev, "clock input or output? (%s).\n",
1246                         strings);
1247                if (!strcmp(strings, "input"))
1248                        bsp_priv->clock_input = true;
1249                else
1250                        bsp_priv->clock_input = false;
1251        }
1252
1253        ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
1254        if (ret) {
1255                bsp_priv->tx_delay = 0x30;
1256                dev_err(dev, "Can not read property: tx_delay.");
1257                dev_err(dev, "set tx_delay to 0x%x\n",
1258                        bsp_priv->tx_delay);
1259        } else {
1260                dev_info(dev, "TX delay(0x%x).\n", value);
1261                bsp_priv->tx_delay = value;
1262        }
1263
1264        ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
1265        if (ret) {
1266                bsp_priv->rx_delay = 0x10;
1267                dev_err(dev, "Can not read property: rx_delay.");
1268                dev_err(dev, "set rx_delay to 0x%x\n",
1269                        bsp_priv->rx_delay);
1270        } else {
1271                dev_info(dev, "RX delay(0x%x).\n", value);
1272                bsp_priv->rx_delay = value;
1273        }
1274
1275        bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1276                                                        "rockchip,grf");
1277
1278        if (plat->phy_node) {
1279                bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node,
1280                                                                 "phy-is-integrated");
1281                if (bsp_priv->integrated_phy) {
1282                        bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL);
1283                        if (IS_ERR(bsp_priv->phy_reset)) {
1284                                dev_err(&pdev->dev, "No PHY reset control found.\n");
1285                                bsp_priv->phy_reset = NULL;
1286                        }
1287                }
1288        }
1289        dev_info(dev, "integrated PHY? (%s).\n",
1290                 bsp_priv->integrated_phy ? "yes" : "no");
1291
1292        bsp_priv->pdev = pdev;
1293
1294        return bsp_priv;
1295}
1296
1297static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
1298{
1299        int ret;
1300        struct device *dev = &bsp_priv->pdev->dev;
1301
1302        ret = gmac_clk_enable(bsp_priv, true);
1303        if (ret)
1304                return ret;
1305
1306        /*rmii or rgmii*/
1307        switch (bsp_priv->phy_iface) {
1308        case PHY_INTERFACE_MODE_RGMII:
1309                dev_info(dev, "init for RGMII\n");
1310                bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay,
1311                                            bsp_priv->rx_delay);
1312                break;
1313        case PHY_INTERFACE_MODE_RGMII_ID:
1314                dev_info(dev, "init for RGMII_ID\n");
1315                bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
1316                break;
1317        case PHY_INTERFACE_MODE_RGMII_RXID:
1318                dev_info(dev, "init for RGMII_RXID\n");
1319                bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0);
1320                break;
1321        case PHY_INTERFACE_MODE_RGMII_TXID:
1322                dev_info(dev, "init for RGMII_TXID\n");
1323                bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay);
1324                break;
1325        case PHY_INTERFACE_MODE_RMII:
1326                dev_info(dev, "init for RMII\n");
1327                bsp_priv->ops->set_to_rmii(bsp_priv);
1328                break;
1329        default:
1330                dev_err(dev, "NO interface defined!\n");
1331        }
1332
1333        ret = phy_power_on(bsp_priv, true);
1334        if (ret) {
1335                gmac_clk_enable(bsp_priv, false);
1336                return ret;
1337        }
1338
1339        pm_runtime_enable(dev);
1340        pm_runtime_get_sync(dev);
1341
1342        if (bsp_priv->integrated_phy)
1343                rk_gmac_integrated_phy_powerup(bsp_priv);
1344
1345        return 0;
1346}
1347
1348static void rk_gmac_powerdown(struct rk_priv_data *gmac)
1349{
1350        struct device *dev = &gmac->pdev->dev;
1351
1352        if (gmac->integrated_phy)
1353                rk_gmac_integrated_phy_powerdown(gmac);
1354
1355        pm_runtime_put_sync(dev);
1356        pm_runtime_disable(dev);
1357
1358        phy_power_on(gmac, false);
1359        gmac_clk_enable(gmac, false);
1360}
1361
1362static void rk_fix_speed(void *priv, unsigned int speed)
1363{
1364        struct rk_priv_data *bsp_priv = priv;
1365        struct device *dev = &bsp_priv->pdev->dev;
1366
1367        switch (bsp_priv->phy_iface) {
1368        case PHY_INTERFACE_MODE_RGMII:
1369        case PHY_INTERFACE_MODE_RGMII_ID:
1370        case PHY_INTERFACE_MODE_RGMII_RXID:
1371        case PHY_INTERFACE_MODE_RGMII_TXID:
1372                bsp_priv->ops->set_rgmii_speed(bsp_priv, speed);
1373                break;
1374        case PHY_INTERFACE_MODE_RMII:
1375                bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
1376                break;
1377        default:
1378                dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
1379        }
1380}
1381
1382static int rk_gmac_probe(struct platform_device *pdev)
1383{
1384        struct plat_stmmacenet_data *plat_dat;
1385        struct stmmac_resources stmmac_res;
1386        const struct rk_gmac_ops *data;
1387        int ret;
1388
1389        data = of_device_get_match_data(&pdev->dev);
1390        if (!data) {
1391                dev_err(&pdev->dev, "no of match data provided\n");
1392                return -EINVAL;
1393        }
1394
1395        ret = stmmac_get_platform_resources(pdev, &stmmac_res);
1396        if (ret)
1397                return ret;
1398
1399        plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
1400        if (IS_ERR(plat_dat))
1401                return PTR_ERR(plat_dat);
1402
1403        plat_dat->has_gmac = true;
1404        plat_dat->fix_mac_speed = rk_fix_speed;
1405
1406        plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data);
1407        if (IS_ERR(plat_dat->bsp_priv)) {
1408                ret = PTR_ERR(plat_dat->bsp_priv);
1409                goto err_remove_config_dt;
1410        }
1411
1412        ret = rk_gmac_clk_init(plat_dat);
1413        if (ret)
1414                return ret;
1415
1416        ret = rk_gmac_powerup(plat_dat->bsp_priv);
1417        if (ret)
1418                goto err_remove_config_dt;
1419
1420        ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
1421        if (ret)
1422                goto err_gmac_powerdown;
1423
1424        return 0;
1425
1426err_gmac_powerdown:
1427        rk_gmac_powerdown(plat_dat->bsp_priv);
1428err_remove_config_dt:
1429        stmmac_remove_config_dt(pdev, plat_dat);
1430
1431        return ret;
1432}
1433
1434static int rk_gmac_remove(struct platform_device *pdev)
1435{
1436        struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(&pdev->dev);
1437        int ret = stmmac_dvr_remove(&pdev->dev);
1438
1439        rk_gmac_powerdown(bsp_priv);
1440
1441        return ret;
1442}
1443
1444#ifdef CONFIG_PM_SLEEP
1445static int rk_gmac_suspend(struct device *dev)
1446{
1447        struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
1448        int ret = stmmac_suspend(dev);
1449
1450        /* Keep the PHY up if we use Wake-on-Lan. */
1451        if (!device_may_wakeup(dev)) {
1452                rk_gmac_powerdown(bsp_priv);
1453                bsp_priv->suspended = true;
1454        }
1455
1456        return ret;
1457}
1458
1459static int rk_gmac_resume(struct device *dev)
1460{
1461        struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
1462
1463        /* The PHY was up for Wake-on-Lan. */
1464        if (bsp_priv->suspended) {
1465                rk_gmac_powerup(bsp_priv);
1466                bsp_priv->suspended = false;
1467        }
1468
1469        return stmmac_resume(dev);
1470}
1471#endif /* CONFIG_PM_SLEEP */
1472
1473static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume);
1474
1475static const struct of_device_id rk_gmac_dwmac_match[] = {
1476        { .compatible = "rockchip,px30-gmac",   .data = &px30_ops   },
1477        { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops },
1478        { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
1479        { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
1480        { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
1481        { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
1482        { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
1483        { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
1484        { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
1485        { }
1486};
1487MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
1488
1489static struct platform_driver rk_gmac_dwmac_driver = {
1490        .probe  = rk_gmac_probe,
1491        .remove = rk_gmac_remove,
1492        .driver = {
1493                .name           = "rk_gmac-dwmac",
1494                .pm             = &rk_gmac_pm_ops,
1495                .of_match_table = rk_gmac_dwmac_match,
1496        },
1497};
1498module_platform_driver(rk_gmac_dwmac_driver);
1499
1500MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
1501MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");
1502MODULE_LICENSE("GPL");
1503