1/* 2 * Xilinx TSN PTP header 3 * 4 * Copyright (C) 2017 Xilinx, Inc. 5 * 6 * Author: Syed S <syeds@xilinx.com> 7 * 8 * This software is licensed under the terms of the GNU General Public 9 * License version 2, as published by the Free Software Foundation, and 10 * may be copied, distributed, and modified under those terms. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18#ifndef _TSN_PTP_H_ 19#define _TSN_PTP_H_ 20 21#define PTP_HW_TSTAMP_SIZE 8 /* 64 bit timestamp */ 22#define PTP_RX_HWBUF_SIZE 256 23#define PTP_RX_FRAME_SIZE 252 24#define PTP_HW_TSTAMP_OFFSET (PTP_RX_HWBUF_SIZE - PTP_HW_TSTAMP_SIZE) 25 26#define PTP_MSG_TYPE_MASK BIT(3) 27#define PTP_TYPE_SYNC 0x0 28#define PTP_TYPE_FOLLOW_UP 0x8 29#define PTP_TYPE_PDELAYREQ 0x2 30#define PTP_TYPE_PDELAYRESP 0x3 31#define PTP_TYPE_PDELAYRESP_FOLLOW_UP 0xA 32#define PTP_TYPE_ANNOUNCE 0xB 33#define PTP_TYPE_SIGNALING 0xC 34 35#define PTP_TX_CONTROL_OFFSET 0x00012000 /**< Tx PTP Control Reg */ 36#define PTP_RX_CONTROL_OFFSET 0x00012004 /**< Rx PTP Control Reg */ 37#define RX_FILTER_CONTROL 0x00012008 /**< Rx Filter Ctrl Reg */ 38 39#define PTP_RX_BASE_OFFSET 0x00010000 40#define PTP_RX_CONTROL_OFFSET 0x00012004 /**< Rx PTP Control Reg */ 41#define PTP_RX_PACKET_FIELD_MASK 0x00000F00 42#define PTP_RX_PACKET_CLEAR 0x00000001 43 44#define PTP_TX_BUFFER_OFFSET(index) (0x00011000 + (index) * 0x100) 45 46#define PTP_TX_CMD_FIELD_LEN 8 47#define PTP_TX_CMD_1STEP_SHIFT BIT(16) 48#define PTP_TX_BUFFER_CMD2_FIELD 0x4 49 50#define PTP_TX_SYNC_OFFSET 0x00011000 51#define PTP_TX_FOLLOW_UP_OFFSET 0x00011100 52#define PTP_TX_PDELAYREQ_OFFSET 0x00011200 53#define PTP_TX_PDELAYRESP_OFFSET 0x00011300 54#define PTP_TX_PDELAYRESP_FOLLOW_UP_OFFSET 0x00011400 55#define PTP_TX_ANNOUNCE_OFFSET 0x00011500 56#define PTP_TX_SIGNALING_OFFSET 0x00011600 57#define PTP_TX_GENERIC_OFFSET 0x00011700 58#define PTP_TX_SEND_SYNC_FRAME_MASK 0x00000001 59#define PTP_TX_SEND_FOLLOWUP_FRAME_MASK 0x00000002 60#define PTP_TX_SEND_PDELAYREQ_FRAME_MASK 0x00000004 61#define PTP_TX_SEND_PDELAYRESP_FRAME_MASK 0x00000008 62#define PTP_TX_SEND_PDELAYRESPFOLLOWUP_FRAME_MASK 0x00000010 63#define PTP_TX_SEND_ANNOUNCE_FRAME_MASK 0x00000020 64#define PTP_TX_SEND_FRAME6_BIT_MASK 0x00000040 65#define PTP_TX_SEND_FRAME7_BIT_MASK 0x00000080 66#define PTP_TX_FRAME_WAITING_MASK 0x0000ff00 67#define PTP_TX_FRAME_WAITING_SHIFT 8 68#define PTP_TX_WAIT_SYNC_FRAME_MASK 0x00000100 69#define PTP_TX_WAIT_FOLLOWUP_FRAME_MASK 0x00000200 70#define PTP_TX_WAIT_PDELAYREQ_FRAME_MASK 0x00000400 71#define PTP_TX_WAIT_PDELAYRESP_FRAME_MASK 0x00000800 72#define PTP_TX_WAIT_PDELAYRESPFOLLOWUP_FRAME_MASK 0x00001000 73#define PTP_TX_WAIT_ANNOUNCE_FRAME_MASK 0x00002000 74#define PTP_TX_WAIT_FRAME6_BIT_MASK 0x00004000 75#define PTP_TX_WAIT_FRAME7_BIT_MASK 0x00008000 76#define PTP_TX_WAIT_ALL_FRAMES_MASK 0x0000FF00 77#define PTP_TX_PACKET_FIELD_MASK 0x00070000 78#define PTP_TX_PACKET_FIELD_SHIFT 16 79/* 1-step Correction Field offset 802.1 ASrev */ 80#define PTP_CRCT_FIELD_OFFSET 22 81/* 1-step Time Of Day offset 1588-2008 */ 82#define PTP_TOD_FIELD_OFFSET 48 83 84int axienet_ptp_xmit(struct sk_buff *skb, struct net_device *ndev); 85irqreturn_t axienet_ptp_rx_irq(int irq, void *_ndev); 86irqreturn_t axienet_ptp_tx_irq(int irq, void *_ndev); 87 88#endif 89