1
2
3
4#include "../wifi.h"
5#include "../efuse.h"
6#include "../base.h"
7#include "../regd.h"
8#include "../cam.h"
9#include "../ps.h"
10#include "../pci.h"
11#include "../pwrseqcmd.h"
12#include "reg.h"
13#include "def.h"
14#include "phy.h"
15#include "dm.h"
16#include "fw.h"
17#include "led.h"
18#include "hw.h"
19#include "pwrseq.h"
20
21#define LLT_CONFIG 5
22
23static void _rtl88ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
24 u8 set_bits, u8 clear_bits)
25{
26 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
27 struct rtl_priv *rtlpriv = rtl_priv(hw);
28
29 rtlpci->reg_bcn_ctrl_val |= set_bits;
30 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
31
32 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
33}
34
35static void _rtl88ee_stop_tx_beacon(struct ieee80211_hw *hw)
36{
37 struct rtl_priv *rtlpriv = rtl_priv(hw);
38 u8 tmp1byte;
39
40 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
41 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
42 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
43 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
44 tmp1byte &= ~(BIT(0));
45 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
46}
47
48static void _rtl88ee_resume_tx_beacon(struct ieee80211_hw *hw)
49{
50 struct rtl_priv *rtlpriv = rtl_priv(hw);
51 u8 tmp1byte;
52
53 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
54 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
55 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
56 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
57 tmp1byte |= BIT(0);
58 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
59}
60
61static void _rtl88ee_enable_bcn_sub_func(struct ieee80211_hw *hw)
62{
63 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(1));
64}
65
66static void _rtl88ee_return_beacon_queue_skb(struct ieee80211_hw *hw)
67{
68 struct rtl_priv *rtlpriv = rtl_priv(hw);
69 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
70 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
71 unsigned long flags;
72
73 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
74 while (skb_queue_len(&ring->queue)) {
75 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
76 struct sk_buff *skb = __skb_dequeue(&ring->queue);
77
78 pci_unmap_single(rtlpci->pdev,
79 rtlpriv->cfg->ops->get_desc(
80 hw,
81 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
82 skb->len, PCI_DMA_TODEVICE);
83 kfree_skb(skb);
84 ring->idx = (ring->idx + 1) % ring->entries;
85 }
86 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
87}
88
89static void _rtl88ee_disable_bcn_sub_func(struct ieee80211_hw *hw)
90{
91 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(1), 0);
92}
93
94static void _rtl88ee_set_fw_clock_on(struct ieee80211_hw *hw,
95 u8 rpwm_val, bool b_need_turn_off_ckk)
96{
97 struct rtl_priv *rtlpriv = rtl_priv(hw);
98 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
99 bool b_support_remote_wake_up;
100 u32 count = 0, isr_regaddr, content;
101 bool schedule_timer = b_need_turn_off_ckk;
102 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
103 (u8 *)(&b_support_remote_wake_up));
104
105 if (!rtlhal->fw_ready)
106 return;
107 if (!rtlpriv->psc.fw_current_inpsmode)
108 return;
109
110 while (1) {
111 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
112 if (rtlhal->fw_clk_change_in_progress) {
113 while (rtlhal->fw_clk_change_in_progress) {
114 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
115 count++;
116 udelay(100);
117 if (count > 1000)
118 return;
119 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
120 }
121 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
122 } else {
123 rtlhal->fw_clk_change_in_progress = false;
124 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
125 break;
126 }
127 }
128
129 if (IS_IN_LOW_POWER_STATE_88E(rtlhal->fw_ps_state)) {
130 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
131 if (FW_PS_IS_ACK(rpwm_val)) {
132 isr_regaddr = REG_HISR;
133 content = rtl_read_dword(rtlpriv, isr_regaddr);
134 while (!(content & IMR_CPWM) && (count < 500)) {
135 udelay(50);
136 count++;
137 content = rtl_read_dword(rtlpriv, isr_regaddr);
138 }
139
140 if (content & IMR_CPWM) {
141 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
142 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_88E;
143 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
144 "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n",
145 rtlhal->fw_ps_state);
146 }
147 }
148
149 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
150 rtlhal->fw_clk_change_in_progress = false;
151 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
152 if (schedule_timer) {
153 mod_timer(&rtlpriv->works.fw_clockoff_timer,
154 jiffies + MSECS(10));
155 }
156
157 } else {
158 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
159 rtlhal->fw_clk_change_in_progress = false;
160 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
161 }
162}
163
164static void _rtl88ee_set_fw_clock_off(struct ieee80211_hw *hw,
165 u8 rpwm_val)
166{
167 struct rtl_priv *rtlpriv = rtl_priv(hw);
168 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
169 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
170 struct rtl8192_tx_ring *ring;
171 enum rf_pwrstate rtstate;
172 bool schedule_timer = false;
173 u8 queue;
174
175 if (!rtlhal->fw_ready)
176 return;
177 if (!rtlpriv->psc.fw_current_inpsmode)
178 return;
179 if (!rtlhal->allow_sw_to_change_hwclc)
180 return;
181 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
182 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
183 return;
184
185 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
186 ring = &rtlpci->tx_ring[queue];
187 if (skb_queue_len(&ring->queue)) {
188 schedule_timer = true;
189 break;
190 }
191 }
192
193 if (schedule_timer) {
194 mod_timer(&rtlpriv->works.fw_clockoff_timer,
195 jiffies + MSECS(10));
196 return;
197 }
198
199 if (FW_PS_STATE(rtlhal->fw_ps_state) !=
200 FW_PS_STATE_RF_OFF_LOW_PWR_88E) {
201 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
202 if (!rtlhal->fw_clk_change_in_progress) {
203 rtlhal->fw_clk_change_in_progress = true;
204 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
205 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
206 rtl_write_word(rtlpriv, REG_HISR, 0x0100);
207 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
208 &rpwm_val);
209 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
210 rtlhal->fw_clk_change_in_progress = false;
211 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
212 } else {
213 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
214 mod_timer(&rtlpriv->works.fw_clockoff_timer,
215 jiffies + MSECS(10));
216 }
217 }
218}
219
220static void _rtl88ee_set_fw_ps_rf_on(struct ieee80211_hw *hw)
221{
222 u8 rpwm_val = 0;
223
224 rpwm_val |= (FW_PS_STATE_RF_OFF_88E | FW_PS_ACK);
225 _rtl88ee_set_fw_clock_on(hw, rpwm_val, true);
226}
227
228static void _rtl88ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw)
229{
230 u8 rpwm_val = 0;
231 rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR_88E;
232 _rtl88ee_set_fw_clock_off(hw, rpwm_val);
233}
234
235void rtl88ee_fw_clk_off_timer_callback(struct timer_list *t)
236{
237 struct rtl_priv *rtlpriv = from_timer(rtlpriv, t,
238 works.fw_clockoff_timer);
239 struct ieee80211_hw *hw = rtlpriv->hw;
240
241 _rtl88ee_set_fw_ps_rf_off_low_power(hw);
242}
243
244static void _rtl88ee_fwlps_leave(struct ieee80211_hw *hw)
245{
246 struct rtl_priv *rtlpriv = rtl_priv(hw);
247 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
248 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
249 bool fw_current_inps = false;
250 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
251
252 if (ppsc->low_power_enable) {
253 rpwm_val = (FW_PS_STATE_ALL_ON_88E|FW_PS_ACK);
254 _rtl88ee_set_fw_clock_on(hw, rpwm_val, false);
255 rtlhal->allow_sw_to_change_hwclc = false;
256 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
257 &fw_pwrmode);
258 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
259 (u8 *)(&fw_current_inps));
260 } else {
261 rpwm_val = FW_PS_STATE_ALL_ON_88E;
262 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
263 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
264 &fw_pwrmode);
265 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
266 (u8 *)(&fw_current_inps));
267 }
268}
269
270static void _rtl88ee_fwlps_enter(struct ieee80211_hw *hw)
271{
272 struct rtl_priv *rtlpriv = rtl_priv(hw);
273 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
274 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
275 bool fw_current_inps = true;
276 u8 rpwm_val;
277
278 if (ppsc->low_power_enable) {
279 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_88E;
280 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
281 (u8 *)(&fw_current_inps));
282 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
283 &ppsc->fwctrl_psmode);
284 rtlhal->allow_sw_to_change_hwclc = true;
285 _rtl88ee_set_fw_clock_off(hw, rpwm_val);
286 } else {
287 rpwm_val = FW_PS_STATE_RF_OFF_88E;
288 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
289 (u8 *)(&fw_current_inps));
290 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
291 &ppsc->fwctrl_psmode);
292 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
293 }
294}
295
296void rtl88ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
297{
298 struct rtl_priv *rtlpriv = rtl_priv(hw);
299 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
300 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
301
302 switch (variable) {
303 case HW_VAR_RCR:
304 *((u32 *)(val)) = rtlpci->receive_config;
305 break;
306 case HW_VAR_RF_STATE:
307 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
308 break;
309 case HW_VAR_FWLPS_RF_ON:{
310 enum rf_pwrstate rfstate;
311 u32 val_rcr;
312
313 rtlpriv->cfg->ops->get_hw_reg(hw,
314 HW_VAR_RF_STATE,
315 (u8 *)(&rfstate));
316 if (rfstate == ERFOFF) {
317 *((bool *)(val)) = true;
318 } else {
319 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
320 val_rcr &= 0x00070000;
321 if (val_rcr)
322 *((bool *)(val)) = false;
323 else
324 *((bool *)(val)) = true;
325 }
326 break; }
327 case HW_VAR_FW_PSMODE_STATUS:
328 *((bool *)(val)) = ppsc->fw_current_inpsmode;
329 break;
330 case HW_VAR_CORRECT_TSF:{
331 u64 tsf;
332 u32 *ptsf_low = (u32 *)&tsf;
333 u32 *ptsf_high = ((u32 *)&tsf) + 1;
334
335 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
336 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
337
338 *((u64 *)(val)) = tsf;
339 break; }
340 case HAL_DEF_WOWLAN:
341 break;
342 default:
343 pr_err("switch case %#x not processed\n", variable);
344 break;
345 }
346}
347
348void rtl88ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
349{
350 struct rtl_priv *rtlpriv = rtl_priv(hw);
351 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
352 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
353 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
354 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
355 u8 idx;
356
357 switch (variable) {
358 case HW_VAR_ETHER_ADDR:
359 for (idx = 0; idx < ETH_ALEN; idx++) {
360 rtl_write_byte(rtlpriv, (REG_MACID + idx),
361 val[idx]);
362 }
363 break;
364 case HW_VAR_BASIC_RATE:{
365 u16 b_rate_cfg = ((u16 *)val)[0];
366 u8 rate_index = 0;
367 b_rate_cfg = b_rate_cfg & 0x15f;
368 b_rate_cfg |= 0x01;
369 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
370 rtl_write_byte(rtlpriv, REG_RRSR + 1,
371 (b_rate_cfg >> 8) & 0xff);
372 while (b_rate_cfg > 0x1) {
373 b_rate_cfg = (b_rate_cfg >> 1);
374 rate_index++;
375 }
376 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
377 rate_index);
378 break;
379 }
380 case HW_VAR_BSSID:
381 for (idx = 0; idx < ETH_ALEN; idx++) {
382 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
383 val[idx]);
384 }
385 break;
386 case HW_VAR_SIFS:
387 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
388 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
389
390 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
391 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
392
393 if (!mac->ht_enable)
394 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
395 0x0e0e);
396 else
397 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
398 *((u16 *)val));
399 break;
400 case HW_VAR_SLOT_TIME:{
401 u8 e_aci;
402
403 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
404 "HW_VAR_SLOT_TIME %x\n", val[0]);
405
406 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
407
408 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
409 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
410 &e_aci);
411 }
412 break;
413 }
414 case HW_VAR_ACK_PREAMBLE:{
415 u8 reg_tmp;
416 u8 short_preamble = (bool)*val;
417 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
418 if (short_preamble) {
419 reg_tmp |= 0x02;
420 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL +
421 2, reg_tmp);
422 } else {
423 reg_tmp |= 0xFD;
424 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL +
425 2, reg_tmp);
426 }
427 break; }
428 case HW_VAR_WPA_CONFIG:
429 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
430 break;
431 case HW_VAR_AMPDU_MIN_SPACE:{
432 u8 min_spacing_to_set;
433 u8 sec_min_space;
434
435 min_spacing_to_set = *val;
436 if (min_spacing_to_set <= 7) {
437 sec_min_space = 0;
438
439 if (min_spacing_to_set < sec_min_space)
440 min_spacing_to_set = sec_min_space;
441
442 mac->min_space_cfg = ((mac->min_space_cfg &
443 0xf8) |
444 min_spacing_to_set);
445
446 *val = min_spacing_to_set;
447
448 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
449 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
450 mac->min_space_cfg);
451
452 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
453 mac->min_space_cfg);
454 }
455 break; }
456 case HW_VAR_SHORTGI_DENSITY:{
457 u8 density_to_set;
458
459 density_to_set = *val;
460 mac->min_space_cfg |= (density_to_set << 3);
461
462 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
463 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
464 mac->min_space_cfg);
465
466 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
467 mac->min_space_cfg);
468 break;
469 }
470 case HW_VAR_AMPDU_FACTOR:{
471 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
472 u8 factor_toset;
473 u8 *p_regtoset = NULL;
474 u8 index = 0;
475
476 p_regtoset = regtoset_normal;
477
478 factor_toset = *val;
479 if (factor_toset <= 3) {
480 factor_toset = (1 << (factor_toset + 2));
481 if (factor_toset > 0xf)
482 factor_toset = 0xf;
483
484 for (index = 0; index < 4; index++) {
485 if ((p_regtoset[index] & 0xf0) >
486 (factor_toset << 4))
487 p_regtoset[index] =
488 (p_regtoset[index] & 0x0f) |
489 (factor_toset << 4);
490
491 if ((p_regtoset[index] & 0x0f) >
492 factor_toset)
493 p_regtoset[index] =
494 (p_regtoset[index] & 0xf0) |
495 (factor_toset);
496
497 rtl_write_byte(rtlpriv,
498 (REG_AGGLEN_LMT + index),
499 p_regtoset[index]);
500
501 }
502
503 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
504 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
505 factor_toset);
506 }
507 break; }
508 case HW_VAR_AC_PARAM:{
509 u8 e_aci = *val;
510 rtl88e_dm_init_edca_turbo(hw);
511
512 if (rtlpci->acm_method != EACMWAY2_SW)
513 rtlpriv->cfg->ops->set_hw_reg(hw,
514 HW_VAR_ACM_CTRL,
515 &e_aci);
516 break; }
517 case HW_VAR_ACM_CTRL:{
518 u8 e_aci = *val;
519 union aci_aifsn *p_aci_aifsn =
520 (union aci_aifsn *)(&(mac->ac[0].aifs));
521 u8 acm = p_aci_aifsn->f.acm;
522 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
523
524 acm_ctrl = acm_ctrl |
525 ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
526
527 if (acm) {
528 switch (e_aci) {
529 case AC0_BE:
530 acm_ctrl |= ACMHW_BEQEN;
531 break;
532 case AC2_VI:
533 acm_ctrl |= ACMHW_VIQEN;
534 break;
535 case AC3_VO:
536 acm_ctrl |= ACMHW_VOQEN;
537 break;
538 default:
539 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
540 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
541 acm);
542 break;
543 }
544 } else {
545 switch (e_aci) {
546 case AC0_BE:
547 acm_ctrl &= (~ACMHW_BEQEN);
548 break;
549 case AC2_VI:
550 acm_ctrl &= (~ACMHW_VIQEN);
551 break;
552 case AC3_VO:
553 acm_ctrl &= (~ACMHW_VOQEN);
554 break;
555 default:
556 pr_err("switch case %#x not processed\n",
557 e_aci);
558 break;
559 }
560 }
561
562 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
563 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
564 acm_ctrl);
565 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
566 break; }
567 case HW_VAR_RCR:
568 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
569 rtlpci->receive_config = ((u32 *)(val))[0];
570 break;
571 case HW_VAR_RETRY_LIMIT:{
572 u8 retry_limit = *val;
573
574 rtl_write_word(rtlpriv, REG_RL,
575 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
576 retry_limit << RETRY_LIMIT_LONG_SHIFT);
577 break; }
578 case HW_VAR_DUAL_TSF_RST:
579 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
580 break;
581 case HW_VAR_EFUSE_BYTES:
582 rtlefuse->efuse_usedbytes = *((u16 *)val);
583 break;
584 case HW_VAR_EFUSE_USAGE:
585 rtlefuse->efuse_usedpercentage = *val;
586 break;
587 case HW_VAR_IO_CMD:
588 rtl88e_phy_set_io_cmd(hw, (*(enum io_type *)val));
589 break;
590 case HW_VAR_SET_RPWM:{
591 u8 rpwm_val;
592
593 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
594 udelay(1);
595
596 if (rpwm_val & BIT(7)) {
597 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val);
598 } else {
599 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val | BIT(7));
600 }
601 break; }
602 case HW_VAR_H2C_FW_PWRMODE:
603 rtl88e_set_fw_pwrmode_cmd(hw, *val);
604 break;
605 case HW_VAR_FW_PSMODE_STATUS:
606 ppsc->fw_current_inpsmode = *((bool *)val);
607 break;
608 case HW_VAR_RESUME_CLK_ON:
609 _rtl88ee_set_fw_ps_rf_on(hw);
610 break;
611 case HW_VAR_FW_LPS_ACTION:{
612 bool enter_fwlps = *((bool *)val);
613
614 if (enter_fwlps)
615 _rtl88ee_fwlps_enter(hw);
616 else
617 _rtl88ee_fwlps_leave(hw);
618
619 break; }
620 case HW_VAR_H2C_FW_JOINBSSRPT:{
621 u8 mstatus = *val;
622 u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
623 u8 count = 0, dlbcn_count = 0;
624 bool b_recover = false;
625
626 if (mstatus == RT_MEDIA_CONNECT) {
627 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
628 NULL);
629
630 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
631 rtl_write_byte(rtlpriv, REG_CR + 1,
632 (tmp_regcr | BIT(0)));
633
634 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
635 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
636
637 tmp_reg422 =
638 rtl_read_byte(rtlpriv,
639 REG_FWHW_TXQ_CTRL + 2);
640 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
641 tmp_reg422 & (~BIT(6)));
642 if (tmp_reg422 & BIT(6))
643 b_recover = true;
644
645 do {
646 bcnvalid_reg = rtl_read_byte(rtlpriv,
647 REG_TDECTRL+2);
648 rtl_write_byte(rtlpriv, REG_TDECTRL+2,
649 (bcnvalid_reg | BIT(0)));
650 _rtl88ee_return_beacon_queue_skb(hw);
651
652 rtl88e_set_fw_rsvdpagepkt(hw, 0);
653 bcnvalid_reg = rtl_read_byte(rtlpriv,
654 REG_TDECTRL+2);
655 count = 0;
656 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
657 count++;
658 udelay(10);
659 bcnvalid_reg =
660 rtl_read_byte(rtlpriv, REG_TDECTRL+2);
661 }
662 dlbcn_count++;
663 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
664
665 if (bcnvalid_reg & BIT(0))
666 rtl_write_byte(rtlpriv, REG_TDECTRL+2, BIT(0));
667
668 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
669 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
670
671 if (b_recover) {
672 rtl_write_byte(rtlpriv,
673 REG_FWHW_TXQ_CTRL + 2,
674 tmp_reg422);
675 }
676
677 rtl_write_byte(rtlpriv, REG_CR + 1,
678 (tmp_regcr & ~(BIT(0))));
679 }
680 rtl88e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val));
681 break; }
682 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
683 rtl88e_set_p2p_ps_offload_cmd(hw, *val);
684 break;
685 case HW_VAR_AID:{
686 u16 u2btmp;
687
688 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
689 u2btmp &= 0xC000;
690 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
691 mac->assoc_id));
692 break; }
693 case HW_VAR_CORRECT_TSF:{
694 u8 btype_ibss = *val;
695
696 if (btype_ibss)
697 _rtl88ee_stop_tx_beacon(hw);
698
699 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
700
701 rtl_write_dword(rtlpriv, REG_TSFTR,
702 (u32)(mac->tsf & 0xffffffff));
703 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
704 (u32)((mac->tsf >> 32) & 0xffffffff));
705
706 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
707
708 if (btype_ibss)
709 _rtl88ee_resume_tx_beacon(hw);
710 break; }
711 case HW_VAR_KEEP_ALIVE: {
712 u8 array[2];
713
714 array[0] = 0xff;
715 array[1] = *((u8 *)val);
716 rtl88e_fill_h2c_cmd(hw, H2C_88E_KEEP_ALIVE_CTRL,
717 2, array);
718 break; }
719 default:
720 pr_err("switch case %#x not processed\n", variable);
721 break;
722 }
723}
724
725static bool _rtl88ee_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
726{
727 struct rtl_priv *rtlpriv = rtl_priv(hw);
728 bool status = true;
729 long count = 0;
730 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
731 _LLT_OP(_LLT_WRITE_ACCESS);
732
733 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
734
735 do {
736 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
737 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
738 break;
739
740 if (count > POLLING_LLT_THRESHOLD) {
741 pr_err("Failed to polling write LLT done at address %d!\n",
742 address);
743 status = false;
744 break;
745 }
746 } while (++count);
747
748 return status;
749}
750
751static bool _rtl88ee_llt_table_init(struct ieee80211_hw *hw)
752{
753 struct rtl_priv *rtlpriv = rtl_priv(hw);
754 unsigned short i;
755 u8 txpktbuf_bndy;
756 u8 maxpage;
757 bool status;
758
759 maxpage = 0xAF;
760 txpktbuf_bndy = 0xAB;
761
762 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x01);
763 rtl_write_dword(rtlpriv, REG_RQPN, 0x80730d29);
764
765
766 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x25FF0000 | txpktbuf_bndy));
767 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
768
769 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
770 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
771
772 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
773 rtl_write_byte(rtlpriv, REG_PBP, 0x11);
774 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
775
776 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
777 status = _rtl88ee_llt_write(hw, i, i + 1);
778 if (true != status)
779 return status;
780 }
781
782 status = _rtl88ee_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
783 if (true != status)
784 return status;
785
786 for (i = txpktbuf_bndy; i < maxpage; i++) {
787 status = _rtl88ee_llt_write(hw, i, (i + 1));
788 if (true != status)
789 return status;
790 }
791
792 status = _rtl88ee_llt_write(hw, maxpage, txpktbuf_bndy);
793 if (true != status)
794 return status;
795
796 return true;
797}
798
799static void _rtl88ee_gen_refresh_led_state(struct ieee80211_hw *hw)
800{
801 struct rtl_priv *rtlpriv = rtl_priv(hw);
802 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
803 struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
804
805 if (rtlpriv->rtlhal.up_first_time)
806 return;
807
808 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
809 rtl88ee_sw_led_on(hw, pled0);
810 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
811 rtl88ee_sw_led_on(hw, pled0);
812 else
813 rtl88ee_sw_led_off(hw, pled0);
814}
815
816static bool _rtl88ee_init_mac(struct ieee80211_hw *hw)
817{
818 struct rtl_priv *rtlpriv = rtl_priv(hw);
819 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
820 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
821
822 u8 bytetmp;
823 u16 wordtmp;
824
825
826 bytetmp = rtl_read_byte(rtlpriv, REG_XCK_OUT_CTRL) & (~BIT(0));
827 rtl_write_byte(rtlpriv, REG_XCK_OUT_CTRL, bytetmp);
828
829 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
830 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
831
832 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
833
834 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
835 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
836 RTL8188EE_NIC_ENABLE_FLOW)) {
837 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
838 "init MAC Fail as rtl_hal_pwrseqcmdparsing\n");
839 return false;
840 }
841
842 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
843 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
844
845 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2);
846 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp|BIT(2));
847
848 bytetmp = rtl_read_byte(rtlpriv, REG_WATCH_DOG+1);
849 rtl_write_byte(rtlpriv, REG_WATCH_DOG+1, bytetmp|BIT(7));
850
851 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1);
852 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1, bytetmp|BIT(1));
853
854 bytetmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);
855 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, bytetmp|BIT(1)|BIT(0));
856 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL+1, 2);
857 rtl_write_word(rtlpriv, REG_TX_RPT_TIME, 0xcdf0);
858
859
860 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
861
862 rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp|BIT(3));
863 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG+1);
864 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+1, (bytetmp & (~BIT(4))));
865 rtl_write_byte(rtlpriv, 0x367, 0x80);
866
867 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
868 rtl_write_byte(rtlpriv, REG_CR+1, 0x06);
869 rtl_write_byte(rtlpriv, MSR, 0x00);
870
871 if (!rtlhal->mac_func_enable) {
872 if (_rtl88ee_llt_table_init(hw) == false) {
873 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
874 "LLT table init fail\n");
875 return false;
876 }
877 }
878 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
879 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
880
881 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
882 wordtmp &= 0xf;
883 wordtmp |= 0xE771;
884 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
885
886 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
887 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff);
888 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
889
890 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
891 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
892 DMA_BIT_MASK(32));
893 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
894 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
895 DMA_BIT_MASK(32));
896 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
897 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
898 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
899 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
900 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
901 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
902 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
903 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
904 rtl_write_dword(rtlpriv, REG_HQ_DESA,
905 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
906 DMA_BIT_MASK(32));
907 rtl_write_dword(rtlpriv, REG_RX_DESA,
908 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
909 DMA_BIT_MASK(32));
910
911
912
913
914 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
915
916 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
917 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0);
918
919 if (rtlhal->earlymode_enable) {
920 bytetmp = rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL);
921 bytetmp |= 0x1f;
922 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, bytetmp);
923 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL+3, 0x81);
924 }
925 _rtl88ee_gen_refresh_led_state(hw);
926 return true;
927}
928
929static void _rtl88ee_hw_configure(struct ieee80211_hw *hw)
930{
931 struct rtl_priv *rtlpriv = rtl_priv(hw);
932 u32 reg_prsr;
933
934 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
935
936 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
937 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
938}
939
940static void _rtl88ee_enable_aspm_back_door(struct ieee80211_hw *hw)
941{
942 struct rtl_priv *rtlpriv = rtl_priv(hw);
943 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
944 u8 tmp1byte = 0;
945 u32 tmp4byte = 0, count = 0;
946
947 rtl_write_word(rtlpriv, 0x354, 0x8104);
948 rtl_write_word(rtlpriv, 0x358, 0x24);
949
950 rtl_write_word(rtlpriv, 0x350, 0x70c);
951 rtl_write_byte(rtlpriv, 0x352, 0x2);
952 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
953 count = 0;
954 while (tmp1byte && count < 20) {
955 udelay(10);
956 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
957 count++;
958 }
959 if (0 == tmp1byte) {
960 tmp4byte = rtl_read_dword(rtlpriv, 0x34c);
961 rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(31));
962 rtl_write_word(rtlpriv, 0x350, 0xf70c);
963 rtl_write_byte(rtlpriv, 0x352, 0x1);
964 }
965
966 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
967 count = 0;
968 while (tmp1byte && count < 20) {
969 udelay(10);
970 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
971 count++;
972 }
973
974 rtl_write_word(rtlpriv, 0x350, 0x718);
975 rtl_write_byte(rtlpriv, 0x352, 0x2);
976 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
977 count = 0;
978 while (tmp1byte && count < 20) {
979 udelay(10);
980 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
981 count++;
982 }
983
984 if (ppsc->support_backdoor || (0 == tmp1byte)) {
985 tmp4byte = rtl_read_dword(rtlpriv, 0x34c);
986 rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(11)|BIT(12));
987 rtl_write_word(rtlpriv, 0x350, 0xf718);
988 rtl_write_byte(rtlpriv, 0x352, 0x1);
989 }
990
991 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
992 count = 0;
993 while (tmp1byte && count < 20) {
994 udelay(10);
995 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
996 count++;
997 }
998}
999
1000void rtl88ee_enable_hw_security_config(struct ieee80211_hw *hw)
1001{
1002 struct rtl_priv *rtlpriv = rtl_priv(hw);
1003 u8 sec_reg_value;
1004
1005 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1006 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1007 rtlpriv->sec.pairwise_enc_algorithm,
1008 rtlpriv->sec.group_enc_algorithm);
1009
1010 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1011 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1012 "not open hw encryption\n");
1013 return;
1014 }
1015
1016 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1017
1018 if (rtlpriv->sec.use_defaultkey) {
1019 sec_reg_value |= SCR_TXUSEDK;
1020 sec_reg_value |= SCR_RXUSEDK;
1021 }
1022
1023 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1024
1025 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1026
1027 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1028 "The SECR-value %x\n", sec_reg_value);
1029
1030 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1031}
1032
1033int rtl88ee_hw_init(struct ieee80211_hw *hw)
1034{
1035 struct rtl_priv *rtlpriv = rtl_priv(hw);
1036 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1037 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1038 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1039 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1040 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1041 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1042 bool rtstatus;
1043 int err = 0;
1044 u8 tmp_u1b, u1byte;
1045 unsigned long flags;
1046
1047 rtlpriv->rtlhal.being_init_adapter = true;
1048
1049
1050
1051
1052
1053
1054
1055 local_save_flags(flags);
1056 local_irq_enable();
1057 rtlhal->fw_ready = false;
1058
1059 rtlpriv->intf_ops->disable_aspm(hw);
1060
1061 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR+1);
1062 u1byte = rtl_read_byte(rtlpriv, REG_CR);
1063 if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) {
1064 rtlhal->mac_func_enable = true;
1065 } else {
1066 rtlhal->mac_func_enable = false;
1067 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;
1068 }
1069
1070 rtstatus = _rtl88ee_init_mac(hw);
1071 if (rtstatus != true) {
1072 pr_info("Init MAC failed\n");
1073 err = 1;
1074 goto exit;
1075 }
1076
1077 err = rtl88e_download_fw(hw, false);
1078 if (err) {
1079 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1080 "Failed to download FW. Init HW without FW now..\n");
1081 err = 1;
1082 goto exit;
1083 }
1084 rtlhal->fw_ready = true;
1085
1086 rtlhal->last_hmeboxnum = 0;
1087 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;
1088 rtlhal->fw_clk_change_in_progress = false;
1089 rtlhal->allow_sw_to_change_hwclc = false;
1090 ppsc->fw_current_inpsmode = false;
1091
1092 rtl88e_phy_mac_config(hw);
1093
1094
1095
1096
1097
1098 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1099 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1100
1101 rtl88e_phy_bb_config(hw);
1102 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1103 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1104
1105 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1106 rtl88e_phy_rf_config(hw);
1107
1108 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1109 RF_CHNLBW, RFREG_OFFSET_MASK);
1110 rtlphy->rfreg_chnlval[0] = rtlphy->rfreg_chnlval[0] & 0xfff00fff;
1111
1112 _rtl88ee_hw_configure(hw);
1113 rtl_cam_reset_all_entry(hw);
1114 rtl88ee_enable_hw_security_config(hw);
1115
1116 rtlhal->mac_func_enable = true;
1117 ppsc->rfpwr_state = ERFON;
1118
1119 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1120 _rtl88ee_enable_aspm_back_door(hw);
1121 rtlpriv->intf_ops->enable_aspm(hw);
1122
1123 if (ppsc->rfpwr_state == ERFON) {
1124 if ((rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) ||
1125 ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) &&
1126 (rtlhal->oem_id == RT_CID_819X_HP))) {
1127 rtl88e_phy_set_rfpath_switch(hw, true);
1128 rtlpriv->dm.fat_table.rx_idle_ant = MAIN_ANT;
1129 } else {
1130 rtl88e_phy_set_rfpath_switch(hw, false);
1131 rtlpriv->dm.fat_table.rx_idle_ant = AUX_ANT;
1132 }
1133 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rx idle ant %s\n",
1134 (rtlpriv->dm.fat_table.rx_idle_ant == MAIN_ANT) ?
1135 ("MAIN_ANT") : ("AUX_ANT"));
1136
1137 if (rtlphy->iqk_initialized) {
1138 rtl88e_phy_iq_calibrate(hw, true);
1139 } else {
1140 rtl88e_phy_iq_calibrate(hw, false);
1141 rtlphy->iqk_initialized = true;
1142 }
1143
1144 rtl88e_dm_check_txpower_tracking(hw);
1145 rtl88e_phy_lc_calibrate(hw);
1146 }
1147
1148 tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1149 if (!(tmp_u1b & BIT(0))) {
1150 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1151 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n");
1152 }
1153
1154 if (!(tmp_u1b & BIT(4))) {
1155 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1156 tmp_u1b &= 0x0F;
1157 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1158 udelay(10);
1159 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1160 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "under 1.5V\n");
1161 }
1162 rtl_write_byte(rtlpriv, REG_NAV_CTRL+2, ((30000+127)/128));
1163 rtl88e_dm_init(hw);
1164exit:
1165 local_irq_restore(flags);
1166 rtlpriv->rtlhal.being_init_adapter = false;
1167 return err;
1168}
1169
1170static enum version_8188e _rtl88ee_read_chip_version(struct ieee80211_hw *hw)
1171{
1172 struct rtl_priv *rtlpriv = rtl_priv(hw);
1173 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1174 enum version_8188e version = VERSION_UNKNOWN;
1175 u32 value32;
1176
1177 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1178 if (value32 & TRP_VAUX_EN) {
1179 version = (enum version_8188e) VERSION_TEST_CHIP_88E;
1180 } else {
1181 version = NORMAL_CHIP;
1182 version = version | ((value32 & TYPE_ID) ? RF_TYPE_2T2R : 0);
1183 version = version | ((value32 & VENDOR_ID) ?
1184 CHIP_VENDOR_UMC : 0);
1185 }
1186
1187 rtlphy->rf_type = RF_1T1R;
1188 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1189 "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1190 "RF_2T2R" : "RF_1T1R");
1191
1192 return version;
1193}
1194
1195static int _rtl88ee_set_media_status(struct ieee80211_hw *hw,
1196 enum nl80211_iftype type)
1197{
1198 struct rtl_priv *rtlpriv = rtl_priv(hw);
1199 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1200 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1201 u8 mode = MSR_NOLINK;
1202
1203 switch (type) {
1204 case NL80211_IFTYPE_UNSPECIFIED:
1205 mode = MSR_NOLINK;
1206 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1207 "Set Network type to NO LINK!\n");
1208 break;
1209 case NL80211_IFTYPE_ADHOC:
1210 case NL80211_IFTYPE_MESH_POINT:
1211 mode = MSR_ADHOC;
1212 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1213 "Set Network type to Ad Hoc!\n");
1214 break;
1215 case NL80211_IFTYPE_STATION:
1216 mode = MSR_INFRA;
1217 ledaction = LED_CTL_LINK;
1218 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1219 "Set Network type to STA!\n");
1220 break;
1221 case NL80211_IFTYPE_AP:
1222 mode = MSR_AP;
1223 ledaction = LED_CTL_LINK;
1224 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1225 "Set Network type to AP!\n");
1226 break;
1227 default:
1228 pr_err("Network type %d not support!\n", type);
1229 return 1;
1230 break;
1231 }
1232
1233
1234
1235
1236
1237
1238
1239 if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1240 mode = MSR_NOLINK;
1241 ledaction = LED_CTL_NO_LINK;
1242 }
1243
1244 if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1245 _rtl88ee_stop_tx_beacon(hw);
1246 _rtl88ee_enable_bcn_sub_func(hw);
1247 } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1248 _rtl88ee_resume_tx_beacon(hw);
1249 _rtl88ee_disable_bcn_sub_func(hw);
1250 } else {
1251 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1252 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1253 mode);
1254 }
1255
1256 rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1257 rtlpriv->cfg->ops->led_control(hw, ledaction);
1258 if (mode == MSR_AP)
1259 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1260 else
1261 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1262 return 0;
1263}
1264
1265void rtl88ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1266{
1267 struct rtl_priv *rtlpriv = rtl_priv(hw);
1268 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1269 u32 reg_rcr = rtlpci->receive_config;
1270
1271 if (rtlpriv->psc.rfpwr_state != ERFON)
1272 return;
1273
1274 if (check_bssid == true) {
1275 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1276 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1277 (u8 *)(®_rcr));
1278 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
1279 } else if (check_bssid == false) {
1280 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1281 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
1282 rtlpriv->cfg->ops->set_hw_reg(hw,
1283 HW_VAR_RCR, (u8 *)(®_rcr));
1284 }
1285
1286}
1287
1288int rtl88ee_set_network_type(struct ieee80211_hw *hw,
1289 enum nl80211_iftype type)
1290{
1291 struct rtl_priv *rtlpriv = rtl_priv(hw);
1292
1293 if (_rtl88ee_set_media_status(hw, type))
1294 return -EOPNOTSUPP;
1295
1296 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1297 if (type != NL80211_IFTYPE_AP &&
1298 type != NL80211_IFTYPE_MESH_POINT)
1299 rtl88ee_set_check_bssid(hw, true);
1300 } else {
1301 rtl88ee_set_check_bssid(hw, false);
1302 }
1303
1304 return 0;
1305}
1306
1307
1308
1309
1310void rtl88ee_set_qos(struct ieee80211_hw *hw, int aci)
1311{
1312 struct rtl_priv *rtlpriv = rtl_priv(hw);
1313 rtl88e_dm_init_edca_turbo(hw);
1314 switch (aci) {
1315 case AC1_BK:
1316 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1317 break;
1318 case AC0_BE:
1319 break;
1320 case AC2_VI:
1321 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1322 break;
1323 case AC3_VO:
1324 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1325 break;
1326 default:
1327 WARN_ONCE(true, "rtl8188ee: invalid aci: %d !\n", aci);
1328 break;
1329 }
1330}
1331
1332void rtl88ee_enable_interrupt(struct ieee80211_hw *hw)
1333{
1334 struct rtl_priv *rtlpriv = rtl_priv(hw);
1335 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1336
1337 rtl_write_dword(rtlpriv, REG_HIMR,
1338 rtlpci->irq_mask[0] & 0xFFFFFFFF);
1339 rtl_write_dword(rtlpriv, REG_HIMRE,
1340 rtlpci->irq_mask[1] & 0xFFFFFFFF);
1341 rtlpci->irq_enabled = true;
1342
1343
1344
1345
1346
1347 rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0);
1348
1349 rtl_write_dword(rtlpriv, REG_HSIMR,
1350 rtlpci->sys_irq_mask & 0xFFFFFFFF);
1351}
1352
1353void rtl88ee_disable_interrupt(struct ieee80211_hw *hw)
1354{
1355 struct rtl_priv *rtlpriv = rtl_priv(hw);
1356 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1357
1358 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1359 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1360 rtlpci->irq_enabled = false;
1361
1362}
1363
1364static void _rtl88ee_poweroff_adapter(struct ieee80211_hw *hw)
1365{
1366 struct rtl_priv *rtlpriv = rtl_priv(hw);
1367 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1368 u8 u1b_tmp;
1369 u32 count = 0;
1370 rtlhal->mac_func_enable = false;
1371 rtlpriv->intf_ops->enable_aspm(hw);
1372
1373 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n");
1374 u1b_tmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);
1375 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, u1b_tmp & (~BIT(1)));
1376
1377 u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1378 while (!(u1b_tmp & BIT(1)) && (count++ < 100)) {
1379 udelay(10);
1380 u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1381 count++;
1382 }
1383 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0xFF);
1384
1385 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1386 PWR_INTF_PCI_MSK,
1387 RTL8188EE_NIC_LPS_ENTER_FLOW);
1388
1389 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1390
1391 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1392 rtl88e_firmware_selfreset(hw);
1393
1394 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1395 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1396 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1397
1398 u1b_tmp = rtl_read_byte(rtlpriv, REG_32K_CTRL);
1399 rtl_write_byte(rtlpriv, REG_32K_CTRL, (u1b_tmp & (~BIT(0))));
1400
1401 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1402 PWR_INTF_PCI_MSK, RTL8188EE_NIC_DISABLE_FLOW);
1403
1404 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1405 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(3))));
1406 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1407 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp | BIT(3)));
1408
1409 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1410
1411 u1b_tmp = rtl_read_byte(rtlpriv, GPIO_IN);
1412 rtl_write_byte(rtlpriv, GPIO_OUT, u1b_tmp);
1413 rtl_write_byte(rtlpriv, GPIO_IO_SEL, 0x7F);
1414
1415 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
1416 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL, (u1b_tmp << 4) | u1b_tmp);
1417 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL+1);
1418 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL+1, u1b_tmp | 0x0F);
1419
1420 rtl_write_dword(rtlpriv, REG_GPIO_IO_SEL_2+2, 0x00080808);
1421}
1422
1423void rtl88ee_card_disable(struct ieee80211_hw *hw)
1424{
1425 struct rtl_priv *rtlpriv = rtl_priv(hw);
1426 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1427 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1428 enum nl80211_iftype opmode;
1429
1430 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8188ee card disable\n");
1431
1432 mac->link_state = MAC80211_NOLINK;
1433 opmode = NL80211_IFTYPE_UNSPECIFIED;
1434
1435 _rtl88ee_set_media_status(hw, opmode);
1436
1437 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1438 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1439 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1440
1441 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1442 _rtl88ee_poweroff_adapter(hw);
1443
1444
1445 rtlpriv->phy.iqk_initialized = false;
1446}
1447
1448void rtl88ee_interrupt_recognized(struct ieee80211_hw *hw,
1449 struct rtl_int *intvec)
1450{
1451 struct rtl_priv *rtlpriv = rtl_priv(hw);
1452 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1453
1454 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1455 rtl_write_dword(rtlpriv, ISR, intvec->inta);
1456
1457 intvec->intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1458 rtl_write_dword(rtlpriv, REG_HISRE, intvec->intb);
1459
1460}
1461
1462void rtl88ee_set_beacon_related_registers(struct ieee80211_hw *hw)
1463{
1464 struct rtl_priv *rtlpriv = rtl_priv(hw);
1465 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1466 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1467 u16 bcn_interval, atim_window;
1468
1469 bcn_interval = mac->beacon_interval;
1470 atim_window = 2;
1471 rtl88ee_disable_interrupt(hw);
1472 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1473 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1474 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1475 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1476 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1477 rtl_write_byte(rtlpriv, 0x606, 0x30);
1478 rtlpci->reg_bcn_ctrl_val |= BIT(3);
1479 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
1480
1481}
1482
1483void rtl88ee_set_beacon_interval(struct ieee80211_hw *hw)
1484{
1485 struct rtl_priv *rtlpriv = rtl_priv(hw);
1486 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1487 u16 bcn_interval = mac->beacon_interval;
1488
1489 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1490 "beacon_interval:%d\n", bcn_interval);
1491
1492 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1493
1494}
1495
1496void rtl88ee_update_interrupt_mask(struct ieee80211_hw *hw,
1497 u32 add_msr, u32 rm_msr)
1498{
1499 struct rtl_priv *rtlpriv = rtl_priv(hw);
1500 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1501
1502 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1503 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1504
1505 if (add_msr)
1506 rtlpci->irq_mask[0] |= add_msr;
1507 if (rm_msr)
1508 rtlpci->irq_mask[0] &= (~rm_msr);
1509 rtl88ee_disable_interrupt(hw);
1510 rtl88ee_enable_interrupt(hw);
1511}
1512
1513static u8 _rtl88e_get_chnl_group(u8 chnl)
1514{
1515 u8 group = 0;
1516
1517 if (chnl < 3)
1518 group = 0;
1519 else if (chnl < 6)
1520 group = 1;
1521 else if (chnl < 9)
1522 group = 2;
1523 else if (chnl < 12)
1524 group = 3;
1525 else if (chnl < 14)
1526 group = 4;
1527 else if (chnl == 14)
1528 group = 5;
1529
1530 return group;
1531}
1532
1533static void set_24g_base(struct txpower_info_2g *pwrinfo24g, u32 rfpath)
1534{
1535 int group, txcnt;
1536
1537 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1538 pwrinfo24g->index_cck_base[rfpath][group] = 0x2D;
1539 pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D;
1540 }
1541 for (txcnt = 0; txcnt < MAX_TX_COUNT; txcnt++) {
1542 if (txcnt == 0) {
1543 pwrinfo24g->bw20_diff[rfpath][0] = 0x02;
1544 pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;
1545 } else {
1546 pwrinfo24g->bw20_diff[rfpath][txcnt] = 0xFE;
1547 pwrinfo24g->bw40_diff[rfpath][txcnt] = 0xFE;
1548 pwrinfo24g->cck_diff[rfpath][txcnt] = 0xFE;
1549 pwrinfo24g->ofdm_diff[rfpath][txcnt] = 0xFE;
1550 }
1551 }
1552}
1553
1554static void read_power_value_fromprom(struct ieee80211_hw *hw,
1555 struct txpower_info_2g *pwrinfo24g,
1556 struct txpower_info_5g *pwrinfo5g,
1557 bool autoload_fail, u8 *hwinfo)
1558{
1559 struct rtl_priv *rtlpriv = rtl_priv(hw);
1560 u32 rfpath, eeaddr = EEPROM_TX_PWR_INX, group, txcnt = 0;
1561
1562 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1563 "hal_ReadPowerValueFromPROM88E():PROMContent[0x%x]=0x%x\n",
1564 (eeaddr+1), hwinfo[eeaddr+1]);
1565 if (0xFF == hwinfo[eeaddr+1])
1566 autoload_fail = true;
1567
1568 if (autoload_fail) {
1569 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1570 "auto load fail : Use Default value!\n");
1571 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
1572
1573 set_24g_base(pwrinfo24g, rfpath);
1574 }
1575 return;
1576 }
1577
1578 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
1579
1580 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1581 pwrinfo24g->index_cck_base[rfpath][group] =
1582 hwinfo[eeaddr++];
1583 if (pwrinfo24g->index_cck_base[rfpath][group] == 0xFF)
1584 pwrinfo24g->index_cck_base[rfpath][group] =
1585 0x2D;
1586 }
1587 for (group = 0 ; group < MAX_CHNL_GROUP_24G-1; group++) {
1588 pwrinfo24g->index_bw40_base[rfpath][group] =
1589 hwinfo[eeaddr++];
1590 if (pwrinfo24g->index_bw40_base[rfpath][group] == 0xFF)
1591 pwrinfo24g->index_bw40_base[rfpath][group] =
1592 0x2D;
1593 }
1594 pwrinfo24g->bw40_diff[rfpath][0] = 0;
1595 if (hwinfo[eeaddr] == 0xFF) {
1596 pwrinfo24g->bw20_diff[rfpath][0] = 0x02;
1597 } else {
1598 pwrinfo24g->bw20_diff[rfpath][0] =
1599 (hwinfo[eeaddr]&0xf0)>>4;
1600
1601 if (pwrinfo24g->bw20_diff[rfpath][0] & BIT(3))
1602 pwrinfo24g->bw20_diff[rfpath][0] |= 0xF0;
1603 }
1604
1605 if (hwinfo[eeaddr] == 0xFF) {
1606 pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;
1607 } else {
1608 pwrinfo24g->ofdm_diff[rfpath][0] =
1609 (hwinfo[eeaddr]&0x0f);
1610
1611 if (pwrinfo24g->ofdm_diff[rfpath][0] & BIT(3))
1612 pwrinfo24g->ofdm_diff[rfpath][0] |= 0xF0;
1613 }
1614 pwrinfo24g->cck_diff[rfpath][0] = 0;
1615 eeaddr++;
1616 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1617 if (hwinfo[eeaddr] == 0xFF) {
1618 pwrinfo24g->bw40_diff[rfpath][txcnt] = 0xFE;
1619 } else {
1620 pwrinfo24g->bw40_diff[rfpath][txcnt] =
1621 (hwinfo[eeaddr]&0xf0)>>4;
1622 if (pwrinfo24g->bw40_diff[rfpath][txcnt] &
1623 BIT(3))
1624 pwrinfo24g->bw40_diff[rfpath][txcnt] |=
1625 0xF0;
1626 }
1627
1628 if (hwinfo[eeaddr] == 0xFF) {
1629 pwrinfo24g->bw20_diff[rfpath][txcnt] =
1630 0xFE;
1631 } else {
1632 pwrinfo24g->bw20_diff[rfpath][txcnt] =
1633 (hwinfo[eeaddr]&0x0f);
1634 if (pwrinfo24g->bw20_diff[rfpath][txcnt] &
1635 BIT(3))
1636 pwrinfo24g->bw20_diff[rfpath][txcnt] |=
1637 0xF0;
1638 }
1639 eeaddr++;
1640
1641 if (hwinfo[eeaddr] == 0xFF) {
1642 pwrinfo24g->ofdm_diff[rfpath][txcnt] = 0xFE;
1643 } else {
1644 pwrinfo24g->ofdm_diff[rfpath][txcnt] =
1645 (hwinfo[eeaddr]&0xf0)>>4;
1646 if (pwrinfo24g->ofdm_diff[rfpath][txcnt] &
1647 BIT(3))
1648 pwrinfo24g->ofdm_diff[rfpath][txcnt] |=
1649 0xF0;
1650 }
1651
1652 if (hwinfo[eeaddr] == 0xFF) {
1653 pwrinfo24g->cck_diff[rfpath][txcnt] = 0xFE;
1654 } else {
1655 pwrinfo24g->cck_diff[rfpath][txcnt] =
1656 (hwinfo[eeaddr]&0x0f);
1657 if (pwrinfo24g->cck_diff[rfpath][txcnt] &
1658 BIT(3))
1659 pwrinfo24g->cck_diff[rfpath][txcnt] |=
1660 0xF0;
1661 }
1662 eeaddr++;
1663 }
1664
1665
1666 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
1667 pwrinfo5g->index_bw40_base[rfpath][group] =
1668 hwinfo[eeaddr++];
1669 if (pwrinfo5g->index_bw40_base[rfpath][group] == 0xFF)
1670 pwrinfo5g->index_bw40_base[rfpath][group] =
1671 0xFE;
1672 }
1673
1674 pwrinfo5g->bw40_diff[rfpath][0] = 0;
1675
1676 if (hwinfo[eeaddr] == 0xFF) {
1677 pwrinfo5g->bw20_diff[rfpath][0] = 0;
1678 } else {
1679 pwrinfo5g->bw20_diff[rfpath][0] =
1680 (hwinfo[eeaddr]&0xf0)>>4;
1681 if (pwrinfo5g->bw20_diff[rfpath][0] & BIT(3))
1682 pwrinfo5g->bw20_diff[rfpath][0] |= 0xF0;
1683 }
1684
1685 if (hwinfo[eeaddr] == 0xFF) {
1686 pwrinfo5g->ofdm_diff[rfpath][0] = 0x04;
1687 } else {
1688 pwrinfo5g->ofdm_diff[rfpath][0] = (hwinfo[eeaddr]&0x0f);
1689 if (pwrinfo5g->ofdm_diff[rfpath][0] & BIT(3))
1690 pwrinfo5g->ofdm_diff[rfpath][0] |= 0xF0;
1691 }
1692 eeaddr++;
1693 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1694 if (hwinfo[eeaddr] == 0xFF) {
1695 pwrinfo5g->bw40_diff[rfpath][txcnt] = 0xFE;
1696 } else {
1697 pwrinfo5g->bw40_diff[rfpath][txcnt] =
1698 (hwinfo[eeaddr]&0xf0)>>4;
1699 if (pwrinfo5g->bw40_diff[rfpath][txcnt] &
1700 BIT(3))
1701 pwrinfo5g->bw40_diff[rfpath][txcnt] |=
1702 0xF0;
1703 }
1704
1705 if (hwinfo[eeaddr] == 0xFF) {
1706 pwrinfo5g->bw20_diff[rfpath][txcnt] = 0xFE;
1707 } else {
1708 pwrinfo5g->bw20_diff[rfpath][txcnt] =
1709 (hwinfo[eeaddr]&0x0f);
1710 if (pwrinfo5g->bw20_diff[rfpath][txcnt] &
1711 BIT(3))
1712 pwrinfo5g->bw20_diff[rfpath][txcnt] |=
1713 0xF0;
1714 }
1715 eeaddr++;
1716 }
1717
1718 if (hwinfo[eeaddr] == 0xFF) {
1719 pwrinfo5g->ofdm_diff[rfpath][1] = 0xFE;
1720 pwrinfo5g->ofdm_diff[rfpath][2] = 0xFE;
1721 } else {
1722 pwrinfo5g->ofdm_diff[rfpath][1] =
1723 (hwinfo[eeaddr]&0xf0)>>4;
1724 pwrinfo5g->ofdm_diff[rfpath][2] =
1725 (hwinfo[eeaddr]&0x0f);
1726 }
1727 eeaddr++;
1728
1729 if (hwinfo[eeaddr] == 0xFF)
1730 pwrinfo5g->ofdm_diff[rfpath][3] = 0xFE;
1731 else
1732 pwrinfo5g->ofdm_diff[rfpath][3] = (hwinfo[eeaddr]&0x0f);
1733 eeaddr++;
1734
1735 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1736 if (pwrinfo5g->ofdm_diff[rfpath][txcnt] == 0xFF)
1737 pwrinfo5g->ofdm_diff[rfpath][txcnt] = 0xFE;
1738 else if (pwrinfo5g->ofdm_diff[rfpath][txcnt] & BIT(3))
1739 pwrinfo5g->ofdm_diff[rfpath][txcnt] |= 0xF0;
1740 }
1741 }
1742}
1743
1744static void _rtl88ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1745 bool autoload_fail,
1746 u8 *hwinfo)
1747{
1748 struct rtl_priv *rtlpriv = rtl_priv(hw);
1749 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1750 struct txpower_info_2g pwrinfo24g;
1751 struct txpower_info_5g pwrinfo5g;
1752 u8 rf_path, index;
1753 u8 i;
1754
1755 read_power_value_fromprom(hw, &pwrinfo24g,
1756 &pwrinfo5g, autoload_fail, hwinfo);
1757
1758 for (rf_path = 0; rf_path < 2; rf_path++) {
1759 for (i = 0; i < 14; i++) {
1760 index = _rtl88e_get_chnl_group(i+1);
1761
1762 rtlefuse->txpwrlevel_cck[rf_path][i] =
1763 pwrinfo24g.index_cck_base[rf_path][index];
1764 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1765 pwrinfo24g.index_bw40_base[rf_path][index];
1766 rtlefuse->txpwr_ht20diff[rf_path][i] =
1767 pwrinfo24g.bw20_diff[rf_path][0];
1768 rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
1769 pwrinfo24g.ofdm_diff[rf_path][0];
1770 }
1771
1772 for (i = 0; i < 14; i++) {
1773 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1774 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = [0x%x / 0x%x ]\n",
1775 rf_path, i,
1776 rtlefuse->txpwrlevel_cck[rf_path][i],
1777 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]);
1778 }
1779 }
1780
1781 if (!autoload_fail)
1782 rtlefuse->eeprom_thermalmeter =
1783 hwinfo[EEPROM_THERMAL_METER_88E];
1784 else
1785 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1786
1787 if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) {
1788 rtlefuse->apk_thermalmeterignore = true;
1789 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1790 }
1791
1792 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1793 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1794 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1795
1796 if (!autoload_fail) {
1797 rtlefuse->eeprom_regulatory =
1798 hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x07;
1799 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
1800 rtlefuse->eeprom_regulatory = 0;
1801 } else {
1802 rtlefuse->eeprom_regulatory = 0;
1803 }
1804 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1805 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1806}
1807
1808static void _rtl88ee_read_adapter_info(struct ieee80211_hw *hw)
1809{
1810 struct rtl_priv *rtlpriv = rtl_priv(hw);
1811 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1812 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1813 int params[] = {RTL8188E_EEPROM_ID, EEPROM_VID, EEPROM_DID,
1814 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
1815 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
1816 COUNTRY_CODE_WORLD_WIDE_13};
1817 u8 *hwinfo;
1818
1819 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
1820 if (!hwinfo)
1821 return;
1822
1823 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
1824 goto exit;
1825
1826 if (rtlefuse->eeprom_oemid == 0xFF)
1827 rtlefuse->eeprom_oemid = 0;
1828
1829 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1830 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
1831
1832 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
1833
1834 _rtl88ee_read_txpower_info_from_hwpg(hw,
1835 rtlefuse->autoload_failflag,
1836 hwinfo);
1837 rtlefuse->txpwr_fromeprom = true;
1838
1839 rtl8188ee_read_bt_coexist_info_from_hwpg(hw,
1840 rtlefuse->autoload_failflag,
1841 hwinfo);
1842
1843
1844 rtlefuse->board_type =
1845 ((hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0xE0) >> 5);
1846 rtlhal->board_type = rtlefuse->board_type;
1847
1848 rtlefuse->wowlan_enable =
1849 ((hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & 0x40) >> 6);
1850
1851 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_88E];
1852 if (hwinfo[EEPROM_XTAL_88E])
1853 rtlefuse->crystalcap = 0x20;
1854
1855 rtlefuse->antenna_div_cfg =
1856 (hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x18) >> 3;
1857 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
1858 rtlefuse->antenna_div_cfg = 0;
1859 if (rtlpriv->btcoexist.eeprom_bt_coexist != 0 &&
1860 rtlpriv->btcoexist.eeprom_bt_ant_num == ANT_X1)
1861 rtlefuse->antenna_div_cfg = 0;
1862
1863 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
1864 if (rtlefuse->antenna_div_type == 0xFF)
1865 rtlefuse->antenna_div_type = 0x01;
1866 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV ||
1867 rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1868 rtlefuse->antenna_div_cfg = 1;
1869
1870 if (rtlhal->oem_id == RT_CID_DEFAULT) {
1871 switch (rtlefuse->eeprom_oemid) {
1872 case EEPROM_CID_DEFAULT:
1873 if (rtlefuse->eeprom_did == 0x8179) {
1874 if (rtlefuse->eeprom_svid == 0x1025) {
1875 rtlhal->oem_id = RT_CID_819X_ACER;
1876 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
1877 rtlefuse->eeprom_smid == 0x0179) ||
1878 (rtlefuse->eeprom_svid == 0x17AA &&
1879 rtlefuse->eeprom_smid == 0x0179)) {
1880 rtlhal->oem_id = RT_CID_819X_LENOVO;
1881 } else if (rtlefuse->eeprom_svid == 0x103c &&
1882 rtlefuse->eeprom_smid == 0x197d) {
1883 rtlhal->oem_id = RT_CID_819X_HP;
1884 } else {
1885 rtlhal->oem_id = RT_CID_DEFAULT;
1886 }
1887 } else {
1888 rtlhal->oem_id = RT_CID_DEFAULT;
1889 }
1890 break;
1891 case EEPROM_CID_TOSHIBA:
1892 rtlhal->oem_id = RT_CID_TOSHIBA;
1893 break;
1894 case EEPROM_CID_QMI:
1895 rtlhal->oem_id = RT_CID_819X_QMI;
1896 break;
1897 case EEPROM_CID_WHQL:
1898 default:
1899 rtlhal->oem_id = RT_CID_DEFAULT;
1900 break;
1901
1902 }
1903 }
1904exit:
1905 kfree(hwinfo);
1906}
1907
1908static void _rtl88ee_hal_customized_behavior(struct ieee80211_hw *hw)
1909{
1910 struct rtl_priv *rtlpriv = rtl_priv(hw);
1911 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1912
1913 rtlpriv->ledctl.led_opendrain = true;
1914
1915 switch (rtlhal->oem_id) {
1916 case RT_CID_819X_HP:
1917 rtlpriv->ledctl.led_opendrain = true;
1918 break;
1919 case RT_CID_819X_LENOVO:
1920 case RT_CID_DEFAULT:
1921 case RT_CID_TOSHIBA:
1922 case RT_CID_CCX:
1923 case RT_CID_819X_ACER:
1924 case RT_CID_WHQL:
1925 default:
1926 break;
1927 }
1928 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1929 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1930}
1931
1932void rtl88ee_read_eeprom_info(struct ieee80211_hw *hw)
1933{
1934 struct rtl_priv *rtlpriv = rtl_priv(hw);
1935 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1936 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1937 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1938 u8 tmp_u1b;
1939
1940 rtlhal->version = _rtl88ee_read_chip_version(hw);
1941 if (get_rf_type(rtlphy) == RF_1T1R)
1942 rtlpriv->dm.rfpath_rxenable[0] = true;
1943 else
1944 rtlpriv->dm.rfpath_rxenable[0] =
1945 rtlpriv->dm.rfpath_rxenable[1] = true;
1946 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1947 rtlhal->version);
1948 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1949 if (tmp_u1b & BIT(4)) {
1950 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1951 rtlefuse->epromtype = EEPROM_93C46;
1952 } else {
1953 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1954 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1955 }
1956 if (tmp_u1b & BIT(5)) {
1957 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1958 rtlefuse->autoload_failflag = false;
1959 _rtl88ee_read_adapter_info(hw);
1960 } else {
1961 pr_err("Autoload ERR!!\n");
1962 }
1963 _rtl88ee_hal_customized_behavior(hw);
1964}
1965
1966static void rtl88ee_update_hal_rate_table(struct ieee80211_hw *hw,
1967 struct ieee80211_sta *sta)
1968{
1969 struct rtl_priv *rtlpriv = rtl_priv(hw);
1970 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1971 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1972 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1973 u32 ratr_value;
1974 u8 ratr_index = 0;
1975 u8 b_nmode = mac->ht_enable;
1976
1977 u16 shortgi_rate;
1978 u32 tmp_ratr_value;
1979 u8 curtxbw_40mhz = mac->bw_40;
1980 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1981 1 : 0;
1982 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1983 1 : 0;
1984 enum wireless_mode wirelessmode = mac->mode;
1985 u32 ratr_mask;
1986
1987 if (rtlhal->current_bandtype == BAND_ON_5G)
1988 ratr_value = sta->supp_rates[1] << 4;
1989 else
1990 ratr_value = sta->supp_rates[0];
1991 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1992 ratr_value = 0xfff;
1993 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1994 sta->ht_cap.mcs.rx_mask[0] << 12);
1995 switch (wirelessmode) {
1996 case WIRELESS_MODE_B:
1997 if (ratr_value & 0x0000000c)
1998 ratr_value &= 0x0000000d;
1999 else
2000 ratr_value &= 0x0000000f;
2001 break;
2002 case WIRELESS_MODE_G:
2003 ratr_value &= 0x00000FF5;
2004 break;
2005 case WIRELESS_MODE_N_24G:
2006 case WIRELESS_MODE_N_5G:
2007 b_nmode = 1;
2008 if (get_rf_type(rtlphy) == RF_1T2R ||
2009 get_rf_type(rtlphy) == RF_1T1R)
2010 ratr_mask = 0x000ff005;
2011 else
2012 ratr_mask = 0x0f0ff005;
2013
2014 ratr_value &= ratr_mask;
2015 break;
2016 default:
2017 if (rtlphy->rf_type == RF_1T2R)
2018 ratr_value &= 0x000ff0ff;
2019 else
2020 ratr_value &= 0x0f0ff0ff;
2021
2022 break;
2023 }
2024
2025 if ((rtlpriv->btcoexist.bt_coexistence) &&
2026 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
2027 (rtlpriv->btcoexist.bt_cur_state) &&
2028 (rtlpriv->btcoexist.bt_ant_isolation) &&
2029 ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
2030 (rtlpriv->btcoexist.bt_service == BT_BUSY)))
2031 ratr_value &= 0x0fffcfc0;
2032 else
2033 ratr_value &= 0x0FFFFFFF;
2034
2035 if (b_nmode &&
2036 ((curtxbw_40mhz && curshortgi_40mhz) ||
2037 (!curtxbw_40mhz && curshortgi_20mhz))) {
2038 ratr_value |= 0x10000000;
2039 tmp_ratr_value = (ratr_value >> 12);
2040
2041 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2042 if ((1 << shortgi_rate) & tmp_ratr_value)
2043 break;
2044 }
2045
2046 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2047 (shortgi_rate << 4) | (shortgi_rate);
2048 }
2049
2050 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2051
2052 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2053 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
2054}
2055
2056static void rtl88ee_update_hal_rate_mask(struct ieee80211_hw *hw,
2057 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
2058{
2059 struct rtl_priv *rtlpriv = rtl_priv(hw);
2060 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2061 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2062 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2063 struct rtl_sta_info *sta_entry = NULL;
2064 u32 ratr_bitmap;
2065 u8 ratr_index;
2066 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2067 ? 1 : 0;
2068 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2069 1 : 0;
2070 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2071 1 : 0;
2072 enum wireless_mode wirelessmode = 0;
2073 bool b_shortgi = false;
2074 u8 rate_mask[5];
2075 u8 macid = 0;
2076
2077
2078 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2079 wirelessmode = sta_entry->wireless_mode;
2080 if (mac->opmode == NL80211_IFTYPE_STATION ||
2081 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2082 curtxbw_40mhz = mac->bw_40;
2083 else if (mac->opmode == NL80211_IFTYPE_AP ||
2084 mac->opmode == NL80211_IFTYPE_ADHOC)
2085 macid = sta->aid + 1;
2086
2087 if (rtlhal->current_bandtype == BAND_ON_5G)
2088 ratr_bitmap = sta->supp_rates[1] << 4;
2089 else
2090 ratr_bitmap = sta->supp_rates[0];
2091 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2092 ratr_bitmap = 0xfff;
2093 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2094 sta->ht_cap.mcs.rx_mask[0] << 12);
2095 switch (wirelessmode) {
2096 case WIRELESS_MODE_B:
2097 ratr_index = RATR_INX_WIRELESS_B;
2098 if (ratr_bitmap & 0x0000000c)
2099 ratr_bitmap &= 0x0000000d;
2100 else
2101 ratr_bitmap &= 0x0000000f;
2102 break;
2103 case WIRELESS_MODE_G:
2104 ratr_index = RATR_INX_WIRELESS_GB;
2105
2106 if (rssi_level == 1)
2107 ratr_bitmap &= 0x00000f00;
2108 else if (rssi_level == 2)
2109 ratr_bitmap &= 0x00000ff0;
2110 else
2111 ratr_bitmap &= 0x00000ff5;
2112 break;
2113 case WIRELESS_MODE_N_24G:
2114 case WIRELESS_MODE_N_5G:
2115 ratr_index = RATR_INX_WIRELESS_NGB;
2116 if (rtlphy->rf_type == RF_1T2R ||
2117 rtlphy->rf_type == RF_1T1R) {
2118 if (curtxbw_40mhz) {
2119 if (rssi_level == 1)
2120 ratr_bitmap &= 0x000f0000;
2121 else if (rssi_level == 2)
2122 ratr_bitmap &= 0x000ff000;
2123 else
2124 ratr_bitmap &= 0x000ff015;
2125 } else {
2126 if (rssi_level == 1)
2127 ratr_bitmap &= 0x000f0000;
2128 else if (rssi_level == 2)
2129 ratr_bitmap &= 0x000ff000;
2130 else
2131 ratr_bitmap &= 0x000ff005;
2132 }
2133 } else {
2134 if (curtxbw_40mhz) {
2135 if (rssi_level == 1)
2136 ratr_bitmap &= 0x0f8f0000;
2137 else if (rssi_level == 2)
2138 ratr_bitmap &= 0x0f8ff000;
2139 else
2140 ratr_bitmap &= 0x0f8ff015;
2141 } else {
2142 if (rssi_level == 1)
2143 ratr_bitmap &= 0x0f8f0000;
2144 else if (rssi_level == 2)
2145 ratr_bitmap &= 0x0f8ff000;
2146 else
2147 ratr_bitmap &= 0x0f8ff005;
2148 }
2149 }
2150
2151
2152 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2153 (!curtxbw_40mhz && curshortgi_20mhz)) {
2154
2155 if (macid == 0)
2156 b_shortgi = true;
2157 else if (macid == 1)
2158 b_shortgi = false;
2159 }
2160 break;
2161 default:
2162 ratr_index = RATR_INX_WIRELESS_NGB;
2163
2164 if (rtlphy->rf_type == RF_1T2R)
2165 ratr_bitmap &= 0x000ff0ff;
2166 else
2167 ratr_bitmap &= 0x0f0ff0ff;
2168 break;
2169 }
2170 sta_entry->ratr_index = ratr_index;
2171
2172 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2173 "ratr_bitmap :%x\n", ratr_bitmap);
2174 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2175 (ratr_index << 28);
2176 rate_mask[4] = macid | (b_shortgi ? 0x20 : 0x00) | 0x80;
2177 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2178 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
2179 ratr_index, ratr_bitmap,
2180 rate_mask[0], rate_mask[1],
2181 rate_mask[2], rate_mask[3],
2182 rate_mask[4]);
2183 rtl88e_fill_h2c_cmd(hw, H2C_88E_RA_MASK, 5, rate_mask);
2184 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
2185}
2186
2187void rtl88ee_update_hal_rate_tbl(struct ieee80211_hw *hw,
2188 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
2189{
2190 struct rtl_priv *rtlpriv = rtl_priv(hw);
2191
2192 if (rtlpriv->dm.useramask)
2193 rtl88ee_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
2194 else
2195 rtl88ee_update_hal_rate_table(hw, sta);
2196}
2197
2198void rtl88ee_update_channel_access_setting(struct ieee80211_hw *hw)
2199{
2200 struct rtl_priv *rtlpriv = rtl_priv(hw);
2201 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2202 u16 sifs_timer;
2203
2204 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time);
2205 if (!mac->ht_enable)
2206 sifs_timer = 0x0a0a;
2207 else
2208 sifs_timer = 0x0e0e;
2209 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2210}
2211
2212bool rtl88ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2213{
2214 struct rtl_priv *rtlpriv = rtl_priv(hw);
2215 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2216 enum rf_pwrstate e_rfpowerstate_toset;
2217 u32 u4tmp;
2218 bool b_actuallyset = false;
2219
2220 if (rtlpriv->rtlhal.being_init_adapter)
2221 return false;
2222
2223 if (ppsc->swrf_processing)
2224 return false;
2225
2226 spin_lock(&rtlpriv->locks.rf_ps_lock);
2227 if (ppsc->rfchange_inprogress) {
2228 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2229 return false;
2230 } else {
2231 ppsc->rfchange_inprogress = true;
2232 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2233 }
2234
2235 u4tmp = rtl_read_dword(rtlpriv, REG_GPIO_OUTPUT);
2236 e_rfpowerstate_toset = (u4tmp & BIT(31)) ? ERFON : ERFOFF;
2237
2238 if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2239 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2240 "GPIOChangeRF - HW Radio ON, RF ON\n");
2241
2242 e_rfpowerstate_toset = ERFON;
2243 ppsc->hwradiooff = false;
2244 b_actuallyset = true;
2245 } else if ((!ppsc->hwradiooff) &&
2246 (e_rfpowerstate_toset == ERFOFF)) {
2247 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2248 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2249
2250 e_rfpowerstate_toset = ERFOFF;
2251 ppsc->hwradiooff = true;
2252 b_actuallyset = true;
2253 }
2254
2255 if (b_actuallyset) {
2256 spin_lock(&rtlpriv->locks.rf_ps_lock);
2257 ppsc->rfchange_inprogress = false;
2258 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2259 } else {
2260 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2261 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2262
2263 spin_lock(&rtlpriv->locks.rf_ps_lock);
2264 ppsc->rfchange_inprogress = false;
2265 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2266 }
2267
2268 *valid = 1;
2269 return !ppsc->hwradiooff;
2270
2271}
2272
2273void rtl88ee_set_key(struct ieee80211_hw *hw, u32 key_index,
2274 u8 *p_macaddr, bool is_group, u8 enc_algo,
2275 bool is_wepkey, bool clear_all)
2276{
2277 struct rtl_priv *rtlpriv = rtl_priv(hw);
2278 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2279 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2280 u8 *macaddr = p_macaddr;
2281 u32 entry_id = 0;
2282 bool is_pairwise = false;
2283 static u8 cam_const_addr[4][6] = {
2284 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2285 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2286 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2287 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2288 };
2289 static u8 cam_const_broad[] = {
2290 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2291 };
2292
2293 if (clear_all) {
2294 u8 idx = 0;
2295 u8 cam_offset = 0;
2296 u8 clear_number = 5;
2297
2298 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2299
2300 for (idx = 0; idx < clear_number; idx++) {
2301 rtl_cam_mark_invalid(hw, cam_offset + idx);
2302 rtl_cam_empty_entry(hw, cam_offset + idx);
2303
2304 if (idx < 5) {
2305 memset(rtlpriv->sec.key_buf[idx], 0,
2306 MAX_KEY_LEN);
2307 rtlpriv->sec.key_len[idx] = 0;
2308 }
2309 }
2310
2311 } else {
2312 switch (enc_algo) {
2313 case WEP40_ENCRYPTION:
2314 enc_algo = CAM_WEP40;
2315 break;
2316 case WEP104_ENCRYPTION:
2317 enc_algo = CAM_WEP104;
2318 break;
2319 case TKIP_ENCRYPTION:
2320 enc_algo = CAM_TKIP;
2321 break;
2322 case AESCCMP_ENCRYPTION:
2323 enc_algo = CAM_AES;
2324 break;
2325 default:
2326 pr_err("switch case %#x not processed\n",
2327 enc_algo);
2328 enc_algo = CAM_TKIP;
2329 break;
2330 }
2331
2332 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2333 macaddr = cam_const_addr[key_index];
2334 entry_id = key_index;
2335 } else {
2336 if (is_group) {
2337 macaddr = cam_const_broad;
2338 entry_id = key_index;
2339 } else {
2340 if (mac->opmode == NL80211_IFTYPE_AP ||
2341 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2342 entry_id =
2343 rtl_cam_get_free_entry(hw, p_macaddr);
2344 if (entry_id >= TOTAL_CAM_ENTRY) {
2345 pr_err("Can not find free hw security cam entry\n");
2346 return;
2347 }
2348 } else {
2349 entry_id = CAM_PAIRWISE_KEY_POSITION;
2350 }
2351 key_index = PAIRWISE_KEYIDX;
2352 is_pairwise = true;
2353 }
2354 }
2355
2356 if (rtlpriv->sec.key_len[key_index] == 0) {
2357 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2358 "delete one entry, entry_id is %d\n",
2359 entry_id);
2360 if (mac->opmode == NL80211_IFTYPE_AP ||
2361 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2362 rtl_cam_del_entry(hw, p_macaddr);
2363 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2364 } else {
2365 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2366 "add one entry\n");
2367 if (is_pairwise) {
2368 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2369 "set Pairwise key\n");
2370
2371 rtl_cam_add_one_entry(hw, macaddr, key_index,
2372 entry_id, enc_algo,
2373 CAM_CONFIG_NO_USEDK,
2374 rtlpriv->sec.key_buf[key_index]);
2375 } else {
2376 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2377 "set group key\n");
2378
2379 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2380 rtl_cam_add_one_entry(hw,
2381 rtlefuse->dev_addr,
2382 PAIRWISE_KEYIDX,
2383 CAM_PAIRWISE_KEY_POSITION,
2384 enc_algo,
2385 CAM_CONFIG_NO_USEDK,
2386 rtlpriv->sec.key_buf
2387 [entry_id]);
2388 }
2389
2390 rtl_cam_add_one_entry(hw, macaddr, key_index,
2391 entry_id, enc_algo,
2392 CAM_CONFIG_NO_USEDK,
2393 rtlpriv->sec.key_buf[entry_id]);
2394 }
2395
2396 }
2397 }
2398}
2399
2400static void rtl8188ee_bt_var_init(struct ieee80211_hw *hw)
2401{
2402 struct rtl_priv *rtlpriv = rtl_priv(hw);
2403
2404 rtlpriv->btcoexist.bt_coexistence =
2405 rtlpriv->btcoexist.eeprom_bt_coexist;
2406 rtlpriv->btcoexist.bt_ant_num = rtlpriv->btcoexist.eeprom_bt_ant_num;
2407 rtlpriv->btcoexist.bt_coexist_type = rtlpriv->btcoexist.eeprom_bt_type;
2408
2409 if (rtlpriv->btcoexist.reg_bt_iso == 2)
2410 rtlpriv->btcoexist.bt_ant_isolation =
2411 rtlpriv->btcoexist.eeprom_bt_ant_isol;
2412 else
2413 rtlpriv->btcoexist.bt_ant_isolation =
2414 rtlpriv->btcoexist.reg_bt_iso;
2415
2416 rtlpriv->btcoexist.bt_radio_shared_type =
2417 rtlpriv->btcoexist.eeprom_bt_radio_shared;
2418
2419 if (rtlpriv->btcoexist.bt_coexistence) {
2420 if (rtlpriv->btcoexist.reg_bt_sco == 1)
2421 rtlpriv->btcoexist.bt_service = BT_OTHER_ACTION;
2422 else if (rtlpriv->btcoexist.reg_bt_sco == 2)
2423 rtlpriv->btcoexist.bt_service = BT_SCO;
2424 else if (rtlpriv->btcoexist.reg_bt_sco == 4)
2425 rtlpriv->btcoexist.bt_service = BT_BUSY;
2426 else if (rtlpriv->btcoexist.reg_bt_sco == 5)
2427 rtlpriv->btcoexist.bt_service = BT_OTHERBUSY;
2428 else
2429 rtlpriv->btcoexist.bt_service = BT_IDLE;
2430
2431 rtlpriv->btcoexist.bt_edca_ul = 0;
2432 rtlpriv->btcoexist.bt_edca_dl = 0;
2433 rtlpriv->btcoexist.bt_rssi_state = 0xff;
2434 }
2435}
2436
2437void rtl8188ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2438 bool auto_load_fail, u8 *hwinfo)
2439{
2440 struct rtl_priv *rtlpriv = rtl_priv(hw);
2441 u8 value;
2442
2443 if (!auto_load_fail) {
2444 rtlpriv->btcoexist.eeprom_bt_coexist =
2445 ((hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & 0xe0) >> 5);
2446 if (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] == 0xFF)
2447 rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2448 value = hwinfo[EEPROM_RF_BT_SETTING_88E];
2449 rtlpriv->btcoexist.eeprom_bt_type = ((value & 0xe) >> 1);
2450 rtlpriv->btcoexist.eeprom_bt_ant_num = (value & 0x1);
2451 rtlpriv->btcoexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4);
2452 rtlpriv->btcoexist.eeprom_bt_radio_shared =
2453 ((value & 0x20) >> 5);
2454 } else {
2455 rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2456 rtlpriv->btcoexist.eeprom_bt_type = BT_2WIRE;
2457 rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2;
2458 rtlpriv->btcoexist.eeprom_bt_ant_isol = 0;
2459 rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2460 }
2461
2462 rtl8188ee_bt_var_init(hw);
2463}
2464
2465void rtl8188ee_bt_reg_init(struct ieee80211_hw *hw)
2466{
2467 struct rtl_priv *rtlpriv = rtl_priv(hw);
2468
2469
2470 rtlpriv->btcoexist.reg_bt_iso = 2;
2471
2472 rtlpriv->btcoexist.reg_bt_sco = 3;
2473
2474 rtlpriv->btcoexist.reg_bt_sco = 0;
2475}
2476
2477void rtl8188ee_bt_hw_init(struct ieee80211_hw *hw)
2478{
2479 struct rtl_priv *rtlpriv = rtl_priv(hw);
2480 struct rtl_phy *rtlphy = &rtlpriv->phy;
2481 u8 u1_tmp;
2482
2483 if (rtlpriv->btcoexist.bt_coexistence &&
2484 ((rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) ||
2485 rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC8)) {
2486 if (rtlpriv->btcoexist.bt_ant_isolation)
2487 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2488
2489 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) &
2490 BIT_OFFSET_LEN_MASK_32(0, 1);
2491 u1_tmp = u1_tmp |
2492 ((rtlpriv->btcoexist.bt_ant_isolation == 1) ?
2493 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2494 ((rtlpriv->btcoexist.bt_service == BT_SCO) ?
2495 0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2496 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2497
2498 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2499 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2500 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2501
2502
2503 if (rtlphy->rf_type == RF_1T1R) {
2504 u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2505 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2506 rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2507
2508 u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2509 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2510 rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2511 }
2512 }
2513}
2514
2515void rtl88ee_suspend(struct ieee80211_hw *hw)
2516{
2517}
2518
2519void rtl88ee_resume(struct ieee80211_hw *hw)
2520{
2521}
2522
