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5#ifndef __RTW_FW_H_
6#define __RTW_FW_H_
7
8#define H2C_PKT_SIZE 32
9#define H2C_PKT_HDR_SIZE 8
10
11
12#define FW_HDR_SIZE 64
13#define FW_HDR_CHKSUM_SIZE 8
14#define FW_HDR_VERSION 4
15#define FW_HDR_SUBVERSION 6
16#define FW_HDR_SUBINDEX 7
17#define FW_HDR_MONTH 16
18#define FW_HDR_DATE 17
19#define FW_HDR_HOUR 18
20#define FW_HDR_MIN 19
21#define FW_HDR_YEAR 20
22#define FW_HDR_MEM_USAGE 24
23#define FW_HDR_H2C_FMT_VER 28
24#define FW_HDR_DMEM_ADDR 32
25#define FW_HDR_DMEM_SIZE 36
26#define FW_HDR_IMEM_SIZE 48
27#define FW_HDR_EMEM_SIZE 52
28#define FW_HDR_EMEM_ADDR 56
29#define FW_HDR_IMEM_ADDR 60
30
31#define FIFO_PAGE_SIZE_SHIFT 12
32#define FIFO_PAGE_SIZE 4096
33#define RSVD_PAGE_START_ADDR 0x780
34#define FIFO_DUMP_ADDR 0x8000
35
36enum rtw_c2h_cmd_id {
37 C2H_BT_INFO = 0x09,
38 C2H_BT_MP_INFO = 0x0b,
39 C2H_HW_FEATURE_REPORT = 0x19,
40 C2H_WLAN_INFO = 0x27,
41 C2H_HW_FEATURE_DUMP = 0xfd,
42 C2H_HALMAC = 0xff,
43};
44
45enum rtw_c2h_cmd_id_ext {
46 C2H_CCX_RPT = 0x0f,
47};
48
49struct rtw_c2h_cmd {
50 u8 id;
51 u8 seq;
52 u8 payload[0];
53} __packed;
54
55enum rtw_rsvd_packet_type {
56 RSVD_BEACON,
57 RSVD_PS_POLL,
58 RSVD_PROBE_RESP,
59 RSVD_NULL,
60 RSVD_QOS_NULL,
61};
62
63enum rtw_fw_rf_type {
64 FW_RF_1T2R = 0,
65 FW_RF_2T4R = 1,
66 FW_RF_2T2R = 2,
67 FW_RF_2T3R = 3,
68 FW_RF_1T1R = 4,
69 FW_RF_2T2R_GREEN = 5,
70 FW_RF_3T3R = 6,
71 FW_RF_3T4R = 7,
72 FW_RF_4T4R = 8,
73 FW_RF_MAX_TYPE = 0xF,
74};
75
76struct rtw_coex_info_req {
77 u8 seq;
78 u8 op_code;
79 u8 para1;
80 u8 para2;
81 u8 para3;
82};
83
84struct rtw_iqk_para {
85 u8 clear;
86 u8 segment_iqk;
87};
88
89struct rtw_rsvd_page {
90 struct list_head list;
91 struct sk_buff *skb;
92 enum rtw_rsvd_packet_type type;
93 u8 page;
94 bool add_txdesc;
95};
96
97
98#define GET_CCX_REPORT_SEQNUM(c2h_payload) (c2h_payload[8] & 0xfc)
99#define GET_CCX_REPORT_STATUS(c2h_payload) (c2h_payload[9] & 0xc0)
100
101
102#define H2C_PKT_CMD_ID 0xFF
103#define H2C_PKT_CATEGORY 0x01
104
105#define H2C_PKT_GENERAL_INFO 0x0D
106#define H2C_PKT_PHYDM_INFO 0x11
107#define H2C_PKT_IQK 0x0E
108
109#define SET_PKT_H2C_CATEGORY(h2c_pkt, value) \
110 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(6, 0))
111#define SET_PKT_H2C_CMD_ID(h2c_pkt, value) \
112 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
113#define SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, value) \
114 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 16))
115#define SET_PKT_H2C_TOTAL_LEN(h2c_pkt, value) \
116 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 0))
117
118static inline void rtw_h2c_pkt_set_header(u8 *h2c_pkt, u8 sub_id)
119{
120 SET_PKT_H2C_CATEGORY(h2c_pkt, H2C_PKT_CATEGORY);
121 SET_PKT_H2C_CMD_ID(h2c_pkt, H2C_PKT_CMD_ID);
122 SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, sub_id);
123}
124
125#define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \
126 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 16))
127#define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value) \
128 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
129
130#define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \
131 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(7, 0))
132#define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \
133 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8))
134#define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \
135 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
136#define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \
137 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24))
138#define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \
139 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28))
140#define IQK_SET_CLEAR(h2c_pkt, value) \
141 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0))
142#define IQK_SET_SEGMENT_IQK(h2c_pkt, value) \
143 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1))
144
145
146#define H2C_CMD_RSVD_PAGE 0x0
147#define H2C_CMD_MEDIA_STATUS_RPT 0x01
148#define H2C_CMD_SET_PWR_MODE 0x20
149#define H2C_CMD_RA_INFO 0x40
150#define H2C_CMD_RSSI_MONITOR 0x42
151
152#define H2C_CMD_COEX_TDMA_TYPE 0x60
153#define H2C_CMD_QUERY_BT_INFO 0x61
154#define H2C_CMD_FORCE_BT_TX_POWER 0x62
155#define H2C_CMD_IGNORE_WLAN_ACTION 0x63
156#define H2C_CMD_WL_CH_INFO 0x66
157#define H2C_CMD_QUERY_BT_MP_INFO 0x67
158#define H2C_CMD_BT_WIFI_CONTROL 0x69
159
160#define SET_H2C_CMD_ID_CLASS(h2c_pkt, value) \
161 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(7, 0))
162
163#define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value) \
164 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
165#define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value) \
166 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
167
168#define SET_PWR_MODE_SET_MODE(h2c_pkt, value) \
169 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(14, 8))
170#define SET_PWR_MODE_SET_RLBM(h2c_pkt, value) \
171 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(19, 16))
172#define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value) \
173 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 20))
174#define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value) \
175 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
176#define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value) \
177 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 5))
178#define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value) \
179 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
180#define SET_RSSI_INFO_MACID(h2c_pkt, value) \
181 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
182#define SET_RSSI_INFO_RSSI(h2c_pkt, value) \
183 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
184#define SET_RSSI_INFO_STBC(h2c_pkt, value) \
185 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, BIT(1))
186#define SET_RA_INFO_MACID(h2c_pkt, value) \
187 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
188#define SET_RA_INFO_RATE_ID(h2c_pkt, value) \
189 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 16))
190#define SET_RA_INFO_INIT_RA_LVL(h2c_pkt, value) \
191 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(22, 21))
192#define SET_RA_INFO_SGI_EN(h2c_pkt, value) \
193 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(23))
194#define SET_RA_INFO_BW_MODE(h2c_pkt, value) \
195 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(25, 24))
196#define SET_RA_INFO_LDPC(h2c_pkt, value) \
197 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(26))
198#define SET_RA_INFO_NO_UPDATE(h2c_pkt, value) \
199 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(27))
200#define SET_RA_INFO_VHT_EN(h2c_pkt, value) \
201 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(29, 28))
202#define SET_RA_INFO_DIS_PT(h2c_pkt, value) \
203 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(30))
204#define SET_RA_INFO_RA_MASK0(h2c_pkt, value) \
205 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
206#define SET_RA_INFO_RA_MASK1(h2c_pkt, value) \
207 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
208#define SET_RA_INFO_RA_MASK2(h2c_pkt, value) \
209 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))
210#define SET_RA_INFO_RA_MASK3(h2c_pkt, value) \
211 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 24))
212#define SET_QUERY_BT_INFO(h2c_pkt, value) \
213 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
214#define SET_WL_CH_INFO_LINK(h2c_pkt, value) \
215 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
216#define SET_WL_CH_INFO_CHNL(h2c_pkt, value) \
217 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
218#define SET_WL_CH_INFO_BW(h2c_pkt, value) \
219 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
220#define SET_BT_MP_INFO_SEQ(h2c_pkt, value) \
221 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12))
222#define SET_BT_MP_INFO_OP_CODE(h2c_pkt, value) \
223 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
224#define SET_BT_MP_INFO_PARA1(h2c_pkt, value) \
225 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
226#define SET_BT_MP_INFO_PARA2(h2c_pkt, value) \
227 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
228#define SET_BT_MP_INFO_PARA3(h2c_pkt, value) \
229 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
230#define SET_BT_TX_POWER_INDEX(h2c_pkt, value) \
231 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
232#define SET_IGNORE_WLAN_ACTION_EN(h2c_pkt, value) \
233 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
234#define SET_COEX_TDMA_TYPE_PARA1(h2c_pkt, value) \
235 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
236#define SET_COEX_TDMA_TYPE_PARA2(h2c_pkt, value) \
237 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
238#define SET_COEX_TDMA_TYPE_PARA3(h2c_pkt, value) \
239 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
240#define SET_COEX_TDMA_TYPE_PARA4(h2c_pkt, value) \
241 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
242#define SET_COEX_TDMA_TYPE_PARA5(h2c_pkt, value) \
243 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
244#define SET_BT_WIFI_CONTROL_OP_CODE(h2c_pkt, value) \
245 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
246#define SET_BT_WIFI_CONTROL_DATA1(h2c_pkt, value) \
247 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
248#define SET_BT_WIFI_CONTROL_DATA2(h2c_pkt, value) \
249 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
250#define SET_BT_WIFI_CONTROL_DATA3(h2c_pkt, value) \
251 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
252#define SET_BT_WIFI_CONTROL_DATA4(h2c_pkt, value) \
253 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
254#define SET_BT_WIFI_CONTROL_DATA5(h2c_pkt, value) \
255 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))
256
257static inline struct rtw_c2h_cmd *get_c2h_from_skb(struct sk_buff *skb)
258{
259 u32 pkt_offset;
260
261 pkt_offset = *((u32 *)skb->cb);
262 return (struct rtw_c2h_cmd *)(skb->data + pkt_offset);
263}
264
265void rtw_fw_c2h_cmd_rx_irqsafe(struct rtw_dev *rtwdev, u32 pkt_offset,
266 struct sk_buff *skb);
267void rtw_fw_c2h_cmd_handle(struct rtw_dev *rtwdev, struct sk_buff *skb);
268void rtw_fw_send_general_info(struct rtw_dev *rtwdev);
269void rtw_fw_send_phydm_info(struct rtw_dev *rtwdev);
270
271void rtw_fw_do_iqk(struct rtw_dev *rtwdev, struct rtw_iqk_para *para);
272void rtw_fw_set_pwr_mode(struct rtw_dev *rtwdev);
273void rtw_fw_query_bt_info(struct rtw_dev *rtwdev);
274void rtw_fw_wl_ch_info(struct rtw_dev *rtwdev, u8 link, u8 ch, u8 bw);
275void rtw_fw_query_bt_mp_info(struct rtw_dev *rtwdev,
276 struct rtw_coex_info_req *req);
277void rtw_fw_force_bt_tx_power(struct rtw_dev *rtwdev, u8 bt_pwr_dec_lvl);
278void rtw_fw_bt_ignore_wlan_action(struct rtw_dev *rtwdev, bool enable);
279void rtw_fw_coex_tdma_type(struct rtw_dev *rtwdev,
280 u8 para1, u8 para2, u8 para3, u8 para4, u8 para5);
281void rtw_fw_bt_wifi_control(struct rtw_dev *rtwdev, u8 op_code, u8 *data);
282void rtw_fw_send_rssi_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si);
283void rtw_fw_send_ra_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si);
284void rtw_fw_media_status_report(struct rtw_dev *rtwdev, u8 mac_id, bool conn);
285void rtw_add_rsvd_page(struct rtw_dev *rtwdev, enum rtw_rsvd_packet_type type,
286 bool txdesc);
287int rtw_fw_write_data_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr,
288 u8 *buf, u32 size);
289void rtw_reset_rsvd_page(struct rtw_dev *rtwdev);
290int rtw_fw_download_rsvd_page(struct rtw_dev *rtwdev,
291 struct ieee80211_vif *vif);
292void rtw_send_rsvd_page_h2c(struct rtw_dev *rtwdev);
293int rtw_dump_drv_rsvd_page(struct rtw_dev *rtwdev,
294 u32 offset, u32 size, u32 *buf);
295#endif
296
