1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24#include <linux/blkdev.h>
25#include <linux/delay.h>
26#include <linux/dma-mapping.h>
27#include <linux/idr.h>
28#include <linux/interrupt.h>
29#include <linux/module.h>
30#include <linux/kthread.h>
31#include <linux/pci.h>
32#include <linux/spinlock.h>
33#include <linux/ctype.h>
34#include <linux/aer.h>
35#include <linux/slab.h>
36#include <linux/firmware.h>
37#include <linux/miscdevice.h>
38#include <linux/percpu.h>
39#include <linux/msi.h>
40#include <linux/irq.h>
41#include <linux/bitops.h>
42#include <linux/crash_dump.h>
43
44#include <scsi/scsi.h>
45#include <scsi/scsi_device.h>
46#include <scsi/scsi_host.h>
47#include <scsi/scsi_transport_fc.h>
48#include <scsi/scsi_tcq.h>
49#include <scsi/fc/fc_fs.h>
50
51#include <linux/nvme-fc-driver.h>
52
53#include "lpfc_hw4.h"
54#include "lpfc_hw.h"
55#include "lpfc_sli.h"
56#include "lpfc_sli4.h"
57#include "lpfc_nl.h"
58#include "lpfc_disc.h"
59#include "lpfc.h"
60#include "lpfc_scsi.h"
61#include "lpfc_nvme.h"
62#include "lpfc_nvmet.h"
63#include "lpfc_logmsg.h"
64#include "lpfc_crtn.h"
65#include "lpfc_vport.h"
66#include "lpfc_version.h"
67#include "lpfc_ids.h"
68
69
70static uint32_t lpfc_present_cpu;
71
72static void lpfc_get_hba_model_desc(struct lpfc_hba *, uint8_t *, uint8_t *);
73static int lpfc_post_rcv_buf(struct lpfc_hba *);
74static int lpfc_sli4_queue_verify(struct lpfc_hba *);
75static int lpfc_create_bootstrap_mbox(struct lpfc_hba *);
76static int lpfc_setup_endian_order(struct lpfc_hba *);
77static void lpfc_destroy_bootstrap_mbox(struct lpfc_hba *);
78static void lpfc_free_els_sgl_list(struct lpfc_hba *);
79static void lpfc_free_nvmet_sgl_list(struct lpfc_hba *);
80static void lpfc_init_sgl_list(struct lpfc_hba *);
81static int lpfc_init_active_sgl_array(struct lpfc_hba *);
82static void lpfc_free_active_sgl(struct lpfc_hba *);
83static int lpfc_hba_down_post_s3(struct lpfc_hba *phba);
84static int lpfc_hba_down_post_s4(struct lpfc_hba *phba);
85static int lpfc_sli4_cq_event_pool_create(struct lpfc_hba *);
86static void lpfc_sli4_cq_event_pool_destroy(struct lpfc_hba *);
87static void lpfc_sli4_cq_event_release_all(struct lpfc_hba *);
88static void lpfc_sli4_disable_intr(struct lpfc_hba *);
89static uint32_t lpfc_sli4_enable_intr(struct lpfc_hba *, uint32_t);
90static void lpfc_sli4_oas_verify(struct lpfc_hba *phba);
91static uint16_t lpfc_find_cpu_handle(struct lpfc_hba *, uint16_t, int);
92static void lpfc_setup_bg(struct lpfc_hba *, struct Scsi_Host *);
93
94static struct scsi_transport_template *lpfc_transport_template = NULL;
95static struct scsi_transport_template *lpfc_vport_transport_template = NULL;
96static DEFINE_IDR(lpfc_hba_index);
97#define LPFC_NVMET_BUF_POST 254
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113int
114lpfc_config_port_prep(struct lpfc_hba *phba)
115{
116 lpfc_vpd_t *vp = &phba->vpd;
117 int i = 0, rc;
118 LPFC_MBOXQ_t *pmb;
119 MAILBOX_t *mb;
120 char *lpfc_vpd_data = NULL;
121 uint16_t offset = 0;
122 static char licensed[56] =
123 "key unlock for use with gnu public licensed code only\0";
124 static int init_key = 1;
125
126 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
127 if (!pmb) {
128 phba->link_state = LPFC_HBA_ERROR;
129 return -ENOMEM;
130 }
131
132 mb = &pmb->u.mb;
133 phba->link_state = LPFC_INIT_MBX_CMDS;
134
135 if (lpfc_is_LC_HBA(phba->pcidev->device)) {
136 if (init_key) {
137 uint32_t *ptext = (uint32_t *) licensed;
138
139 for (i = 0; i < 56; i += sizeof (uint32_t), ptext++)
140 *ptext = cpu_to_be32(*ptext);
141 init_key = 0;
142 }
143
144 lpfc_read_nv(phba, pmb);
145 memset((char*)mb->un.varRDnvp.rsvd3, 0,
146 sizeof (mb->un.varRDnvp.rsvd3));
147 memcpy((char*)mb->un.varRDnvp.rsvd3, licensed,
148 sizeof (licensed));
149
150 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
151
152 if (rc != MBX_SUCCESS) {
153 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX,
154 "0324 Config Port initialization "
155 "error, mbxCmd x%x READ_NVPARM, "
156 "mbxStatus x%x\n",
157 mb->mbxCommand, mb->mbxStatus);
158 mempool_free(pmb, phba->mbox_mem_pool);
159 return -ERESTART;
160 }
161 memcpy(phba->wwnn, (char *)mb->un.varRDnvp.nodename,
162 sizeof(phba->wwnn));
163 memcpy(phba->wwpn, (char *)mb->un.varRDnvp.portname,
164 sizeof(phba->wwpn));
165 }
166
167
168
169
170
171 phba->sli3_options &= (uint32_t)LPFC_SLI3_BG_ENABLED;
172
173
174 lpfc_read_rev(phba, pmb);
175 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
176 if (rc != MBX_SUCCESS) {
177 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
178 "0439 Adapter failed to init, mbxCmd x%x "
179 "READ_REV, mbxStatus x%x\n",
180 mb->mbxCommand, mb->mbxStatus);
181 mempool_free( pmb, phba->mbox_mem_pool);
182 return -ERESTART;
183 }
184
185
186
187
188
189
190 if (mb->un.varRdRev.rr == 0) {
191 vp->rev.rBit = 0;
192 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
193 "0440 Adapter failed to init, READ_REV has "
194 "missing revision information.\n");
195 mempool_free(pmb, phba->mbox_mem_pool);
196 return -ERESTART;
197 }
198
199 if (phba->sli_rev == 3 && !mb->un.varRdRev.v3rsp) {
200 mempool_free(pmb, phba->mbox_mem_pool);
201 return -EINVAL;
202 }
203
204
205 vp->rev.rBit = 1;
206 memcpy(&vp->sli3Feat, &mb->un.varRdRev.sli3Feat, sizeof(uint32_t));
207 vp->rev.sli1FwRev = mb->un.varRdRev.sli1FwRev;
208 memcpy(vp->rev.sli1FwName, (char*) mb->un.varRdRev.sli1FwName, 16);
209 vp->rev.sli2FwRev = mb->un.varRdRev.sli2FwRev;
210 memcpy(vp->rev.sli2FwName, (char *) mb->un.varRdRev.sli2FwName, 16);
211 vp->rev.biuRev = mb->un.varRdRev.biuRev;
212 vp->rev.smRev = mb->un.varRdRev.smRev;
213 vp->rev.smFwRev = mb->un.varRdRev.un.smFwRev;
214 vp->rev.endecRev = mb->un.varRdRev.endecRev;
215 vp->rev.fcphHigh = mb->un.varRdRev.fcphHigh;
216 vp->rev.fcphLow = mb->un.varRdRev.fcphLow;
217 vp->rev.feaLevelHigh = mb->un.varRdRev.feaLevelHigh;
218 vp->rev.feaLevelLow = mb->un.varRdRev.feaLevelLow;
219 vp->rev.postKernRev = mb->un.varRdRev.postKernRev;
220 vp->rev.opFwRev = mb->un.varRdRev.opFwRev;
221
222
223
224
225
226 if (vp->rev.feaLevelHigh < 9)
227 phba->sli3_options |= LPFC_SLI3_VPORT_TEARDOWN;
228
229 if (lpfc_is_LC_HBA(phba->pcidev->device))
230 memcpy(phba->RandomData, (char *)&mb->un.varWords[24],
231 sizeof (phba->RandomData));
232
233
234 lpfc_vpd_data = kmalloc(DMP_VPD_SIZE, GFP_KERNEL);
235 if (!lpfc_vpd_data)
236 goto out_free_mbox;
237 do {
238 lpfc_dump_mem(phba, pmb, offset, DMP_REGION_VPD);
239 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
240
241 if (rc != MBX_SUCCESS) {
242 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
243 "0441 VPD not present on adapter, "
244 "mbxCmd x%x DUMP VPD, mbxStatus x%x\n",
245 mb->mbxCommand, mb->mbxStatus);
246 mb->un.varDmp.word_cnt = 0;
247 }
248
249
250
251 if (mb->un.varDmp.word_cnt == 0)
252 break;
253 if (mb->un.varDmp.word_cnt > DMP_VPD_SIZE - offset)
254 mb->un.varDmp.word_cnt = DMP_VPD_SIZE - offset;
255 lpfc_sli_pcimem_bcopy(((uint8_t *)mb) + DMP_RSP_OFFSET,
256 lpfc_vpd_data + offset,
257 mb->un.varDmp.word_cnt);
258 offset += mb->un.varDmp.word_cnt;
259 } while (mb->un.varDmp.word_cnt && offset < DMP_VPD_SIZE);
260 lpfc_parse_vpd(phba, lpfc_vpd_data, offset);
261
262 kfree(lpfc_vpd_data);
263out_free_mbox:
264 mempool_free(pmb, phba->mbox_mem_pool);
265 return 0;
266}
267
268
269
270
271
272
273
274
275
276
277
278static void
279lpfc_config_async_cmpl(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq)
280{
281 if (pmboxq->u.mb.mbxStatus == MBX_SUCCESS)
282 phba->temp_sensor_support = 1;
283 else
284 phba->temp_sensor_support = 0;
285 mempool_free(pmboxq, phba->mbox_mem_pool);
286 return;
287}
288
289
290
291
292
293
294
295
296
297
298
299static void
300lpfc_dump_wakeup_param_cmpl(struct lpfc_hba *phba, LPFC_MBOXQ_t *pmboxq)
301{
302 struct prog_id *prg;
303 uint32_t prog_id_word;
304 char dist = ' ';
305
306 char dist_char[] = "nabx";
307
308 if (pmboxq->u.mb.mbxStatus != MBX_SUCCESS) {
309 mempool_free(pmboxq, phba->mbox_mem_pool);
310 return;
311 }
312
313 prg = (struct prog_id *) &prog_id_word;
314
315
316 prog_id_word = pmboxq->u.mb.un.varWords[7];
317
318
319 if (prg->dist < 4)
320 dist = dist_char[prg->dist];
321
322 if ((prg->dist == 3) && (prg->num == 0))
323 snprintf(phba->OptionROMVersion, 32, "%d.%d%d",
324 prg->ver, prg->rev, prg->lev);
325 else
326 snprintf(phba->OptionROMVersion, 32, "%d.%d%d%c%d",
327 prg->ver, prg->rev, prg->lev,
328 dist, prg->num);
329 mempool_free(pmboxq, phba->mbox_mem_pool);
330 return;
331}
332
333
334
335
336
337
338
339
340
341
342void
343lpfc_update_vport_wwn(struct lpfc_vport *vport)
344{
345 uint8_t vvvl = vport->fc_sparam.cmn.valid_vendor_ver_level;
346 u32 *fawwpn_key = (u32 *)&vport->fc_sparam.un.vendorVersion[0];
347
348
349 if (vport->phba->cfg_soft_wwnn)
350 u64_to_wwn(vport->phba->cfg_soft_wwnn,
351 vport->fc_sparam.nodeName.u.wwn);
352 if (vport->phba->cfg_soft_wwpn)
353 u64_to_wwn(vport->phba->cfg_soft_wwpn,
354 vport->fc_sparam.portName.u.wwn);
355
356
357
358
359
360 if (vport->fc_nodename.u.wwn[0] == 0 || vport->phba->cfg_soft_wwnn)
361 memcpy(&vport->fc_nodename, &vport->fc_sparam.nodeName,
362 sizeof(struct lpfc_name));
363 else
364 memcpy(&vport->fc_sparam.nodeName, &vport->fc_nodename,
365 sizeof(struct lpfc_name));
366
367
368
369
370
371 if (vport->fc_portname.u.wwn[0] != 0 &&
372 memcmp(&vport->fc_portname, &vport->fc_sparam.portName,
373 sizeof(struct lpfc_name)))
374 vport->vport_flag |= FAWWPN_PARAM_CHG;
375
376 if (vport->fc_portname.u.wwn[0] == 0 ||
377 vport->phba->cfg_soft_wwpn ||
378 (vvvl == 1 && cpu_to_be32(*fawwpn_key) == FAPWWN_KEY_VENDOR) ||
379 vport->vport_flag & FAWWPN_SET) {
380 memcpy(&vport->fc_portname, &vport->fc_sparam.portName,
381 sizeof(struct lpfc_name));
382 vport->vport_flag &= ~FAWWPN_SET;
383 if (vvvl == 1 && cpu_to_be32(*fawwpn_key) == FAPWWN_KEY_VENDOR)
384 vport->vport_flag |= FAWWPN_SET;
385 }
386 else
387 memcpy(&vport->fc_sparam.portName, &vport->fc_portname,
388 sizeof(struct lpfc_name));
389}
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404int
405lpfc_config_port_post(struct lpfc_hba *phba)
406{
407 struct lpfc_vport *vport = phba->pport;
408 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
409 LPFC_MBOXQ_t *pmb;
410 MAILBOX_t *mb;
411 struct lpfc_dmabuf *mp;
412 struct lpfc_sli *psli = &phba->sli;
413 uint32_t status, timeout;
414 int i, j;
415 int rc;
416
417 spin_lock_irq(&phba->hbalock);
418
419
420
421
422 if (phba->over_temp_state == HBA_OVER_TEMP)
423 phba->over_temp_state = HBA_NORMAL_TEMP;
424 spin_unlock_irq(&phba->hbalock);
425
426 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
427 if (!pmb) {
428 phba->link_state = LPFC_HBA_ERROR;
429 return -ENOMEM;
430 }
431 mb = &pmb->u.mb;
432
433
434 rc = lpfc_read_sparam(phba, pmb, 0);
435 if (rc) {
436 mempool_free(pmb, phba->mbox_mem_pool);
437 return -ENOMEM;
438 }
439
440 pmb->vport = vport;
441 if (lpfc_sli_issue_mbox(phba, pmb, MBX_POLL) != MBX_SUCCESS) {
442 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
443 "0448 Adapter failed init, mbxCmd x%x "
444 "READ_SPARM mbxStatus x%x\n",
445 mb->mbxCommand, mb->mbxStatus);
446 phba->link_state = LPFC_HBA_ERROR;
447 mp = (struct lpfc_dmabuf *)pmb->ctx_buf;
448 mempool_free(pmb, phba->mbox_mem_pool);
449 lpfc_mbuf_free(phba, mp->virt, mp->phys);
450 kfree(mp);
451 return -EIO;
452 }
453
454 mp = (struct lpfc_dmabuf *)pmb->ctx_buf;
455
456 memcpy(&vport->fc_sparam, mp->virt, sizeof (struct serv_parm));
457 lpfc_mbuf_free(phba, mp->virt, mp->phys);
458 kfree(mp);
459 pmb->ctx_buf = NULL;
460 lpfc_update_vport_wwn(vport);
461
462
463 fc_host_node_name(shost) = wwn_to_u64(vport->fc_nodename.u.wwn);
464 fc_host_port_name(shost) = wwn_to_u64(vport->fc_portname.u.wwn);
465 fc_host_max_npiv_vports(shost) = phba->max_vpi;
466
467
468
469 if (phba->SerialNumber[0] == 0) {
470 uint8_t *outptr;
471
472 outptr = &vport->fc_nodename.u.s.IEEE[0];
473 for (i = 0; i < 12; i++) {
474 status = *outptr++;
475 j = ((status & 0xf0) >> 4);
476 if (j <= 9)
477 phba->SerialNumber[i] =
478 (char)((uint8_t) 0x30 + (uint8_t) j);
479 else
480 phba->SerialNumber[i] =
481 (char)((uint8_t) 0x61 + (uint8_t) (j - 10));
482 i++;
483 j = (status & 0xf);
484 if (j <= 9)
485 phba->SerialNumber[i] =
486 (char)((uint8_t) 0x30 + (uint8_t) j);
487 else
488 phba->SerialNumber[i] =
489 (char)((uint8_t) 0x61 + (uint8_t) (j - 10));
490 }
491 }
492
493 lpfc_read_config(phba, pmb);
494 pmb->vport = vport;
495 if (lpfc_sli_issue_mbox(phba, pmb, MBX_POLL) != MBX_SUCCESS) {
496 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
497 "0453 Adapter failed to init, mbxCmd x%x "
498 "READ_CONFIG, mbxStatus x%x\n",
499 mb->mbxCommand, mb->mbxStatus);
500 phba->link_state = LPFC_HBA_ERROR;
501 mempool_free( pmb, phba->mbox_mem_pool);
502 return -EIO;
503 }
504
505
506 lpfc_sli_read_link_ste(phba);
507
508
509 i = (mb->un.varRdConfig.max_xri + 1);
510 if (phba->cfg_hba_queue_depth > i) {
511 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
512 "3359 HBA queue depth changed from %d to %d\n",
513 phba->cfg_hba_queue_depth, i);
514 phba->cfg_hba_queue_depth = i;
515 }
516
517
518 i = (mb->un.varRdConfig.max_xri >> 3);
519 if (phba->pport->cfg_lun_queue_depth > i) {
520 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
521 "3360 LUN queue depth changed from %d to %d\n",
522 phba->pport->cfg_lun_queue_depth, i);
523 phba->pport->cfg_lun_queue_depth = i;
524 }
525
526 phba->lmt = mb->un.varRdConfig.lmt;
527
528
529 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
530
531 phba->link_state = LPFC_LINK_DOWN;
532
533
534 if (psli->sli3_ring[LPFC_EXTRA_RING].sli.sli3.cmdringaddr)
535 psli->sli3_ring[LPFC_EXTRA_RING].flag |= LPFC_STOP_IOCB_EVENT;
536 if (psli->sli3_ring[LPFC_FCP_RING].sli.sli3.cmdringaddr)
537 psli->sli3_ring[LPFC_FCP_RING].flag |= LPFC_STOP_IOCB_EVENT;
538
539
540 if (phba->sli_rev != 3)
541 lpfc_post_rcv_buf(phba);
542
543
544
545
546 if (phba->intr_type == MSIX) {
547 rc = lpfc_config_msi(phba, pmb);
548 if (rc) {
549 mempool_free(pmb, phba->mbox_mem_pool);
550 return -EIO;
551 }
552 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
553 if (rc != MBX_SUCCESS) {
554 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX,
555 "0352 Config MSI mailbox command "
556 "failed, mbxCmd x%x, mbxStatus x%x\n",
557 pmb->u.mb.mbxCommand,
558 pmb->u.mb.mbxStatus);
559 mempool_free(pmb, phba->mbox_mem_pool);
560 return -EIO;
561 }
562 }
563
564 spin_lock_irq(&phba->hbalock);
565
566 phba->hba_flag &= ~HBA_ERATT_HANDLED;
567
568
569 if (lpfc_readl(phba->HCregaddr, &status)) {
570 spin_unlock_irq(&phba->hbalock);
571 return -EIO;
572 }
573 status |= HC_MBINT_ENA | HC_ERINT_ENA | HC_LAINT_ENA;
574 if (psli->num_rings > 0)
575 status |= HC_R0INT_ENA;
576 if (psli->num_rings > 1)
577 status |= HC_R1INT_ENA;
578 if (psli->num_rings > 2)
579 status |= HC_R2INT_ENA;
580 if (psli->num_rings > 3)
581 status |= HC_R3INT_ENA;
582
583 if ((phba->cfg_poll & ENABLE_FCP_RING_POLLING) &&
584 (phba->cfg_poll & DISABLE_FCP_RING_INT))
585 status &= ~(HC_R0INT_ENA);
586
587 writel(status, phba->HCregaddr);
588 readl(phba->HCregaddr);
589 spin_unlock_irq(&phba->hbalock);
590
591
592 timeout = phba->fc_ratov * 2;
593 mod_timer(&vport->els_tmofunc,
594 jiffies + msecs_to_jiffies(1000 * timeout));
595
596 mod_timer(&phba->hb_tmofunc,
597 jiffies + msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
598 phba->hb_outstanding = 0;
599 phba->last_completion_time = jiffies;
600
601 mod_timer(&phba->eratt_poll,
602 jiffies + msecs_to_jiffies(1000 * phba->eratt_poll_interval));
603
604 if (phba->hba_flag & LINK_DISABLED) {
605 lpfc_printf_log(phba,
606 KERN_ERR, LOG_INIT,
607 "2598 Adapter Link is disabled.\n");
608 lpfc_down_link(phba, pmb);
609 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
610 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
611 if ((rc != MBX_SUCCESS) && (rc != MBX_BUSY)) {
612 lpfc_printf_log(phba,
613 KERN_ERR, LOG_INIT,
614 "2599 Adapter failed to issue DOWN_LINK"
615 " mbox command rc 0x%x\n", rc);
616
617 mempool_free(pmb, phba->mbox_mem_pool);
618 return -EIO;
619 }
620 } else if (phba->cfg_suppress_link_up == LPFC_INITIALIZE_LINK) {
621 mempool_free(pmb, phba->mbox_mem_pool);
622 rc = phba->lpfc_hba_init_link(phba, MBX_NOWAIT);
623 if (rc)
624 return rc;
625 }
626
627 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
628 if (!pmb) {
629 phba->link_state = LPFC_HBA_ERROR;
630 return -ENOMEM;
631 }
632
633 lpfc_config_async(phba, pmb, LPFC_ELS_RING);
634 pmb->mbox_cmpl = lpfc_config_async_cmpl;
635 pmb->vport = phba->pport;
636 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
637
638 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
639 lpfc_printf_log(phba,
640 KERN_ERR,
641 LOG_INIT,
642 "0456 Adapter failed to issue "
643 "ASYNCEVT_ENABLE mbox status x%x\n",
644 rc);
645 mempool_free(pmb, phba->mbox_mem_pool);
646 }
647
648
649 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
650 if (!pmb) {
651 phba->link_state = LPFC_HBA_ERROR;
652 return -ENOMEM;
653 }
654
655 lpfc_dump_wakeup_param(phba, pmb);
656 pmb->mbox_cmpl = lpfc_dump_wakeup_param_cmpl;
657 pmb->vport = phba->pport;
658 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
659
660 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
661 lpfc_printf_log(phba, KERN_ERR, LOG_INIT, "0435 Adapter failed "
662 "to get Option ROM version status x%x\n", rc);
663 mempool_free(pmb, phba->mbox_mem_pool);
664 }
665
666 return 0;
667}
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683static int
684lpfc_hba_init_link(struct lpfc_hba *phba, uint32_t flag)
685{
686 return lpfc_hba_init_link_fc_topology(phba, phba->cfg_topology, flag);
687}
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704int
705lpfc_hba_init_link_fc_topology(struct lpfc_hba *phba, uint32_t fc_topology,
706 uint32_t flag)
707{
708 struct lpfc_vport *vport = phba->pport;
709 LPFC_MBOXQ_t *pmb;
710 MAILBOX_t *mb;
711 int rc;
712
713 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
714 if (!pmb) {
715 phba->link_state = LPFC_HBA_ERROR;
716 return -ENOMEM;
717 }
718 mb = &pmb->u.mb;
719 pmb->vport = vport;
720
721 if ((phba->cfg_link_speed > LPFC_USER_LINK_SPEED_MAX) ||
722 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_1G) &&
723 !(phba->lmt & LMT_1Gb)) ||
724 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_2G) &&
725 !(phba->lmt & LMT_2Gb)) ||
726 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_4G) &&
727 !(phba->lmt & LMT_4Gb)) ||
728 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_8G) &&
729 !(phba->lmt & LMT_8Gb)) ||
730 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_10G) &&
731 !(phba->lmt & LMT_10Gb)) ||
732 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_16G) &&
733 !(phba->lmt & LMT_16Gb)) ||
734 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_32G) &&
735 !(phba->lmt & LMT_32Gb)) ||
736 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_64G) &&
737 !(phba->lmt & LMT_64Gb))) {
738
739 lpfc_printf_log(phba, KERN_ERR, LOG_LINK_EVENT,
740 "1302 Invalid speed for this board:%d "
741 "Reset link speed to auto.\n",
742 phba->cfg_link_speed);
743 phba->cfg_link_speed = LPFC_USER_LINK_SPEED_AUTO;
744 }
745 lpfc_init_link(phba, pmb, fc_topology, phba->cfg_link_speed);
746 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
747 if (phba->sli_rev < LPFC_SLI_REV4)
748 lpfc_set_loopback_flag(phba);
749 rc = lpfc_sli_issue_mbox(phba, pmb, flag);
750 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
751 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
752 "0498 Adapter failed to init, mbxCmd x%x "
753 "INIT_LINK, mbxStatus x%x\n",
754 mb->mbxCommand, mb->mbxStatus);
755 if (phba->sli_rev <= LPFC_SLI_REV3) {
756
757 writel(0, phba->HCregaddr);
758 readl(phba->HCregaddr);
759
760 writel(0xffffffff, phba->HAregaddr);
761 readl(phba->HAregaddr);
762 }
763 phba->link_state = LPFC_HBA_ERROR;
764 if (rc != MBX_BUSY || flag == MBX_POLL)
765 mempool_free(pmb, phba->mbox_mem_pool);
766 return -EIO;
767 }
768 phba->cfg_suppress_link_up = LPFC_INITIALIZE_LINK;
769 if (flag == MBX_POLL)
770 mempool_free(pmb, phba->mbox_mem_pool);
771
772 return 0;
773}
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788static int
789lpfc_hba_down_link(struct lpfc_hba *phba, uint32_t flag)
790{
791 LPFC_MBOXQ_t *pmb;
792 int rc;
793
794 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
795 if (!pmb) {
796 phba->link_state = LPFC_HBA_ERROR;
797 return -ENOMEM;
798 }
799
800 lpfc_printf_log(phba,
801 KERN_ERR, LOG_INIT,
802 "0491 Adapter Link is disabled.\n");
803 lpfc_down_link(phba, pmb);
804 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
805 rc = lpfc_sli_issue_mbox(phba, pmb, flag);
806 if ((rc != MBX_SUCCESS) && (rc != MBX_BUSY)) {
807 lpfc_printf_log(phba,
808 KERN_ERR, LOG_INIT,
809 "2522 Adapter failed to issue DOWN_LINK"
810 " mbox command rc 0x%x\n", rc);
811
812 mempool_free(pmb, phba->mbox_mem_pool);
813 return -EIO;
814 }
815 if (flag == MBX_POLL)
816 mempool_free(pmb, phba->mbox_mem_pool);
817
818 return 0;
819}
820
821
822
823
824
825
826
827
828
829
830
831
832int
833lpfc_hba_down_prep(struct lpfc_hba *phba)
834{
835 struct lpfc_vport **vports;
836 int i;
837
838 if (phba->sli_rev <= LPFC_SLI_REV3) {
839
840 writel(0, phba->HCregaddr);
841 readl(phba->HCregaddr);
842 }
843
844 if (phba->pport->load_flag & FC_UNLOADING)
845 lpfc_cleanup_discovery_resources(phba->pport);
846 else {
847 vports = lpfc_create_vport_work_array(phba);
848 if (vports != NULL)
849 for (i = 0; i <= phba->max_vports &&
850 vports[i] != NULL; i++)
851 lpfc_cleanup_discovery_resources(vports[i]);
852 lpfc_destroy_vport_work_array(phba, vports);
853 }
854 return 0;
855}
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870static void
871lpfc_sli4_free_sp_events(struct lpfc_hba *phba)
872{
873 struct lpfc_iocbq *rspiocbq;
874 struct hbq_dmabuf *dmabuf;
875 struct lpfc_cq_event *cq_event;
876
877 spin_lock_irq(&phba->hbalock);
878 phba->hba_flag &= ~HBA_SP_QUEUE_EVT;
879 spin_unlock_irq(&phba->hbalock);
880
881 while (!list_empty(&phba->sli4_hba.sp_queue_event)) {
882
883 spin_lock_irq(&phba->hbalock);
884 list_remove_head(&phba->sli4_hba.sp_queue_event,
885 cq_event, struct lpfc_cq_event, list);
886 spin_unlock_irq(&phba->hbalock);
887
888 switch (bf_get(lpfc_wcqe_c_code, &cq_event->cqe.wcqe_cmpl)) {
889 case CQE_CODE_COMPL_WQE:
890 rspiocbq = container_of(cq_event, struct lpfc_iocbq,
891 cq_event);
892 lpfc_sli_release_iocbq(phba, rspiocbq);
893 break;
894 case CQE_CODE_RECEIVE:
895 case CQE_CODE_RECEIVE_V1:
896 dmabuf = container_of(cq_event, struct hbq_dmabuf,
897 cq_event);
898 lpfc_in_buf_free(phba, &dmabuf->dbuf);
899 }
900 }
901}
902
903
904
905
906
907
908
909
910
911
912
913
914static void
915lpfc_hba_free_post_buf(struct lpfc_hba *phba)
916{
917 struct lpfc_sli *psli = &phba->sli;
918 struct lpfc_sli_ring *pring;
919 struct lpfc_dmabuf *mp, *next_mp;
920 LIST_HEAD(buflist);
921 int count;
922
923 if (phba->sli3_options & LPFC_SLI3_HBQ_ENABLED)
924 lpfc_sli_hbqbuf_free_all(phba);
925 else {
926
927 pring = &psli->sli3_ring[LPFC_ELS_RING];
928 spin_lock_irq(&phba->hbalock);
929 list_splice_init(&pring->postbufq, &buflist);
930 spin_unlock_irq(&phba->hbalock);
931
932 count = 0;
933 list_for_each_entry_safe(mp, next_mp, &buflist, list) {
934 list_del(&mp->list);
935 count++;
936 lpfc_mbuf_free(phba, mp->virt, mp->phys);
937 kfree(mp);
938 }
939
940 spin_lock_irq(&phba->hbalock);
941 pring->postbufq_cnt -= count;
942 spin_unlock_irq(&phba->hbalock);
943 }
944}
945
946
947
948
949
950
951
952
953
954
955
956static void
957lpfc_hba_clean_txcmplq(struct lpfc_hba *phba)
958{
959 struct lpfc_sli *psli = &phba->sli;
960 struct lpfc_queue *qp = NULL;
961 struct lpfc_sli_ring *pring;
962 LIST_HEAD(completions);
963 int i;
964 struct lpfc_iocbq *piocb, *next_iocb;
965
966 if (phba->sli_rev != LPFC_SLI_REV4) {
967 for (i = 0; i < psli->num_rings; i++) {
968 pring = &psli->sli3_ring[i];
969 spin_lock_irq(&phba->hbalock);
970
971
972
973
974 list_splice_init(&pring->txcmplq, &completions);
975 pring->txcmplq_cnt = 0;
976 spin_unlock_irq(&phba->hbalock);
977
978 lpfc_sli_abort_iocb_ring(phba, pring);
979 }
980
981 lpfc_sli_cancel_iocbs(phba, &completions,
982 IOSTAT_LOCAL_REJECT, IOERR_SLI_ABORTED);
983 return;
984 }
985 list_for_each_entry(qp, &phba->sli4_hba.lpfc_wq_list, wq_list) {
986 pring = qp->pring;
987 if (!pring)
988 continue;
989 spin_lock_irq(&pring->ring_lock);
990 list_for_each_entry_safe(piocb, next_iocb,
991 &pring->txcmplq, list)
992 piocb->iocb_flag &= ~LPFC_IO_ON_TXCMPLQ;
993 list_splice_init(&pring->txcmplq, &completions);
994 pring->txcmplq_cnt = 0;
995 spin_unlock_irq(&pring->ring_lock);
996 lpfc_sli_abort_iocb_ring(phba, pring);
997 }
998
999 lpfc_sli_cancel_iocbs(phba, &completions,
1000 IOSTAT_LOCAL_REJECT, IOERR_SLI_ABORTED);
1001}
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015static int
1016lpfc_hba_down_post_s3(struct lpfc_hba *phba)
1017{
1018 lpfc_hba_free_post_buf(phba);
1019 lpfc_hba_clean_txcmplq(phba);
1020 return 0;
1021}
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034static int
1035lpfc_hba_down_post_s4(struct lpfc_hba *phba)
1036{
1037 struct lpfc_io_buf *psb, *psb_next;
1038 struct lpfc_nvmet_rcv_ctx *ctxp, *ctxp_next;
1039 struct lpfc_sli4_hdw_queue *qp;
1040 LIST_HEAD(aborts);
1041 LIST_HEAD(nvme_aborts);
1042 LIST_HEAD(nvmet_aborts);
1043 struct lpfc_sglq *sglq_entry = NULL;
1044 int cnt, idx;
1045
1046
1047 lpfc_sli_hbqbuf_free_all(phba);
1048 lpfc_hba_clean_txcmplq(phba);
1049
1050
1051
1052
1053
1054
1055
1056 spin_lock_irq(&phba->hbalock);
1057
1058
1059
1060
1061 spin_lock(&phba->sli4_hba.sgl_list_lock);
1062 list_for_each_entry(sglq_entry,
1063 &phba->sli4_hba.lpfc_abts_els_sgl_list, list)
1064 sglq_entry->state = SGL_FREED;
1065
1066 list_splice_init(&phba->sli4_hba.lpfc_abts_els_sgl_list,
1067 &phba->sli4_hba.lpfc_els_sgl_list);
1068
1069
1070 spin_unlock(&phba->sli4_hba.sgl_list_lock);
1071
1072
1073
1074
1075 cnt = 0;
1076 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
1077 qp = &phba->sli4_hba.hdwq[idx];
1078
1079 spin_lock(&qp->abts_io_buf_list_lock);
1080 list_splice_init(&qp->lpfc_abts_io_buf_list,
1081 &aborts);
1082
1083 list_for_each_entry_safe(psb, psb_next, &aborts, list) {
1084 psb->pCmd = NULL;
1085 psb->status = IOSTAT_SUCCESS;
1086 cnt++;
1087 }
1088 spin_lock(&qp->io_buf_list_put_lock);
1089 list_splice_init(&aborts, &qp->lpfc_io_buf_list_put);
1090 qp->put_io_bufs += qp->abts_scsi_io_bufs;
1091 qp->put_io_bufs += qp->abts_nvme_io_bufs;
1092 qp->abts_scsi_io_bufs = 0;
1093 qp->abts_nvme_io_bufs = 0;
1094 spin_unlock(&qp->io_buf_list_put_lock);
1095 spin_unlock(&qp->abts_io_buf_list_lock);
1096 }
1097 spin_unlock_irq(&phba->hbalock);
1098
1099 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
1100 spin_lock_irq(&phba->sli4_hba.abts_nvmet_buf_list_lock);
1101 list_splice_init(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list,
1102 &nvmet_aborts);
1103 spin_unlock_irq(&phba->sli4_hba.abts_nvmet_buf_list_lock);
1104 list_for_each_entry_safe(ctxp, ctxp_next, &nvmet_aborts, list) {
1105 ctxp->flag &= ~(LPFC_NVMET_XBUSY | LPFC_NVMET_ABORT_OP);
1106 lpfc_nvmet_ctxbuf_post(phba, ctxp->ctxbuf);
1107 }
1108 }
1109
1110 lpfc_sli4_free_sp_events(phba);
1111 return cnt;
1112}
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125int
1126lpfc_hba_down_post(struct lpfc_hba *phba)
1127{
1128 return (*phba->lpfc_hba_down_post)(phba);
1129}
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143static void
1144lpfc_hb_timeout(struct timer_list *t)
1145{
1146 struct lpfc_hba *phba;
1147 uint32_t tmo_posted;
1148 unsigned long iflag;
1149
1150 phba = from_timer(phba, t, hb_tmofunc);
1151
1152
1153 spin_lock_irqsave(&phba->pport->work_port_lock, iflag);
1154 tmo_posted = phba->pport->work_port_events & WORKER_HB_TMO;
1155 if (!tmo_posted)
1156 phba->pport->work_port_events |= WORKER_HB_TMO;
1157 spin_unlock_irqrestore(&phba->pport->work_port_lock, iflag);
1158
1159
1160 if (!tmo_posted)
1161 lpfc_worker_wake_up(phba);
1162 return;
1163}
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177static void
1178lpfc_rrq_timeout(struct timer_list *t)
1179{
1180 struct lpfc_hba *phba;
1181 unsigned long iflag;
1182
1183 phba = from_timer(phba, t, rrq_tmr);
1184 spin_lock_irqsave(&phba->pport->work_port_lock, iflag);
1185 if (!(phba->pport->load_flag & FC_UNLOADING))
1186 phba->hba_flag |= HBA_RRQ_ACTIVE;
1187 else
1188 phba->hba_flag &= ~HBA_RRQ_ACTIVE;
1189 spin_unlock_irqrestore(&phba->pport->work_port_lock, iflag);
1190
1191 if (!(phba->pport->load_flag & FC_UNLOADING))
1192 lpfc_worker_wake_up(phba);
1193}
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211static void
1212lpfc_hb_mbox_cmpl(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq)
1213{
1214 unsigned long drvr_flag;
1215
1216 spin_lock_irqsave(&phba->hbalock, drvr_flag);
1217 phba->hb_outstanding = 0;
1218 spin_unlock_irqrestore(&phba->hbalock, drvr_flag);
1219
1220
1221 mempool_free(pmboxq, phba->mbox_mem_pool);
1222 if (!(phba->pport->fc_flag & FC_OFFLINE_MODE) &&
1223 !(phba->link_state == LPFC_HBA_ERROR) &&
1224 !(phba->pport->load_flag & FC_UNLOADING))
1225 mod_timer(&phba->hb_tmofunc,
1226 jiffies +
1227 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
1228 return;
1229}
1230
1231static void
1232lpfc_hb_eq_delay_work(struct work_struct *work)
1233{
1234 struct lpfc_hba *phba = container_of(to_delayed_work(work),
1235 struct lpfc_hba, eq_delay_work);
1236 struct lpfc_eq_intr_info *eqi, *eqi_new;
1237 struct lpfc_queue *eq, *eq_next;
1238 unsigned char *eqcnt = NULL;
1239 uint32_t usdelay;
1240 int i;
1241 bool update = false;
1242
1243 if (!phba->cfg_auto_imax || phba->pport->load_flag & FC_UNLOADING)
1244 return;
1245
1246 if (phba->link_state == LPFC_HBA_ERROR ||
1247 phba->pport->fc_flag & FC_OFFLINE_MODE)
1248 goto requeue;
1249
1250 eqcnt = kcalloc(num_possible_cpus(), sizeof(unsigned char),
1251 GFP_KERNEL);
1252 if (!eqcnt)
1253 goto requeue;
1254
1255 if (phba->cfg_irq_chann > 1) {
1256
1257 for (i = 0; i < phba->cfg_irq_chann; i++) {
1258
1259 eq = phba->sli4_hba.hba_eq_hdl[i].eq;
1260 if (!eq)
1261 continue;
1262 if (eq->q_mode) {
1263 update = true;
1264 break;
1265 }
1266 if (eqcnt[eq->last_cpu] < 2)
1267 eqcnt[eq->last_cpu]++;
1268 }
1269 } else
1270 update = true;
1271
1272 for_each_present_cpu(i) {
1273 eqi = per_cpu_ptr(phba->sli4_hba.eq_info, i);
1274 if (!update && eqcnt[i] < 2) {
1275 eqi->icnt = 0;
1276 continue;
1277 }
1278
1279 usdelay = (eqi->icnt / LPFC_IMAX_THRESHOLD) *
1280 LPFC_EQ_DELAY_STEP;
1281 if (usdelay > LPFC_MAX_AUTO_EQ_DELAY)
1282 usdelay = LPFC_MAX_AUTO_EQ_DELAY;
1283
1284 eqi->icnt = 0;
1285
1286 list_for_each_entry_safe(eq, eq_next, &eqi->list, cpu_list) {
1287 if (eq->last_cpu != i) {
1288 eqi_new = per_cpu_ptr(phba->sli4_hba.eq_info,
1289 eq->last_cpu);
1290 list_move_tail(&eq->cpu_list, &eqi_new->list);
1291 continue;
1292 }
1293 if (usdelay != eq->q_mode)
1294 lpfc_modify_hba_eq_delay(phba, eq->hdwq, 1,
1295 usdelay);
1296 }
1297 }
1298
1299 kfree(eqcnt);
1300
1301requeue:
1302 queue_delayed_work(phba->wq, &phba->eq_delay_work,
1303 msecs_to_jiffies(LPFC_EQ_DELAY_MSECS));
1304}
1305
1306
1307
1308
1309
1310
1311
1312
1313static void lpfc_hb_mxp_handler(struct lpfc_hba *phba)
1314{
1315 u32 i;
1316 u32 hwq_count;
1317
1318 hwq_count = phba->cfg_hdw_queue;
1319 for (i = 0; i < hwq_count; i++) {
1320
1321 lpfc_adjust_pvt_pool_count(phba, i);
1322
1323
1324 lpfc_adjust_high_watermark(phba, i);
1325
1326#ifdef LPFC_MXP_STAT
1327
1328 lpfc_snapshot_mxp(phba, i);
1329#endif
1330 }
1331}
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349void
1350lpfc_hb_timeout_handler(struct lpfc_hba *phba)
1351{
1352 struct lpfc_vport **vports;
1353 LPFC_MBOXQ_t *pmboxq;
1354 struct lpfc_dmabuf *buf_ptr;
1355 int retval, i;
1356 struct lpfc_sli *psli = &phba->sli;
1357 LIST_HEAD(completions);
1358
1359 if (phba->cfg_xri_rebalancing) {
1360
1361 lpfc_hb_mxp_handler(phba);
1362 }
1363
1364 vports = lpfc_create_vport_work_array(phba);
1365 if (vports != NULL)
1366 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
1367 lpfc_rcv_seq_check_edtov(vports[i]);
1368 lpfc_fdmi_num_disc_check(vports[i]);
1369 }
1370 lpfc_destroy_vport_work_array(phba, vports);
1371
1372 if ((phba->link_state == LPFC_HBA_ERROR) ||
1373 (phba->pport->load_flag & FC_UNLOADING) ||
1374 (phba->pport->fc_flag & FC_OFFLINE_MODE))
1375 return;
1376
1377 spin_lock_irq(&phba->pport->work_port_lock);
1378
1379 if (time_after(phba->last_completion_time +
1380 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL),
1381 jiffies)) {
1382 spin_unlock_irq(&phba->pport->work_port_lock);
1383 if (!phba->hb_outstanding)
1384 mod_timer(&phba->hb_tmofunc,
1385 jiffies +
1386 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
1387 else
1388 mod_timer(&phba->hb_tmofunc,
1389 jiffies +
1390 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
1391 return;
1392 }
1393 spin_unlock_irq(&phba->pport->work_port_lock);
1394
1395 if (phba->elsbuf_cnt &&
1396 (phba->elsbuf_cnt == phba->elsbuf_prev_cnt)) {
1397 spin_lock_irq(&phba->hbalock);
1398 list_splice_init(&phba->elsbuf, &completions);
1399 phba->elsbuf_cnt = 0;
1400 phba->elsbuf_prev_cnt = 0;
1401 spin_unlock_irq(&phba->hbalock);
1402
1403 while (!list_empty(&completions)) {
1404 list_remove_head(&completions, buf_ptr,
1405 struct lpfc_dmabuf, list);
1406 lpfc_mbuf_free(phba, buf_ptr->virt, buf_ptr->phys);
1407 kfree(buf_ptr);
1408 }
1409 }
1410 phba->elsbuf_prev_cnt = phba->elsbuf_cnt;
1411
1412
1413 if (phba->cfg_enable_hba_heartbeat) {
1414 if (!phba->hb_outstanding) {
1415 if ((!(psli->sli_flag & LPFC_SLI_MBOX_ACTIVE)) &&
1416 (list_empty(&psli->mboxq))) {
1417 pmboxq = mempool_alloc(phba->mbox_mem_pool,
1418 GFP_KERNEL);
1419 if (!pmboxq) {
1420 mod_timer(&phba->hb_tmofunc,
1421 jiffies +
1422 msecs_to_jiffies(1000 *
1423 LPFC_HB_MBOX_INTERVAL));
1424 return;
1425 }
1426
1427 lpfc_heart_beat(phba, pmboxq);
1428 pmboxq->mbox_cmpl = lpfc_hb_mbox_cmpl;
1429 pmboxq->vport = phba->pport;
1430 retval = lpfc_sli_issue_mbox(phba, pmboxq,
1431 MBX_NOWAIT);
1432
1433 if (retval != MBX_BUSY &&
1434 retval != MBX_SUCCESS) {
1435 mempool_free(pmboxq,
1436 phba->mbox_mem_pool);
1437 mod_timer(&phba->hb_tmofunc,
1438 jiffies +
1439 msecs_to_jiffies(1000 *
1440 LPFC_HB_MBOX_INTERVAL));
1441 return;
1442 }
1443 phba->skipped_hb = 0;
1444 phba->hb_outstanding = 1;
1445 } else if (time_before_eq(phba->last_completion_time,
1446 phba->skipped_hb)) {
1447 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
1448 "2857 Last completion time not "
1449 " updated in %d ms\n",
1450 jiffies_to_msecs(jiffies
1451 - phba->last_completion_time));
1452 } else
1453 phba->skipped_hb = jiffies;
1454
1455 mod_timer(&phba->hb_tmofunc,
1456 jiffies +
1457 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
1458 return;
1459 } else {
1460
1461
1462
1463
1464
1465 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
1466 "0459 Adapter heartbeat still out"
1467 "standing:last compl time was %d ms.\n",
1468 jiffies_to_msecs(jiffies
1469 - phba->last_completion_time));
1470 mod_timer(&phba->hb_tmofunc,
1471 jiffies +
1472 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
1473 }
1474 } else {
1475 mod_timer(&phba->hb_tmofunc,
1476 jiffies +
1477 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
1478 }
1479}
1480
1481
1482
1483
1484
1485
1486
1487
1488static void
1489lpfc_offline_eratt(struct lpfc_hba *phba)
1490{
1491 struct lpfc_sli *psli = &phba->sli;
1492
1493 spin_lock_irq(&phba->hbalock);
1494 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
1495 spin_unlock_irq(&phba->hbalock);
1496 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
1497
1498 lpfc_offline(phba);
1499 lpfc_reset_barrier(phba);
1500 spin_lock_irq(&phba->hbalock);
1501 lpfc_sli_brdreset(phba);
1502 spin_unlock_irq(&phba->hbalock);
1503 lpfc_hba_down_post(phba);
1504 lpfc_sli_brdready(phba, HS_MBRDY);
1505 lpfc_unblock_mgmt_io(phba);
1506 phba->link_state = LPFC_HBA_ERROR;
1507 return;
1508}
1509
1510
1511
1512
1513
1514
1515
1516
1517void
1518lpfc_sli4_offline_eratt(struct lpfc_hba *phba)
1519{
1520 spin_lock_irq(&phba->hbalock);
1521 phba->link_state = LPFC_HBA_ERROR;
1522 spin_unlock_irq(&phba->hbalock);
1523
1524 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
1525 lpfc_sli_flush_io_rings(phba);
1526 lpfc_offline(phba);
1527 lpfc_hba_down_post(phba);
1528 lpfc_unblock_mgmt_io(phba);
1529}
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540static void
1541lpfc_handle_deferred_eratt(struct lpfc_hba *phba)
1542{
1543 uint32_t old_host_status = phba->work_hs;
1544 struct lpfc_sli *psli = &phba->sli;
1545
1546
1547
1548
1549 if (pci_channel_offline(phba->pcidev)) {
1550 spin_lock_irq(&phba->hbalock);
1551 phba->hba_flag &= ~DEFER_ERATT;
1552 spin_unlock_irq(&phba->hbalock);
1553 return;
1554 }
1555
1556 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1557 "0479 Deferred Adapter Hardware Error "
1558 "Data: x%x x%x x%x\n",
1559 phba->work_hs,
1560 phba->work_status[0], phba->work_status[1]);
1561
1562 spin_lock_irq(&phba->hbalock);
1563 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
1564 spin_unlock_irq(&phba->hbalock);
1565
1566
1567
1568
1569
1570
1571
1572 lpfc_sli_abort_fcp_rings(phba);
1573
1574
1575
1576
1577
1578 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
1579 lpfc_offline(phba);
1580
1581
1582 while (phba->work_hs & HS_FFER1) {
1583 msleep(100);
1584 if (lpfc_readl(phba->HSregaddr, &phba->work_hs)) {
1585 phba->work_hs = UNPLUG_ERR ;
1586 break;
1587 }
1588
1589 if (phba->pport->load_flag & FC_UNLOADING) {
1590 phba->work_hs = 0;
1591 break;
1592 }
1593 }
1594
1595
1596
1597
1598
1599
1600 if ((!phba->work_hs) && (!(phba->pport->load_flag & FC_UNLOADING)))
1601 phba->work_hs = old_host_status & ~HS_FFER1;
1602
1603 spin_lock_irq(&phba->hbalock);
1604 phba->hba_flag &= ~DEFER_ERATT;
1605 spin_unlock_irq(&phba->hbalock);
1606 phba->work_status[0] = readl(phba->MBslimaddr + 0xa8);
1607 phba->work_status[1] = readl(phba->MBslimaddr + 0xac);
1608}
1609
1610static void
1611lpfc_board_errevt_to_mgmt(struct lpfc_hba *phba)
1612{
1613 struct lpfc_board_event_header board_event;
1614 struct Scsi_Host *shost;
1615
1616 board_event.event_type = FC_REG_BOARD_EVENT;
1617 board_event.subcategory = LPFC_EVENT_PORTINTERR;
1618 shost = lpfc_shost_from_vport(phba->pport);
1619 fc_host_post_vendor_event(shost, fc_get_event_number(),
1620 sizeof(board_event),
1621 (char *) &board_event,
1622 LPFC_NL_VENDOR_ID);
1623}
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635static void
1636lpfc_handle_eratt_s3(struct lpfc_hba *phba)
1637{
1638 struct lpfc_vport *vport = phba->pport;
1639 struct lpfc_sli *psli = &phba->sli;
1640 uint32_t event_data;
1641 unsigned long temperature;
1642 struct temp_event temp_event_data;
1643 struct Scsi_Host *shost;
1644
1645
1646
1647
1648 if (pci_channel_offline(phba->pcidev)) {
1649 spin_lock_irq(&phba->hbalock);
1650 phba->hba_flag &= ~DEFER_ERATT;
1651 spin_unlock_irq(&phba->hbalock);
1652 return;
1653 }
1654
1655
1656 if (!phba->cfg_enable_hba_reset)
1657 return;
1658
1659
1660 lpfc_board_errevt_to_mgmt(phba);
1661
1662 if (phba->hba_flag & DEFER_ERATT)
1663 lpfc_handle_deferred_eratt(phba);
1664
1665 if ((phba->work_hs & HS_FFER6) || (phba->work_hs & HS_FFER8)) {
1666 if (phba->work_hs & HS_FFER6)
1667
1668 lpfc_printf_log(phba, KERN_INFO, LOG_LINK_EVENT,
1669 "1301 Re-establishing Link "
1670 "Data: x%x x%x x%x\n",
1671 phba->work_hs, phba->work_status[0],
1672 phba->work_status[1]);
1673 if (phba->work_hs & HS_FFER8)
1674
1675 lpfc_printf_log(phba, KERN_INFO, LOG_LINK_EVENT,
1676 "2861 Host Authentication device "
1677 "zeroization Data:x%x x%x x%x\n",
1678 phba->work_hs, phba->work_status[0],
1679 phba->work_status[1]);
1680
1681 spin_lock_irq(&phba->hbalock);
1682 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
1683 spin_unlock_irq(&phba->hbalock);
1684
1685
1686
1687
1688
1689
1690
1691 lpfc_sli_abort_fcp_rings(phba);
1692
1693
1694
1695
1696
1697 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
1698 lpfc_offline(phba);
1699 lpfc_sli_brdrestart(phba);
1700 if (lpfc_online(phba) == 0) {
1701 lpfc_unblock_mgmt_io(phba);
1702 return;
1703 }
1704 lpfc_unblock_mgmt_io(phba);
1705 } else if (phba->work_hs & HS_CRIT_TEMP) {
1706 temperature = readl(phba->MBslimaddr + TEMPERATURE_OFFSET);
1707 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
1708 temp_event_data.event_code = LPFC_CRIT_TEMP;
1709 temp_event_data.data = (uint32_t)temperature;
1710
1711 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1712 "0406 Adapter maximum temperature exceeded "
1713 "(%ld), taking this port offline "
1714 "Data: x%x x%x x%x\n",
1715 temperature, phba->work_hs,
1716 phba->work_status[0], phba->work_status[1]);
1717
1718 shost = lpfc_shost_from_vport(phba->pport);
1719 fc_host_post_vendor_event(shost, fc_get_event_number(),
1720 sizeof(temp_event_data),
1721 (char *) &temp_event_data,
1722 SCSI_NL_VID_TYPE_PCI
1723 | PCI_VENDOR_ID_EMULEX);
1724
1725 spin_lock_irq(&phba->hbalock);
1726 phba->over_temp_state = HBA_OVER_TEMP;
1727 spin_unlock_irq(&phba->hbalock);
1728 lpfc_offline_eratt(phba);
1729
1730 } else {
1731
1732
1733
1734
1735 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1736 "0457 Adapter Hardware Error "
1737 "Data: x%x x%x x%x\n",
1738 phba->work_hs,
1739 phba->work_status[0], phba->work_status[1]);
1740
1741 event_data = FC_REG_DUMP_EVENT;
1742 shost = lpfc_shost_from_vport(vport);
1743 fc_host_post_vendor_event(shost, fc_get_event_number(),
1744 sizeof(event_data), (char *) &event_data,
1745 SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX);
1746
1747 lpfc_offline_eratt(phba);
1748 }
1749 return;
1750}
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763static int
1764lpfc_sli4_port_sta_fn_reset(struct lpfc_hba *phba, int mbx_action,
1765 bool en_rn_msg)
1766{
1767 int rc;
1768 uint32_t intr_mode;
1769
1770 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) >=
1771 LPFC_SLI_INTF_IF_TYPE_2) {
1772
1773
1774
1775
1776 rc = lpfc_sli4_pdev_status_reg_wait(phba);
1777 if (rc)
1778 return rc;
1779 }
1780
1781
1782 if (en_rn_msg)
1783 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1784 "2887 Reset Needed: Attempting Port "
1785 "Recovery...\n");
1786 lpfc_offline_prep(phba, mbx_action);
1787 lpfc_sli_flush_io_rings(phba);
1788 lpfc_offline(phba);
1789
1790 lpfc_sli4_disable_intr(phba);
1791 rc = lpfc_sli_brdrestart(phba);
1792 if (rc) {
1793 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1794 "6309 Failed to restart board\n");
1795 return rc;
1796 }
1797
1798 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
1799 if (intr_mode == LPFC_INTR_ERROR) {
1800 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1801 "3175 Failed to enable interrupt\n");
1802 return -EIO;
1803 }
1804 phba->intr_mode = intr_mode;
1805 rc = lpfc_online(phba);
1806 if (rc == 0)
1807 lpfc_unblock_mgmt_io(phba);
1808
1809 return rc;
1810}
1811
1812
1813
1814
1815
1816
1817
1818
1819static void
1820lpfc_handle_eratt_s4(struct lpfc_hba *phba)
1821{
1822 struct lpfc_vport *vport = phba->pport;
1823 uint32_t event_data;
1824 struct Scsi_Host *shost;
1825 uint32_t if_type;
1826 struct lpfc_register portstat_reg = {0};
1827 uint32_t reg_err1, reg_err2;
1828 uint32_t uerrlo_reg, uemasklo_reg;
1829 uint32_t smphr_port_status = 0, pci_rd_rc1, pci_rd_rc2;
1830 bool en_rn_msg = true;
1831 struct temp_event temp_event_data;
1832 struct lpfc_register portsmphr_reg;
1833 int rc, i;
1834
1835
1836
1837
1838 if (pci_channel_offline(phba->pcidev)) {
1839 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1840 "3166 pci channel is offline\n");
1841 lpfc_sli4_offline_eratt(phba);
1842 return;
1843 }
1844
1845 memset(&portsmphr_reg, 0, sizeof(portsmphr_reg));
1846 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
1847 switch (if_type) {
1848 case LPFC_SLI_INTF_IF_TYPE_0:
1849 pci_rd_rc1 = lpfc_readl(
1850 phba->sli4_hba.u.if_type0.UERRLOregaddr,
1851 &uerrlo_reg);
1852 pci_rd_rc2 = lpfc_readl(
1853 phba->sli4_hba.u.if_type0.UEMASKLOregaddr,
1854 &uemasklo_reg);
1855
1856 if (pci_rd_rc1 == -EIO && pci_rd_rc2 == -EIO)
1857 return;
1858 if (!(phba->hba_flag & HBA_RECOVERABLE_UE)) {
1859 lpfc_sli4_offline_eratt(phba);
1860 return;
1861 }
1862 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1863 "7623 Checking UE recoverable");
1864
1865 for (i = 0; i < phba->sli4_hba.ue_to_sr / 1000; i++) {
1866 if (lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
1867 &portsmphr_reg.word0))
1868 continue;
1869
1870 smphr_port_status = bf_get(lpfc_port_smphr_port_status,
1871 &portsmphr_reg);
1872 if ((smphr_port_status & LPFC_PORT_SEM_MASK) ==
1873 LPFC_PORT_SEM_UE_RECOVERABLE)
1874 break;
1875
1876 msleep(1000);
1877 }
1878
1879 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1880 "4827 smphr_port_status x%x : Waited %dSec",
1881 smphr_port_status, i);
1882
1883
1884 if ((smphr_port_status & LPFC_PORT_SEM_MASK) ==
1885 LPFC_PORT_SEM_UE_RECOVERABLE) {
1886 for (i = 0; i < 20; i++) {
1887 msleep(1000);
1888 if (!lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
1889 &portsmphr_reg.word0) &&
1890 (LPFC_POST_STAGE_PORT_READY ==
1891 bf_get(lpfc_port_smphr_port_status,
1892 &portsmphr_reg))) {
1893 rc = lpfc_sli4_port_sta_fn_reset(phba,
1894 LPFC_MBX_NO_WAIT, en_rn_msg);
1895 if (rc == 0)
1896 return;
1897 lpfc_printf_log(phba,
1898 KERN_ERR, LOG_INIT,
1899 "4215 Failed to recover UE");
1900 break;
1901 }
1902 }
1903 }
1904 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1905 "7624 Firmware not ready: Failing UE recovery,"
1906 " waited %dSec", i);
1907 phba->link_state = LPFC_HBA_ERROR;
1908 break;
1909
1910 case LPFC_SLI_INTF_IF_TYPE_2:
1911 case LPFC_SLI_INTF_IF_TYPE_6:
1912 pci_rd_rc1 = lpfc_readl(
1913 phba->sli4_hba.u.if_type2.STATUSregaddr,
1914 &portstat_reg.word0);
1915
1916 if (pci_rd_rc1 == -EIO) {
1917 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1918 "3151 PCI bus read access failure: x%x\n",
1919 readl(phba->sli4_hba.u.if_type2.STATUSregaddr));
1920 lpfc_sli4_offline_eratt(phba);
1921 return;
1922 }
1923 reg_err1 = readl(phba->sli4_hba.u.if_type2.ERR1regaddr);
1924 reg_err2 = readl(phba->sli4_hba.u.if_type2.ERR2regaddr);
1925 if (bf_get(lpfc_sliport_status_oti, &portstat_reg)) {
1926 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1927 "2889 Port Overtemperature event, "
1928 "taking port offline Data: x%x x%x\n",
1929 reg_err1, reg_err2);
1930
1931 phba->sfp_alarm |= LPFC_TRANSGRESSION_HIGH_TEMPERATURE;
1932 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
1933 temp_event_data.event_code = LPFC_CRIT_TEMP;
1934 temp_event_data.data = 0xFFFFFFFF;
1935
1936 shost = lpfc_shost_from_vport(phba->pport);
1937 fc_host_post_vendor_event(shost, fc_get_event_number(),
1938 sizeof(temp_event_data),
1939 (char *)&temp_event_data,
1940 SCSI_NL_VID_TYPE_PCI
1941 | PCI_VENDOR_ID_EMULEX);
1942
1943 spin_lock_irq(&phba->hbalock);
1944 phba->over_temp_state = HBA_OVER_TEMP;
1945 spin_unlock_irq(&phba->hbalock);
1946 lpfc_sli4_offline_eratt(phba);
1947 return;
1948 }
1949 if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
1950 reg_err2 == SLIPORT_ERR2_REG_FW_RESTART) {
1951 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1952 "3143 Port Down: Firmware Update "
1953 "Detected\n");
1954 en_rn_msg = false;
1955 } else if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
1956 reg_err2 == SLIPORT_ERR2_REG_FORCED_DUMP)
1957 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1958 "3144 Port Down: Debug Dump\n");
1959 else if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
1960 reg_err2 == SLIPORT_ERR2_REG_FUNC_PROVISON)
1961 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1962 "3145 Port Down: Provisioning\n");
1963
1964
1965 if (!phba->cfg_enable_hba_reset)
1966 return;
1967
1968
1969 rc = lpfc_sli4_port_sta_fn_reset(phba, LPFC_MBX_NO_WAIT,
1970 en_rn_msg);
1971 if (rc == 0) {
1972
1973 if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
1974 reg_err2 == SLIPORT_ERR2_REG_FORCED_DUMP)
1975 return;
1976 else
1977 break;
1978 }
1979
1980 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1981 "3152 Unrecoverable error\n");
1982 phba->link_state = LPFC_HBA_ERROR;
1983 break;
1984 case LPFC_SLI_INTF_IF_TYPE_1:
1985 default:
1986 break;
1987 }
1988 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
1989 "3123 Report dump event to upper layer\n");
1990
1991 lpfc_board_errevt_to_mgmt(phba);
1992
1993 event_data = FC_REG_DUMP_EVENT;
1994 shost = lpfc_shost_from_vport(vport);
1995 fc_host_post_vendor_event(shost, fc_get_event_number(),
1996 sizeof(event_data), (char *) &event_data,
1997 SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX);
1998}
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011void
2012lpfc_handle_eratt(struct lpfc_hba *phba)
2013{
2014 (*phba->lpfc_handle_eratt)(phba);
2015}
2016
2017
2018
2019
2020
2021
2022
2023
2024void
2025lpfc_handle_latt(struct lpfc_hba *phba)
2026{
2027 struct lpfc_vport *vport = phba->pport;
2028 struct lpfc_sli *psli = &phba->sli;
2029 LPFC_MBOXQ_t *pmb;
2030 volatile uint32_t control;
2031 struct lpfc_dmabuf *mp;
2032 int rc = 0;
2033
2034 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
2035 if (!pmb) {
2036 rc = 1;
2037 goto lpfc_handle_latt_err_exit;
2038 }
2039
2040 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
2041 if (!mp) {
2042 rc = 2;
2043 goto lpfc_handle_latt_free_pmb;
2044 }
2045
2046 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
2047 if (!mp->virt) {
2048 rc = 3;
2049 goto lpfc_handle_latt_free_mp;
2050 }
2051
2052
2053 lpfc_els_flush_all_cmd(phba);
2054
2055 psli->slistat.link_event++;
2056 lpfc_read_topology(phba, pmb, mp);
2057 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
2058 pmb->vport = vport;
2059
2060 phba->sli.sli3_ring[LPFC_ELS_RING].flag |= LPFC_STOP_IOCB_EVENT;
2061 rc = lpfc_sli_issue_mbox (phba, pmb, MBX_NOWAIT);
2062 if (rc == MBX_NOT_FINISHED) {
2063 rc = 4;
2064 goto lpfc_handle_latt_free_mbuf;
2065 }
2066
2067
2068 spin_lock_irq(&phba->hbalock);
2069 writel(HA_LATT, phba->HAregaddr);
2070 readl(phba->HAregaddr);
2071 spin_unlock_irq(&phba->hbalock);
2072
2073 return;
2074
2075lpfc_handle_latt_free_mbuf:
2076 phba->sli.sli3_ring[LPFC_ELS_RING].flag &= ~LPFC_STOP_IOCB_EVENT;
2077 lpfc_mbuf_free(phba, mp->virt, mp->phys);
2078lpfc_handle_latt_free_mp:
2079 kfree(mp);
2080lpfc_handle_latt_free_pmb:
2081 mempool_free(pmb, phba->mbox_mem_pool);
2082lpfc_handle_latt_err_exit:
2083
2084 spin_lock_irq(&phba->hbalock);
2085 psli->sli_flag |= LPFC_PROCESS_LA;
2086 control = readl(phba->HCregaddr);
2087 control |= HC_LAINT_ENA;
2088 writel(control, phba->HCregaddr);
2089 readl(phba->HCregaddr);
2090
2091
2092 writel(HA_LATT, phba->HAregaddr);
2093 readl(phba->HAregaddr);
2094 spin_unlock_irq(&phba->hbalock);
2095 lpfc_linkdown(phba);
2096 phba->link_state = LPFC_HBA_ERROR;
2097
2098 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX,
2099 "0300 LATT: Cannot issue READ_LA: Data:%d\n", rc);
2100
2101 return;
2102}
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118int
2119lpfc_parse_vpd(struct lpfc_hba *phba, uint8_t *vpd, int len)
2120{
2121 uint8_t lenlo, lenhi;
2122 int Length;
2123 int i, j;
2124 int finished = 0;
2125 int index = 0;
2126
2127 if (!vpd)
2128 return 0;
2129
2130
2131 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
2132 "0455 Vital Product Data: x%x x%x x%x x%x\n",
2133 (uint32_t) vpd[0], (uint32_t) vpd[1], (uint32_t) vpd[2],
2134 (uint32_t) vpd[3]);
2135 while (!finished && (index < (len - 4))) {
2136 switch (vpd[index]) {
2137 case 0x82:
2138 case 0x91:
2139 index += 1;
2140 lenlo = vpd[index];
2141 index += 1;
2142 lenhi = vpd[index];
2143 index += 1;
2144 i = ((((unsigned short)lenhi) << 8) + lenlo);
2145 index += i;
2146 break;
2147 case 0x90:
2148 index += 1;
2149 lenlo = vpd[index];
2150 index += 1;
2151 lenhi = vpd[index];
2152 index += 1;
2153 Length = ((((unsigned short)lenhi) << 8) + lenlo);
2154 if (Length > len - index)
2155 Length = len - index;
2156 while (Length > 0) {
2157
2158 if ((vpd[index] == 'S') && (vpd[index+1] == 'N')) {
2159 index += 2;
2160 i = vpd[index];
2161 index += 1;
2162 j = 0;
2163 Length -= (3+i);
2164 while(i--) {
2165 phba->SerialNumber[j++] = vpd[index++];
2166 if (j == 31)
2167 break;
2168 }
2169 phba->SerialNumber[j] = 0;
2170 continue;
2171 }
2172 else if ((vpd[index] == 'V') && (vpd[index+1] == '1')) {
2173 phba->vpd_flag |= VPD_MODEL_DESC;
2174 index += 2;
2175 i = vpd[index];
2176 index += 1;
2177 j = 0;
2178 Length -= (3+i);
2179 while(i--) {
2180 phba->ModelDesc[j++] = vpd[index++];
2181 if (j == 255)
2182 break;
2183 }
2184 phba->ModelDesc[j] = 0;
2185 continue;
2186 }
2187 else if ((vpd[index] == 'V') && (vpd[index+1] == '2')) {
2188 phba->vpd_flag |= VPD_MODEL_NAME;
2189 index += 2;
2190 i = vpd[index];
2191 index += 1;
2192 j = 0;
2193 Length -= (3+i);
2194 while(i--) {
2195 phba->ModelName[j++] = vpd[index++];
2196 if (j == 79)
2197 break;
2198 }
2199 phba->ModelName[j] = 0;
2200 continue;
2201 }
2202 else if ((vpd[index] == 'V') && (vpd[index+1] == '3')) {
2203 phba->vpd_flag |= VPD_PROGRAM_TYPE;
2204 index += 2;
2205 i = vpd[index];
2206 index += 1;
2207 j = 0;
2208 Length -= (3+i);
2209 while(i--) {
2210 phba->ProgramType[j++] = vpd[index++];
2211 if (j == 255)
2212 break;
2213 }
2214 phba->ProgramType[j] = 0;
2215 continue;
2216 }
2217 else if ((vpd[index] == 'V') && (vpd[index+1] == '4')) {
2218 phba->vpd_flag |= VPD_PORT;
2219 index += 2;
2220 i = vpd[index];
2221 index += 1;
2222 j = 0;
2223 Length -= (3+i);
2224 while(i--) {
2225 if ((phba->sli_rev == LPFC_SLI_REV4) &&
2226 (phba->sli4_hba.pport_name_sta ==
2227 LPFC_SLI4_PPNAME_GET)) {
2228 j++;
2229 index++;
2230 } else
2231 phba->Port[j++] = vpd[index++];
2232 if (j == 19)
2233 break;
2234 }
2235 if ((phba->sli_rev != LPFC_SLI_REV4) ||
2236 (phba->sli4_hba.pport_name_sta ==
2237 LPFC_SLI4_PPNAME_NON))
2238 phba->Port[j] = 0;
2239 continue;
2240 }
2241 else {
2242 index += 2;
2243 i = vpd[index];
2244 index += 1;
2245 index += i;
2246 Length -= (3 + i);
2247 }
2248 }
2249 finished = 0;
2250 break;
2251 case 0x78:
2252 finished = 1;
2253 break;
2254 default:
2255 index ++;
2256 break;
2257 }
2258 }
2259
2260 return(1);
2261}
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275static void
2276lpfc_get_hba_model_desc(struct lpfc_hba *phba, uint8_t *mdp, uint8_t *descp)
2277{
2278 lpfc_vpd_t *vp;
2279 uint16_t dev_id = phba->pcidev->device;
2280 int max_speed;
2281 int GE = 0;
2282 int oneConnect = 0;
2283 struct {
2284 char *name;
2285 char *bus;
2286 char *function;
2287 } m = {"<Unknown>", "", ""};
2288
2289 if (mdp && mdp[0] != '\0'
2290 && descp && descp[0] != '\0')
2291 return;
2292
2293 if (phba->lmt & LMT_64Gb)
2294 max_speed = 64;
2295 else if (phba->lmt & LMT_32Gb)
2296 max_speed = 32;
2297 else if (phba->lmt & LMT_16Gb)
2298 max_speed = 16;
2299 else if (phba->lmt & LMT_10Gb)
2300 max_speed = 10;
2301 else if (phba->lmt & LMT_8Gb)
2302 max_speed = 8;
2303 else if (phba->lmt & LMT_4Gb)
2304 max_speed = 4;
2305 else if (phba->lmt & LMT_2Gb)
2306 max_speed = 2;
2307 else if (phba->lmt & LMT_1Gb)
2308 max_speed = 1;
2309 else
2310 max_speed = 0;
2311
2312 vp = &phba->vpd;
2313
2314 switch (dev_id) {
2315 case PCI_DEVICE_ID_FIREFLY:
2316 m = (typeof(m)){"LP6000", "PCI",
2317 "Obsolete, Unsupported Fibre Channel Adapter"};
2318 break;
2319 case PCI_DEVICE_ID_SUPERFLY:
2320 if (vp->rev.biuRev >= 1 && vp->rev.biuRev <= 3)
2321 m = (typeof(m)){"LP7000", "PCI", ""};
2322 else
2323 m = (typeof(m)){"LP7000E", "PCI", ""};
2324 m.function = "Obsolete, Unsupported Fibre Channel Adapter";
2325 break;
2326 case PCI_DEVICE_ID_DRAGONFLY:
2327 m = (typeof(m)){"LP8000", "PCI",
2328 "Obsolete, Unsupported Fibre Channel Adapter"};
2329 break;
2330 case PCI_DEVICE_ID_CENTAUR:
2331 if (FC_JEDEC_ID(vp->rev.biuRev) == CENTAUR_2G_JEDEC_ID)
2332 m = (typeof(m)){"LP9002", "PCI", ""};
2333 else
2334 m = (typeof(m)){"LP9000", "PCI", ""};
2335 m.function = "Obsolete, Unsupported Fibre Channel Adapter";
2336 break;
2337 case PCI_DEVICE_ID_RFLY:
2338 m = (typeof(m)){"LP952", "PCI",
2339 "Obsolete, Unsupported Fibre Channel Adapter"};
2340 break;
2341 case PCI_DEVICE_ID_PEGASUS:
2342 m = (typeof(m)){"LP9802", "PCI-X",
2343 "Obsolete, Unsupported Fibre Channel Adapter"};
2344 break;
2345 case PCI_DEVICE_ID_THOR:
2346 m = (typeof(m)){"LP10000", "PCI-X",
2347 "Obsolete, Unsupported Fibre Channel Adapter"};
2348 break;
2349 case PCI_DEVICE_ID_VIPER:
2350 m = (typeof(m)){"LPX1000", "PCI-X",
2351 "Obsolete, Unsupported Fibre Channel Adapter"};
2352 break;
2353 case PCI_DEVICE_ID_PFLY:
2354 m = (typeof(m)){"LP982", "PCI-X",
2355 "Obsolete, Unsupported Fibre Channel Adapter"};
2356 break;
2357 case PCI_DEVICE_ID_TFLY:
2358 m = (typeof(m)){"LP1050", "PCI-X",
2359 "Obsolete, Unsupported Fibre Channel Adapter"};
2360 break;
2361 case PCI_DEVICE_ID_HELIOS:
2362 m = (typeof(m)){"LP11000", "PCI-X2",
2363 "Obsolete, Unsupported Fibre Channel Adapter"};
2364 break;
2365 case PCI_DEVICE_ID_HELIOS_SCSP:
2366 m = (typeof(m)){"LP11000-SP", "PCI-X2",
2367 "Obsolete, Unsupported Fibre Channel Adapter"};
2368 break;
2369 case PCI_DEVICE_ID_HELIOS_DCSP:
2370 m = (typeof(m)){"LP11002-SP", "PCI-X2",
2371 "Obsolete, Unsupported Fibre Channel Adapter"};
2372 break;
2373 case PCI_DEVICE_ID_NEPTUNE:
2374 m = (typeof(m)){"LPe1000", "PCIe",
2375 "Obsolete, Unsupported Fibre Channel Adapter"};
2376 break;
2377 case PCI_DEVICE_ID_NEPTUNE_SCSP:
2378 m = (typeof(m)){"LPe1000-SP", "PCIe",
2379 "Obsolete, Unsupported Fibre Channel Adapter"};
2380 break;
2381 case PCI_DEVICE_ID_NEPTUNE_DCSP:
2382 m = (typeof(m)){"LPe1002-SP", "PCIe",
2383 "Obsolete, Unsupported Fibre Channel Adapter"};
2384 break;
2385 case PCI_DEVICE_ID_BMID:
2386 m = (typeof(m)){"LP1150", "PCI-X2", "Fibre Channel Adapter"};
2387 break;
2388 case PCI_DEVICE_ID_BSMB:
2389 m = (typeof(m)){"LP111", "PCI-X2",
2390 "Obsolete, Unsupported Fibre Channel Adapter"};
2391 break;
2392 case PCI_DEVICE_ID_ZEPHYR:
2393 m = (typeof(m)){"LPe11000", "PCIe", "Fibre Channel Adapter"};
2394 break;
2395 case PCI_DEVICE_ID_ZEPHYR_SCSP:
2396 m = (typeof(m)){"LPe11000", "PCIe", "Fibre Channel Adapter"};
2397 break;
2398 case PCI_DEVICE_ID_ZEPHYR_DCSP:
2399 m = (typeof(m)){"LP2105", "PCIe", "FCoE Adapter"};
2400 GE = 1;
2401 break;
2402 case PCI_DEVICE_ID_ZMID:
2403 m = (typeof(m)){"LPe1150", "PCIe", "Fibre Channel Adapter"};
2404 break;
2405 case PCI_DEVICE_ID_ZSMB:
2406 m = (typeof(m)){"LPe111", "PCIe", "Fibre Channel Adapter"};
2407 break;
2408 case PCI_DEVICE_ID_LP101:
2409 m = (typeof(m)){"LP101", "PCI-X",
2410 "Obsolete, Unsupported Fibre Channel Adapter"};
2411 break;
2412 case PCI_DEVICE_ID_LP10000S:
2413 m = (typeof(m)){"LP10000-S", "PCI",
2414 "Obsolete, Unsupported Fibre Channel Adapter"};
2415 break;
2416 case PCI_DEVICE_ID_LP11000S:
2417 m = (typeof(m)){"LP11000-S", "PCI-X2",
2418 "Obsolete, Unsupported Fibre Channel Adapter"};
2419 break;
2420 case PCI_DEVICE_ID_LPE11000S:
2421 m = (typeof(m)){"LPe11000-S", "PCIe",
2422 "Obsolete, Unsupported Fibre Channel Adapter"};
2423 break;
2424 case PCI_DEVICE_ID_SAT:
2425 m = (typeof(m)){"LPe12000", "PCIe", "Fibre Channel Adapter"};
2426 break;
2427 case PCI_DEVICE_ID_SAT_MID:
2428 m = (typeof(m)){"LPe1250", "PCIe", "Fibre Channel Adapter"};
2429 break;
2430 case PCI_DEVICE_ID_SAT_SMB:
2431 m = (typeof(m)){"LPe121", "PCIe", "Fibre Channel Adapter"};
2432 break;
2433 case PCI_DEVICE_ID_SAT_DCSP:
2434 m = (typeof(m)){"LPe12002-SP", "PCIe", "Fibre Channel Adapter"};
2435 break;
2436 case PCI_DEVICE_ID_SAT_SCSP:
2437 m = (typeof(m)){"LPe12000-SP", "PCIe", "Fibre Channel Adapter"};
2438 break;
2439 case PCI_DEVICE_ID_SAT_S:
2440 m = (typeof(m)){"LPe12000-S", "PCIe", "Fibre Channel Adapter"};
2441 break;
2442 case PCI_DEVICE_ID_HORNET:
2443 m = (typeof(m)){"LP21000", "PCIe",
2444 "Obsolete, Unsupported FCoE Adapter"};
2445 GE = 1;
2446 break;
2447 case PCI_DEVICE_ID_PROTEUS_VF:
2448 m = (typeof(m)){"LPev12000", "PCIe IOV",
2449 "Obsolete, Unsupported Fibre Channel Adapter"};
2450 break;
2451 case PCI_DEVICE_ID_PROTEUS_PF:
2452 m = (typeof(m)){"LPev12000", "PCIe IOV",
2453 "Obsolete, Unsupported Fibre Channel Adapter"};
2454 break;
2455 case PCI_DEVICE_ID_PROTEUS_S:
2456 m = (typeof(m)){"LPemv12002-S", "PCIe IOV",
2457 "Obsolete, Unsupported Fibre Channel Adapter"};
2458 break;
2459 case PCI_DEVICE_ID_TIGERSHARK:
2460 oneConnect = 1;
2461 m = (typeof(m)){"OCe10100", "PCIe", "FCoE"};
2462 break;
2463 case PCI_DEVICE_ID_TOMCAT:
2464 oneConnect = 1;
2465 m = (typeof(m)){"OCe11100", "PCIe", "FCoE"};
2466 break;
2467 case PCI_DEVICE_ID_FALCON:
2468 m = (typeof(m)){"LPSe12002-ML1-E", "PCIe",
2469 "EmulexSecure Fibre"};
2470 break;
2471 case PCI_DEVICE_ID_BALIUS:
2472 m = (typeof(m)){"LPVe12002", "PCIe Shared I/O",
2473 "Obsolete, Unsupported Fibre Channel Adapter"};
2474 break;
2475 case PCI_DEVICE_ID_LANCER_FC:
2476 m = (typeof(m)){"LPe16000", "PCIe", "Fibre Channel Adapter"};
2477 break;
2478 case PCI_DEVICE_ID_LANCER_FC_VF:
2479 m = (typeof(m)){"LPe16000", "PCIe",
2480 "Obsolete, Unsupported Fibre Channel Adapter"};
2481 break;
2482 case PCI_DEVICE_ID_LANCER_FCOE:
2483 oneConnect = 1;
2484 m = (typeof(m)){"OCe15100", "PCIe", "FCoE"};
2485 break;
2486 case PCI_DEVICE_ID_LANCER_FCOE_VF:
2487 oneConnect = 1;
2488 m = (typeof(m)){"OCe15100", "PCIe",
2489 "Obsolete, Unsupported FCoE"};
2490 break;
2491 case PCI_DEVICE_ID_LANCER_G6_FC:
2492 m = (typeof(m)){"LPe32000", "PCIe", "Fibre Channel Adapter"};
2493 break;
2494 case PCI_DEVICE_ID_LANCER_G7_FC:
2495 m = (typeof(m)){"LPe36000", "PCIe", "Fibre Channel Adapter"};
2496 break;
2497 case PCI_DEVICE_ID_SKYHAWK:
2498 case PCI_DEVICE_ID_SKYHAWK_VF:
2499 oneConnect = 1;
2500 m = (typeof(m)){"OCe14000", "PCIe", "FCoE"};
2501 break;
2502 default:
2503 m = (typeof(m)){"Unknown", "", ""};
2504 break;
2505 }
2506
2507 if (mdp && mdp[0] == '\0')
2508 snprintf(mdp, 79,"%s", m.name);
2509
2510
2511
2512
2513 if (descp && descp[0] == '\0') {
2514 if (oneConnect)
2515 snprintf(descp, 255,
2516 "Emulex OneConnect %s, %s Initiator %s",
2517 m.name, m.function,
2518 phba->Port);
2519 else if (max_speed == 0)
2520 snprintf(descp, 255,
2521 "Emulex %s %s %s",
2522 m.name, m.bus, m.function);
2523 else
2524 snprintf(descp, 255,
2525 "Emulex %s %d%s %s %s",
2526 m.name, max_speed, (GE) ? "GE" : "Gb",
2527 m.bus, m.function);
2528 }
2529}
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543int
2544lpfc_post_buffer(struct lpfc_hba *phba, struct lpfc_sli_ring *pring, int cnt)
2545{
2546 IOCB_t *icmd;
2547 struct lpfc_iocbq *iocb;
2548 struct lpfc_dmabuf *mp1, *mp2;
2549
2550 cnt += pring->missbufcnt;
2551
2552
2553 while (cnt > 0) {
2554
2555 iocb = lpfc_sli_get_iocbq(phba);
2556 if (iocb == NULL) {
2557 pring->missbufcnt = cnt;
2558 return cnt;
2559 }
2560 icmd = &iocb->iocb;
2561
2562
2563
2564 mp1 = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL);
2565 if (mp1)
2566 mp1->virt = lpfc_mbuf_alloc(phba, MEM_PRI, &mp1->phys);
2567 if (!mp1 || !mp1->virt) {
2568 kfree(mp1);
2569 lpfc_sli_release_iocbq(phba, iocb);
2570 pring->missbufcnt = cnt;
2571 return cnt;
2572 }
2573
2574 INIT_LIST_HEAD(&mp1->list);
2575
2576 if (cnt > 1) {
2577 mp2 = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL);
2578 if (mp2)
2579 mp2->virt = lpfc_mbuf_alloc(phba, MEM_PRI,
2580 &mp2->phys);
2581 if (!mp2 || !mp2->virt) {
2582 kfree(mp2);
2583 lpfc_mbuf_free(phba, mp1->virt, mp1->phys);
2584 kfree(mp1);
2585 lpfc_sli_release_iocbq(phba, iocb);
2586 pring->missbufcnt = cnt;
2587 return cnt;
2588 }
2589
2590 INIT_LIST_HEAD(&mp2->list);
2591 } else {
2592 mp2 = NULL;
2593 }
2594
2595 icmd->un.cont64[0].addrHigh = putPaddrHigh(mp1->phys);
2596 icmd->un.cont64[0].addrLow = putPaddrLow(mp1->phys);
2597 icmd->un.cont64[0].tus.f.bdeSize = FCELSSIZE;
2598 icmd->ulpBdeCount = 1;
2599 cnt--;
2600 if (mp2) {
2601 icmd->un.cont64[1].addrHigh = putPaddrHigh(mp2->phys);
2602 icmd->un.cont64[1].addrLow = putPaddrLow(mp2->phys);
2603 icmd->un.cont64[1].tus.f.bdeSize = FCELSSIZE;
2604 cnt--;
2605 icmd->ulpBdeCount = 2;
2606 }
2607
2608 icmd->ulpCommand = CMD_QUE_RING_BUF64_CN;
2609 icmd->ulpLe = 1;
2610
2611 if (lpfc_sli_issue_iocb(phba, pring->ringno, iocb, 0) ==
2612 IOCB_ERROR) {
2613 lpfc_mbuf_free(phba, mp1->virt, mp1->phys);
2614 kfree(mp1);
2615 cnt++;
2616 if (mp2) {
2617 lpfc_mbuf_free(phba, mp2->virt, mp2->phys);
2618 kfree(mp2);
2619 cnt++;
2620 }
2621 lpfc_sli_release_iocbq(phba, iocb);
2622 pring->missbufcnt = cnt;
2623 return cnt;
2624 }
2625 lpfc_sli_ringpostbuf_put(phba, pring, mp1);
2626 if (mp2)
2627 lpfc_sli_ringpostbuf_put(phba, pring, mp2);
2628 }
2629 pring->missbufcnt = 0;
2630 return 0;
2631}
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644static int
2645lpfc_post_rcv_buf(struct lpfc_hba *phba)
2646{
2647 struct lpfc_sli *psli = &phba->sli;
2648
2649
2650 lpfc_post_buffer(phba, &psli->sli3_ring[LPFC_ELS_RING], LPFC_BUF_RING0);
2651
2652
2653 return 0;
2654}
2655
2656#define S(N,V) (((V)<<(N))|((V)>>(32-(N))))
2657
2658
2659
2660
2661
2662
2663
2664
2665static void
2666lpfc_sha_init(uint32_t * HashResultPointer)
2667{
2668 HashResultPointer[0] = 0x67452301;
2669 HashResultPointer[1] = 0xEFCDAB89;
2670 HashResultPointer[2] = 0x98BADCFE;
2671 HashResultPointer[3] = 0x10325476;
2672 HashResultPointer[4] = 0xC3D2E1F0;
2673}
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685static void
2686lpfc_sha_iterate(uint32_t * HashResultPointer, uint32_t * HashWorkingPointer)
2687{
2688 int t;
2689 uint32_t TEMP;
2690 uint32_t A, B, C, D, E;
2691 t = 16;
2692 do {
2693 HashWorkingPointer[t] =
2694 S(1,
2695 HashWorkingPointer[t - 3] ^ HashWorkingPointer[t -
2696 8] ^
2697 HashWorkingPointer[t - 14] ^ HashWorkingPointer[t - 16]);
2698 } while (++t <= 79);
2699 t = 0;
2700 A = HashResultPointer[0];
2701 B = HashResultPointer[1];
2702 C = HashResultPointer[2];
2703 D = HashResultPointer[3];
2704 E = HashResultPointer[4];
2705
2706 do {
2707 if (t < 20) {
2708 TEMP = ((B & C) | ((~B) & D)) + 0x5A827999;
2709 } else if (t < 40) {
2710 TEMP = (B ^ C ^ D) + 0x6ED9EBA1;
2711 } else if (t < 60) {
2712 TEMP = ((B & C) | (B & D) | (C & D)) + 0x8F1BBCDC;
2713 } else {
2714 TEMP = (B ^ C ^ D) + 0xCA62C1D6;
2715 }
2716 TEMP += S(5, A) + E + HashWorkingPointer[t];
2717 E = D;
2718 D = C;
2719 C = S(30, B);
2720 B = A;
2721 A = TEMP;
2722 } while (++t <= 79);
2723
2724 HashResultPointer[0] += A;
2725 HashResultPointer[1] += B;
2726 HashResultPointer[2] += C;
2727 HashResultPointer[3] += D;
2728 HashResultPointer[4] += E;
2729
2730}
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742static void
2743lpfc_challenge_key(uint32_t * RandomChallenge, uint32_t * HashWorking)
2744{
2745 *HashWorking = (*RandomChallenge ^ *HashWorking);
2746}
2747
2748
2749
2750
2751
2752
2753
2754
2755void
2756lpfc_hba_init(struct lpfc_hba *phba, uint32_t *hbainit)
2757{
2758 int t;
2759 uint32_t *HashWorking;
2760 uint32_t *pwwnn = (uint32_t *) phba->wwnn;
2761
2762 HashWorking = kcalloc(80, sizeof(uint32_t), GFP_KERNEL);
2763 if (!HashWorking)
2764 return;
2765
2766 HashWorking[0] = HashWorking[78] = *pwwnn++;
2767 HashWorking[1] = HashWorking[79] = *pwwnn;
2768
2769 for (t = 0; t < 7; t++)
2770 lpfc_challenge_key(phba->RandomData + t, HashWorking + t);
2771
2772 lpfc_sha_init(hbainit);
2773 lpfc_sha_iterate(hbainit, HashWorking);
2774 kfree(HashWorking);
2775}
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786void
2787lpfc_cleanup(struct lpfc_vport *vport)
2788{
2789 struct lpfc_hba *phba = vport->phba;
2790 struct lpfc_nodelist *ndlp, *next_ndlp;
2791 int i = 0;
2792
2793 if (phba->link_state > LPFC_LINK_DOWN)
2794 lpfc_port_link_failure(vport);
2795
2796 list_for_each_entry_safe(ndlp, next_ndlp, &vport->fc_nodes, nlp_listp) {
2797 if (!NLP_CHK_NODE_ACT(ndlp)) {
2798 ndlp = lpfc_enable_node(vport, ndlp,
2799 NLP_STE_UNUSED_NODE);
2800 if (!ndlp)
2801 continue;
2802 spin_lock_irq(&phba->ndlp_lock);
2803 NLP_SET_FREE_REQ(ndlp);
2804 spin_unlock_irq(&phba->ndlp_lock);
2805
2806 lpfc_nlp_put(ndlp);
2807 continue;
2808 }
2809 spin_lock_irq(&phba->ndlp_lock);
2810 if (NLP_CHK_FREE_REQ(ndlp)) {
2811
2812 spin_unlock_irq(&phba->ndlp_lock);
2813 continue;
2814 } else
2815
2816 NLP_SET_FREE_REQ(ndlp);
2817 spin_unlock_irq(&phba->ndlp_lock);
2818
2819 if (vport->port_type != LPFC_PHYSICAL_PORT &&
2820 ndlp->nlp_DID == Fabric_DID) {
2821
2822 lpfc_nlp_put(ndlp);
2823 continue;
2824 }
2825
2826
2827
2828
2829 if (ndlp->nlp_state == NLP_STE_UNUSED_NODE) {
2830 lpfc_nlp_put(ndlp);
2831 continue;
2832 }
2833
2834 if (ndlp->nlp_type & NLP_FABRIC)
2835 lpfc_disc_state_machine(vport, ndlp, NULL,
2836 NLP_EVT_DEVICE_RECOVERY);
2837
2838 lpfc_disc_state_machine(vport, ndlp, NULL,
2839 NLP_EVT_DEVICE_RM);
2840 }
2841
2842
2843
2844
2845
2846 while (!list_empty(&vport->fc_nodes)) {
2847 if (i++ > 3000) {
2848 lpfc_printf_vlog(vport, KERN_ERR, LOG_DISCOVERY,
2849 "0233 Nodelist not empty\n");
2850 list_for_each_entry_safe(ndlp, next_ndlp,
2851 &vport->fc_nodes, nlp_listp) {
2852 lpfc_printf_vlog(ndlp->vport, KERN_ERR,
2853 LOG_NODE,
2854 "0282 did:x%x ndlp:x%px "
2855 "usgmap:x%x refcnt:%d\n",
2856 ndlp->nlp_DID, (void *)ndlp,
2857 ndlp->nlp_usg_map,
2858 kref_read(&ndlp->kref));
2859 }
2860 break;
2861 }
2862
2863
2864 msleep(10);
2865 }
2866 lpfc_cleanup_vports_rrqs(vport, NULL);
2867}
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877void
2878lpfc_stop_vport_timers(struct lpfc_vport *vport)
2879{
2880 del_timer_sync(&vport->els_tmofunc);
2881 del_timer_sync(&vport->delayed_disc_tmo);
2882 lpfc_can_disctmo(vport);
2883 return;
2884}
2885
2886
2887
2888
2889
2890
2891
2892
2893void
2894__lpfc_sli4_stop_fcf_redisc_wait_timer(struct lpfc_hba *phba)
2895{
2896
2897 phba->fcf.fcf_flag &= ~FCF_REDISC_PEND;
2898
2899
2900 del_timer(&phba->fcf.redisc_wait);
2901}
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912void
2913lpfc_sli4_stop_fcf_redisc_wait_timer(struct lpfc_hba *phba)
2914{
2915 spin_lock_irq(&phba->hbalock);
2916 if (!(phba->fcf.fcf_flag & FCF_REDISC_PEND)) {
2917
2918 spin_unlock_irq(&phba->hbalock);
2919 return;
2920 }
2921 __lpfc_sli4_stop_fcf_redisc_wait_timer(phba);
2922
2923 phba->fcf.fcf_flag &= ~(FCF_DEAD_DISC | FCF_ACVL_DISC);
2924 spin_unlock_irq(&phba->hbalock);
2925}
2926
2927
2928
2929
2930
2931
2932
2933
2934void
2935lpfc_stop_hba_timers(struct lpfc_hba *phba)
2936{
2937 if (phba->pport)
2938 lpfc_stop_vport_timers(phba->pport);
2939 cancel_delayed_work_sync(&phba->eq_delay_work);
2940 del_timer_sync(&phba->sli.mbox_tmo);
2941 del_timer_sync(&phba->fabric_block_timer);
2942 del_timer_sync(&phba->eratt_poll);
2943 del_timer_sync(&phba->hb_tmofunc);
2944 if (phba->sli_rev == LPFC_SLI_REV4) {
2945 del_timer_sync(&phba->rrq_tmr);
2946 phba->hba_flag &= ~HBA_RRQ_ACTIVE;
2947 }
2948 phba->hb_outstanding = 0;
2949
2950 switch (phba->pci_dev_grp) {
2951 case LPFC_PCI_DEV_LP:
2952
2953 del_timer_sync(&phba->fcp_poll_timer);
2954 break;
2955 case LPFC_PCI_DEV_OC:
2956
2957 lpfc_sli4_stop_fcf_redisc_wait_timer(phba);
2958 break;
2959 default:
2960 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
2961 "0297 Invalid device group (x%x)\n",
2962 phba->pci_dev_grp);
2963 break;
2964 }
2965 return;
2966}
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978static void
2979lpfc_block_mgmt_io(struct lpfc_hba *phba, int mbx_action)
2980{
2981 unsigned long iflag;
2982 uint8_t actcmd = MBX_HEARTBEAT;
2983 unsigned long timeout;
2984
2985 spin_lock_irqsave(&phba->hbalock, iflag);
2986 phba->sli.sli_flag |= LPFC_BLOCK_MGMT_IO;
2987 spin_unlock_irqrestore(&phba->hbalock, iflag);
2988 if (mbx_action == LPFC_MBX_NO_WAIT)
2989 return;
2990 timeout = msecs_to_jiffies(LPFC_MBOX_TMO * 1000) + jiffies;
2991 spin_lock_irqsave(&phba->hbalock, iflag);
2992 if (phba->sli.mbox_active) {
2993 actcmd = phba->sli.mbox_active->u.mb.mbxCommand;
2994
2995
2996
2997 timeout = msecs_to_jiffies(lpfc_mbox_tmo_val(phba,
2998 phba->sli.mbox_active) * 1000) + jiffies;
2999 }
3000 spin_unlock_irqrestore(&phba->hbalock, iflag);
3001
3002
3003 while (phba->sli.mbox_active) {
3004
3005 msleep(2);
3006 if (time_after(jiffies, timeout)) {
3007 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3008 "2813 Mgmt IO is Blocked %x "
3009 "- mbox cmd %x still active\n",
3010 phba->sli.sli_flag, actcmd);
3011 break;
3012 }
3013 }
3014}
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024void
3025lpfc_sli4_node_prep(struct lpfc_hba *phba)
3026{
3027 struct lpfc_nodelist *ndlp, *next_ndlp;
3028 struct lpfc_vport **vports;
3029 int i, rpi;
3030 unsigned long flags;
3031
3032 if (phba->sli_rev != LPFC_SLI_REV4)
3033 return;
3034
3035 vports = lpfc_create_vport_work_array(phba);
3036 if (vports == NULL)
3037 return;
3038
3039 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
3040 if (vports[i]->load_flag & FC_UNLOADING)
3041 continue;
3042
3043 list_for_each_entry_safe(ndlp, next_ndlp,
3044 &vports[i]->fc_nodes,
3045 nlp_listp) {
3046 if (!NLP_CHK_NODE_ACT(ndlp))
3047 continue;
3048 rpi = lpfc_sli4_alloc_rpi(phba);
3049 if (rpi == LPFC_RPI_ALLOC_ERROR) {
3050 spin_lock_irqsave(&phba->ndlp_lock, flags);
3051 NLP_CLR_NODE_ACT(ndlp);
3052 spin_unlock_irqrestore(&phba->ndlp_lock, flags);
3053 continue;
3054 }
3055 ndlp->nlp_rpi = rpi;
3056 lpfc_printf_vlog(ndlp->vport, KERN_INFO, LOG_NODE,
3057 "0009 rpi:%x DID:%x "
3058 "flg:%x map:%x x%px\n", ndlp->nlp_rpi,
3059 ndlp->nlp_DID, ndlp->nlp_flag,
3060 ndlp->nlp_usg_map, ndlp);
3061 }
3062 }
3063 lpfc_destroy_vport_work_array(phba, vports);
3064}
3065
3066
3067
3068
3069
3070
3071
3072
3073static void lpfc_create_expedite_pool(struct lpfc_hba *phba)
3074{
3075 struct lpfc_sli4_hdw_queue *qp;
3076 struct lpfc_io_buf *lpfc_ncmd;
3077 struct lpfc_io_buf *lpfc_ncmd_next;
3078 struct lpfc_epd_pool *epd_pool;
3079 unsigned long iflag;
3080
3081 epd_pool = &phba->epd_pool;
3082 qp = &phba->sli4_hba.hdwq[0];
3083
3084 spin_lock_init(&epd_pool->lock);
3085 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3086 spin_lock(&epd_pool->lock);
3087 INIT_LIST_HEAD(&epd_pool->list);
3088 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3089 &qp->lpfc_io_buf_list_put, list) {
3090 list_move_tail(&lpfc_ncmd->list, &epd_pool->list);
3091 lpfc_ncmd->expedite = true;
3092 qp->put_io_bufs--;
3093 epd_pool->count++;
3094 if (epd_pool->count >= XRI_BATCH)
3095 break;
3096 }
3097 spin_unlock(&epd_pool->lock);
3098 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3099}
3100
3101
3102
3103
3104
3105
3106
3107
3108static void lpfc_destroy_expedite_pool(struct lpfc_hba *phba)
3109{
3110 struct lpfc_sli4_hdw_queue *qp;
3111 struct lpfc_io_buf *lpfc_ncmd;
3112 struct lpfc_io_buf *lpfc_ncmd_next;
3113 struct lpfc_epd_pool *epd_pool;
3114 unsigned long iflag;
3115
3116 epd_pool = &phba->epd_pool;
3117 qp = &phba->sli4_hba.hdwq[0];
3118
3119 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3120 spin_lock(&epd_pool->lock);
3121 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3122 &epd_pool->list, list) {
3123 list_move_tail(&lpfc_ncmd->list,
3124 &qp->lpfc_io_buf_list_put);
3125 lpfc_ncmd->flags = false;
3126 qp->put_io_bufs++;
3127 epd_pool->count--;
3128 }
3129 spin_unlock(&epd_pool->lock);
3130 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3131}
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141void lpfc_create_multixri_pools(struct lpfc_hba *phba)
3142{
3143 u32 i, j;
3144 u32 hwq_count;
3145 u32 count_per_hwq;
3146 struct lpfc_io_buf *lpfc_ncmd;
3147 struct lpfc_io_buf *lpfc_ncmd_next;
3148 unsigned long iflag;
3149 struct lpfc_sli4_hdw_queue *qp;
3150 struct lpfc_multixri_pool *multixri_pool;
3151 struct lpfc_pbl_pool *pbl_pool;
3152 struct lpfc_pvt_pool *pvt_pool;
3153
3154 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3155 "1234 num_hdw_queue=%d num_present_cpu=%d common_xri_cnt=%d\n",
3156 phba->cfg_hdw_queue, phba->sli4_hba.num_present_cpu,
3157 phba->sli4_hba.io_xri_cnt);
3158
3159 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
3160 lpfc_create_expedite_pool(phba);
3161
3162 hwq_count = phba->cfg_hdw_queue;
3163 count_per_hwq = phba->sli4_hba.io_xri_cnt / hwq_count;
3164
3165 for (i = 0; i < hwq_count; i++) {
3166 multixri_pool = kzalloc(sizeof(*multixri_pool), GFP_KERNEL);
3167
3168 if (!multixri_pool) {
3169 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3170 "1238 Failed to allocate memory for "
3171 "multixri_pool\n");
3172
3173 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
3174 lpfc_destroy_expedite_pool(phba);
3175
3176 j = 0;
3177 while (j < i) {
3178 qp = &phba->sli4_hba.hdwq[j];
3179 kfree(qp->p_multixri_pool);
3180 j++;
3181 }
3182 phba->cfg_xri_rebalancing = 0;
3183 return;
3184 }
3185
3186 qp = &phba->sli4_hba.hdwq[i];
3187 qp->p_multixri_pool = multixri_pool;
3188
3189 multixri_pool->xri_limit = count_per_hwq;
3190 multixri_pool->rrb_next_hwqid = i;
3191
3192
3193 pbl_pool = &multixri_pool->pbl_pool;
3194 spin_lock_init(&pbl_pool->lock);
3195 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3196 spin_lock(&pbl_pool->lock);
3197 INIT_LIST_HEAD(&pbl_pool->list);
3198 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3199 &qp->lpfc_io_buf_list_put, list) {
3200 list_move_tail(&lpfc_ncmd->list, &pbl_pool->list);
3201 qp->put_io_bufs--;
3202 pbl_pool->count++;
3203 }
3204 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3205 "1235 Moved %d buffers from PUT list over to pbl_pool[%d]\n",
3206 pbl_pool->count, i);
3207 spin_unlock(&pbl_pool->lock);
3208 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3209
3210
3211 pvt_pool = &multixri_pool->pvt_pool;
3212 pvt_pool->high_watermark = multixri_pool->xri_limit / 2;
3213 pvt_pool->low_watermark = XRI_BATCH;
3214 spin_lock_init(&pvt_pool->lock);
3215 spin_lock_irqsave(&pvt_pool->lock, iflag);
3216 INIT_LIST_HEAD(&pvt_pool->list);
3217 pvt_pool->count = 0;
3218 spin_unlock_irqrestore(&pvt_pool->lock, iflag);
3219 }
3220}
3221
3222
3223
3224
3225
3226
3227
3228static void lpfc_destroy_multixri_pools(struct lpfc_hba *phba)
3229{
3230 u32 i;
3231 u32 hwq_count;
3232 struct lpfc_io_buf *lpfc_ncmd;
3233 struct lpfc_io_buf *lpfc_ncmd_next;
3234 unsigned long iflag;
3235 struct lpfc_sli4_hdw_queue *qp;
3236 struct lpfc_multixri_pool *multixri_pool;
3237 struct lpfc_pbl_pool *pbl_pool;
3238 struct lpfc_pvt_pool *pvt_pool;
3239
3240 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
3241 lpfc_destroy_expedite_pool(phba);
3242
3243 if (!(phba->pport->load_flag & FC_UNLOADING))
3244 lpfc_sli_flush_io_rings(phba);
3245
3246 hwq_count = phba->cfg_hdw_queue;
3247
3248 for (i = 0; i < hwq_count; i++) {
3249 qp = &phba->sli4_hba.hdwq[i];
3250 multixri_pool = qp->p_multixri_pool;
3251 if (!multixri_pool)
3252 continue;
3253
3254 qp->p_multixri_pool = NULL;
3255
3256 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3257
3258
3259 pbl_pool = &multixri_pool->pbl_pool;
3260 spin_lock(&pbl_pool->lock);
3261
3262 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3263 "1236 Moving %d buffers from pbl_pool[%d] TO PUT list\n",
3264 pbl_pool->count, i);
3265
3266 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3267 &pbl_pool->list, list) {
3268 list_move_tail(&lpfc_ncmd->list,
3269 &qp->lpfc_io_buf_list_put);
3270 qp->put_io_bufs++;
3271 pbl_pool->count--;
3272 }
3273
3274 INIT_LIST_HEAD(&pbl_pool->list);
3275 pbl_pool->count = 0;
3276
3277 spin_unlock(&pbl_pool->lock);
3278
3279
3280 pvt_pool = &multixri_pool->pvt_pool;
3281 spin_lock(&pvt_pool->lock);
3282
3283 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3284 "1237 Moving %d buffers from pvt_pool[%d] TO PUT list\n",
3285 pvt_pool->count, i);
3286
3287 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3288 &pvt_pool->list, list) {
3289 list_move_tail(&lpfc_ncmd->list,
3290 &qp->lpfc_io_buf_list_put);
3291 qp->put_io_bufs++;
3292 pvt_pool->count--;
3293 }
3294
3295 INIT_LIST_HEAD(&pvt_pool->list);
3296 pvt_pool->count = 0;
3297
3298 spin_unlock(&pvt_pool->lock);
3299 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3300
3301 kfree(multixri_pool);
3302 }
3303}
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317int
3318lpfc_online(struct lpfc_hba *phba)
3319{
3320 struct lpfc_vport *vport;
3321 struct lpfc_vport **vports;
3322 int i, error = 0;
3323 bool vpis_cleared = false;
3324
3325 if (!phba)
3326 return 0;
3327 vport = phba->pport;
3328
3329 if (!(vport->fc_flag & FC_OFFLINE_MODE))
3330 return 0;
3331
3332 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
3333 "0458 Bring Adapter online\n");
3334
3335 lpfc_block_mgmt_io(phba, LPFC_MBX_WAIT);
3336
3337 if (phba->sli_rev == LPFC_SLI_REV4) {
3338 if (lpfc_sli4_hba_setup(phba)) {
3339 lpfc_unblock_mgmt_io(phba);
3340 return 1;
3341 }
3342 spin_lock_irq(&phba->hbalock);
3343 if (!phba->sli4_hba.max_cfg_param.vpi_used)
3344 vpis_cleared = true;
3345 spin_unlock_irq(&phba->hbalock);
3346
3347
3348
3349
3350 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME &&
3351 !phba->nvmet_support) {
3352 error = lpfc_nvme_create_localport(phba->pport);
3353 if (error)
3354 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
3355 "6132 NVME restore reg failed "
3356 "on nvmei error x%x\n", error);
3357 }
3358 } else {
3359 lpfc_sli_queue_init(phba);
3360 if (lpfc_sli_hba_setup(phba)) {
3361 lpfc_unblock_mgmt_io(phba);
3362 return 1;
3363 }
3364 }
3365
3366 vports = lpfc_create_vport_work_array(phba);
3367 if (vports != NULL) {
3368 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
3369 struct Scsi_Host *shost;
3370 shost = lpfc_shost_from_vport(vports[i]);
3371 spin_lock_irq(shost->host_lock);
3372 vports[i]->fc_flag &= ~FC_OFFLINE_MODE;
3373 if (phba->sli3_options & LPFC_SLI3_NPIV_ENABLED)
3374 vports[i]->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
3375 if (phba->sli_rev == LPFC_SLI_REV4) {
3376 vports[i]->fc_flag |= FC_VPORT_NEEDS_INIT_VPI;
3377 if ((vpis_cleared) &&
3378 (vports[i]->port_type !=
3379 LPFC_PHYSICAL_PORT))
3380 vports[i]->vpi = 0;
3381 }
3382 spin_unlock_irq(shost->host_lock);
3383 }
3384 }
3385 lpfc_destroy_vport_work_array(phba, vports);
3386
3387 if (phba->cfg_xri_rebalancing)
3388 lpfc_create_multixri_pools(phba);
3389
3390 lpfc_unblock_mgmt_io(phba);
3391 return 0;
3392}
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405void
3406lpfc_unblock_mgmt_io(struct lpfc_hba * phba)
3407{
3408 unsigned long iflag;
3409
3410 spin_lock_irqsave(&phba->hbalock, iflag);
3411 phba->sli.sli_flag &= ~LPFC_BLOCK_MGMT_IO;
3412 spin_unlock_irqrestore(&phba->hbalock, iflag);
3413}
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423void
3424lpfc_offline_prep(struct lpfc_hba *phba, int mbx_action)
3425{
3426 struct lpfc_vport *vport = phba->pport;
3427 struct lpfc_nodelist *ndlp, *next_ndlp;
3428 struct lpfc_vport **vports;
3429 struct Scsi_Host *shost;
3430 int i;
3431
3432 if (vport->fc_flag & FC_OFFLINE_MODE)
3433 return;
3434
3435 lpfc_block_mgmt_io(phba, mbx_action);
3436
3437 lpfc_linkdown(phba);
3438
3439
3440 vports = lpfc_create_vport_work_array(phba);
3441 if (vports != NULL) {
3442 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
3443 if (vports[i]->load_flag & FC_UNLOADING)
3444 continue;
3445 shost = lpfc_shost_from_vport(vports[i]);
3446 spin_lock_irq(shost->host_lock);
3447 vports[i]->vpi_state &= ~LPFC_VPI_REGISTERED;
3448 vports[i]->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
3449 vports[i]->fc_flag &= ~FC_VFI_REGISTERED;
3450 spin_unlock_irq(shost->host_lock);
3451
3452 shost = lpfc_shost_from_vport(vports[i]);
3453 list_for_each_entry_safe(ndlp, next_ndlp,
3454 &vports[i]->fc_nodes,
3455 nlp_listp) {
3456 if (!NLP_CHK_NODE_ACT(ndlp))
3457 continue;
3458 if (ndlp->nlp_state == NLP_STE_UNUSED_NODE)
3459 continue;
3460 if (ndlp->nlp_type & NLP_FABRIC) {
3461 lpfc_disc_state_machine(vports[i], ndlp,
3462 NULL, NLP_EVT_DEVICE_RECOVERY);
3463 lpfc_disc_state_machine(vports[i], ndlp,
3464 NULL, NLP_EVT_DEVICE_RM);
3465 }
3466 spin_lock_irq(shost->host_lock);
3467 ndlp->nlp_flag &= ~NLP_NPR_ADISC;
3468 spin_unlock_irq(shost->host_lock);
3469
3470
3471
3472
3473
3474 if (phba->sli_rev == LPFC_SLI_REV4) {
3475 lpfc_printf_vlog(ndlp->vport,
3476 KERN_INFO, LOG_NODE,
3477 "0011 lpfc_offline: "
3478 "ndlp:x%px did %x "
3479 "usgmap:x%x rpi:%x\n",
3480 ndlp, ndlp->nlp_DID,
3481 ndlp->nlp_usg_map,
3482 ndlp->nlp_rpi);
3483
3484 lpfc_sli4_free_rpi(phba, ndlp->nlp_rpi);
3485 }
3486 lpfc_unreg_rpi(vports[i], ndlp);
3487 }
3488 }
3489 }
3490 lpfc_destroy_vport_work_array(phba, vports);
3491
3492 lpfc_sli_mbox_sys_shutdown(phba, mbx_action);
3493
3494 if (phba->wq)
3495 flush_workqueue(phba->wq);
3496}
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506void
3507lpfc_offline(struct lpfc_hba *phba)
3508{
3509 struct Scsi_Host *shost;
3510 struct lpfc_vport **vports;
3511 int i;
3512
3513 if (phba->pport->fc_flag & FC_OFFLINE_MODE)
3514 return;
3515
3516
3517 lpfc_stop_port(phba);
3518
3519
3520
3521
3522 lpfc_nvmet_destroy_targetport(phba);
3523 lpfc_nvme_destroy_localport(phba->pport);
3524
3525 vports = lpfc_create_vport_work_array(phba);
3526 if (vports != NULL)
3527 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++)
3528 lpfc_stop_vport_timers(vports[i]);
3529 lpfc_destroy_vport_work_array(phba, vports);
3530 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
3531 "0460 Bring Adapter offline\n");
3532
3533
3534 lpfc_sli_hba_down(phba);
3535 spin_lock_irq(&phba->hbalock);
3536 phba->work_ha = 0;
3537 spin_unlock_irq(&phba->hbalock);
3538 vports = lpfc_create_vport_work_array(phba);
3539 if (vports != NULL)
3540 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
3541 shost = lpfc_shost_from_vport(vports[i]);
3542 spin_lock_irq(shost->host_lock);
3543 vports[i]->work_port_events = 0;
3544 vports[i]->fc_flag |= FC_OFFLINE_MODE;
3545 spin_unlock_irq(shost->host_lock);
3546 }
3547 lpfc_destroy_vport_work_array(phba, vports);
3548
3549 if (phba->cfg_xri_rebalancing)
3550 lpfc_destroy_multixri_pools(phba);
3551}
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561static void
3562lpfc_scsi_free(struct lpfc_hba *phba)
3563{
3564 struct lpfc_io_buf *sb, *sb_next;
3565
3566 if (!(phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP))
3567 return;
3568
3569 spin_lock_irq(&phba->hbalock);
3570
3571
3572
3573 spin_lock(&phba->scsi_buf_list_put_lock);
3574 list_for_each_entry_safe(sb, sb_next, &phba->lpfc_scsi_buf_list_put,
3575 list) {
3576 list_del(&sb->list);
3577 dma_pool_free(phba->lpfc_sg_dma_buf_pool, sb->data,
3578 sb->dma_handle);
3579 kfree(sb);
3580 phba->total_scsi_bufs--;
3581 }
3582 spin_unlock(&phba->scsi_buf_list_put_lock);
3583
3584 spin_lock(&phba->scsi_buf_list_get_lock);
3585 list_for_each_entry_safe(sb, sb_next, &phba->lpfc_scsi_buf_list_get,
3586 list) {
3587 list_del(&sb->list);
3588 dma_pool_free(phba->lpfc_sg_dma_buf_pool, sb->data,
3589 sb->dma_handle);
3590 kfree(sb);
3591 phba->total_scsi_bufs--;
3592 }
3593 spin_unlock(&phba->scsi_buf_list_get_lock);
3594 spin_unlock_irq(&phba->hbalock);
3595}
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605void
3606lpfc_io_free(struct lpfc_hba *phba)
3607{
3608 struct lpfc_io_buf *lpfc_ncmd, *lpfc_ncmd_next;
3609 struct lpfc_sli4_hdw_queue *qp;
3610 int idx;
3611
3612 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
3613 qp = &phba->sli4_hba.hdwq[idx];
3614
3615 spin_lock(&qp->io_buf_list_put_lock);
3616 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3617 &qp->lpfc_io_buf_list_put,
3618 list) {
3619 list_del(&lpfc_ncmd->list);
3620 qp->put_io_bufs--;
3621 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
3622 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
3623 if (phba->cfg_xpsgl && !phba->nvmet_support)
3624 lpfc_put_sgl_per_hdwq(phba, lpfc_ncmd);
3625 lpfc_put_cmd_rsp_buf_per_hdwq(phba, lpfc_ncmd);
3626 kfree(lpfc_ncmd);
3627 qp->total_io_bufs--;
3628 }
3629 spin_unlock(&qp->io_buf_list_put_lock);
3630
3631 spin_lock(&qp->io_buf_list_get_lock);
3632 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3633 &qp->lpfc_io_buf_list_get,
3634 list) {
3635 list_del(&lpfc_ncmd->list);
3636 qp->get_io_bufs--;
3637 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
3638 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
3639 if (phba->cfg_xpsgl && !phba->nvmet_support)
3640 lpfc_put_sgl_per_hdwq(phba, lpfc_ncmd);
3641 lpfc_put_cmd_rsp_buf_per_hdwq(phba, lpfc_ncmd);
3642 kfree(lpfc_ncmd);
3643 qp->total_io_bufs--;
3644 }
3645 spin_unlock(&qp->io_buf_list_get_lock);
3646 }
3647}
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661int
3662lpfc_sli4_els_sgl_update(struct lpfc_hba *phba)
3663{
3664 struct lpfc_sglq *sglq_entry = NULL, *sglq_entry_next = NULL;
3665 uint16_t i, lxri, xri_cnt, els_xri_cnt;
3666 LIST_HEAD(els_sgl_list);
3667 int rc;
3668
3669
3670
3671
3672 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
3673
3674 if (els_xri_cnt > phba->sli4_hba.els_xri_cnt) {
3675
3676 xri_cnt = els_xri_cnt - phba->sli4_hba.els_xri_cnt;
3677 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3678 "3157 ELS xri-sgl count increased from "
3679 "%d to %d\n", phba->sli4_hba.els_xri_cnt,
3680 els_xri_cnt);
3681
3682 for (i = 0; i < xri_cnt; i++) {
3683 sglq_entry = kzalloc(sizeof(struct lpfc_sglq),
3684 GFP_KERNEL);
3685 if (sglq_entry == NULL) {
3686 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3687 "2562 Failure to allocate an "
3688 "ELS sgl entry:%d\n", i);
3689 rc = -ENOMEM;
3690 goto out_free_mem;
3691 }
3692 sglq_entry->buff_type = GEN_BUFF_TYPE;
3693 sglq_entry->virt = lpfc_mbuf_alloc(phba, 0,
3694 &sglq_entry->phys);
3695 if (sglq_entry->virt == NULL) {
3696 kfree(sglq_entry);
3697 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3698 "2563 Failure to allocate an "
3699 "ELS mbuf:%d\n", i);
3700 rc = -ENOMEM;
3701 goto out_free_mem;
3702 }
3703 sglq_entry->sgl = sglq_entry->virt;
3704 memset(sglq_entry->sgl, 0, LPFC_BPL_SIZE);
3705 sglq_entry->state = SGL_FREED;
3706 list_add_tail(&sglq_entry->list, &els_sgl_list);
3707 }
3708 spin_lock_irq(&phba->hbalock);
3709 spin_lock(&phba->sli4_hba.sgl_list_lock);
3710 list_splice_init(&els_sgl_list,
3711 &phba->sli4_hba.lpfc_els_sgl_list);
3712 spin_unlock(&phba->sli4_hba.sgl_list_lock);
3713 spin_unlock_irq(&phba->hbalock);
3714 } else if (els_xri_cnt < phba->sli4_hba.els_xri_cnt) {
3715
3716 xri_cnt = phba->sli4_hba.els_xri_cnt - els_xri_cnt;
3717 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3718 "3158 ELS xri-sgl count decreased from "
3719 "%d to %d\n", phba->sli4_hba.els_xri_cnt,
3720 els_xri_cnt);
3721 spin_lock_irq(&phba->hbalock);
3722 spin_lock(&phba->sli4_hba.sgl_list_lock);
3723 list_splice_init(&phba->sli4_hba.lpfc_els_sgl_list,
3724 &els_sgl_list);
3725
3726 for (i = 0; i < xri_cnt; i++) {
3727 list_remove_head(&els_sgl_list,
3728 sglq_entry, struct lpfc_sglq, list);
3729 if (sglq_entry) {
3730 __lpfc_mbuf_free(phba, sglq_entry->virt,
3731 sglq_entry->phys);
3732 kfree(sglq_entry);
3733 }
3734 }
3735 list_splice_init(&els_sgl_list,
3736 &phba->sli4_hba.lpfc_els_sgl_list);
3737 spin_unlock(&phba->sli4_hba.sgl_list_lock);
3738 spin_unlock_irq(&phba->hbalock);
3739 } else
3740 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3741 "3163 ELS xri-sgl count unchanged: %d\n",
3742 els_xri_cnt);
3743 phba->sli4_hba.els_xri_cnt = els_xri_cnt;
3744
3745
3746 sglq_entry = NULL;
3747 sglq_entry_next = NULL;
3748 list_for_each_entry_safe(sglq_entry, sglq_entry_next,
3749 &phba->sli4_hba.lpfc_els_sgl_list, list) {
3750 lxri = lpfc_sli4_next_xritag(phba);
3751 if (lxri == NO_XRI) {
3752 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3753 "2400 Failed to allocate xri for "
3754 "ELS sgl\n");
3755 rc = -ENOMEM;
3756 goto out_free_mem;
3757 }
3758 sglq_entry->sli4_lxritag = lxri;
3759 sglq_entry->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
3760 }
3761 return 0;
3762
3763out_free_mem:
3764 lpfc_free_els_sgl_list(phba);
3765 return rc;
3766}
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780int
3781lpfc_sli4_nvmet_sgl_update(struct lpfc_hba *phba)
3782{
3783 struct lpfc_sglq *sglq_entry = NULL, *sglq_entry_next = NULL;
3784 uint16_t i, lxri, xri_cnt, els_xri_cnt;
3785 uint16_t nvmet_xri_cnt;
3786 LIST_HEAD(nvmet_sgl_list);
3787 int rc;
3788
3789
3790
3791
3792 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
3793
3794
3795 nvmet_xri_cnt = phba->sli4_hba.max_cfg_param.max_xri - els_xri_cnt;
3796 if (nvmet_xri_cnt > phba->sli4_hba.nvmet_xri_cnt) {
3797
3798 xri_cnt = nvmet_xri_cnt - phba->sli4_hba.nvmet_xri_cnt;
3799 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3800 "6302 NVMET xri-sgl cnt grew from %d to %d\n",
3801 phba->sli4_hba.nvmet_xri_cnt, nvmet_xri_cnt);
3802
3803 for (i = 0; i < xri_cnt; i++) {
3804 sglq_entry = kzalloc(sizeof(struct lpfc_sglq),
3805 GFP_KERNEL);
3806 if (sglq_entry == NULL) {
3807 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3808 "6303 Failure to allocate an "
3809 "NVMET sgl entry:%d\n", i);
3810 rc = -ENOMEM;
3811 goto out_free_mem;
3812 }
3813 sglq_entry->buff_type = NVMET_BUFF_TYPE;
3814 sglq_entry->virt = lpfc_nvmet_buf_alloc(phba, 0,
3815 &sglq_entry->phys);
3816 if (sglq_entry->virt == NULL) {
3817 kfree(sglq_entry);
3818 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3819 "6304 Failure to allocate an "
3820 "NVMET buf:%d\n", i);
3821 rc = -ENOMEM;
3822 goto out_free_mem;
3823 }
3824 sglq_entry->sgl = sglq_entry->virt;
3825 memset(sglq_entry->sgl, 0,
3826 phba->cfg_sg_dma_buf_size);
3827 sglq_entry->state = SGL_FREED;
3828 list_add_tail(&sglq_entry->list, &nvmet_sgl_list);
3829 }
3830 spin_lock_irq(&phba->hbalock);
3831 spin_lock(&phba->sli4_hba.sgl_list_lock);
3832 list_splice_init(&nvmet_sgl_list,
3833 &phba->sli4_hba.lpfc_nvmet_sgl_list);
3834 spin_unlock(&phba->sli4_hba.sgl_list_lock);
3835 spin_unlock_irq(&phba->hbalock);
3836 } else if (nvmet_xri_cnt < phba->sli4_hba.nvmet_xri_cnt) {
3837
3838 xri_cnt = phba->sli4_hba.nvmet_xri_cnt - nvmet_xri_cnt;
3839 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3840 "6305 NVMET xri-sgl count decreased from "
3841 "%d to %d\n", phba->sli4_hba.nvmet_xri_cnt,
3842 nvmet_xri_cnt);
3843 spin_lock_irq(&phba->hbalock);
3844 spin_lock(&phba->sli4_hba.sgl_list_lock);
3845 list_splice_init(&phba->sli4_hba.lpfc_nvmet_sgl_list,
3846 &nvmet_sgl_list);
3847
3848 for (i = 0; i < xri_cnt; i++) {
3849 list_remove_head(&nvmet_sgl_list,
3850 sglq_entry, struct lpfc_sglq, list);
3851 if (sglq_entry) {
3852 lpfc_nvmet_buf_free(phba, sglq_entry->virt,
3853 sglq_entry->phys);
3854 kfree(sglq_entry);
3855 }
3856 }
3857 list_splice_init(&nvmet_sgl_list,
3858 &phba->sli4_hba.lpfc_nvmet_sgl_list);
3859 spin_unlock(&phba->sli4_hba.sgl_list_lock);
3860 spin_unlock_irq(&phba->hbalock);
3861 } else
3862 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3863 "6306 NVMET xri-sgl count unchanged: %d\n",
3864 nvmet_xri_cnt);
3865 phba->sli4_hba.nvmet_xri_cnt = nvmet_xri_cnt;
3866
3867
3868 sglq_entry = NULL;
3869 sglq_entry_next = NULL;
3870 list_for_each_entry_safe(sglq_entry, sglq_entry_next,
3871 &phba->sli4_hba.lpfc_nvmet_sgl_list, list) {
3872 lxri = lpfc_sli4_next_xritag(phba);
3873 if (lxri == NO_XRI) {
3874 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3875 "6307 Failed to allocate xri for "
3876 "NVMET sgl\n");
3877 rc = -ENOMEM;
3878 goto out_free_mem;
3879 }
3880 sglq_entry->sli4_lxritag = lxri;
3881 sglq_entry->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
3882 }
3883 return 0;
3884
3885out_free_mem:
3886 lpfc_free_nvmet_sgl_list(phba);
3887 return rc;
3888}
3889
3890int
3891lpfc_io_buf_flush(struct lpfc_hba *phba, struct list_head *cbuf)
3892{
3893 LIST_HEAD(blist);
3894 struct lpfc_sli4_hdw_queue *qp;
3895 struct lpfc_io_buf *lpfc_cmd;
3896 struct lpfc_io_buf *iobufp, *prev_iobufp;
3897 int idx, cnt, xri, inserted;
3898
3899 cnt = 0;
3900 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
3901 qp = &phba->sli4_hba.hdwq[idx];
3902 spin_lock_irq(&qp->io_buf_list_get_lock);
3903 spin_lock(&qp->io_buf_list_put_lock);
3904
3905
3906 list_splice_init(&qp->lpfc_io_buf_list_get, &blist);
3907 list_splice(&qp->lpfc_io_buf_list_put, &blist);
3908 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_get);
3909 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_put);
3910 cnt += qp->get_io_bufs + qp->put_io_bufs;
3911 qp->get_io_bufs = 0;
3912 qp->put_io_bufs = 0;
3913 qp->total_io_bufs = 0;
3914 spin_unlock(&qp->io_buf_list_put_lock);
3915 spin_unlock_irq(&qp->io_buf_list_get_lock);
3916 }
3917
3918
3919
3920
3921
3922
3923 for (idx = 0; idx < cnt; idx++) {
3924 list_remove_head(&blist, lpfc_cmd, struct lpfc_io_buf, list);
3925 if (!lpfc_cmd)
3926 return cnt;
3927 if (idx == 0) {
3928 list_add_tail(&lpfc_cmd->list, cbuf);
3929 continue;
3930 }
3931 xri = lpfc_cmd->cur_iocbq.sli4_xritag;
3932 inserted = 0;
3933 prev_iobufp = NULL;
3934 list_for_each_entry(iobufp, cbuf, list) {
3935 if (xri < iobufp->cur_iocbq.sli4_xritag) {
3936 if (prev_iobufp)
3937 list_add(&lpfc_cmd->list,
3938 &prev_iobufp->list);
3939 else
3940 list_add(&lpfc_cmd->list, cbuf);
3941 inserted = 1;
3942 break;
3943 }
3944 prev_iobufp = iobufp;
3945 }
3946 if (!inserted)
3947 list_add_tail(&lpfc_cmd->list, cbuf);
3948 }
3949 return cnt;
3950}
3951
3952int
3953lpfc_io_buf_replenish(struct lpfc_hba *phba, struct list_head *cbuf)
3954{
3955 struct lpfc_sli4_hdw_queue *qp;
3956 struct lpfc_io_buf *lpfc_cmd;
3957 int idx, cnt;
3958
3959 qp = phba->sli4_hba.hdwq;
3960 cnt = 0;
3961 while (!list_empty(cbuf)) {
3962 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
3963 list_remove_head(cbuf, lpfc_cmd,
3964 struct lpfc_io_buf, list);
3965 if (!lpfc_cmd)
3966 return cnt;
3967 cnt++;
3968 qp = &phba->sli4_hba.hdwq[idx];
3969 lpfc_cmd->hdwq_no = idx;
3970 lpfc_cmd->hdwq = qp;
3971 lpfc_cmd->cur_iocbq.wqe_cmpl = NULL;
3972 lpfc_cmd->cur_iocbq.iocb_cmpl = NULL;
3973 spin_lock(&qp->io_buf_list_put_lock);
3974 list_add_tail(&lpfc_cmd->list,
3975 &qp->lpfc_io_buf_list_put);
3976 qp->put_io_bufs++;
3977 qp->total_io_bufs++;
3978 spin_unlock(&qp->io_buf_list_put_lock);
3979 }
3980 }
3981 return cnt;
3982}
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996int
3997lpfc_sli4_io_sgl_update(struct lpfc_hba *phba)
3998{
3999 struct lpfc_io_buf *lpfc_ncmd = NULL, *lpfc_ncmd_next = NULL;
4000 uint16_t i, lxri, els_xri_cnt;
4001 uint16_t io_xri_cnt, io_xri_max;
4002 LIST_HEAD(io_sgl_list);
4003 int rc, cnt;
4004
4005
4006
4007
4008
4009
4010 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
4011 io_xri_max = phba->sli4_hba.max_cfg_param.max_xri - els_xri_cnt;
4012 phba->sli4_hba.io_xri_max = io_xri_max;
4013
4014 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
4015 "6074 Current allocated XRI sgl count:%d, "
4016 "maximum XRI count:%d\n",
4017 phba->sli4_hba.io_xri_cnt,
4018 phba->sli4_hba.io_xri_max);
4019
4020 cnt = lpfc_io_buf_flush(phba, &io_sgl_list);
4021
4022 if (phba->sli4_hba.io_xri_cnt > phba->sli4_hba.io_xri_max) {
4023
4024 io_xri_cnt = phba->sli4_hba.io_xri_cnt -
4025 phba->sli4_hba.io_xri_max;
4026
4027 for (i = 0; i < io_xri_cnt; i++) {
4028 list_remove_head(&io_sgl_list, lpfc_ncmd,
4029 struct lpfc_io_buf, list);
4030 if (lpfc_ncmd) {
4031 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
4032 lpfc_ncmd->data,
4033 lpfc_ncmd->dma_handle);
4034 kfree(lpfc_ncmd);
4035 }
4036 }
4037 phba->sli4_hba.io_xri_cnt -= io_xri_cnt;
4038 }
4039
4040
4041 lpfc_ncmd = NULL;
4042 lpfc_ncmd_next = NULL;
4043 phba->sli4_hba.io_xri_cnt = cnt;
4044 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
4045 &io_sgl_list, list) {
4046 lxri = lpfc_sli4_next_xritag(phba);
4047 if (lxri == NO_XRI) {
4048 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4049 "6075 Failed to allocate xri for "
4050 "nvme buffer\n");
4051 rc = -ENOMEM;
4052 goto out_free_mem;
4053 }
4054 lpfc_ncmd->cur_iocbq.sli4_lxritag = lxri;
4055 lpfc_ncmd->cur_iocbq.sli4_xritag = phba->sli4_hba.xri_ids[lxri];
4056 }
4057 cnt = lpfc_io_buf_replenish(phba, &io_sgl_list);
4058 return 0;
4059
4060out_free_mem:
4061 lpfc_io_free(phba);
4062 return rc;
4063}
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076
4077
4078
4079int
4080lpfc_new_io_buf(struct lpfc_hba *phba, int num_to_alloc)
4081{
4082 struct lpfc_io_buf *lpfc_ncmd;
4083 struct lpfc_iocbq *pwqeq;
4084 uint16_t iotag, lxri = 0;
4085 int bcnt, num_posted;
4086 LIST_HEAD(prep_nblist);
4087 LIST_HEAD(post_nblist);
4088 LIST_HEAD(nvme_nblist);
4089
4090 phba->sli4_hba.io_xri_cnt = 0;
4091 for (bcnt = 0; bcnt < num_to_alloc; bcnt++) {
4092 lpfc_ncmd = kzalloc(sizeof(*lpfc_ncmd), GFP_KERNEL);
4093 if (!lpfc_ncmd)
4094 break;
4095
4096
4097
4098
4099
4100 lpfc_ncmd->data = dma_pool_zalloc(phba->lpfc_sg_dma_buf_pool,
4101 GFP_KERNEL,
4102 &lpfc_ncmd->dma_handle);
4103 if (!lpfc_ncmd->data) {
4104 kfree(lpfc_ncmd);
4105 break;
4106 }
4107
4108 if (phba->cfg_xpsgl && !phba->nvmet_support) {
4109 INIT_LIST_HEAD(&lpfc_ncmd->dma_sgl_xtra_list);
4110 } else {
4111
4112
4113
4114
4115 if ((phba->sli3_options & LPFC_SLI3_BG_ENABLED) &&
4116 (((unsigned long)(lpfc_ncmd->data) &
4117 (unsigned long)(SLI4_PAGE_SIZE - 1)) != 0)) {
4118 lpfc_printf_log(phba, KERN_ERR, LOG_FCP,
4119 "3369 Memory alignment err: "
4120 "addr=%lx\n",
4121 (unsigned long)lpfc_ncmd->data);
4122 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
4123 lpfc_ncmd->data,
4124 lpfc_ncmd->dma_handle);
4125 kfree(lpfc_ncmd);
4126 break;
4127 }
4128 }
4129
4130 INIT_LIST_HEAD(&lpfc_ncmd->dma_cmd_rsp_list);
4131
4132 lxri = lpfc_sli4_next_xritag(phba);
4133 if (lxri == NO_XRI) {
4134 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
4135 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
4136 kfree(lpfc_ncmd);
4137 break;
4138 }
4139 pwqeq = &lpfc_ncmd->cur_iocbq;
4140
4141
4142 iotag = lpfc_sli_next_iotag(phba, pwqeq);
4143 if (iotag == 0) {
4144 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
4145 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
4146 kfree(lpfc_ncmd);
4147 lpfc_printf_log(phba, KERN_ERR, LOG_NVME_IOERR,
4148 "6121 Failed to allocate IOTAG for"
4149 " XRI:0x%x\n", lxri);
4150 lpfc_sli4_free_xri(phba, lxri);
4151 break;
4152 }
4153 pwqeq->sli4_lxritag = lxri;
4154 pwqeq->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
4155 pwqeq->context1 = lpfc_ncmd;
4156
4157
4158 lpfc_ncmd->dma_sgl = lpfc_ncmd->data;
4159 lpfc_ncmd->dma_phys_sgl = lpfc_ncmd->dma_handle;
4160 lpfc_ncmd->cur_iocbq.context1 = lpfc_ncmd;
4161 spin_lock_init(&lpfc_ncmd->buf_lock);
4162
4163
4164 list_add_tail(&lpfc_ncmd->list, &post_nblist);
4165 phba->sli4_hba.io_xri_cnt++;
4166 }
4167 lpfc_printf_log(phba, KERN_INFO, LOG_NVME,
4168 "6114 Allocate %d out of %d requested new NVME "
4169 "buffers\n", bcnt, num_to_alloc);
4170
4171
4172 if (!list_empty(&post_nblist))
4173 num_posted = lpfc_sli4_post_io_sgl_list(
4174 phba, &post_nblist, bcnt);
4175 else
4176 num_posted = 0;
4177
4178 return num_posted;
4179}
4180
4181static uint64_t
4182lpfc_get_wwpn(struct lpfc_hba *phba)
4183{
4184 uint64_t wwn;
4185 int rc;
4186 LPFC_MBOXQ_t *mboxq;
4187 MAILBOX_t *mb;
4188
4189 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
4190 GFP_KERNEL);
4191 if (!mboxq)
4192 return (uint64_t)-1;
4193
4194
4195 lpfc_read_nv(phba, mboxq);
4196 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
4197 if (rc != MBX_SUCCESS) {
4198 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4199 "6019 Mailbox failed , mbxCmd x%x "
4200 "READ_NV, mbxStatus x%x\n",
4201 bf_get(lpfc_mqe_command, &mboxq->u.mqe),
4202 bf_get(lpfc_mqe_status, &mboxq->u.mqe));
4203 mempool_free(mboxq, phba->mbox_mem_pool);
4204 return (uint64_t) -1;
4205 }
4206 mb = &mboxq->u.mb;
4207 memcpy(&wwn, (char *)mb->un.varRDnvp.portname, sizeof(uint64_t));
4208
4209 mempool_free(mboxq, phba->mbox_mem_pool);
4210 if (phba->sli_rev == LPFC_SLI_REV4)
4211 return be64_to_cpu(wwn);
4212 else
4213 return rol64(wwn, 32);
4214}
4215
4216
4217
4218
4219
4220
4221
4222
4223
4224
4225
4226
4227
4228
4229
4230
4231
4232struct lpfc_vport *
4233lpfc_create_port(struct lpfc_hba *phba, int instance, struct device *dev)
4234{
4235 struct lpfc_vport *vport;
4236 struct Scsi_Host *shost = NULL;
4237 int error = 0;
4238 int i;
4239 uint64_t wwn;
4240 bool use_no_reset_hba = false;
4241 int rc;
4242
4243 if (lpfc_no_hba_reset_cnt) {
4244 if (phba->sli_rev < LPFC_SLI_REV4 &&
4245 dev == &phba->pcidev->dev) {
4246
4247 lpfc_sli_brdrestart(phba);
4248 rc = lpfc_sli_chipset_init(phba);
4249 if (rc)
4250 return NULL;
4251 }
4252 wwn = lpfc_get_wwpn(phba);
4253 }
4254
4255 for (i = 0; i < lpfc_no_hba_reset_cnt; i++) {
4256 if (wwn == lpfc_no_hba_reset[i]) {
4257 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4258 "6020 Setting use_no_reset port=%llx\n",
4259 wwn);
4260 use_no_reset_hba = true;
4261 break;
4262 }
4263 }
4264
4265 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) {
4266 if (dev != &phba->pcidev->dev) {
4267 shost = scsi_host_alloc(&lpfc_vport_template,
4268 sizeof(struct lpfc_vport));
4269 } else {
4270 if (!use_no_reset_hba)
4271 shost = scsi_host_alloc(&lpfc_template,
4272 sizeof(struct lpfc_vport));
4273 else
4274 shost = scsi_host_alloc(&lpfc_template_no_hr,
4275 sizeof(struct lpfc_vport));
4276 }
4277 } else if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
4278 shost = scsi_host_alloc(&lpfc_template_nvme,
4279 sizeof(struct lpfc_vport));
4280 }
4281 if (!shost)
4282 goto out;
4283
4284 vport = (struct lpfc_vport *) shost->hostdata;
4285 vport->phba = phba;
4286 vport->load_flag |= FC_LOADING;
4287 vport->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
4288 vport->fc_rscn_flush = 0;
4289 lpfc_get_vport_cfgparam(vport);
4290
4291
4292 vport->cfg_enable_fc4_type = phba->cfg_enable_fc4_type;
4293
4294 shost->unique_id = instance;
4295 shost->max_id = LPFC_MAX_TARGET;
4296 shost->max_lun = vport->cfg_max_luns;
4297 shost->this_id = -1;
4298 shost->max_cmd_len = 16;
4299
4300 if (phba->sli_rev == LPFC_SLI_REV4) {
4301 if (!phba->cfg_fcp_mq_threshold ||
4302 phba->cfg_fcp_mq_threshold > phba->cfg_hdw_queue)
4303 phba->cfg_fcp_mq_threshold = phba->cfg_hdw_queue;
4304
4305 shost->nr_hw_queues = min_t(int, 2 * num_possible_nodes(),
4306 phba->cfg_fcp_mq_threshold);
4307
4308 shost->dma_boundary =
4309 phba->sli4_hba.pc_sli4_params.sge_supp_len-1;
4310
4311 if (phba->cfg_xpsgl && !phba->nvmet_support)
4312 shost->sg_tablesize = LPFC_MAX_SG_TABLESIZE;
4313 else
4314 shost->sg_tablesize = phba->cfg_scsi_seg_cnt;
4315 } else
4316
4317
4318
4319 shost->nr_hw_queues = 1;
4320
4321
4322
4323
4324
4325
4326 shost->can_queue = phba->cfg_hba_queue_depth - 10;
4327 if (dev != &phba->pcidev->dev) {
4328 shost->transportt = lpfc_vport_transport_template;
4329 vport->port_type = LPFC_NPIV_PORT;
4330 } else {
4331 shost->transportt = lpfc_transport_template;
4332 vport->port_type = LPFC_PHYSICAL_PORT;
4333 }
4334
4335
4336 INIT_LIST_HEAD(&vport->fc_nodes);
4337 INIT_LIST_HEAD(&vport->rcv_buffer_list);
4338 spin_lock_init(&vport->work_port_lock);
4339
4340 timer_setup(&vport->fc_disctmo, lpfc_disc_timeout, 0);
4341
4342 timer_setup(&vport->els_tmofunc, lpfc_els_timeout, 0);
4343
4344 timer_setup(&vport->delayed_disc_tmo, lpfc_delayed_disc_tmo, 0);
4345
4346 if (phba->sli3_options & LPFC_SLI3_BG_ENABLED)
4347 lpfc_setup_bg(phba, shost);
4348
4349 error = scsi_add_host_with_dma(shost, dev, &phba->pcidev->dev);
4350 if (error)
4351 goto out_put_shost;
4352
4353 spin_lock_irq(&phba->port_list_lock);
4354 list_add_tail(&vport->listentry, &phba->port_list);
4355 spin_unlock_irq(&phba->port_list_lock);
4356 return vport;
4357
4358out_put_shost:
4359 scsi_host_put(shost);
4360out:
4361 return NULL;
4362}
4363
4364
4365
4366
4367
4368
4369
4370
4371void
4372destroy_port(struct lpfc_vport *vport)
4373{
4374 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
4375 struct lpfc_hba *phba = vport->phba;
4376
4377 lpfc_debugfs_terminate(vport);
4378 fc_remove_host(shost);
4379 scsi_remove_host(shost);
4380
4381 spin_lock_irq(&phba->port_list_lock);
4382 list_del_init(&vport->listentry);
4383 spin_unlock_irq(&phba->port_list_lock);
4384
4385 lpfc_cleanup(vport);
4386 return;
4387}
4388
4389
4390
4391
4392
4393
4394
4395
4396
4397
4398
4399int
4400lpfc_get_instance(void)
4401{
4402 int ret;
4403
4404 ret = idr_alloc(&lpfc_hba_index, NULL, 0, 0, GFP_KERNEL);
4405 return ret < 0 ? -1 : ret;
4406}
4407
4408
4409
4410
4411
4412
4413
4414
4415
4416
4417
4418
4419
4420
4421
4422
4423int lpfc_scan_finished(struct Scsi_Host *shost, unsigned long time)
4424{
4425 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
4426 struct lpfc_hba *phba = vport->phba;
4427 int stat = 0;
4428
4429 spin_lock_irq(shost->host_lock);
4430
4431 if (vport->load_flag & FC_UNLOADING) {
4432 stat = 1;
4433 goto finished;
4434 }
4435 if (time >= msecs_to_jiffies(30 * 1000)) {
4436 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
4437 "0461 Scanning longer than 30 "
4438 "seconds. Continuing initialization\n");
4439 stat = 1;
4440 goto finished;
4441 }
4442 if (time >= msecs_to_jiffies(15 * 1000) &&
4443 phba->link_state <= LPFC_LINK_DOWN) {
4444 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
4445 "0465 Link down longer than 15 "
4446 "seconds. Continuing initialization\n");
4447 stat = 1;
4448 goto finished;
4449 }
4450
4451 if (vport->port_state != LPFC_VPORT_READY)
4452 goto finished;
4453 if (vport->num_disc_nodes || vport->fc_prli_sent)
4454 goto finished;
4455 if (vport->fc_map_cnt == 0 && time < msecs_to_jiffies(2 * 1000))
4456 goto finished;
4457 if ((phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) != 0)
4458 goto finished;
4459
4460 stat = 1;
4461
4462finished:
4463 spin_unlock_irq(shost->host_lock);
4464 return stat;
4465}
4466
4467static void lpfc_host_supported_speeds_set(struct Scsi_Host *shost)
4468{
4469 struct lpfc_vport *vport = (struct lpfc_vport *)shost->hostdata;
4470 struct lpfc_hba *phba = vport->phba;
4471
4472 fc_host_supported_speeds(shost) = 0;
4473 if (phba->lmt & LMT_128Gb)
4474 fc_host_supported_speeds(shost) |= FC_PORTSPEED_128GBIT;
4475 if (phba->lmt & LMT_64Gb)
4476 fc_host_supported_speeds(shost) |= FC_PORTSPEED_64GBIT;
4477 if (phba->lmt & LMT_32Gb)
4478 fc_host_supported_speeds(shost) |= FC_PORTSPEED_32GBIT;
4479 if (phba->lmt & LMT_16Gb)
4480 fc_host_supported_speeds(shost) |= FC_PORTSPEED_16GBIT;
4481 if (phba->lmt & LMT_10Gb)
4482 fc_host_supported_speeds(shost) |= FC_PORTSPEED_10GBIT;
4483 if (phba->lmt & LMT_8Gb)
4484 fc_host_supported_speeds(shost) |= FC_PORTSPEED_8GBIT;
4485 if (phba->lmt & LMT_4Gb)
4486 fc_host_supported_speeds(shost) |= FC_PORTSPEED_4GBIT;
4487 if (phba->lmt & LMT_2Gb)
4488 fc_host_supported_speeds(shost) |= FC_PORTSPEED_2GBIT;
4489 if (phba->lmt & LMT_1Gb)
4490 fc_host_supported_speeds(shost) |= FC_PORTSPEED_1GBIT;
4491}
4492
4493
4494
4495
4496
4497
4498
4499
4500void lpfc_host_attrib_init(struct Scsi_Host *shost)
4501{
4502 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
4503 struct lpfc_hba *phba = vport->phba;
4504
4505
4506
4507
4508 fc_host_node_name(shost) = wwn_to_u64(vport->fc_nodename.u.wwn);
4509 fc_host_port_name(shost) = wwn_to_u64(vport->fc_portname.u.wwn);
4510 fc_host_supported_classes(shost) = FC_COS_CLASS3;
4511
4512 memset(fc_host_supported_fc4s(shost), 0,
4513 sizeof(fc_host_supported_fc4s(shost)));
4514 fc_host_supported_fc4s(shost)[2] = 1;
4515 fc_host_supported_fc4s(shost)[7] = 1;
4516
4517 lpfc_vport_symbolic_node_name(vport, fc_host_symbolic_name(shost),
4518 sizeof fc_host_symbolic_name(shost));
4519
4520 lpfc_host_supported_speeds_set(shost);
4521
4522 fc_host_maxframe_size(shost) =
4523 (((uint32_t) vport->fc_sparam.cmn.bbRcvSizeMsb & 0x0F) << 8) |
4524 (uint32_t) vport->fc_sparam.cmn.bbRcvSizeLsb;
4525
4526 fc_host_dev_loss_tmo(shost) = vport->cfg_devloss_tmo;
4527
4528
4529 memset(fc_host_active_fc4s(shost), 0,
4530 sizeof(fc_host_active_fc4s(shost)));
4531 fc_host_active_fc4s(shost)[2] = 1;
4532 fc_host_active_fc4s(shost)[7] = 1;
4533
4534 fc_host_max_npiv_vports(shost) = phba->max_vpi;
4535 spin_lock_irq(shost->host_lock);
4536 vport->load_flag &= ~FC_LOADING;
4537 spin_unlock_irq(shost->host_lock);
4538}
4539
4540
4541
4542
4543
4544
4545
4546
4547
4548static void
4549lpfc_stop_port_s3(struct lpfc_hba *phba)
4550{
4551
4552 writel(0, phba->HCregaddr);
4553 readl(phba->HCregaddr);
4554
4555 writel(0xffffffff, phba->HAregaddr);
4556 readl(phba->HAregaddr);
4557
4558
4559 lpfc_stop_hba_timers(phba);
4560 phba->pport->work_port_events = 0;
4561}
4562
4563
4564
4565
4566
4567
4568
4569
4570
4571static void
4572lpfc_stop_port_s4(struct lpfc_hba *phba)
4573{
4574
4575 lpfc_stop_hba_timers(phba);
4576 if (phba->pport)
4577 phba->pport->work_port_events = 0;
4578 phba->sli4_hba.intr_enable = 0;
4579}
4580
4581
4582
4583
4584
4585
4586
4587
4588void
4589lpfc_stop_port(struct lpfc_hba *phba)
4590{
4591 phba->lpfc_stop_port(phba);
4592
4593 if (phba->wq)
4594 flush_workqueue(phba->wq);
4595}
4596
4597
4598
4599
4600
4601
4602
4603void
4604lpfc_fcf_redisc_wait_start_timer(struct lpfc_hba *phba)
4605{
4606 unsigned long fcf_redisc_wait_tmo =
4607 (jiffies + msecs_to_jiffies(LPFC_FCF_REDISCOVER_WAIT_TMO));
4608
4609 mod_timer(&phba->fcf.redisc_wait, fcf_redisc_wait_tmo);
4610 spin_lock_irq(&phba->hbalock);
4611
4612 phba->fcf.fcf_flag &= ~(FCF_AVAILABLE | FCF_SCAN_DONE);
4613
4614 phba->fcf.fcf_flag |= FCF_REDISC_PEND;
4615 spin_unlock_irq(&phba->hbalock);
4616}
4617
4618
4619
4620
4621
4622
4623
4624
4625
4626
4627
4628static void
4629lpfc_sli4_fcf_redisc_wait_tmo(struct timer_list *t)
4630{
4631 struct lpfc_hba *phba = from_timer(phba, t, fcf.redisc_wait);
4632
4633
4634 spin_lock_irq(&phba->hbalock);
4635 if (!(phba->fcf.fcf_flag & FCF_REDISC_PEND)) {
4636 spin_unlock_irq(&phba->hbalock);
4637 return;
4638 }
4639
4640 phba->fcf.fcf_flag &= ~FCF_REDISC_PEND;
4641
4642 phba->fcf.fcf_flag |= FCF_REDISC_EVT;
4643 spin_unlock_irq(&phba->hbalock);
4644 lpfc_printf_log(phba, KERN_INFO, LOG_FIP,
4645 "2776 FCF rediscover quiescent timer expired\n");
4646
4647 lpfc_worker_wake_up(phba);
4648}
4649
4650
4651
4652
4653
4654
4655
4656
4657static void
4658lpfc_sli4_parse_latt_fault(struct lpfc_hba *phba,
4659 struct lpfc_acqe_link *acqe_link)
4660{
4661 switch (bf_get(lpfc_acqe_link_fault, acqe_link)) {
4662 case LPFC_ASYNC_LINK_FAULT_NONE:
4663 case LPFC_ASYNC_LINK_FAULT_LOCAL:
4664 case LPFC_ASYNC_LINK_FAULT_REMOTE:
4665 case LPFC_ASYNC_LINK_FAULT_LR_LRR:
4666 break;
4667 default:
4668 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
4669 "0398 Unknown link fault code: x%x\n",
4670 bf_get(lpfc_acqe_link_fault, acqe_link));
4671 break;
4672 }
4673}
4674
4675
4676
4677
4678
4679
4680
4681
4682
4683
4684
4685static uint8_t
4686lpfc_sli4_parse_latt_type(struct lpfc_hba *phba,
4687 struct lpfc_acqe_link *acqe_link)
4688{
4689 uint8_t att_type;
4690
4691 switch (bf_get(lpfc_acqe_link_status, acqe_link)) {
4692 case LPFC_ASYNC_LINK_STATUS_DOWN:
4693 case LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN:
4694 att_type = LPFC_ATT_LINK_DOWN;
4695 break;
4696 case LPFC_ASYNC_LINK_STATUS_UP:
4697
4698 att_type = LPFC_ATT_RESERVED;
4699 break;
4700 case LPFC_ASYNC_LINK_STATUS_LOGICAL_UP:
4701 att_type = LPFC_ATT_LINK_UP;
4702 break;
4703 default:
4704 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
4705 "0399 Invalid link attention type: x%x\n",
4706 bf_get(lpfc_acqe_link_status, acqe_link));
4707 att_type = LPFC_ATT_RESERVED;
4708 break;
4709 }
4710 return att_type;
4711}
4712
4713
4714
4715
4716
4717
4718
4719
4720
4721uint32_t
4722lpfc_sli_port_speed_get(struct lpfc_hba *phba)
4723{
4724 uint32_t link_speed;
4725
4726 if (!lpfc_is_link_up(phba))
4727 return 0;
4728
4729 if (phba->sli_rev <= LPFC_SLI_REV3) {
4730 switch (phba->fc_linkspeed) {
4731 case LPFC_LINK_SPEED_1GHZ:
4732 link_speed = 1000;
4733 break;
4734 case LPFC_LINK_SPEED_2GHZ:
4735 link_speed = 2000;
4736 break;
4737 case LPFC_LINK_SPEED_4GHZ:
4738 link_speed = 4000;
4739 break;
4740 case LPFC_LINK_SPEED_8GHZ:
4741 link_speed = 8000;
4742 break;
4743 case LPFC_LINK_SPEED_10GHZ:
4744 link_speed = 10000;
4745 break;
4746 case LPFC_LINK_SPEED_16GHZ:
4747 link_speed = 16000;
4748 break;
4749 default:
4750 link_speed = 0;
4751 }
4752 } else {
4753 if (phba->sli4_hba.link_state.logical_speed)
4754 link_speed =
4755 phba->sli4_hba.link_state.logical_speed;
4756 else
4757 link_speed = phba->sli4_hba.link_state.speed;
4758 }
4759 return link_speed;
4760}
4761
4762
4763
4764
4765
4766
4767
4768
4769
4770
4771
4772
4773static uint32_t
4774lpfc_sli4_port_speed_parse(struct lpfc_hba *phba, uint32_t evt_code,
4775 uint8_t speed_code)
4776{
4777 uint32_t port_speed;
4778
4779 switch (evt_code) {
4780 case LPFC_TRAILER_CODE_LINK:
4781 switch (speed_code) {
4782 case LPFC_ASYNC_LINK_SPEED_ZERO:
4783 port_speed = 0;
4784 break;
4785 case LPFC_ASYNC_LINK_SPEED_10MBPS:
4786 port_speed = 10;
4787 break;
4788 case LPFC_ASYNC_LINK_SPEED_100MBPS:
4789 port_speed = 100;
4790 break;
4791 case LPFC_ASYNC_LINK_SPEED_1GBPS:
4792 port_speed = 1000;
4793 break;
4794 case LPFC_ASYNC_LINK_SPEED_10GBPS:
4795 port_speed = 10000;
4796 break;
4797 case LPFC_ASYNC_LINK_SPEED_20GBPS:
4798 port_speed = 20000;
4799 break;
4800 case LPFC_ASYNC_LINK_SPEED_25GBPS:
4801 port_speed = 25000;
4802 break;
4803 case LPFC_ASYNC_LINK_SPEED_40GBPS:
4804 port_speed = 40000;
4805 break;
4806 default:
4807 port_speed = 0;
4808 }
4809 break;
4810 case LPFC_TRAILER_CODE_FC:
4811 switch (speed_code) {
4812 case LPFC_FC_LA_SPEED_UNKNOWN:
4813 port_speed = 0;
4814 break;
4815 case LPFC_FC_LA_SPEED_1G:
4816 port_speed = 1000;
4817 break;
4818 case LPFC_FC_LA_SPEED_2G:
4819 port_speed = 2000;
4820 break;
4821 case LPFC_FC_LA_SPEED_4G:
4822 port_speed = 4000;
4823 break;
4824 case LPFC_FC_LA_SPEED_8G:
4825 port_speed = 8000;
4826 break;
4827 case LPFC_FC_LA_SPEED_10G:
4828 port_speed = 10000;
4829 break;
4830 case LPFC_FC_LA_SPEED_16G:
4831 port_speed = 16000;
4832 break;
4833 case LPFC_FC_LA_SPEED_32G:
4834 port_speed = 32000;
4835 break;
4836 case LPFC_FC_LA_SPEED_64G:
4837 port_speed = 64000;
4838 break;
4839 case LPFC_FC_LA_SPEED_128G:
4840 port_speed = 128000;
4841 break;
4842 default:
4843 port_speed = 0;
4844 }
4845 break;
4846 default:
4847 port_speed = 0;
4848 }
4849 return port_speed;
4850}
4851
4852
4853
4854
4855
4856
4857
4858
4859static void
4860lpfc_sli4_async_link_evt(struct lpfc_hba *phba,
4861 struct lpfc_acqe_link *acqe_link)
4862{
4863 struct lpfc_dmabuf *mp;
4864 LPFC_MBOXQ_t *pmb;
4865 MAILBOX_t *mb;
4866 struct lpfc_mbx_read_top *la;
4867 uint8_t att_type;
4868 int rc;
4869
4870 att_type = lpfc_sli4_parse_latt_type(phba, acqe_link);
4871 if (att_type != LPFC_ATT_LINK_DOWN && att_type != LPFC_ATT_LINK_UP)
4872 return;
4873 phba->fcoe_eventtag = acqe_link->event_tag;
4874 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
4875 if (!pmb) {
4876 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4877 "0395 The mboxq allocation failed\n");
4878 return;
4879 }
4880 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
4881 if (!mp) {
4882 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4883 "0396 The lpfc_dmabuf allocation failed\n");
4884 goto out_free_pmb;
4885 }
4886 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
4887 if (!mp->virt) {
4888 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4889 "0397 The mbuf allocation failed\n");
4890 goto out_free_dmabuf;
4891 }
4892
4893
4894 lpfc_els_flush_all_cmd(phba);
4895
4896
4897 phba->sli4_hba.els_wq->pring->flag |= LPFC_STOP_IOCB_EVENT;
4898
4899
4900 phba->sli.slistat.link_event++;
4901
4902
4903 lpfc_read_topology(phba, pmb, mp);
4904 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
4905 pmb->vport = phba->pport;
4906
4907
4908 phba->sli4_hba.link_state.speed =
4909 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_LINK,
4910 bf_get(lpfc_acqe_link_speed, acqe_link));
4911 phba->sli4_hba.link_state.duplex =
4912 bf_get(lpfc_acqe_link_duplex, acqe_link);
4913 phba->sli4_hba.link_state.status =
4914 bf_get(lpfc_acqe_link_status, acqe_link);
4915 phba->sli4_hba.link_state.type =
4916 bf_get(lpfc_acqe_link_type, acqe_link);
4917 phba->sli4_hba.link_state.number =
4918 bf_get(lpfc_acqe_link_number, acqe_link);
4919 phba->sli4_hba.link_state.fault =
4920 bf_get(lpfc_acqe_link_fault, acqe_link);
4921 phba->sli4_hba.link_state.logical_speed =
4922 bf_get(lpfc_acqe_logical_link_speed, acqe_link) * 10;
4923
4924 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
4925 "2900 Async FC/FCoE Link event - Speed:%dGBit "
4926 "duplex:x%x LA Type:x%x Port Type:%d Port Number:%d "
4927 "Logical speed:%dMbps Fault:%d\n",
4928 phba->sli4_hba.link_state.speed,
4929 phba->sli4_hba.link_state.topology,
4930 phba->sli4_hba.link_state.status,
4931 phba->sli4_hba.link_state.type,
4932 phba->sli4_hba.link_state.number,
4933 phba->sli4_hba.link_state.logical_speed,
4934 phba->sli4_hba.link_state.fault);
4935
4936
4937
4938
4939 if (!(phba->hba_flag & HBA_FCOE_MODE)) {
4940 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
4941 if (rc == MBX_NOT_FINISHED)
4942 goto out_free_dmabuf;
4943 return;
4944 }
4945
4946
4947
4948
4949
4950
4951 mb = &pmb->u.mb;
4952 mb->mbxStatus = MBX_SUCCESS;
4953
4954
4955 lpfc_sli4_parse_latt_fault(phba, acqe_link);
4956
4957
4958 la = (struct lpfc_mbx_read_top *) &pmb->u.mb.un.varReadTop;
4959 la->eventTag = acqe_link->event_tag;
4960 bf_set(lpfc_mbx_read_top_att_type, la, att_type);
4961 bf_set(lpfc_mbx_read_top_link_spd, la,
4962 (bf_get(lpfc_acqe_link_speed, acqe_link)));
4963
4964
4965 bf_set(lpfc_mbx_read_top_topology, la, LPFC_TOPOLOGY_PT_PT);
4966 bf_set(lpfc_mbx_read_top_alpa_granted, la, 0);
4967 bf_set(lpfc_mbx_read_top_il, la, 0);
4968 bf_set(lpfc_mbx_read_top_pb, la, 0);
4969 bf_set(lpfc_mbx_read_top_fa, la, 0);
4970 bf_set(lpfc_mbx_read_top_mm, la, 0);
4971
4972
4973 lpfc_mbx_cmpl_read_topology(phba, pmb);
4974
4975 return;
4976
4977out_free_dmabuf:
4978 kfree(mp);
4979out_free_pmb:
4980 mempool_free(pmb, phba->mbox_mem_pool);
4981}
4982
4983
4984
4985
4986
4987
4988
4989
4990
4991
4992
4993
4994
4995static uint8_t
4996lpfc_async_link_speed_to_read_top(struct lpfc_hba *phba, uint8_t speed_code)
4997{
4998 uint8_t port_speed;
4999
5000 switch (speed_code) {
5001 case LPFC_FC_LA_SPEED_1G:
5002 port_speed = LPFC_LINK_SPEED_1GHZ;
5003 break;
5004 case LPFC_FC_LA_SPEED_2G:
5005 port_speed = LPFC_LINK_SPEED_2GHZ;
5006 break;
5007 case LPFC_FC_LA_SPEED_4G:
5008 port_speed = LPFC_LINK_SPEED_4GHZ;
5009 break;
5010 case LPFC_FC_LA_SPEED_8G:
5011 port_speed = LPFC_LINK_SPEED_8GHZ;
5012 break;
5013 case LPFC_FC_LA_SPEED_16G:
5014 port_speed = LPFC_LINK_SPEED_16GHZ;
5015 break;
5016 case LPFC_FC_LA_SPEED_32G:
5017 port_speed = LPFC_LINK_SPEED_32GHZ;
5018 break;
5019 case LPFC_FC_LA_SPEED_64G:
5020 port_speed = LPFC_LINK_SPEED_64GHZ;
5021 break;
5022 case LPFC_FC_LA_SPEED_128G:
5023 port_speed = LPFC_LINK_SPEED_128GHZ;
5024 break;
5025 case LPFC_FC_LA_SPEED_256G:
5026 port_speed = LPFC_LINK_SPEED_256GHZ;
5027 break;
5028 default:
5029 port_speed = 0;
5030 break;
5031 }
5032
5033 return port_speed;
5034}
5035
5036#define trunk_link_status(__idx)\
5037 bf_get(lpfc_acqe_fc_la_trunk_config_port##__idx, acqe_fc) ?\
5038 ((phba->trunk_link.link##__idx.state == LPFC_LINK_UP) ?\
5039 "Link up" : "Link down") : "NA"
5040
5041#define trunk_port_fault(__idx)\
5042 bf_get(lpfc_acqe_fc_la_trunk_config_port##__idx, acqe_fc) ?\
5043 (port_fault & (1 << __idx) ? "YES" : "NO") : "NA"
5044
5045static void
5046lpfc_update_trunk_link_status(struct lpfc_hba *phba,
5047 struct lpfc_acqe_fc_la *acqe_fc)
5048{
5049 uint8_t port_fault = bf_get(lpfc_acqe_fc_la_trunk_linkmask, acqe_fc);
5050 uint8_t err = bf_get(lpfc_acqe_fc_la_trunk_fault, acqe_fc);
5051
5052 phba->sli4_hba.link_state.speed =
5053 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_FC,
5054 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
5055
5056 phba->sli4_hba.link_state.logical_speed =
5057 bf_get(lpfc_acqe_fc_la_llink_spd, acqe_fc) * 10;
5058
5059 phba->fc_linkspeed =
5060 lpfc_async_link_speed_to_read_top(
5061 phba,
5062 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
5063
5064 if (bf_get(lpfc_acqe_fc_la_trunk_config_port0, acqe_fc)) {
5065 phba->trunk_link.link0.state =
5066 bf_get(lpfc_acqe_fc_la_trunk_link_status_port0, acqe_fc)
5067 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
5068 phba->trunk_link.link0.fault = port_fault & 0x1 ? err : 0;
5069 }
5070 if (bf_get(lpfc_acqe_fc_la_trunk_config_port1, acqe_fc)) {
5071 phba->trunk_link.link1.state =
5072 bf_get(lpfc_acqe_fc_la_trunk_link_status_port1, acqe_fc)
5073 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
5074 phba->trunk_link.link1.fault = port_fault & 0x2 ? err : 0;
5075 }
5076 if (bf_get(lpfc_acqe_fc_la_trunk_config_port2, acqe_fc)) {
5077 phba->trunk_link.link2.state =
5078 bf_get(lpfc_acqe_fc_la_trunk_link_status_port2, acqe_fc)
5079 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
5080 phba->trunk_link.link2.fault = port_fault & 0x4 ? err : 0;
5081 }
5082 if (bf_get(lpfc_acqe_fc_la_trunk_config_port3, acqe_fc)) {
5083 phba->trunk_link.link3.state =
5084 bf_get(lpfc_acqe_fc_la_trunk_link_status_port3, acqe_fc)
5085 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
5086 phba->trunk_link.link3.fault = port_fault & 0x8 ? err : 0;
5087 }
5088
5089 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5090 "2910 Async FC Trunking Event - Speed:%d\n"
5091 "\tLogical speed:%d "
5092 "port0: %s port1: %s port2: %s port3: %s\n",
5093 phba->sli4_hba.link_state.speed,
5094 phba->sli4_hba.link_state.logical_speed,
5095 trunk_link_status(0), trunk_link_status(1),
5096 trunk_link_status(2), trunk_link_status(3));
5097
5098 if (port_fault)
5099 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5100 "3202 trunk error:0x%x (%s) seen on port0:%s "
5101
5102
5103
5104
5105
5106 "port1:%s port2:%s port3:%s\n", err, err > 0xA ?
5107 "UNDEFINED. update driver." : trunk_errmsg[err],
5108 trunk_port_fault(0), trunk_port_fault(1),
5109 trunk_port_fault(2), trunk_port_fault(3));
5110}
5111
5112
5113
5114
5115
5116
5117
5118
5119
5120
5121
5122static void
5123lpfc_sli4_async_fc_evt(struct lpfc_hba *phba, struct lpfc_acqe_fc_la *acqe_fc)
5124{
5125 struct lpfc_dmabuf *mp;
5126 LPFC_MBOXQ_t *pmb;
5127 MAILBOX_t *mb;
5128 struct lpfc_mbx_read_top *la;
5129 int rc;
5130
5131 if (bf_get(lpfc_trailer_type, acqe_fc) !=
5132 LPFC_FC_LA_EVENT_TYPE_FC_LINK) {
5133 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5134 "2895 Non FC link Event detected.(%d)\n",
5135 bf_get(lpfc_trailer_type, acqe_fc));
5136 return;
5137 }
5138
5139 if (bf_get(lpfc_acqe_fc_la_att_type, acqe_fc) ==
5140 LPFC_FC_LA_TYPE_TRUNKING_EVENT) {
5141 lpfc_update_trunk_link_status(phba, acqe_fc);
5142 return;
5143 }
5144
5145
5146 phba->sli4_hba.link_state.speed =
5147 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_FC,
5148 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
5149 phba->sli4_hba.link_state.duplex = LPFC_ASYNC_LINK_DUPLEX_FULL;
5150 phba->sli4_hba.link_state.topology =
5151 bf_get(lpfc_acqe_fc_la_topology, acqe_fc);
5152 phba->sli4_hba.link_state.status =
5153 bf_get(lpfc_acqe_fc_la_att_type, acqe_fc);
5154 phba->sli4_hba.link_state.type =
5155 bf_get(lpfc_acqe_fc_la_port_type, acqe_fc);
5156 phba->sli4_hba.link_state.number =
5157 bf_get(lpfc_acqe_fc_la_port_number, acqe_fc);
5158 phba->sli4_hba.link_state.fault =
5159 bf_get(lpfc_acqe_link_fault, acqe_fc);
5160
5161 if (bf_get(lpfc_acqe_fc_la_att_type, acqe_fc) ==
5162 LPFC_FC_LA_TYPE_LINK_DOWN)
5163 phba->sli4_hba.link_state.logical_speed = 0;
5164 else if (!phba->sli4_hba.conf_trunk)
5165 phba->sli4_hba.link_state.logical_speed =
5166 bf_get(lpfc_acqe_fc_la_llink_spd, acqe_fc) * 10;
5167
5168 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5169 "2896 Async FC event - Speed:%dGBaud Topology:x%x "
5170 "LA Type:x%x Port Type:%d Port Number:%d Logical speed:"
5171 "%dMbps Fault:%d\n",
5172 phba->sli4_hba.link_state.speed,
5173 phba->sli4_hba.link_state.topology,
5174 phba->sli4_hba.link_state.status,
5175 phba->sli4_hba.link_state.type,
5176 phba->sli4_hba.link_state.number,
5177 phba->sli4_hba.link_state.logical_speed,
5178 phba->sli4_hba.link_state.fault);
5179 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
5180 if (!pmb) {
5181 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5182 "2897 The mboxq allocation failed\n");
5183 return;
5184 }
5185 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
5186 if (!mp) {
5187 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5188 "2898 The lpfc_dmabuf allocation failed\n");
5189 goto out_free_pmb;
5190 }
5191 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
5192 if (!mp->virt) {
5193 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5194 "2899 The mbuf allocation failed\n");
5195 goto out_free_dmabuf;
5196 }
5197
5198
5199 lpfc_els_flush_all_cmd(phba);
5200
5201
5202 phba->sli4_hba.els_wq->pring->flag |= LPFC_STOP_IOCB_EVENT;
5203
5204
5205 phba->sli.slistat.link_event++;
5206
5207
5208 lpfc_read_topology(phba, pmb, mp);
5209 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
5210 pmb->vport = phba->pport;
5211
5212 if (phba->sli4_hba.link_state.status != LPFC_FC_LA_TYPE_LINK_UP) {
5213 phba->link_flag &= ~(LS_MDS_LINK_DOWN | LS_MDS_LOOPBACK);
5214
5215 switch (phba->sli4_hba.link_state.status) {
5216 case LPFC_FC_LA_TYPE_MDS_LINK_DOWN:
5217 phba->link_flag |= LS_MDS_LINK_DOWN;
5218 break;
5219 case LPFC_FC_LA_TYPE_MDS_LOOPBACK:
5220 phba->link_flag |= LS_MDS_LOOPBACK;
5221 break;
5222 default:
5223 break;
5224 }
5225
5226
5227 mb = &pmb->u.mb;
5228 mb->mbxStatus = MBX_SUCCESS;
5229
5230
5231 lpfc_sli4_parse_latt_fault(phba, (void *)acqe_fc);
5232
5233
5234 la = (struct lpfc_mbx_read_top *)&pmb->u.mb.un.varReadTop;
5235 la->eventTag = acqe_fc->event_tag;
5236
5237 if (phba->sli4_hba.link_state.status ==
5238 LPFC_FC_LA_TYPE_UNEXP_WWPN) {
5239 bf_set(lpfc_mbx_read_top_att_type, la,
5240 LPFC_FC_LA_TYPE_UNEXP_WWPN);
5241 } else {
5242 bf_set(lpfc_mbx_read_top_att_type, la,
5243 LPFC_FC_LA_TYPE_LINK_DOWN);
5244 }
5245
5246 lpfc_mbx_cmpl_read_topology(phba, pmb);
5247
5248 return;
5249 }
5250
5251 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
5252 if (rc == MBX_NOT_FINISHED)
5253 goto out_free_dmabuf;
5254 return;
5255
5256out_free_dmabuf:
5257 kfree(mp);
5258out_free_pmb:
5259 mempool_free(pmb, phba->mbox_mem_pool);
5260}
5261
5262
5263
5264
5265
5266
5267
5268
5269static void
5270lpfc_sli4_async_sli_evt(struct lpfc_hba *phba, struct lpfc_acqe_sli *acqe_sli)
5271{
5272 char port_name;
5273 char message[128];
5274 uint8_t status;
5275 uint8_t evt_type;
5276 uint8_t operational = 0;
5277 struct temp_event temp_event_data;
5278 struct lpfc_acqe_misconfigured_event *misconfigured;
5279 struct Scsi_Host *shost;
5280 struct lpfc_vport **vports;
5281 int rc, i;
5282
5283 evt_type = bf_get(lpfc_trailer_type, acqe_sli);
5284
5285 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5286 "2901 Async SLI event - Event Data1:x%08x Event Data2:"
5287 "x%08x SLI Event Type:%d\n",
5288 acqe_sli->event_data1, acqe_sli->event_data2,
5289 evt_type);
5290
5291 port_name = phba->Port[0];
5292 if (port_name == 0x00)
5293 port_name = '?';
5294
5295 switch (evt_type) {
5296 case LPFC_SLI_EVENT_TYPE_OVER_TEMP:
5297 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
5298 temp_event_data.event_code = LPFC_THRESHOLD_TEMP;
5299 temp_event_data.data = (uint32_t)acqe_sli->event_data1;
5300
5301 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
5302 "3190 Over Temperature:%d Celsius- Port Name %c\n",
5303 acqe_sli->event_data1, port_name);
5304
5305 phba->sfp_warning |= LPFC_TRANSGRESSION_HIGH_TEMPERATURE;
5306 shost = lpfc_shost_from_vport(phba->pport);
5307 fc_host_post_vendor_event(shost, fc_get_event_number(),
5308 sizeof(temp_event_data),
5309 (char *)&temp_event_data,
5310 SCSI_NL_VID_TYPE_PCI
5311 | PCI_VENDOR_ID_EMULEX);
5312 break;
5313 case LPFC_SLI_EVENT_TYPE_NORM_TEMP:
5314 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
5315 temp_event_data.event_code = LPFC_NORMAL_TEMP;
5316 temp_event_data.data = (uint32_t)acqe_sli->event_data1;
5317
5318 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5319 "3191 Normal Temperature:%d Celsius - Port Name %c\n",
5320 acqe_sli->event_data1, port_name);
5321
5322 shost = lpfc_shost_from_vport(phba->pport);
5323 fc_host_post_vendor_event(shost, fc_get_event_number(),
5324 sizeof(temp_event_data),
5325 (char *)&temp_event_data,
5326 SCSI_NL_VID_TYPE_PCI
5327 | PCI_VENDOR_ID_EMULEX);
5328 break;
5329 case LPFC_SLI_EVENT_TYPE_MISCONFIGURED:
5330 misconfigured = (struct lpfc_acqe_misconfigured_event *)
5331 &acqe_sli->event_data1;
5332
5333
5334 switch (phba->sli4_hba.lnk_info.lnk_no) {
5335 case LPFC_LINK_NUMBER_0:
5336 status = bf_get(lpfc_sli_misconfigured_port0_state,
5337 &misconfigured->theEvent);
5338 operational = bf_get(lpfc_sli_misconfigured_port0_op,
5339 &misconfigured->theEvent);
5340 break;
5341 case LPFC_LINK_NUMBER_1:
5342 status = bf_get(lpfc_sli_misconfigured_port1_state,
5343 &misconfigured->theEvent);
5344 operational = bf_get(lpfc_sli_misconfigured_port1_op,
5345 &misconfigured->theEvent);
5346 break;
5347 case LPFC_LINK_NUMBER_2:
5348 status = bf_get(lpfc_sli_misconfigured_port2_state,
5349 &misconfigured->theEvent);
5350 operational = bf_get(lpfc_sli_misconfigured_port2_op,
5351 &misconfigured->theEvent);
5352 break;
5353 case LPFC_LINK_NUMBER_3:
5354 status = bf_get(lpfc_sli_misconfigured_port3_state,
5355 &misconfigured->theEvent);
5356 operational = bf_get(lpfc_sli_misconfigured_port3_op,
5357 &misconfigured->theEvent);
5358 break;
5359 default:
5360 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5361 "3296 "
5362 "LPFC_SLI_EVENT_TYPE_MISCONFIGURED "
5363 "event: Invalid link %d",
5364 phba->sli4_hba.lnk_info.lnk_no);
5365 return;
5366 }
5367
5368
5369 if (phba->sli4_hba.lnk_info.optic_state == status)
5370 return;
5371
5372 switch (status) {
5373 case LPFC_SLI_EVENT_STATUS_VALID:
5374 sprintf(message, "Physical Link is functional");
5375 break;
5376 case LPFC_SLI_EVENT_STATUS_NOT_PRESENT:
5377 sprintf(message, "Optics faulted/incorrectly "
5378 "installed/not installed - Reseat optics, "
5379 "if issue not resolved, replace.");
5380 break;
5381 case LPFC_SLI_EVENT_STATUS_WRONG_TYPE:
5382 sprintf(message,
5383 "Optics of two types installed - Remove one "
5384 "optic or install matching pair of optics.");
5385 break;
5386 case LPFC_SLI_EVENT_STATUS_UNSUPPORTED:
5387 sprintf(message, "Incompatible optics - Replace with "
5388 "compatible optics for card to function.");
5389 break;
5390 case LPFC_SLI_EVENT_STATUS_UNQUALIFIED:
5391 sprintf(message, "Unqualified optics - Replace with "
5392 "Avago optics for Warranty and Technical "
5393 "Support - Link is%s operational",
5394 (operational) ? " not" : "");
5395 break;
5396 case LPFC_SLI_EVENT_STATUS_UNCERTIFIED:
5397 sprintf(message, "Uncertified optics - Replace with "
5398 "Avago-certified optics to enable link "
5399 "operation - Link is%s operational",
5400 (operational) ? " not" : "");
5401 break;
5402 default:
5403
5404 sprintf(message, "Unknown event status x%02x", status);
5405 break;
5406 }
5407
5408
5409 rc = lpfc_sli4_read_config(phba);
5410 if (rc) {
5411 phba->lmt = 0;
5412 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5413 "3194 Unable to retrieve supported "
5414 "speeds, rc = 0x%x\n", rc);
5415 }
5416 vports = lpfc_create_vport_work_array(phba);
5417 if (vports != NULL) {
5418 for (i = 0; i <= phba->max_vports && vports[i] != NULL;
5419 i++) {
5420 shost = lpfc_shost_from_vport(vports[i]);
5421 lpfc_host_supported_speeds_set(shost);
5422 }
5423 }
5424 lpfc_destroy_vport_work_array(phba, vports);
5425
5426 phba->sli4_hba.lnk_info.optic_state = status;
5427 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5428 "3176 Port Name %c %s\n", port_name, message);
5429 break;
5430 case LPFC_SLI_EVENT_TYPE_REMOTE_DPORT:
5431 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5432 "3192 Remote DPort Test Initiated - "
5433 "Event Data1:x%08x Event Data2: x%08x\n",
5434 acqe_sli->event_data1, acqe_sli->event_data2);
5435 break;
5436 default:
5437 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5438 "3193 Async SLI event - Event Data1:x%08x Event Data2:"
5439 "x%08x SLI Event Type:%d\n",
5440 acqe_sli->event_data1, acqe_sli->event_data2,
5441 evt_type);
5442 break;
5443 }
5444}
5445
5446
5447
5448
5449
5450
5451
5452
5453
5454
5455
5456static struct lpfc_nodelist *
5457lpfc_sli4_perform_vport_cvl(struct lpfc_vport *vport)
5458{
5459 struct lpfc_nodelist *ndlp;
5460 struct Scsi_Host *shost;
5461 struct lpfc_hba *phba;
5462
5463 if (!vport)
5464 return NULL;
5465 phba = vport->phba;
5466 if (!phba)
5467 return NULL;
5468 ndlp = lpfc_findnode_did(vport, Fabric_DID);
5469 if (!ndlp) {
5470
5471 ndlp = lpfc_nlp_init(vport, Fabric_DID);
5472 if (!ndlp)
5473 return 0;
5474
5475 ndlp->nlp_type |= NLP_FABRIC;
5476
5477 lpfc_enqueue_node(vport, ndlp);
5478 } else if (!NLP_CHK_NODE_ACT(ndlp)) {
5479
5480 ndlp = lpfc_enable_node(vport, ndlp, NLP_STE_UNUSED_NODE);
5481 if (!ndlp)
5482 return 0;
5483 }
5484 if ((phba->pport->port_state < LPFC_FLOGI) &&
5485 (phba->pport->port_state != LPFC_VPORT_FAILED))
5486 return NULL;
5487
5488 if ((vport != phba->pport) && (vport->port_state < LPFC_FDISC)
5489 && (vport->port_state != LPFC_VPORT_FAILED))
5490 return NULL;
5491 shost = lpfc_shost_from_vport(vport);
5492 if (!shost)
5493 return NULL;
5494 lpfc_linkdown_port(vport);
5495 lpfc_cleanup_pending_mbox(vport);
5496 spin_lock_irq(shost->host_lock);
5497 vport->fc_flag |= FC_VPORT_CVL_RCVD;
5498 spin_unlock_irq(shost->host_lock);
5499
5500 return ndlp;
5501}
5502
5503
5504
5505
5506
5507
5508
5509
5510static void
5511lpfc_sli4_perform_all_vport_cvl(struct lpfc_hba *phba)
5512{
5513 struct lpfc_vport **vports;
5514 int i;
5515
5516 vports = lpfc_create_vport_work_array(phba);
5517 if (vports)
5518 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++)
5519 lpfc_sli4_perform_vport_cvl(vports[i]);
5520 lpfc_destroy_vport_work_array(phba, vports);
5521}
5522
5523
5524
5525
5526
5527
5528
5529
5530static void
5531lpfc_sli4_async_fip_evt(struct lpfc_hba *phba,
5532 struct lpfc_acqe_fip *acqe_fip)
5533{
5534 uint8_t event_type = bf_get(lpfc_trailer_type, acqe_fip);
5535 int rc;
5536 struct lpfc_vport *vport;
5537 struct lpfc_nodelist *ndlp;
5538 struct Scsi_Host *shost;
5539 int active_vlink_present;
5540 struct lpfc_vport **vports;
5541 int i;
5542
5543 phba->fc_eventTag = acqe_fip->event_tag;
5544 phba->fcoe_eventtag = acqe_fip->event_tag;
5545 switch (event_type) {
5546 case LPFC_FIP_EVENT_TYPE_NEW_FCF:
5547 case LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD:
5548 if (event_type == LPFC_FIP_EVENT_TYPE_NEW_FCF)
5549 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
5550 LOG_DISCOVERY,
5551 "2546 New FCF event, evt_tag:x%x, "
5552 "index:x%x\n",
5553 acqe_fip->event_tag,
5554 acqe_fip->index);
5555 else
5556 lpfc_printf_log(phba, KERN_WARNING, LOG_FIP |
5557 LOG_DISCOVERY,
5558 "2788 FCF param modified event, "
5559 "evt_tag:x%x, index:x%x\n",
5560 acqe_fip->event_tag,
5561 acqe_fip->index);
5562 if (phba->fcf.fcf_flag & FCF_DISCOVERY) {
5563
5564
5565
5566
5567
5568 lpfc_printf_log(phba, KERN_INFO, LOG_FIP |
5569 LOG_DISCOVERY,
5570 "2779 Read FCF (x%x) for updating "
5571 "roundrobin FCF failover bmask\n",
5572 acqe_fip->index);
5573 rc = lpfc_sli4_read_fcf_rec(phba, acqe_fip->index);
5574 }
5575
5576
5577 spin_lock_irq(&phba->hbalock);
5578 if (phba->hba_flag & FCF_TS_INPROG) {
5579 spin_unlock_irq(&phba->hbalock);
5580 break;
5581 }
5582
5583 if (phba->fcf.fcf_flag & (FCF_REDISC_EVT | FCF_REDISC_PEND)) {
5584 spin_unlock_irq(&phba->hbalock);
5585 break;
5586 }
5587
5588
5589 if (phba->fcf.fcf_flag & FCF_SCAN_DONE) {
5590 spin_unlock_irq(&phba->hbalock);
5591 break;
5592 }
5593 spin_unlock_irq(&phba->hbalock);
5594
5595
5596 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
5597 "2770 Start FCF table scan per async FCF "
5598 "event, evt_tag:x%x, index:x%x\n",
5599 acqe_fip->event_tag, acqe_fip->index);
5600 rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba,
5601 LPFC_FCOE_FCF_GET_FIRST);
5602 if (rc)
5603 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
5604 "2547 Issue FCF scan read FCF mailbox "
5605 "command failed (x%x)\n", rc);
5606 break;
5607
5608 case LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL:
5609 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5610 "2548 FCF Table full count 0x%x tag 0x%x\n",
5611 bf_get(lpfc_acqe_fip_fcf_count, acqe_fip),
5612 acqe_fip->event_tag);
5613 break;
5614
5615 case LPFC_FIP_EVENT_TYPE_FCF_DEAD:
5616 phba->fcoe_cvl_eventtag = acqe_fip->event_tag;
5617 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
5618 "2549 FCF (x%x) disconnected from network, "
5619 "tag:x%x\n", acqe_fip->index, acqe_fip->event_tag);
5620
5621
5622
5623
5624 spin_lock_irq(&phba->hbalock);
5625 if ((phba->fcf.fcf_flag & FCF_DISCOVERY) &&
5626 (phba->fcf.current_rec.fcf_indx != acqe_fip->index)) {
5627 spin_unlock_irq(&phba->hbalock);
5628
5629 lpfc_sli4_fcf_rr_index_clear(phba, acqe_fip->index);
5630 break;
5631 }
5632 spin_unlock_irq(&phba->hbalock);
5633
5634
5635 if (phba->fcf.current_rec.fcf_indx != acqe_fip->index)
5636 break;
5637
5638
5639
5640
5641
5642
5643
5644 spin_lock_irq(&phba->hbalock);
5645
5646 phba->fcf.fcf_flag |= FCF_DEAD_DISC;
5647 spin_unlock_irq(&phba->hbalock);
5648
5649 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
5650 "2771 Start FCF fast failover process due to "
5651 "FCF DEAD event: evt_tag:x%x, fcf_index:x%x "
5652 "\n", acqe_fip->event_tag, acqe_fip->index);
5653 rc = lpfc_sli4_redisc_fcf_table(phba);
5654 if (rc) {
5655 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
5656 LOG_DISCOVERY,
5657 "2772 Issue FCF rediscover mailbox "
5658 "command failed, fail through to FCF "
5659 "dead event\n");
5660 spin_lock_irq(&phba->hbalock);
5661 phba->fcf.fcf_flag &= ~FCF_DEAD_DISC;
5662 spin_unlock_irq(&phba->hbalock);
5663
5664
5665
5666
5667 lpfc_sli4_fcf_dead_failthrough(phba);
5668 } else {
5669
5670 lpfc_sli4_clear_fcf_rr_bmask(phba);
5671
5672
5673
5674
5675 lpfc_sli4_perform_all_vport_cvl(phba);
5676 }
5677 break;
5678 case LPFC_FIP_EVENT_TYPE_CVL:
5679 phba->fcoe_cvl_eventtag = acqe_fip->event_tag;
5680 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
5681 "2718 Clear Virtual Link Received for VPI 0x%x"
5682 " tag 0x%x\n", acqe_fip->index, acqe_fip->event_tag);
5683
5684 vport = lpfc_find_vport_by_vpid(phba,
5685 acqe_fip->index);
5686 ndlp = lpfc_sli4_perform_vport_cvl(vport);
5687 if (!ndlp)
5688 break;
5689 active_vlink_present = 0;
5690
5691 vports = lpfc_create_vport_work_array(phba);
5692 if (vports) {
5693 for (i = 0; i <= phba->max_vports && vports[i] != NULL;
5694 i++) {
5695 if ((!(vports[i]->fc_flag &
5696 FC_VPORT_CVL_RCVD)) &&
5697 (vports[i]->port_state > LPFC_FDISC)) {
5698 active_vlink_present = 1;
5699 break;
5700 }
5701 }
5702 lpfc_destroy_vport_work_array(phba, vports);
5703 }
5704
5705
5706
5707
5708
5709
5710 if (!(vport->load_flag & FC_UNLOADING) &&
5711 active_vlink_present) {
5712
5713
5714
5715
5716 mod_timer(&ndlp->nlp_delayfunc,
5717 jiffies + msecs_to_jiffies(1000));
5718 shost = lpfc_shost_from_vport(vport);
5719 spin_lock_irq(shost->host_lock);
5720 ndlp->nlp_flag |= NLP_DELAY_TMO;
5721 spin_unlock_irq(shost->host_lock);
5722 ndlp->nlp_last_elscmd = ELS_CMD_FDISC;
5723 vport->port_state = LPFC_FDISC;
5724 } else {
5725
5726
5727
5728
5729
5730
5731
5732 spin_lock_irq(&phba->hbalock);
5733 if (phba->fcf.fcf_flag & FCF_DISCOVERY) {
5734 spin_unlock_irq(&phba->hbalock);
5735 break;
5736 }
5737
5738 phba->fcf.fcf_flag |= FCF_ACVL_DISC;
5739 spin_unlock_irq(&phba->hbalock);
5740 lpfc_printf_log(phba, KERN_INFO, LOG_FIP |
5741 LOG_DISCOVERY,
5742 "2773 Start FCF failover per CVL, "
5743 "evt_tag:x%x\n", acqe_fip->event_tag);
5744 rc = lpfc_sli4_redisc_fcf_table(phba);
5745 if (rc) {
5746 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
5747 LOG_DISCOVERY,
5748 "2774 Issue FCF rediscover "
5749 "mailbox command failed, "
5750 "through to CVL event\n");
5751 spin_lock_irq(&phba->hbalock);
5752 phba->fcf.fcf_flag &= ~FCF_ACVL_DISC;
5753 spin_unlock_irq(&phba->hbalock);
5754
5755
5756
5757
5758 lpfc_retry_pport_discovery(phba);
5759 } else
5760
5761
5762
5763
5764 lpfc_sli4_clear_fcf_rr_bmask(phba);
5765 }
5766 break;
5767 default:
5768 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5769 "0288 Unknown FCoE event type 0x%x event tag "
5770 "0x%x\n", event_type, acqe_fip->event_tag);
5771 break;
5772 }
5773}
5774
5775
5776
5777
5778
5779
5780
5781
5782static void
5783lpfc_sli4_async_dcbx_evt(struct lpfc_hba *phba,
5784 struct lpfc_acqe_dcbx *acqe_dcbx)
5785{
5786 phba->fc_eventTag = acqe_dcbx->event_tag;
5787 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5788 "0290 The SLI4 DCBX asynchronous event is not "
5789 "handled yet\n");
5790}
5791
5792
5793
5794
5795
5796
5797
5798
5799
5800
5801static void
5802lpfc_sli4_async_grp5_evt(struct lpfc_hba *phba,
5803 struct lpfc_acqe_grp5 *acqe_grp5)
5804{
5805 uint16_t prev_ll_spd;
5806
5807 phba->fc_eventTag = acqe_grp5->event_tag;
5808 phba->fcoe_eventtag = acqe_grp5->event_tag;
5809 prev_ll_spd = phba->sli4_hba.link_state.logical_speed;
5810 phba->sli4_hba.link_state.logical_speed =
5811 (bf_get(lpfc_acqe_grp5_llink_spd, acqe_grp5)) * 10;
5812 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5813 "2789 GRP5 Async Event: Updating logical link speed "
5814 "from %dMbps to %dMbps\n", prev_ll_spd,
5815 phba->sli4_hba.link_state.logical_speed);
5816}
5817
5818
5819
5820
5821
5822
5823
5824
5825void lpfc_sli4_async_event_proc(struct lpfc_hba *phba)
5826{
5827 struct lpfc_cq_event *cq_event;
5828
5829
5830 spin_lock_irq(&phba->hbalock);
5831 phba->hba_flag &= ~ASYNC_EVENT;
5832 spin_unlock_irq(&phba->hbalock);
5833
5834 while (!list_empty(&phba->sli4_hba.sp_asynce_work_queue)) {
5835
5836 spin_lock_irq(&phba->hbalock);
5837 list_remove_head(&phba->sli4_hba.sp_asynce_work_queue,
5838 cq_event, struct lpfc_cq_event, list);
5839 spin_unlock_irq(&phba->hbalock);
5840
5841 switch (bf_get(lpfc_trailer_code, &cq_event->cqe.mcqe_cmpl)) {
5842 case LPFC_TRAILER_CODE_LINK:
5843 lpfc_sli4_async_link_evt(phba,
5844 &cq_event->cqe.acqe_link);
5845 break;
5846 case LPFC_TRAILER_CODE_FCOE:
5847 lpfc_sli4_async_fip_evt(phba, &cq_event->cqe.acqe_fip);
5848 break;
5849 case LPFC_TRAILER_CODE_DCBX:
5850 lpfc_sli4_async_dcbx_evt(phba,
5851 &cq_event->cqe.acqe_dcbx);
5852 break;
5853 case LPFC_TRAILER_CODE_GRP5:
5854 lpfc_sli4_async_grp5_evt(phba,
5855 &cq_event->cqe.acqe_grp5);
5856 break;
5857 case LPFC_TRAILER_CODE_FC:
5858 lpfc_sli4_async_fc_evt(phba, &cq_event->cqe.acqe_fc);
5859 break;
5860 case LPFC_TRAILER_CODE_SLI:
5861 lpfc_sli4_async_sli_evt(phba, &cq_event->cqe.acqe_sli);
5862 break;
5863 default:
5864 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5865 "1804 Invalid asynchrous event code: "
5866 "x%x\n", bf_get(lpfc_trailer_code,
5867 &cq_event->cqe.mcqe_cmpl));
5868 break;
5869 }
5870
5871 lpfc_sli4_cq_event_release(phba, cq_event);
5872 }
5873}
5874
5875
5876
5877
5878
5879
5880
5881
5882void lpfc_sli4_fcf_redisc_event_proc(struct lpfc_hba *phba)
5883{
5884 int rc;
5885
5886 spin_lock_irq(&phba->hbalock);
5887
5888 phba->fcf.fcf_flag &= ~FCF_REDISC_EVT;
5889
5890 phba->fcf.failover_rec.flag = 0;
5891
5892 phba->fcf.fcf_flag |= FCF_REDISC_FOV;
5893 spin_unlock_irq(&phba->hbalock);
5894
5895
5896 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
5897 "2777 Start post-quiescent FCF table scan\n");
5898 rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba, LPFC_FCOE_FCF_GET_FIRST);
5899 if (rc)
5900 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
5901 "2747 Issue FCF scan read FCF mailbox "
5902 "command failed 0x%x\n", rc);
5903}
5904
5905
5906
5907
5908
5909
5910
5911
5912
5913
5914
5915int
5916lpfc_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)
5917{
5918 int rc;
5919
5920
5921 phba->pci_dev_grp = dev_grp;
5922
5923
5924 if (dev_grp == LPFC_PCI_DEV_OC)
5925 phba->sli_rev = LPFC_SLI_REV4;
5926
5927
5928 rc = lpfc_init_api_table_setup(phba, dev_grp);
5929 if (rc)
5930 return -ENODEV;
5931
5932 rc = lpfc_scsi_api_table_setup(phba, dev_grp);
5933 if (rc)
5934 return -ENODEV;
5935
5936 rc = lpfc_sli_api_table_setup(phba, dev_grp);
5937 if (rc)
5938 return -ENODEV;
5939
5940 rc = lpfc_mbox_api_table_setup(phba, dev_grp);
5941 if (rc)
5942 return -ENODEV;
5943
5944 return 0;
5945}
5946
5947
5948
5949
5950
5951
5952
5953
5954
5955static void lpfc_log_intr_mode(struct lpfc_hba *phba, uint32_t intr_mode)
5956{
5957 switch (intr_mode) {
5958 case 0:
5959 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
5960 "0470 Enable INTx interrupt mode.\n");
5961 break;
5962 case 1:
5963 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
5964 "0481 Enabled MSI interrupt mode.\n");
5965 break;
5966 case 2:
5967 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
5968 "0480 Enabled MSI-X interrupt mode.\n");
5969 break;
5970 default:
5971 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5972 "0482 Illegal interrupt mode.\n");
5973 break;
5974 }
5975 return;
5976}
5977
5978
5979
5980
5981
5982
5983
5984
5985
5986
5987
5988
5989static int
5990lpfc_enable_pci_dev(struct lpfc_hba *phba)
5991{
5992 struct pci_dev *pdev;
5993
5994
5995 if (!phba->pcidev)
5996 goto out_error;
5997 else
5998 pdev = phba->pcidev;
5999
6000 if (pci_enable_device_mem(pdev))
6001 goto out_error;
6002
6003 if (pci_request_mem_regions(pdev, LPFC_DRIVER_NAME))
6004 goto out_disable_device;
6005
6006 pci_set_master(pdev);
6007 pci_try_set_mwi(pdev);
6008 pci_save_state(pdev);
6009
6010
6011 if (pci_is_pcie(pdev))
6012 pdev->needs_freset = 1;
6013
6014 return 0;
6015
6016out_disable_device:
6017 pci_disable_device(pdev);
6018out_error:
6019 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6020 "1401 Failed to enable pci device\n");
6021 return -ENODEV;
6022}
6023
6024
6025
6026
6027
6028
6029
6030
6031static void
6032lpfc_disable_pci_dev(struct lpfc_hba *phba)
6033{
6034 struct pci_dev *pdev;
6035
6036
6037 if (!phba->pcidev)
6038 return;
6039 else
6040 pdev = phba->pcidev;
6041
6042 pci_release_mem_regions(pdev);
6043 pci_disable_device(pdev);
6044
6045 return;
6046}
6047
6048
6049
6050
6051
6052
6053
6054
6055
6056
6057void
6058lpfc_reset_hba(struct lpfc_hba *phba)
6059{
6060
6061 if (!phba->cfg_enable_hba_reset) {
6062 phba->link_state = LPFC_HBA_ERROR;
6063 return;
6064 }
6065 if (phba->sli.sli_flag & LPFC_SLI_ACTIVE)
6066 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
6067 else
6068 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
6069 lpfc_offline(phba);
6070 lpfc_sli_brdrestart(phba);
6071 lpfc_online(phba);
6072 lpfc_unblock_mgmt_io(phba);
6073}
6074
6075
6076
6077
6078
6079
6080
6081
6082
6083
6084
6085uint16_t
6086lpfc_sli_sriov_nr_virtfn_get(struct lpfc_hba *phba)
6087{
6088 struct pci_dev *pdev = phba->pcidev;
6089 uint16_t nr_virtfn;
6090 int pos;
6091
6092 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
6093 if (pos == 0)
6094 return 0;
6095
6096 pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF, &nr_virtfn);
6097 return nr_virtfn;
6098}
6099
6100
6101
6102
6103
6104
6105
6106
6107
6108
6109
6110
6111int
6112lpfc_sli_probe_sriov_nr_virtfn(struct lpfc_hba *phba, int nr_vfn)
6113{
6114 struct pci_dev *pdev = phba->pcidev;
6115 uint16_t max_nr_vfn;
6116 int rc;
6117
6118 max_nr_vfn = lpfc_sli_sriov_nr_virtfn_get(phba);
6119 if (nr_vfn > max_nr_vfn) {
6120 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6121 "3057 Requested vfs (%d) greater than "
6122 "supported vfs (%d)", nr_vfn, max_nr_vfn);
6123 return -EINVAL;
6124 }
6125
6126 rc = pci_enable_sriov(pdev, nr_vfn);
6127 if (rc) {
6128 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6129 "2806 Failed to enable sriov on this device "
6130 "with vfn number nr_vf:%d, rc:%d\n",
6131 nr_vfn, rc);
6132 } else
6133 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6134 "2807 Successful enable sriov on this device "
6135 "with vfn number nr_vf:%d\n", nr_vfn);
6136 return rc;
6137}
6138
6139
6140
6141
6142
6143
6144
6145
6146
6147
6148
6149
6150static int
6151lpfc_setup_driver_resource_phase1(struct lpfc_hba *phba)
6152{
6153 struct lpfc_sli *psli = &phba->sli;
6154
6155
6156
6157
6158 atomic_set(&phba->fast_event_count, 0);
6159 spin_lock_init(&phba->hbalock);
6160
6161
6162 spin_lock_init(&phba->ndlp_lock);
6163
6164
6165 spin_lock_init(&phba->port_list_lock);
6166 INIT_LIST_HEAD(&phba->port_list);
6167
6168 INIT_LIST_HEAD(&phba->work_list);
6169 init_waitqueue_head(&phba->wait_4_mlo_m_q);
6170
6171
6172 init_waitqueue_head(&phba->work_waitq);
6173
6174 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
6175 "1403 Protocols supported %s %s %s\n",
6176 ((phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) ?
6177 "SCSI" : " "),
6178 ((phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) ?
6179 "NVME" : " "),
6180 (phba->nvmet_support ? "NVMET" : " "));
6181
6182
6183 spin_lock_init(&phba->scsi_buf_list_get_lock);
6184 INIT_LIST_HEAD(&phba->lpfc_scsi_buf_list_get);
6185 spin_lock_init(&phba->scsi_buf_list_put_lock);
6186 INIT_LIST_HEAD(&phba->lpfc_scsi_buf_list_put);
6187
6188
6189 INIT_LIST_HEAD(&phba->fabric_iocb_list);
6190
6191
6192 INIT_LIST_HEAD(&phba->elsbuf);
6193
6194
6195 INIT_LIST_HEAD(&phba->fcf_conn_rec_list);
6196
6197
6198 spin_lock_init(&phba->devicelock);
6199 INIT_LIST_HEAD(&phba->luns);
6200
6201
6202 timer_setup(&psli->mbox_tmo, lpfc_mbox_timeout, 0);
6203
6204 timer_setup(&phba->fabric_block_timer, lpfc_fabric_block_timeout, 0);
6205
6206 timer_setup(&phba->eratt_poll, lpfc_poll_eratt, 0);
6207
6208 timer_setup(&phba->hb_tmofunc, lpfc_hb_timeout, 0);
6209
6210 INIT_DELAYED_WORK(&phba->eq_delay_work, lpfc_hb_eq_delay_work);
6211
6212 return 0;
6213}
6214
6215
6216
6217
6218
6219
6220
6221
6222
6223
6224
6225
6226static int
6227lpfc_sli_driver_resource_setup(struct lpfc_hba *phba)
6228{
6229 int rc, entry_sz;
6230
6231
6232
6233
6234
6235
6236 timer_setup(&phba->fcp_poll_timer, lpfc_poll_timeout, 0);
6237
6238
6239 phba->work_ha_mask = (HA_ERATT | HA_MBATT | HA_LATT);
6240 phba->work_ha_mask |= (HA_RXMASK << (LPFC_ELS_RING * 4));
6241
6242
6243 lpfc_get_cfgparam(phba);
6244
6245
6246 rc = lpfc_setup_driver_resource_phase1(phba);
6247 if (rc)
6248 return -ENODEV;
6249
6250 if (phba->pcidev->device == PCI_DEVICE_ID_HORNET) {
6251 phba->menlo_flag |= HBA_MENLO_SUPPORT;
6252
6253 if (phba->cfg_sg_seg_cnt < LPFC_DEFAULT_MENLO_SG_SEG_CNT)
6254 phba->cfg_sg_seg_cnt = LPFC_DEFAULT_MENLO_SG_SEG_CNT;
6255 }
6256
6257 if (!phba->sli.sli3_ring)
6258 phba->sli.sli3_ring = kcalloc(LPFC_SLI3_MAX_RING,
6259 sizeof(struct lpfc_sli_ring),
6260 GFP_KERNEL);
6261 if (!phba->sli.sli3_ring)
6262 return -ENOMEM;
6263
6264
6265
6266
6267
6268
6269
6270 lpfc_vport_template.sg_tablesize = phba->cfg_sg_seg_cnt;
6271 lpfc_template_no_hr.sg_tablesize = phba->cfg_sg_seg_cnt;
6272 lpfc_template.sg_tablesize = phba->cfg_sg_seg_cnt;
6273
6274 if (phba->sli_rev == LPFC_SLI_REV4)
6275 entry_sz = sizeof(struct sli4_sge);
6276 else
6277 entry_sz = sizeof(struct ulp_bde64);
6278
6279
6280 if (phba->cfg_enable_bg) {
6281
6282
6283
6284
6285
6286
6287
6288
6289
6290 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
6291 sizeof(struct fcp_rsp) +
6292 (LPFC_MAX_SG_SEG_CNT * entry_sz);
6293
6294 if (phba->cfg_sg_seg_cnt > LPFC_MAX_SG_SEG_CNT_DIF)
6295 phba->cfg_sg_seg_cnt = LPFC_MAX_SG_SEG_CNT_DIF;
6296
6297
6298 phba->cfg_total_seg_cnt = LPFC_MAX_SG_SEG_CNT;
6299 } else {
6300
6301
6302
6303
6304
6305 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
6306 sizeof(struct fcp_rsp) +
6307 ((phba->cfg_sg_seg_cnt + 2) * entry_sz);
6308
6309
6310 phba->cfg_total_seg_cnt = phba->cfg_sg_seg_cnt + 2;
6311 }
6312
6313 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_FCP,
6314 "9088 sg_tablesize:%d dmabuf_size:%d total_bde:%d\n",
6315 phba->cfg_sg_seg_cnt, phba->cfg_sg_dma_buf_size,
6316 phba->cfg_total_seg_cnt);
6317
6318 phba->max_vpi = LPFC_MAX_VPI;
6319
6320 phba->max_vports = 0;
6321
6322
6323
6324
6325 lpfc_sli_setup(phba);
6326 lpfc_sli_queue_init(phba);
6327
6328
6329 if (lpfc_mem_alloc(phba, BPL_ALIGN_SZ))
6330 return -ENOMEM;
6331
6332 phba->lpfc_sg_dma_buf_pool =
6333 dma_pool_create("lpfc_sg_dma_buf_pool",
6334 &phba->pcidev->dev, phba->cfg_sg_dma_buf_size,
6335 BPL_ALIGN_SZ, 0);
6336
6337 if (!phba->lpfc_sg_dma_buf_pool)
6338 goto fail_free_mem;
6339
6340 phba->lpfc_cmd_rsp_buf_pool =
6341 dma_pool_create("lpfc_cmd_rsp_buf_pool",
6342 &phba->pcidev->dev,
6343 sizeof(struct fcp_cmnd) +
6344 sizeof(struct fcp_rsp),
6345 BPL_ALIGN_SZ, 0);
6346
6347 if (!phba->lpfc_cmd_rsp_buf_pool)
6348 goto fail_free_dma_buf_pool;
6349
6350
6351
6352
6353
6354 if (phba->cfg_sriov_nr_virtfn > 0) {
6355 rc = lpfc_sli_probe_sriov_nr_virtfn(phba,
6356 phba->cfg_sriov_nr_virtfn);
6357 if (rc) {
6358 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6359 "2808 Requested number of SR-IOV "
6360 "virtual functions (%d) is not "
6361 "supported\n",
6362 phba->cfg_sriov_nr_virtfn);
6363 phba->cfg_sriov_nr_virtfn = 0;
6364 }
6365 }
6366
6367 return 0;
6368
6369fail_free_dma_buf_pool:
6370 dma_pool_destroy(phba->lpfc_sg_dma_buf_pool);
6371 phba->lpfc_sg_dma_buf_pool = NULL;
6372fail_free_mem:
6373 lpfc_mem_free(phba);
6374 return -ENOMEM;
6375}
6376
6377
6378
6379
6380
6381
6382
6383
6384static void
6385lpfc_sli_driver_resource_unset(struct lpfc_hba *phba)
6386{
6387
6388 lpfc_mem_free_all(phba);
6389
6390 return;
6391}
6392
6393
6394
6395
6396
6397
6398
6399
6400
6401
6402
6403
6404static int
6405lpfc_sli4_driver_resource_setup(struct lpfc_hba *phba)
6406{
6407 LPFC_MBOXQ_t *mboxq;
6408 MAILBOX_t *mb;
6409 int rc, i, max_buf_size;
6410 uint8_t pn_page[LPFC_MAX_SUPPORTED_PAGES] = {0};
6411 struct lpfc_mqe *mqe;
6412 int longs;
6413 int extra;
6414 uint64_t wwn;
6415 u32 if_type;
6416 u32 if_fam;
6417
6418 phba->sli4_hba.num_present_cpu = lpfc_present_cpu;
6419 phba->sli4_hba.num_possible_cpu = num_possible_cpus();
6420 phba->sli4_hba.curr_disp_cpu = 0;
6421
6422
6423 lpfc_get_cfgparam(phba);
6424
6425
6426 rc = lpfc_setup_driver_resource_phase1(phba);
6427 if (rc)
6428 return -ENODEV;
6429
6430
6431 rc = lpfc_sli4_post_status_check(phba);
6432 if (rc)
6433 return -ENODEV;
6434
6435
6436
6437
6438 phba->wq = alloc_workqueue("lpfc_wq", WQ_MEM_RECLAIM, 0);
6439
6440
6441
6442
6443
6444 timer_setup(&phba->rrq_tmr, lpfc_rrq_timeout, 0);
6445
6446
6447 timer_setup(&phba->fcf.redisc_wait, lpfc_sli4_fcf_redisc_wait_tmo, 0);
6448
6449
6450
6451
6452
6453 memset((uint8_t *)&phba->mbox_ext_buf_ctx, 0,
6454 sizeof(struct lpfc_mbox_ext_buf_ctx));
6455 INIT_LIST_HEAD(&phba->mbox_ext_buf_ctx.ext_dmabuf_list);
6456
6457 phba->max_vpi = LPFC_MAX_VPI;
6458
6459
6460 phba->max_vports = 0;
6461
6462
6463 phba->valid_vlan = 0;
6464 phba->fc_map[0] = LPFC_FCOE_FCF_MAP0;
6465 phba->fc_map[1] = LPFC_FCOE_FCF_MAP1;
6466 phba->fc_map[2] = LPFC_FCOE_FCF_MAP2;
6467
6468
6469
6470
6471
6472
6473
6474
6475 INIT_LIST_HEAD(&phba->hbqs[LPFC_ELS_HBQ].hbq_buffer_list);
6476 phba->hbqs[LPFC_ELS_HBQ].hbq_alloc_buffer = lpfc_sli4_rb_alloc;
6477 phba->hbqs[LPFC_ELS_HBQ].hbq_free_buffer = lpfc_sli4_rb_free;
6478
6479
6480
6481
6482
6483 spin_lock_init(&phba->sli4_hba.abts_io_buf_list_lock);
6484 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_io_buf_list);
6485
6486 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
6487
6488 spin_lock_init(&phba->sli4_hba.abts_nvmet_buf_list_lock);
6489 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
6490 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_nvmet_io_wait_list);
6491 spin_lock_init(&phba->sli4_hba.t_active_list_lock);
6492 INIT_LIST_HEAD(&phba->sli4_hba.t_active_ctx_list);
6493 }
6494
6495
6496 spin_lock_init(&phba->sli4_hba.sgl_list_lock);
6497 spin_lock_init(&phba->sli4_hba.nvmet_io_wait_lock);
6498
6499
6500
6501
6502
6503
6504 INIT_LIST_HEAD(&phba->sli4_hba.sp_cqe_event_pool);
6505
6506 INIT_LIST_HEAD(&phba->sli4_hba.sp_queue_event);
6507
6508 INIT_LIST_HEAD(&phba->sli4_hba.sp_asynce_work_queue);
6509
6510 INIT_LIST_HEAD(&phba->sli4_hba.sp_fcp_xri_aborted_work_queue);
6511
6512 INIT_LIST_HEAD(&phba->sli4_hba.sp_els_xri_aborted_work_queue);
6513
6514 INIT_LIST_HEAD(&phba->sli4_hba.sp_unsol_work_queue);
6515
6516
6517 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_rpi_blk_list);
6518 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_xri_blk_list);
6519 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_vfi_blk_list);
6520 INIT_LIST_HEAD(&phba->lpfc_vpi_blk_list);
6521
6522
6523
6524
6525 INIT_LIST_HEAD(&phba->sli.mboxq);
6526 INIT_LIST_HEAD(&phba->sli.mboxq_cmpl);
6527
6528
6529 phba->sli4_hba.lnk_info.optic_state = 0xff;
6530
6531
6532 rc = lpfc_mem_alloc(phba, SGL_ALIGN_SZ);
6533 if (rc)
6534 return -ENOMEM;
6535
6536
6537 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) >=
6538 LPFC_SLI_INTF_IF_TYPE_2) {
6539 rc = lpfc_pci_function_reset(phba);
6540 if (unlikely(rc)) {
6541 rc = -ENODEV;
6542 goto out_free_mem;
6543 }
6544 phba->temp_sensor_support = 1;
6545 }
6546
6547
6548 rc = lpfc_create_bootstrap_mbox(phba);
6549 if (unlikely(rc))
6550 goto out_free_mem;
6551
6552
6553 rc = lpfc_setup_endian_order(phba);
6554 if (unlikely(rc))
6555 goto out_free_bsmbx;
6556
6557
6558 rc = lpfc_sli4_read_config(phba);
6559 if (unlikely(rc))
6560 goto out_free_bsmbx;
6561 rc = lpfc_mem_alloc_active_rrq_pool_s4(phba);
6562 if (unlikely(rc))
6563 goto out_free_bsmbx;
6564
6565
6566 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
6567 LPFC_SLI_INTF_IF_TYPE_0) {
6568 rc = lpfc_pci_function_reset(phba);
6569 if (unlikely(rc))
6570 goto out_free_bsmbx;
6571 }
6572
6573 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
6574 GFP_KERNEL);
6575 if (!mboxq) {
6576 rc = -ENOMEM;
6577 goto out_free_bsmbx;
6578 }
6579
6580
6581 phba->nvmet_support = 0;
6582 if (lpfc_enable_nvmet_cnt) {
6583
6584
6585 lpfc_read_nv(phba, mboxq);
6586 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
6587 if (rc != MBX_SUCCESS) {
6588 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
6589 "6016 Mailbox failed , mbxCmd x%x "
6590 "READ_NV, mbxStatus x%x\n",
6591 bf_get(lpfc_mqe_command, &mboxq->u.mqe),
6592 bf_get(lpfc_mqe_status, &mboxq->u.mqe));
6593 mempool_free(mboxq, phba->mbox_mem_pool);
6594 rc = -EIO;
6595 goto out_free_bsmbx;
6596 }
6597 mb = &mboxq->u.mb;
6598 memcpy(&wwn, (char *)mb->un.varRDnvp.nodename,
6599 sizeof(uint64_t));
6600 wwn = cpu_to_be64(wwn);
6601 phba->sli4_hba.wwnn.u.name = wwn;
6602 memcpy(&wwn, (char *)mb->un.varRDnvp.portname,
6603 sizeof(uint64_t));
6604
6605 wwn = cpu_to_be64(wwn);
6606 phba->sli4_hba.wwpn.u.name = wwn;
6607
6608
6609 for (i = 0; i < lpfc_enable_nvmet_cnt; i++) {
6610 if (wwn == lpfc_enable_nvmet[i]) {
6611#if (IS_ENABLED(CONFIG_NVME_TARGET_FC))
6612 if (lpfc_nvmet_mem_alloc(phba))
6613 break;
6614
6615 phba->nvmet_support = 1;
6616
6617 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6618 "6017 NVME Target %016llx\n",
6619 wwn);
6620#else
6621 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6622 "6021 Can't enable NVME Target."
6623 " NVME_TARGET_FC infrastructure"
6624 " is not in kernel\n");
6625#endif
6626
6627 phba->cfg_xri_rebalancing = 0;
6628 break;
6629 }
6630 }
6631 }
6632
6633 lpfc_nvme_mod_param_dep(phba);
6634
6635
6636 lpfc_supported_pages(mboxq);
6637 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
6638 if (!rc) {
6639 mqe = &mboxq->u.mqe;
6640 memcpy(&pn_page[0], ((uint8_t *)&mqe->un.supp_pages.word3),
6641 LPFC_MAX_SUPPORTED_PAGES);
6642 for (i = 0; i < LPFC_MAX_SUPPORTED_PAGES; i++) {
6643 switch (pn_page[i]) {
6644 case LPFC_SLI4_PARAMETERS:
6645 phba->sli4_hba.pc_sli4_params.supported = 1;
6646 break;
6647 default:
6648 break;
6649 }
6650 }
6651
6652 if (phba->sli4_hba.pc_sli4_params.supported)
6653 rc = lpfc_pc_sli4_params_get(phba, mboxq);
6654 if (rc) {
6655 mempool_free(mboxq, phba->mbox_mem_pool);
6656 rc = -EIO;
6657 goto out_free_bsmbx;
6658 }
6659 }
6660
6661
6662
6663
6664
6665
6666 rc = lpfc_get_sli4_parameters(phba, mboxq);
6667 if (rc) {
6668 if_type = bf_get(lpfc_sli_intf_if_type,
6669 &phba->sli4_hba.sli_intf);
6670 if_fam = bf_get(lpfc_sli_intf_sli_family,
6671 &phba->sli4_hba.sli_intf);
6672 if (phba->sli4_hba.extents_in_use &&
6673 phba->sli4_hba.rpi_hdrs_in_use) {
6674 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6675 "2999 Unsupported SLI4 Parameters "
6676 "Extents and RPI headers enabled.\n");
6677 if (if_type == LPFC_SLI_INTF_IF_TYPE_0 &&
6678 if_fam == LPFC_SLI_INTF_FAMILY_BE2) {
6679 mempool_free(mboxq, phba->mbox_mem_pool);
6680 rc = -EIO;
6681 goto out_free_bsmbx;
6682 }
6683 }
6684 if (!(if_type == LPFC_SLI_INTF_IF_TYPE_0 &&
6685 if_fam == LPFC_SLI_INTF_FAMILY_BE2)) {
6686 mempool_free(mboxq, phba->mbox_mem_pool);
6687 rc = -EIO;
6688 goto out_free_bsmbx;
6689 }
6690 }
6691
6692
6693
6694
6695
6696 extra = 2;
6697 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
6698 extra++;
6699
6700
6701
6702
6703
6704
6705 max_buf_size = (2 * SLI4_PAGE_SIZE);
6706
6707
6708
6709
6710
6711 if (phba->sli3_options & LPFC_SLI3_BG_ENABLED) {
6712
6713
6714
6715
6716
6717
6718
6719
6720
6721
6722
6723 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
6724 sizeof(struct fcp_rsp) + max_buf_size;
6725
6726
6727 phba->cfg_total_seg_cnt = LPFC_MAX_SGL_SEG_CNT;
6728
6729
6730
6731
6732
6733 if (phba->cfg_enable_bg &&
6734 phba->cfg_sg_seg_cnt > LPFC_MAX_BG_SLI4_SEG_CNT_DIF)
6735 phba->cfg_scsi_seg_cnt = LPFC_MAX_BG_SLI4_SEG_CNT_DIF;
6736 else
6737 phba->cfg_scsi_seg_cnt = phba->cfg_sg_seg_cnt;
6738
6739 } else {
6740
6741
6742
6743
6744
6745 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
6746 sizeof(struct fcp_rsp) +
6747 ((phba->cfg_sg_seg_cnt + extra) *
6748 sizeof(struct sli4_sge));
6749
6750
6751 phba->cfg_total_seg_cnt = phba->cfg_sg_seg_cnt + extra;
6752 phba->cfg_scsi_seg_cnt = phba->cfg_sg_seg_cnt;
6753
6754
6755
6756
6757
6758 }
6759
6760 if (phba->cfg_xpsgl && !phba->nvmet_support)
6761 phba->cfg_sg_dma_buf_size = LPFC_DEFAULT_XPSGL_SIZE;
6762 else if (phba->cfg_sg_dma_buf_size <= LPFC_MIN_SG_SLI4_BUF_SZ)
6763 phba->cfg_sg_dma_buf_size = LPFC_MIN_SG_SLI4_BUF_SZ;
6764 else
6765 phba->cfg_sg_dma_buf_size =
6766 SLI4_PAGE_ALIGN(phba->cfg_sg_dma_buf_size);
6767
6768 phba->border_sge_num = phba->cfg_sg_dma_buf_size /
6769 sizeof(struct sli4_sge);
6770
6771
6772 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
6773 if (phba->cfg_sg_seg_cnt > LPFC_MAX_NVME_SEG_CNT) {
6774 lpfc_printf_log(phba, KERN_INFO, LOG_NVME | LOG_INIT,
6775 "6300 Reducing NVME sg segment "
6776 "cnt to %d\n",
6777 LPFC_MAX_NVME_SEG_CNT);
6778 phba->cfg_nvme_seg_cnt = LPFC_MAX_NVME_SEG_CNT;
6779 } else
6780 phba->cfg_nvme_seg_cnt = phba->cfg_sg_seg_cnt;
6781 }
6782
6783
6784 lpfc_vport_template.sg_tablesize = phba->cfg_scsi_seg_cnt;
6785 lpfc_template.sg_tablesize = phba->cfg_scsi_seg_cnt;
6786 lpfc_template_no_hr.sg_tablesize = phba->cfg_scsi_seg_cnt;
6787
6788 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_FCP,
6789 "9087 sg_seg_cnt:%d dmabuf_size:%d "
6790 "total:%d scsi:%d nvme:%d\n",
6791 phba->cfg_sg_seg_cnt, phba->cfg_sg_dma_buf_size,
6792 phba->cfg_total_seg_cnt, phba->cfg_scsi_seg_cnt,
6793 phba->cfg_nvme_seg_cnt);
6794
6795 if (phba->cfg_sg_dma_buf_size < SLI4_PAGE_SIZE)
6796 i = phba->cfg_sg_dma_buf_size;
6797 else
6798 i = SLI4_PAGE_SIZE;
6799
6800 phba->lpfc_sg_dma_buf_pool =
6801 dma_pool_create("lpfc_sg_dma_buf_pool",
6802 &phba->pcidev->dev,
6803 phba->cfg_sg_dma_buf_size,
6804 i, 0);
6805 if (!phba->lpfc_sg_dma_buf_pool)
6806 goto out_free_bsmbx;
6807
6808 phba->lpfc_cmd_rsp_buf_pool =
6809 dma_pool_create("lpfc_cmd_rsp_buf_pool",
6810 &phba->pcidev->dev,
6811 sizeof(struct fcp_cmnd) +
6812 sizeof(struct fcp_rsp),
6813 i, 0);
6814 if (!phba->lpfc_cmd_rsp_buf_pool)
6815 goto out_free_sg_dma_buf;
6816
6817 mempool_free(mboxq, phba->mbox_mem_pool);
6818
6819
6820 lpfc_sli4_oas_verify(phba);
6821
6822
6823 lpfc_sli4_ras_init(phba);
6824
6825
6826 rc = lpfc_sli4_queue_verify(phba);
6827 if (rc)
6828 goto out_free_cmd_rsp_buf;
6829
6830
6831 rc = lpfc_sli4_cq_event_pool_create(phba);
6832 if (rc)
6833 goto out_free_cmd_rsp_buf;
6834
6835
6836 lpfc_init_sgl_list(phba);
6837
6838
6839 rc = lpfc_init_active_sgl_array(phba);
6840 if (rc) {
6841 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6842 "1430 Failed to initialize sgl list.\n");
6843 goto out_destroy_cq_event_pool;
6844 }
6845 rc = lpfc_sli4_init_rpi_hdrs(phba);
6846 if (rc) {
6847 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6848 "1432 Failed to initialize rpi headers.\n");
6849 goto out_free_active_sgl;
6850 }
6851
6852
6853 longs = (LPFC_SLI4_FCF_TBL_INDX_MAX + BITS_PER_LONG - 1)/BITS_PER_LONG;
6854 phba->fcf.fcf_rr_bmask = kcalloc(longs, sizeof(unsigned long),
6855 GFP_KERNEL);
6856 if (!phba->fcf.fcf_rr_bmask) {
6857 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6858 "2759 Failed allocate memory for FCF round "
6859 "robin failover bmask\n");
6860 rc = -ENOMEM;
6861 goto out_remove_rpi_hdrs;
6862 }
6863
6864 phba->sli4_hba.hba_eq_hdl = kcalloc(phba->cfg_irq_chann,
6865 sizeof(struct lpfc_hba_eq_hdl),
6866 GFP_KERNEL);
6867 if (!phba->sli4_hba.hba_eq_hdl) {
6868 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6869 "2572 Failed allocate memory for "
6870 "fast-path per-EQ handle array\n");
6871 rc = -ENOMEM;
6872 goto out_free_fcf_rr_bmask;
6873 }
6874
6875 phba->sli4_hba.cpu_map = kcalloc(phba->sli4_hba.num_possible_cpu,
6876 sizeof(struct lpfc_vector_map_info),
6877 GFP_KERNEL);
6878 if (!phba->sli4_hba.cpu_map) {
6879 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6880 "3327 Failed allocate memory for msi-x "
6881 "interrupt vector mapping\n");
6882 rc = -ENOMEM;
6883 goto out_free_hba_eq_hdl;
6884 }
6885
6886 phba->sli4_hba.eq_info = alloc_percpu(struct lpfc_eq_intr_info);
6887 if (!phba->sli4_hba.eq_info) {
6888 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6889 "3321 Failed allocation for per_cpu stats\n");
6890 rc = -ENOMEM;
6891 goto out_free_hba_cpu_map;
6892 }
6893
6894
6895
6896
6897 if (phba->cfg_sriov_nr_virtfn > 0) {
6898 rc = lpfc_sli_probe_sriov_nr_virtfn(phba,
6899 phba->cfg_sriov_nr_virtfn);
6900 if (rc) {
6901 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6902 "3020 Requested number of SR-IOV "
6903 "virtual functions (%d) is not "
6904 "supported\n",
6905 phba->cfg_sriov_nr_virtfn);
6906 phba->cfg_sriov_nr_virtfn = 0;
6907 }
6908 }
6909
6910 return 0;
6911
6912out_free_hba_cpu_map:
6913 kfree(phba->sli4_hba.cpu_map);
6914out_free_hba_eq_hdl:
6915 kfree(phba->sli4_hba.hba_eq_hdl);
6916out_free_fcf_rr_bmask:
6917 kfree(phba->fcf.fcf_rr_bmask);
6918out_remove_rpi_hdrs:
6919 lpfc_sli4_remove_rpi_hdrs(phba);
6920out_free_active_sgl:
6921 lpfc_free_active_sgl(phba);
6922out_destroy_cq_event_pool:
6923 lpfc_sli4_cq_event_pool_destroy(phba);
6924out_free_cmd_rsp_buf:
6925 dma_pool_destroy(phba->lpfc_cmd_rsp_buf_pool);
6926 phba->lpfc_cmd_rsp_buf_pool = NULL;
6927out_free_sg_dma_buf:
6928 dma_pool_destroy(phba->lpfc_sg_dma_buf_pool);
6929 phba->lpfc_sg_dma_buf_pool = NULL;
6930out_free_bsmbx:
6931 lpfc_destroy_bootstrap_mbox(phba);
6932out_free_mem:
6933 lpfc_mem_free(phba);
6934 return rc;
6935}
6936
6937
6938
6939
6940
6941
6942
6943
6944static void
6945lpfc_sli4_driver_resource_unset(struct lpfc_hba *phba)
6946{
6947 struct lpfc_fcf_conn_entry *conn_entry, *next_conn_entry;
6948
6949 free_percpu(phba->sli4_hba.eq_info);
6950
6951
6952 kfree(phba->sli4_hba.cpu_map);
6953 phba->sli4_hba.num_possible_cpu = 0;
6954 phba->sli4_hba.num_present_cpu = 0;
6955 phba->sli4_hba.curr_disp_cpu = 0;
6956
6957
6958 kfree(phba->sli4_hba.hba_eq_hdl);
6959
6960
6961 lpfc_sli4_remove_rpi_hdrs(phba);
6962 lpfc_sli4_remove_rpis(phba);
6963
6964
6965 kfree(phba->fcf.fcf_rr_bmask);
6966
6967
6968 lpfc_free_active_sgl(phba);
6969 lpfc_free_els_sgl_list(phba);
6970 lpfc_free_nvmet_sgl_list(phba);
6971
6972
6973 lpfc_sli4_cq_event_release_all(phba);
6974 lpfc_sli4_cq_event_pool_destroy(phba);
6975
6976
6977 lpfc_sli4_dealloc_resource_identifiers(phba);
6978
6979
6980 lpfc_destroy_bootstrap_mbox(phba);
6981
6982
6983 lpfc_mem_free_all(phba);
6984
6985
6986 list_for_each_entry_safe(conn_entry, next_conn_entry,
6987 &phba->fcf_conn_rec_list, list) {
6988 list_del_init(&conn_entry->list);
6989 kfree(conn_entry);
6990 }
6991
6992 return;
6993}
6994
6995
6996
6997
6998
6999
7000
7001
7002
7003
7004
7005int
7006lpfc_init_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)
7007{
7008 phba->lpfc_hba_init_link = lpfc_hba_init_link;
7009 phba->lpfc_hba_down_link = lpfc_hba_down_link;
7010 phba->lpfc_selective_reset = lpfc_selective_reset;
7011 switch (dev_grp) {
7012 case LPFC_PCI_DEV_LP:
7013 phba->lpfc_hba_down_post = lpfc_hba_down_post_s3;
7014 phba->lpfc_handle_eratt = lpfc_handle_eratt_s3;
7015 phba->lpfc_stop_port = lpfc_stop_port_s3;
7016 break;
7017 case LPFC_PCI_DEV_OC:
7018 phba->lpfc_hba_down_post = lpfc_hba_down_post_s4;
7019 phba->lpfc_handle_eratt = lpfc_handle_eratt_s4;
7020 phba->lpfc_stop_port = lpfc_stop_port_s4;
7021 break;
7022 default:
7023 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7024 "1431 Invalid HBA PCI-device group: 0x%x\n",
7025 dev_grp);
7026 return -ENODEV;
7027 break;
7028 }
7029 return 0;
7030}
7031
7032
7033
7034
7035
7036
7037
7038
7039
7040
7041
7042
7043static int
7044lpfc_setup_driver_resource_phase2(struct lpfc_hba *phba)
7045{
7046 int error;
7047
7048
7049 phba->worker_thread = kthread_run(lpfc_do_work, phba,
7050 "lpfc_worker_%d", phba->brd_no);
7051 if (IS_ERR(phba->worker_thread)) {
7052 error = PTR_ERR(phba->worker_thread);
7053 return error;
7054 }
7055
7056 return 0;
7057}
7058
7059
7060
7061
7062
7063
7064
7065
7066
7067static void
7068lpfc_unset_driver_resource_phase2(struct lpfc_hba *phba)
7069{
7070 if (phba->wq) {
7071 flush_workqueue(phba->wq);
7072 destroy_workqueue(phba->wq);
7073 phba->wq = NULL;
7074 }
7075
7076
7077 if (phba->worker_thread)
7078 kthread_stop(phba->worker_thread);
7079}
7080
7081
7082
7083
7084
7085
7086
7087void
7088lpfc_free_iocb_list(struct lpfc_hba *phba)
7089{
7090 struct lpfc_iocbq *iocbq_entry = NULL, *iocbq_next = NULL;
7091
7092 spin_lock_irq(&phba->hbalock);
7093 list_for_each_entry_safe(iocbq_entry, iocbq_next,
7094 &phba->lpfc_iocb_list, list) {
7095 list_del(&iocbq_entry->list);
7096 kfree(iocbq_entry);
7097 phba->total_iocbq_bufs--;
7098 }
7099 spin_unlock_irq(&phba->hbalock);
7100
7101 return;
7102}
7103
7104
7105
7106
7107
7108
7109
7110
7111
7112
7113
7114
7115int
7116lpfc_init_iocb_list(struct lpfc_hba *phba, int iocb_count)
7117{
7118 struct lpfc_iocbq *iocbq_entry = NULL;
7119 uint16_t iotag;
7120 int i;
7121
7122
7123 INIT_LIST_HEAD(&phba->lpfc_iocb_list);
7124 for (i = 0; i < iocb_count; i++) {
7125 iocbq_entry = kzalloc(sizeof(struct lpfc_iocbq), GFP_KERNEL);
7126 if (iocbq_entry == NULL) {
7127 printk(KERN_ERR "%s: only allocated %d iocbs of "
7128 "expected %d count. Unloading driver.\n",
7129 __func__, i, LPFC_IOCB_LIST_CNT);
7130 goto out_free_iocbq;
7131 }
7132
7133 iotag = lpfc_sli_next_iotag(phba, iocbq_entry);
7134 if (iotag == 0) {
7135 kfree(iocbq_entry);
7136 printk(KERN_ERR "%s: failed to allocate IOTAG. "
7137 "Unloading driver.\n", __func__);
7138 goto out_free_iocbq;
7139 }
7140 iocbq_entry->sli4_lxritag = NO_XRI;
7141 iocbq_entry->sli4_xritag = NO_XRI;
7142
7143 spin_lock_irq(&phba->hbalock);
7144 list_add(&iocbq_entry->list, &phba->lpfc_iocb_list);
7145 phba->total_iocbq_bufs++;
7146 spin_unlock_irq(&phba->hbalock);
7147 }
7148
7149 return 0;
7150
7151out_free_iocbq:
7152 lpfc_free_iocb_list(phba);
7153
7154 return -ENOMEM;
7155}
7156
7157
7158
7159
7160
7161
7162
7163
7164void
7165lpfc_free_sgl_list(struct lpfc_hba *phba, struct list_head *sglq_list)
7166{
7167 struct lpfc_sglq *sglq_entry = NULL, *sglq_next = NULL;
7168
7169 list_for_each_entry_safe(sglq_entry, sglq_next, sglq_list, list) {
7170 list_del(&sglq_entry->list);
7171 lpfc_mbuf_free(phba, sglq_entry->virt, sglq_entry->phys);
7172 kfree(sglq_entry);
7173 }
7174}
7175
7176
7177
7178
7179
7180
7181
7182static void
7183lpfc_free_els_sgl_list(struct lpfc_hba *phba)
7184{
7185 LIST_HEAD(sglq_list);
7186
7187
7188 spin_lock_irq(&phba->hbalock);
7189 spin_lock(&phba->sli4_hba.sgl_list_lock);
7190 list_splice_init(&phba->sli4_hba.lpfc_els_sgl_list, &sglq_list);
7191 spin_unlock(&phba->sli4_hba.sgl_list_lock);
7192 spin_unlock_irq(&phba->hbalock);
7193
7194
7195 lpfc_free_sgl_list(phba, &sglq_list);
7196}
7197
7198
7199
7200
7201
7202
7203
7204static void
7205lpfc_free_nvmet_sgl_list(struct lpfc_hba *phba)
7206{
7207 struct lpfc_sglq *sglq_entry = NULL, *sglq_next = NULL;
7208 LIST_HEAD(sglq_list);
7209
7210
7211 spin_lock_irq(&phba->hbalock);
7212 spin_lock(&phba->sli4_hba.sgl_list_lock);
7213 list_splice_init(&phba->sli4_hba.lpfc_nvmet_sgl_list, &sglq_list);
7214 spin_unlock(&phba->sli4_hba.sgl_list_lock);
7215 spin_unlock_irq(&phba->hbalock);
7216
7217
7218 list_for_each_entry_safe(sglq_entry, sglq_next, &sglq_list, list) {
7219 list_del(&sglq_entry->list);
7220 lpfc_nvmet_buf_free(phba, sglq_entry->virt, sglq_entry->phys);
7221 kfree(sglq_entry);
7222 }
7223
7224
7225
7226
7227
7228 phba->sli4_hba.nvmet_xri_cnt = 0;
7229}
7230
7231
7232
7233
7234
7235
7236
7237
7238static int
7239lpfc_init_active_sgl_array(struct lpfc_hba *phba)
7240{
7241 int size;
7242 size = sizeof(struct lpfc_sglq *);
7243 size *= phba->sli4_hba.max_cfg_param.max_xri;
7244
7245 phba->sli4_hba.lpfc_sglq_active_list =
7246 kzalloc(size, GFP_KERNEL);
7247 if (!phba->sli4_hba.lpfc_sglq_active_list)
7248 return -ENOMEM;
7249 return 0;
7250}
7251
7252
7253
7254
7255
7256
7257
7258
7259
7260static void
7261lpfc_free_active_sgl(struct lpfc_hba *phba)
7262{
7263 kfree(phba->sli4_hba.lpfc_sglq_active_list);
7264}
7265
7266
7267
7268
7269
7270
7271
7272
7273
7274static void
7275lpfc_init_sgl_list(struct lpfc_hba *phba)
7276{
7277
7278 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_els_sgl_list);
7279 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_els_sgl_list);
7280 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_nvmet_sgl_list);
7281 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
7282
7283
7284 phba->sli4_hba.els_xri_cnt = 0;
7285
7286
7287 phba->sli4_hba.io_xri_cnt = 0;
7288}
7289
7290
7291
7292
7293
7294
7295
7296
7297
7298
7299
7300
7301
7302
7303
7304int
7305lpfc_sli4_init_rpi_hdrs(struct lpfc_hba *phba)
7306{
7307 int rc = 0;
7308 struct lpfc_rpi_hdr *rpi_hdr;
7309
7310 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_rpi_hdr_list);
7311 if (!phba->sli4_hba.rpi_hdrs_in_use)
7312 return rc;
7313 if (phba->sli4_hba.extents_in_use)
7314 return -EIO;
7315
7316 rpi_hdr = lpfc_sli4_create_rpi_hdr(phba);
7317 if (!rpi_hdr) {
7318 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX | LOG_SLI,
7319 "0391 Error during rpi post operation\n");
7320 lpfc_sli4_remove_rpis(phba);
7321 rc = -ENODEV;
7322 }
7323
7324 return rc;
7325}
7326
7327
7328
7329
7330
7331
7332
7333
7334
7335
7336
7337
7338
7339
7340struct lpfc_rpi_hdr *
7341lpfc_sli4_create_rpi_hdr(struct lpfc_hba *phba)
7342{
7343 uint16_t rpi_limit, curr_rpi_range;
7344 struct lpfc_dmabuf *dmabuf;
7345 struct lpfc_rpi_hdr *rpi_hdr;
7346
7347
7348
7349
7350
7351
7352 if (!phba->sli4_hba.rpi_hdrs_in_use)
7353 return NULL;
7354 if (phba->sli4_hba.extents_in_use)
7355 return NULL;
7356
7357
7358 rpi_limit = phba->sli4_hba.max_cfg_param.max_rpi;
7359
7360 spin_lock_irq(&phba->hbalock);
7361
7362
7363
7364
7365
7366 curr_rpi_range = phba->sli4_hba.next_rpi;
7367 spin_unlock_irq(&phba->hbalock);
7368
7369
7370 if (curr_rpi_range == rpi_limit)
7371 return NULL;
7372
7373
7374
7375
7376
7377 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
7378 if (!dmabuf)
7379 return NULL;
7380
7381 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev,
7382 LPFC_HDR_TEMPLATE_SIZE,
7383 &dmabuf->phys, GFP_KERNEL);
7384 if (!dmabuf->virt) {
7385 rpi_hdr = NULL;
7386 goto err_free_dmabuf;
7387 }
7388
7389 if (!IS_ALIGNED(dmabuf->phys, LPFC_HDR_TEMPLATE_SIZE)) {
7390 rpi_hdr = NULL;
7391 goto err_free_coherent;
7392 }
7393
7394
7395 rpi_hdr = kzalloc(sizeof(struct lpfc_rpi_hdr), GFP_KERNEL);
7396 if (!rpi_hdr)
7397 goto err_free_coherent;
7398
7399 rpi_hdr->dmabuf = dmabuf;
7400 rpi_hdr->len = LPFC_HDR_TEMPLATE_SIZE;
7401 rpi_hdr->page_count = 1;
7402 spin_lock_irq(&phba->hbalock);
7403
7404
7405 rpi_hdr->start_rpi = curr_rpi_range;
7406 rpi_hdr->next_rpi = phba->sli4_hba.next_rpi + LPFC_RPI_HDR_COUNT;
7407 list_add_tail(&rpi_hdr->list, &phba->sli4_hba.lpfc_rpi_hdr_list);
7408
7409 spin_unlock_irq(&phba->hbalock);
7410 return rpi_hdr;
7411
7412 err_free_coherent:
7413 dma_free_coherent(&phba->pcidev->dev, LPFC_HDR_TEMPLATE_SIZE,
7414 dmabuf->virt, dmabuf->phys);
7415 err_free_dmabuf:
7416 kfree(dmabuf);
7417 return NULL;
7418}
7419
7420
7421
7422
7423
7424
7425
7426
7427
7428
7429void
7430lpfc_sli4_remove_rpi_hdrs(struct lpfc_hba *phba)
7431{
7432 struct lpfc_rpi_hdr *rpi_hdr, *next_rpi_hdr;
7433
7434 if (!phba->sli4_hba.rpi_hdrs_in_use)
7435 goto exit;
7436
7437 list_for_each_entry_safe(rpi_hdr, next_rpi_hdr,
7438 &phba->sli4_hba.lpfc_rpi_hdr_list, list) {
7439 list_del(&rpi_hdr->list);
7440 dma_free_coherent(&phba->pcidev->dev, rpi_hdr->len,
7441 rpi_hdr->dmabuf->virt, rpi_hdr->dmabuf->phys);
7442 kfree(rpi_hdr->dmabuf);
7443 kfree(rpi_hdr);
7444 }
7445 exit:
7446
7447 phba->sli4_hba.next_rpi = 0;
7448}
7449
7450
7451
7452
7453
7454
7455
7456
7457
7458
7459
7460
7461
7462static struct lpfc_hba *
7463lpfc_hba_alloc(struct pci_dev *pdev)
7464{
7465 struct lpfc_hba *phba;
7466
7467
7468 phba = kzalloc(sizeof(struct lpfc_hba), GFP_KERNEL);
7469 if (!phba) {
7470 dev_err(&pdev->dev, "failed to allocate hba struct\n");
7471 return NULL;
7472 }
7473
7474
7475 phba->pcidev = pdev;
7476
7477
7478 phba->brd_no = lpfc_get_instance();
7479 if (phba->brd_no < 0) {
7480 kfree(phba);
7481 return NULL;
7482 }
7483 phba->eratt_poll_interval = LPFC_ERATT_POLL_INTERVAL;
7484
7485 spin_lock_init(&phba->ct_ev_lock);
7486 INIT_LIST_HEAD(&phba->ct_ev_waiters);
7487
7488 return phba;
7489}
7490
7491
7492
7493
7494
7495
7496
7497
7498static void
7499lpfc_hba_free(struct lpfc_hba *phba)
7500{
7501 if (phba->sli_rev == LPFC_SLI_REV4)
7502 kfree(phba->sli4_hba.hdwq);
7503
7504
7505 idr_remove(&lpfc_hba_index, phba->brd_no);
7506
7507
7508 kfree(phba->sli.sli3_ring);
7509 phba->sli.sli3_ring = NULL;
7510
7511 kfree(phba);
7512 return;
7513}
7514
7515
7516
7517
7518
7519
7520
7521
7522
7523
7524
7525
7526static int
7527lpfc_create_shost(struct lpfc_hba *phba)
7528{
7529 struct lpfc_vport *vport;
7530 struct Scsi_Host *shost;
7531
7532
7533 phba->fc_edtov = FF_DEF_EDTOV;
7534 phba->fc_ratov = FF_DEF_RATOV;
7535 phba->fc_altov = FF_DEF_ALTOV;
7536 phba->fc_arbtov = FF_DEF_ARBTOV;
7537
7538 atomic_set(&phba->sdev_cnt, 0);
7539 vport = lpfc_create_port(phba, phba->brd_no, &phba->pcidev->dev);
7540 if (!vport)
7541 return -ENODEV;
7542
7543 shost = lpfc_shost_from_vport(vport);
7544 phba->pport = vport;
7545
7546 if (phba->nvmet_support) {
7547
7548 if (phba->txrdy_payload_pool == NULL) {
7549 phba->txrdy_payload_pool = dma_pool_create(
7550 "txrdy_pool", &phba->pcidev->dev,
7551 TXRDY_PAYLOAD_LEN, 16, 0);
7552 if (phba->txrdy_payload_pool) {
7553 phba->targetport = NULL;
7554 phba->cfg_enable_fc4_type = LPFC_ENABLE_NVME;
7555 lpfc_printf_log(phba, KERN_INFO,
7556 LOG_INIT | LOG_NVME_DISC,
7557 "6076 NVME Target Found\n");
7558 }
7559 }
7560 }
7561
7562 lpfc_debugfs_initialize(vport);
7563
7564 pci_set_drvdata(phba->pcidev, shost);
7565
7566
7567
7568
7569
7570 vport->load_flag |= FC_ALLOW_FDMI;
7571 if (phba->cfg_enable_SmartSAN ||
7572 (phba->cfg_fdmi_on == LPFC_FDMI_SUPPORT)) {
7573
7574
7575 vport->fdmi_hba_mask = LPFC_FDMI2_HBA_ATTR;
7576 if (phba->cfg_enable_SmartSAN)
7577 vport->fdmi_port_mask = LPFC_FDMI2_SMART_ATTR;
7578 else
7579 vport->fdmi_port_mask = LPFC_FDMI2_PORT_ATTR;
7580 }
7581 return 0;
7582}
7583
7584
7585
7586
7587
7588
7589
7590
7591static void
7592lpfc_destroy_shost(struct lpfc_hba *phba)
7593{
7594 struct lpfc_vport *vport = phba->pport;
7595
7596
7597 destroy_port(vport);
7598
7599 return;
7600}
7601
7602
7603
7604
7605
7606
7607
7608
7609
7610static void
7611lpfc_setup_bg(struct lpfc_hba *phba, struct Scsi_Host *shost)
7612{
7613 uint32_t old_mask;
7614 uint32_t old_guard;
7615
7616 if (phba->cfg_prot_mask && phba->cfg_prot_guard) {
7617 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7618 "1478 Registering BlockGuard with the "
7619 "SCSI layer\n");
7620
7621 old_mask = phba->cfg_prot_mask;
7622 old_guard = phba->cfg_prot_guard;
7623
7624
7625 phba->cfg_prot_mask &= (SHOST_DIF_TYPE1_PROTECTION |
7626 SHOST_DIX_TYPE0_PROTECTION |
7627 SHOST_DIX_TYPE1_PROTECTION);
7628 phba->cfg_prot_guard &= (SHOST_DIX_GUARD_IP |
7629 SHOST_DIX_GUARD_CRC);
7630
7631
7632 if (phba->cfg_prot_mask == SHOST_DIX_TYPE1_PROTECTION)
7633 phba->cfg_prot_mask |= SHOST_DIF_TYPE1_PROTECTION;
7634
7635 if (phba->cfg_prot_mask && phba->cfg_prot_guard) {
7636 if ((old_mask != phba->cfg_prot_mask) ||
7637 (old_guard != phba->cfg_prot_guard))
7638 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7639 "1475 Registering BlockGuard with the "
7640 "SCSI layer: mask %d guard %d\n",
7641 phba->cfg_prot_mask,
7642 phba->cfg_prot_guard);
7643
7644 scsi_host_set_prot(shost, phba->cfg_prot_mask);
7645 scsi_host_set_guard(shost, phba->cfg_prot_guard);
7646 } else
7647 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7648 "1479 Not Registering BlockGuard with the SCSI "
7649 "layer, Bad protection parameters: %d %d\n",
7650 old_mask, old_guard);
7651 }
7652}
7653
7654
7655
7656
7657
7658
7659
7660
7661static void
7662lpfc_post_init_setup(struct lpfc_hba *phba)
7663{
7664 struct Scsi_Host *shost;
7665 struct lpfc_adapter_event_header adapter_event;
7666
7667
7668 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
7669
7670
7671
7672
7673
7674 shost = pci_get_drvdata(phba->pcidev);
7675 shost->can_queue = phba->cfg_hba_queue_depth - 10;
7676
7677 lpfc_host_attrib_init(shost);
7678
7679 if (phba->cfg_poll & DISABLE_FCP_RING_INT) {
7680 spin_lock_irq(shost->host_lock);
7681 lpfc_poll_start_timer(phba);
7682 spin_unlock_irq(shost->host_lock);
7683 }
7684
7685 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7686 "0428 Perform SCSI scan\n");
7687
7688 adapter_event.event_type = FC_REG_ADAPTER_EVENT;
7689 adapter_event.subcategory = LPFC_EVENT_ARRIVAL;
7690 fc_host_post_vendor_event(shost, fc_get_event_number(),
7691 sizeof(adapter_event),
7692 (char *) &adapter_event,
7693 LPFC_NL_VENDOR_ID);
7694 return;
7695}
7696
7697
7698
7699
7700
7701
7702
7703
7704
7705
7706
7707
7708static int
7709lpfc_sli_pci_mem_setup(struct lpfc_hba *phba)
7710{
7711 struct pci_dev *pdev = phba->pcidev;
7712 unsigned long bar0map_len, bar2map_len;
7713 int i, hbq_count;
7714 void *ptr;
7715 int error;
7716
7717 if (!pdev)
7718 return -ENODEV;
7719
7720
7721 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
7722 if (error)
7723 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
7724 if (error)
7725 return error;
7726 error = -ENODEV;
7727
7728
7729
7730
7731 phba->pci_bar0_map = pci_resource_start(pdev, 0);
7732 bar0map_len = pci_resource_len(pdev, 0);
7733
7734 phba->pci_bar2_map = pci_resource_start(pdev, 2);
7735 bar2map_len = pci_resource_len(pdev, 2);
7736
7737
7738 phba->slim_memmap_p = ioremap(phba->pci_bar0_map, bar0map_len);
7739 if (!phba->slim_memmap_p) {
7740 dev_printk(KERN_ERR, &pdev->dev,
7741 "ioremap failed for SLIM memory.\n");
7742 goto out;
7743 }
7744
7745
7746 phba->ctrl_regs_memmap_p = ioremap(phba->pci_bar2_map, bar2map_len);
7747 if (!phba->ctrl_regs_memmap_p) {
7748 dev_printk(KERN_ERR, &pdev->dev,
7749 "ioremap failed for HBA control registers.\n");
7750 goto out_iounmap_slim;
7751 }
7752
7753
7754 phba->slim2p.virt = dma_alloc_coherent(&pdev->dev, SLI2_SLIM_SIZE,
7755 &phba->slim2p.phys, GFP_KERNEL);
7756 if (!phba->slim2p.virt)
7757 goto out_iounmap;
7758
7759 phba->mbox = phba->slim2p.virt + offsetof(struct lpfc_sli2_slim, mbx);
7760 phba->mbox_ext = (phba->slim2p.virt +
7761 offsetof(struct lpfc_sli2_slim, mbx_ext_words));
7762 phba->pcb = (phba->slim2p.virt + offsetof(struct lpfc_sli2_slim, pcb));
7763 phba->IOCBs = (phba->slim2p.virt +
7764 offsetof(struct lpfc_sli2_slim, IOCBs));
7765
7766 phba->hbqslimp.virt = dma_alloc_coherent(&pdev->dev,
7767 lpfc_sli_hbq_size(),
7768 &phba->hbqslimp.phys,
7769 GFP_KERNEL);
7770 if (!phba->hbqslimp.virt)
7771 goto out_free_slim;
7772
7773 hbq_count = lpfc_sli_hbq_count();
7774 ptr = phba->hbqslimp.virt;
7775 for (i = 0; i < hbq_count; ++i) {
7776 phba->hbqs[i].hbq_virt = ptr;
7777 INIT_LIST_HEAD(&phba->hbqs[i].hbq_buffer_list);
7778 ptr += (lpfc_hbq_defs[i]->entry_count *
7779 sizeof(struct lpfc_hbq_entry));
7780 }
7781 phba->hbqs[LPFC_ELS_HBQ].hbq_alloc_buffer = lpfc_els_hbq_alloc;
7782 phba->hbqs[LPFC_ELS_HBQ].hbq_free_buffer = lpfc_els_hbq_free;
7783
7784 memset(phba->hbqslimp.virt, 0, lpfc_sli_hbq_size());
7785
7786 phba->MBslimaddr = phba->slim_memmap_p;
7787 phba->HAregaddr = phba->ctrl_regs_memmap_p + HA_REG_OFFSET;
7788 phba->CAregaddr = phba->ctrl_regs_memmap_p + CA_REG_OFFSET;
7789 phba->HSregaddr = phba->ctrl_regs_memmap_p + HS_REG_OFFSET;
7790 phba->HCregaddr = phba->ctrl_regs_memmap_p + HC_REG_OFFSET;
7791
7792 return 0;
7793
7794out_free_slim:
7795 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
7796 phba->slim2p.virt, phba->slim2p.phys);
7797out_iounmap:
7798 iounmap(phba->ctrl_regs_memmap_p);
7799out_iounmap_slim:
7800 iounmap(phba->slim_memmap_p);
7801out:
7802 return error;
7803}
7804
7805
7806
7807
7808
7809
7810
7811
7812static void
7813lpfc_sli_pci_mem_unset(struct lpfc_hba *phba)
7814{
7815 struct pci_dev *pdev;
7816
7817
7818 if (!phba->pcidev)
7819 return;
7820 else
7821 pdev = phba->pcidev;
7822
7823
7824 dma_free_coherent(&pdev->dev, lpfc_sli_hbq_size(),
7825 phba->hbqslimp.virt, phba->hbqslimp.phys);
7826 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
7827 phba->slim2p.virt, phba->slim2p.phys);
7828
7829
7830 iounmap(phba->ctrl_regs_memmap_p);
7831 iounmap(phba->slim_memmap_p);
7832
7833 return;
7834}
7835
7836
7837
7838
7839
7840
7841
7842
7843
7844
7845int
7846lpfc_sli4_post_status_check(struct lpfc_hba *phba)
7847{
7848 struct lpfc_register portsmphr_reg, uerrlo_reg, uerrhi_reg;
7849 struct lpfc_register reg_data;
7850 int i, port_error = 0;
7851 uint32_t if_type;
7852
7853 memset(&portsmphr_reg, 0, sizeof(portsmphr_reg));
7854 memset(®_data, 0, sizeof(reg_data));
7855 if (!phba->sli4_hba.PSMPHRregaddr)
7856 return -ENODEV;
7857
7858
7859 for (i = 0; i < 3000; i++) {
7860 if (lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
7861 &portsmphr_reg.word0) ||
7862 (bf_get(lpfc_port_smphr_perr, &portsmphr_reg))) {
7863
7864 port_error = -ENODEV;
7865 break;
7866 }
7867 if (LPFC_POST_STAGE_PORT_READY ==
7868 bf_get(lpfc_port_smphr_port_status, &portsmphr_reg))
7869 break;
7870 msleep(10);
7871 }
7872
7873
7874
7875
7876
7877 if (port_error) {
7878 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7879 "1408 Port Failed POST - portsmphr=0x%x, "
7880 "perr=x%x, sfi=x%x, nip=x%x, ipc=x%x, scr1=x%x, "
7881 "scr2=x%x, hscratch=x%x, pstatus=x%x\n",
7882 portsmphr_reg.word0,
7883 bf_get(lpfc_port_smphr_perr, &portsmphr_reg),
7884 bf_get(lpfc_port_smphr_sfi, &portsmphr_reg),
7885 bf_get(lpfc_port_smphr_nip, &portsmphr_reg),
7886 bf_get(lpfc_port_smphr_ipc, &portsmphr_reg),
7887 bf_get(lpfc_port_smphr_scr1, &portsmphr_reg),
7888 bf_get(lpfc_port_smphr_scr2, &portsmphr_reg),
7889 bf_get(lpfc_port_smphr_host_scratch, &portsmphr_reg),
7890 bf_get(lpfc_port_smphr_port_status, &portsmphr_reg));
7891 } else {
7892 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7893 "2534 Device Info: SLIFamily=0x%x, "
7894 "SLIRev=0x%x, IFType=0x%x, SLIHint_1=0x%x, "
7895 "SLIHint_2=0x%x, FT=0x%x\n",
7896 bf_get(lpfc_sli_intf_sli_family,
7897 &phba->sli4_hba.sli_intf),
7898 bf_get(lpfc_sli_intf_slirev,
7899 &phba->sli4_hba.sli_intf),
7900 bf_get(lpfc_sli_intf_if_type,
7901 &phba->sli4_hba.sli_intf),
7902 bf_get(lpfc_sli_intf_sli_hint1,
7903 &phba->sli4_hba.sli_intf),
7904 bf_get(lpfc_sli_intf_sli_hint2,
7905 &phba->sli4_hba.sli_intf),
7906 bf_get(lpfc_sli_intf_func_type,
7907 &phba->sli4_hba.sli_intf));
7908
7909
7910
7911
7912
7913 if_type = bf_get(lpfc_sli_intf_if_type,
7914 &phba->sli4_hba.sli_intf);
7915 switch (if_type) {
7916 case LPFC_SLI_INTF_IF_TYPE_0:
7917 phba->sli4_hba.ue_mask_lo =
7918 readl(phba->sli4_hba.u.if_type0.UEMASKLOregaddr);
7919 phba->sli4_hba.ue_mask_hi =
7920 readl(phba->sli4_hba.u.if_type0.UEMASKHIregaddr);
7921 uerrlo_reg.word0 =
7922 readl(phba->sli4_hba.u.if_type0.UERRLOregaddr);
7923 uerrhi_reg.word0 =
7924 readl(phba->sli4_hba.u.if_type0.UERRHIregaddr);
7925 if ((~phba->sli4_hba.ue_mask_lo & uerrlo_reg.word0) ||
7926 (~phba->sli4_hba.ue_mask_hi & uerrhi_reg.word0)) {
7927 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7928 "1422 Unrecoverable Error "
7929 "Detected during POST "
7930 "uerr_lo_reg=0x%x, "
7931 "uerr_hi_reg=0x%x, "
7932 "ue_mask_lo_reg=0x%x, "
7933 "ue_mask_hi_reg=0x%x\n",
7934 uerrlo_reg.word0,
7935 uerrhi_reg.word0,
7936 phba->sli4_hba.ue_mask_lo,
7937 phba->sli4_hba.ue_mask_hi);
7938 port_error = -ENODEV;
7939 }
7940 break;
7941 case LPFC_SLI_INTF_IF_TYPE_2:
7942 case LPFC_SLI_INTF_IF_TYPE_6:
7943
7944 if (lpfc_readl(phba->sli4_hba.u.if_type2.STATUSregaddr,
7945 ®_data.word0) ||
7946 (bf_get(lpfc_sliport_status_err, ®_data) &&
7947 !bf_get(lpfc_sliport_status_rn, ®_data))) {
7948 phba->work_status[0] =
7949 readl(phba->sli4_hba.u.if_type2.
7950 ERR1regaddr);
7951 phba->work_status[1] =
7952 readl(phba->sli4_hba.u.if_type2.
7953 ERR2regaddr);
7954 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7955 "2888 Unrecoverable port error "
7956 "following POST: port status reg "
7957 "0x%x, port_smphr reg 0x%x, "
7958 "error 1=0x%x, error 2=0x%x\n",
7959 reg_data.word0,
7960 portsmphr_reg.word0,
7961 phba->work_status[0],
7962 phba->work_status[1]);
7963 port_error = -ENODEV;
7964 }
7965 break;
7966 case LPFC_SLI_INTF_IF_TYPE_1:
7967 default:
7968 break;
7969 }
7970 }
7971 return port_error;
7972}
7973
7974
7975
7976
7977
7978
7979
7980
7981
7982static void
7983lpfc_sli4_bar0_register_memmap(struct lpfc_hba *phba, uint32_t if_type)
7984{
7985 switch (if_type) {
7986 case LPFC_SLI_INTF_IF_TYPE_0:
7987 phba->sli4_hba.u.if_type0.UERRLOregaddr =
7988 phba->sli4_hba.conf_regs_memmap_p + LPFC_UERR_STATUS_LO;
7989 phba->sli4_hba.u.if_type0.UERRHIregaddr =
7990 phba->sli4_hba.conf_regs_memmap_p + LPFC_UERR_STATUS_HI;
7991 phba->sli4_hba.u.if_type0.UEMASKLOregaddr =
7992 phba->sli4_hba.conf_regs_memmap_p + LPFC_UE_MASK_LO;
7993 phba->sli4_hba.u.if_type0.UEMASKHIregaddr =
7994 phba->sli4_hba.conf_regs_memmap_p + LPFC_UE_MASK_HI;
7995 phba->sli4_hba.SLIINTFregaddr =
7996 phba->sli4_hba.conf_regs_memmap_p + LPFC_SLI_INTF;
7997 break;
7998 case LPFC_SLI_INTF_IF_TYPE_2:
7999 phba->sli4_hba.u.if_type2.EQDregaddr =
8000 phba->sli4_hba.conf_regs_memmap_p +
8001 LPFC_CTL_PORT_EQ_DELAY_OFFSET;
8002 phba->sli4_hba.u.if_type2.ERR1regaddr =
8003 phba->sli4_hba.conf_regs_memmap_p +
8004 LPFC_CTL_PORT_ER1_OFFSET;
8005 phba->sli4_hba.u.if_type2.ERR2regaddr =
8006 phba->sli4_hba.conf_regs_memmap_p +
8007 LPFC_CTL_PORT_ER2_OFFSET;
8008 phba->sli4_hba.u.if_type2.CTRLregaddr =
8009 phba->sli4_hba.conf_regs_memmap_p +
8010 LPFC_CTL_PORT_CTL_OFFSET;
8011 phba->sli4_hba.u.if_type2.STATUSregaddr =
8012 phba->sli4_hba.conf_regs_memmap_p +
8013 LPFC_CTL_PORT_STA_OFFSET;
8014 phba->sli4_hba.SLIINTFregaddr =
8015 phba->sli4_hba.conf_regs_memmap_p + LPFC_SLI_INTF;
8016 phba->sli4_hba.PSMPHRregaddr =
8017 phba->sli4_hba.conf_regs_memmap_p +
8018 LPFC_CTL_PORT_SEM_OFFSET;
8019 phba->sli4_hba.RQDBregaddr =
8020 phba->sli4_hba.conf_regs_memmap_p +
8021 LPFC_ULP0_RQ_DOORBELL;
8022 phba->sli4_hba.WQDBregaddr =
8023 phba->sli4_hba.conf_regs_memmap_p +
8024 LPFC_ULP0_WQ_DOORBELL;
8025 phba->sli4_hba.CQDBregaddr =
8026 phba->sli4_hba.conf_regs_memmap_p + LPFC_EQCQ_DOORBELL;
8027 phba->sli4_hba.EQDBregaddr = phba->sli4_hba.CQDBregaddr;
8028 phba->sli4_hba.MQDBregaddr =
8029 phba->sli4_hba.conf_regs_memmap_p + LPFC_MQ_DOORBELL;
8030 phba->sli4_hba.BMBXregaddr =
8031 phba->sli4_hba.conf_regs_memmap_p + LPFC_BMBX;
8032 break;
8033 case LPFC_SLI_INTF_IF_TYPE_6:
8034 phba->sli4_hba.u.if_type2.EQDregaddr =
8035 phba->sli4_hba.conf_regs_memmap_p +
8036 LPFC_CTL_PORT_EQ_DELAY_OFFSET;
8037 phba->sli4_hba.u.if_type2.ERR1regaddr =
8038 phba->sli4_hba.conf_regs_memmap_p +
8039 LPFC_CTL_PORT_ER1_OFFSET;
8040 phba->sli4_hba.u.if_type2.ERR2regaddr =
8041 phba->sli4_hba.conf_regs_memmap_p +
8042 LPFC_CTL_PORT_ER2_OFFSET;
8043 phba->sli4_hba.u.if_type2.CTRLregaddr =
8044 phba->sli4_hba.conf_regs_memmap_p +
8045 LPFC_CTL_PORT_CTL_OFFSET;
8046 phba->sli4_hba.u.if_type2.STATUSregaddr =
8047 phba->sli4_hba.conf_regs_memmap_p +
8048 LPFC_CTL_PORT_STA_OFFSET;
8049 phba->sli4_hba.PSMPHRregaddr =
8050 phba->sli4_hba.conf_regs_memmap_p +
8051 LPFC_CTL_PORT_SEM_OFFSET;
8052 phba->sli4_hba.BMBXregaddr =
8053 phba->sli4_hba.conf_regs_memmap_p + LPFC_BMBX;
8054 break;
8055 case LPFC_SLI_INTF_IF_TYPE_1:
8056 default:
8057 dev_printk(KERN_ERR, &phba->pcidev->dev,
8058 "FATAL - unsupported SLI4 interface type - %d\n",
8059 if_type);
8060 break;
8061 }
8062}
8063
8064
8065
8066
8067
8068
8069
8070static void
8071lpfc_sli4_bar1_register_memmap(struct lpfc_hba *phba, uint32_t if_type)
8072{
8073 switch (if_type) {
8074 case LPFC_SLI_INTF_IF_TYPE_0:
8075 phba->sli4_hba.PSMPHRregaddr =
8076 phba->sli4_hba.ctrl_regs_memmap_p +
8077 LPFC_SLIPORT_IF0_SMPHR;
8078 phba->sli4_hba.ISRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
8079 LPFC_HST_ISR0;
8080 phba->sli4_hba.IMRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
8081 LPFC_HST_IMR0;
8082 phba->sli4_hba.ISCRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
8083 LPFC_HST_ISCR0;
8084 break;
8085 case LPFC_SLI_INTF_IF_TYPE_6:
8086 phba->sli4_hba.RQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8087 LPFC_IF6_RQ_DOORBELL;
8088 phba->sli4_hba.WQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8089 LPFC_IF6_WQ_DOORBELL;
8090 phba->sli4_hba.CQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8091 LPFC_IF6_CQ_DOORBELL;
8092 phba->sli4_hba.EQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8093 LPFC_IF6_EQ_DOORBELL;
8094 phba->sli4_hba.MQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8095 LPFC_IF6_MQ_DOORBELL;
8096 break;
8097 case LPFC_SLI_INTF_IF_TYPE_2:
8098 case LPFC_SLI_INTF_IF_TYPE_1:
8099 default:
8100 dev_err(&phba->pcidev->dev,
8101 "FATAL - unsupported SLI4 interface type - %d\n",
8102 if_type);
8103 break;
8104 }
8105}
8106
8107
8108
8109
8110
8111
8112
8113
8114
8115
8116
8117static int
8118lpfc_sli4_bar2_register_memmap(struct lpfc_hba *phba, uint32_t vf)
8119{
8120 if (vf > LPFC_VIR_FUNC_MAX)
8121 return -ENODEV;
8122
8123 phba->sli4_hba.RQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
8124 vf * LPFC_VFR_PAGE_SIZE +
8125 LPFC_ULP0_RQ_DOORBELL);
8126 phba->sli4_hba.WQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
8127 vf * LPFC_VFR_PAGE_SIZE +
8128 LPFC_ULP0_WQ_DOORBELL);
8129 phba->sli4_hba.CQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
8130 vf * LPFC_VFR_PAGE_SIZE +
8131 LPFC_EQCQ_DOORBELL);
8132 phba->sli4_hba.EQDBregaddr = phba->sli4_hba.CQDBregaddr;
8133 phba->sli4_hba.MQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
8134 vf * LPFC_VFR_PAGE_SIZE + LPFC_MQ_DOORBELL);
8135 phba->sli4_hba.BMBXregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
8136 vf * LPFC_VFR_PAGE_SIZE + LPFC_BMBX);
8137 return 0;
8138}
8139
8140
8141
8142
8143
8144
8145
8146
8147
8148
8149
8150
8151
8152
8153
8154
8155static int
8156lpfc_create_bootstrap_mbox(struct lpfc_hba *phba)
8157{
8158 uint32_t bmbx_size;
8159 struct lpfc_dmabuf *dmabuf;
8160 struct dma_address *dma_address;
8161 uint32_t pa_addr;
8162 uint64_t phys_addr;
8163
8164 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
8165 if (!dmabuf)
8166 return -ENOMEM;
8167
8168
8169
8170
8171
8172 bmbx_size = sizeof(struct lpfc_bmbx_create) + (LPFC_ALIGN_16_BYTE - 1);
8173 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev, bmbx_size,
8174 &dmabuf->phys, GFP_KERNEL);
8175 if (!dmabuf->virt) {
8176 kfree(dmabuf);
8177 return -ENOMEM;
8178 }
8179
8180
8181
8182
8183
8184
8185
8186
8187 phba->sli4_hba.bmbx.dmabuf = dmabuf;
8188 phba->sli4_hba.bmbx.bmbx_size = bmbx_size;
8189
8190 phba->sli4_hba.bmbx.avirt = PTR_ALIGN(dmabuf->virt,
8191 LPFC_ALIGN_16_BYTE);
8192 phba->sli4_hba.bmbx.aphys = ALIGN(dmabuf->phys,
8193 LPFC_ALIGN_16_BYTE);
8194
8195
8196
8197
8198
8199
8200
8201
8202
8203 dma_address = &phba->sli4_hba.bmbx.dma_address;
8204 phys_addr = (uint64_t)phba->sli4_hba.bmbx.aphys;
8205 pa_addr = (uint32_t) ((phys_addr >> 34) & 0x3fffffff);
8206 dma_address->addr_hi = (uint32_t) ((pa_addr << 2) |
8207 LPFC_BMBX_BIT1_ADDR_HI);
8208
8209 pa_addr = (uint32_t) ((phba->sli4_hba.bmbx.aphys >> 4) & 0x3fffffff);
8210 dma_address->addr_lo = (uint32_t) ((pa_addr << 2) |
8211 LPFC_BMBX_BIT1_ADDR_LO);
8212 return 0;
8213}
8214
8215
8216
8217
8218
8219
8220
8221
8222
8223
8224
8225
8226static void
8227lpfc_destroy_bootstrap_mbox(struct lpfc_hba *phba)
8228{
8229 dma_free_coherent(&phba->pcidev->dev,
8230 phba->sli4_hba.bmbx.bmbx_size,
8231 phba->sli4_hba.bmbx.dmabuf->virt,
8232 phba->sli4_hba.bmbx.dmabuf->phys);
8233
8234 kfree(phba->sli4_hba.bmbx.dmabuf);
8235 memset(&phba->sli4_hba.bmbx, 0, sizeof(struct lpfc_bmbx));
8236}
8237
8238
8239
8240
8241
8242
8243
8244
8245
8246
8247
8248
8249
8250
8251
8252int
8253lpfc_sli4_read_config(struct lpfc_hba *phba)
8254{
8255 LPFC_MBOXQ_t *pmb;
8256 struct lpfc_mbx_read_config *rd_config;
8257 union lpfc_sli4_cfg_shdr *shdr;
8258 uint32_t shdr_status, shdr_add_status;
8259 struct lpfc_mbx_get_func_cfg *get_func_cfg;
8260 struct lpfc_rsrc_desc_fcfcoe *desc;
8261 char *pdesc_0;
8262 uint16_t forced_link_speed;
8263 uint32_t if_type, qmin;
8264 int length, i, rc = 0, rc2;
8265
8266 pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
8267 if (!pmb) {
8268 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
8269 "2011 Unable to allocate memory for issuing "
8270 "SLI_CONFIG_SPECIAL mailbox command\n");
8271 return -ENOMEM;
8272 }
8273
8274 lpfc_read_config(phba, pmb);
8275
8276 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
8277 if (rc != MBX_SUCCESS) {
8278 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
8279 "2012 Mailbox failed , mbxCmd x%x "
8280 "READ_CONFIG, mbxStatus x%x\n",
8281 bf_get(lpfc_mqe_command, &pmb->u.mqe),
8282 bf_get(lpfc_mqe_status, &pmb->u.mqe));
8283 rc = -EIO;
8284 } else {
8285 rd_config = &pmb->u.mqe.un.rd_config;
8286 if (bf_get(lpfc_mbx_rd_conf_lnk_ldv, rd_config)) {
8287 phba->sli4_hba.lnk_info.lnk_dv = LPFC_LNK_DAT_VAL;
8288 phba->sli4_hba.lnk_info.lnk_tp =
8289 bf_get(lpfc_mbx_rd_conf_lnk_type, rd_config);
8290 phba->sli4_hba.lnk_info.lnk_no =
8291 bf_get(lpfc_mbx_rd_conf_lnk_numb, rd_config);
8292 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
8293 "3081 lnk_type:%d, lnk_numb:%d\n",
8294 phba->sli4_hba.lnk_info.lnk_tp,
8295 phba->sli4_hba.lnk_info.lnk_no);
8296 } else
8297 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
8298 "3082 Mailbox (x%x) returned ldv:x0\n",
8299 bf_get(lpfc_mqe_command, &pmb->u.mqe));
8300 if (bf_get(lpfc_mbx_rd_conf_bbscn_def, rd_config)) {
8301 phba->bbcredit_support = 1;
8302 phba->sli4_hba.bbscn_params.word0 = rd_config->word8;
8303 }
8304
8305 phba->sli4_hba.conf_trunk =
8306 bf_get(lpfc_mbx_rd_conf_trunk, rd_config);
8307 phba->sli4_hba.extents_in_use =
8308 bf_get(lpfc_mbx_rd_conf_extnts_inuse, rd_config);
8309 phba->sli4_hba.max_cfg_param.max_xri =
8310 bf_get(lpfc_mbx_rd_conf_xri_count, rd_config);
8311
8312 if (is_kdump_kernel() &&
8313 phba->sli4_hba.max_cfg_param.max_xri > 512)
8314 phba->sli4_hba.max_cfg_param.max_xri = 512;
8315 phba->sli4_hba.max_cfg_param.xri_base =
8316 bf_get(lpfc_mbx_rd_conf_xri_base, rd_config);
8317 phba->sli4_hba.max_cfg_param.max_vpi =
8318 bf_get(lpfc_mbx_rd_conf_vpi_count, rd_config);
8319
8320 if (phba->sli4_hba.max_cfg_param.max_vpi > LPFC_MAX_VPORTS)
8321 phba->sli4_hba.max_cfg_param.max_vpi = LPFC_MAX_VPORTS;
8322 phba->sli4_hba.max_cfg_param.vpi_base =
8323 bf_get(lpfc_mbx_rd_conf_vpi_base, rd_config);
8324 phba->sli4_hba.max_cfg_param.max_rpi =
8325 bf_get(lpfc_mbx_rd_conf_rpi_count, rd_config);
8326 phba->sli4_hba.max_cfg_param.rpi_base =
8327 bf_get(lpfc_mbx_rd_conf_rpi_base, rd_config);
8328 phba->sli4_hba.max_cfg_param.max_vfi =
8329 bf_get(lpfc_mbx_rd_conf_vfi_count, rd_config);
8330 phba->sli4_hba.max_cfg_param.vfi_base =
8331 bf_get(lpfc_mbx_rd_conf_vfi_base, rd_config);
8332 phba->sli4_hba.max_cfg_param.max_fcfi =
8333 bf_get(lpfc_mbx_rd_conf_fcfi_count, rd_config);
8334 phba->sli4_hba.max_cfg_param.max_eq =
8335 bf_get(lpfc_mbx_rd_conf_eq_count, rd_config);
8336 phba->sli4_hba.max_cfg_param.max_rq =
8337 bf_get(lpfc_mbx_rd_conf_rq_count, rd_config);
8338 phba->sli4_hba.max_cfg_param.max_wq =
8339 bf_get(lpfc_mbx_rd_conf_wq_count, rd_config);
8340 phba->sli4_hba.max_cfg_param.max_cq =
8341 bf_get(lpfc_mbx_rd_conf_cq_count, rd_config);
8342 phba->lmt = bf_get(lpfc_mbx_rd_conf_lmt, rd_config);
8343 phba->sli4_hba.next_xri = phba->sli4_hba.max_cfg_param.xri_base;
8344 phba->vpi_base = phba->sli4_hba.max_cfg_param.vpi_base;
8345 phba->vfi_base = phba->sli4_hba.max_cfg_param.vfi_base;
8346 phba->max_vpi = (phba->sli4_hba.max_cfg_param.max_vpi > 0) ?
8347 (phba->sli4_hba.max_cfg_param.max_vpi - 1) : 0;
8348 phba->max_vports = phba->max_vpi;
8349 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
8350 "2003 cfg params Extents? %d "
8351 "XRI(B:%d M:%d), "
8352 "VPI(B:%d M:%d) "
8353 "VFI(B:%d M:%d) "
8354 "RPI(B:%d M:%d) "
8355 "FCFI:%d EQ:%d CQ:%d WQ:%d RQ:%d\n",
8356 phba->sli4_hba.extents_in_use,
8357 phba->sli4_hba.max_cfg_param.xri_base,
8358 phba->sli4_hba.max_cfg_param.max_xri,
8359 phba->sli4_hba.max_cfg_param.vpi_base,
8360 phba->sli4_hba.max_cfg_param.max_vpi,
8361 phba->sli4_hba.max_cfg_param.vfi_base,
8362 phba->sli4_hba.max_cfg_param.max_vfi,
8363 phba->sli4_hba.max_cfg_param.rpi_base,
8364 phba->sli4_hba.max_cfg_param.max_rpi,
8365 phba->sli4_hba.max_cfg_param.max_fcfi,
8366 phba->sli4_hba.max_cfg_param.max_eq,
8367 phba->sli4_hba.max_cfg_param.max_cq,
8368 phba->sli4_hba.max_cfg_param.max_wq,
8369 phba->sli4_hba.max_cfg_param.max_rq);
8370
8371
8372
8373
8374
8375 qmin = phba->sli4_hba.max_cfg_param.max_wq;
8376 if (phba->sli4_hba.max_cfg_param.max_cq < qmin)
8377 qmin = phba->sli4_hba.max_cfg_param.max_cq;
8378 if (phba->sli4_hba.max_cfg_param.max_eq < qmin)
8379 qmin = phba->sli4_hba.max_cfg_param.max_eq;
8380
8381
8382
8383
8384
8385
8386 qmin -= 4;
8387
8388
8389 if ((phba->cfg_irq_chann > qmin) ||
8390 (phba->cfg_hdw_queue > qmin)) {
8391 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
8392 "2005 Reducing Queues: "
8393 "WQ %d CQ %d EQ %d: min %d: "
8394 "IRQ %d HDWQ %d\n",
8395 phba->sli4_hba.max_cfg_param.max_wq,
8396 phba->sli4_hba.max_cfg_param.max_cq,
8397 phba->sli4_hba.max_cfg_param.max_eq,
8398 qmin, phba->cfg_irq_chann,
8399 phba->cfg_hdw_queue);
8400
8401 if (phba->cfg_irq_chann > qmin)
8402 phba->cfg_irq_chann = qmin;
8403 if (phba->cfg_hdw_queue > qmin)
8404 phba->cfg_hdw_queue = qmin;
8405 }
8406 }
8407
8408 if (rc)
8409 goto read_cfg_out;
8410
8411
8412 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
8413 if (if_type >= LPFC_SLI_INTF_IF_TYPE_2) {
8414 forced_link_speed =
8415 bf_get(lpfc_mbx_rd_conf_link_speed, rd_config);
8416 if (forced_link_speed) {
8417 phba->hba_flag |= HBA_FORCED_LINK_SPEED;
8418
8419 switch (forced_link_speed) {
8420 case LINK_SPEED_1G:
8421 phba->cfg_link_speed =
8422 LPFC_USER_LINK_SPEED_1G;
8423 break;
8424 case LINK_SPEED_2G:
8425 phba->cfg_link_speed =
8426 LPFC_USER_LINK_SPEED_2G;
8427 break;
8428 case LINK_SPEED_4G:
8429 phba->cfg_link_speed =
8430 LPFC_USER_LINK_SPEED_4G;
8431 break;
8432 case LINK_SPEED_8G:
8433 phba->cfg_link_speed =
8434 LPFC_USER_LINK_SPEED_8G;
8435 break;
8436 case LINK_SPEED_10G:
8437 phba->cfg_link_speed =
8438 LPFC_USER_LINK_SPEED_10G;
8439 break;
8440 case LINK_SPEED_16G:
8441 phba->cfg_link_speed =
8442 LPFC_USER_LINK_SPEED_16G;
8443 break;
8444 case LINK_SPEED_32G:
8445 phba->cfg_link_speed =
8446 LPFC_USER_LINK_SPEED_32G;
8447 break;
8448 case LINK_SPEED_64G:
8449 phba->cfg_link_speed =
8450 LPFC_USER_LINK_SPEED_64G;
8451 break;
8452 case 0xffff:
8453 phba->cfg_link_speed =
8454 LPFC_USER_LINK_SPEED_AUTO;
8455 break;
8456 default:
8457 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
8458 "0047 Unrecognized link "
8459 "speed : %d\n",
8460 forced_link_speed);
8461 phba->cfg_link_speed =
8462 LPFC_USER_LINK_SPEED_AUTO;
8463 }
8464 }
8465 }
8466
8467
8468 length = phba->sli4_hba.max_cfg_param.max_xri -
8469 lpfc_sli4_get_els_iocb_cnt(phba);
8470 if (phba->cfg_hba_queue_depth > length) {
8471 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
8472 "3361 HBA queue depth changed from %d to %d\n",
8473 phba->cfg_hba_queue_depth, length);
8474 phba->cfg_hba_queue_depth = length;
8475 }
8476
8477 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) <
8478 LPFC_SLI_INTF_IF_TYPE_2)
8479 goto read_cfg_out;
8480
8481
8482 length = (sizeof(struct lpfc_mbx_get_func_cfg) -
8483 sizeof(struct lpfc_sli4_cfg_mhdr));
8484 lpfc_sli4_config(phba, pmb, LPFC_MBOX_SUBSYSTEM_COMMON,
8485 LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG,
8486 length, LPFC_SLI4_MBX_EMBED);
8487
8488 rc2 = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
8489 shdr = (union lpfc_sli4_cfg_shdr *)
8490 &pmb->u.mqe.un.sli4_config.header.cfg_shdr;
8491 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
8492 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &shdr->response);
8493 if (rc2 || shdr_status || shdr_add_status) {
8494 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
8495 "3026 Mailbox failed , mbxCmd x%x "
8496 "GET_FUNCTION_CONFIG, mbxStatus x%x\n",
8497 bf_get(lpfc_mqe_command, &pmb->u.mqe),
8498 bf_get(lpfc_mqe_status, &pmb->u.mqe));
8499 goto read_cfg_out;
8500 }
8501
8502
8503 get_func_cfg = &pmb->u.mqe.un.get_func_cfg;
8504
8505 pdesc_0 = (char *)&get_func_cfg->func_cfg.desc[0];
8506 desc = (struct lpfc_rsrc_desc_fcfcoe *)pdesc_0;
8507 length = bf_get(lpfc_rsrc_desc_fcfcoe_length, desc);
8508 if (length == LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD)
8509 length = LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH;
8510 else if (length != LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH)
8511 goto read_cfg_out;
8512
8513 for (i = 0; i < LPFC_RSRC_DESC_MAX_NUM; i++) {
8514 desc = (struct lpfc_rsrc_desc_fcfcoe *)(pdesc_0 + length * i);
8515 if (LPFC_RSRC_DESC_TYPE_FCFCOE ==
8516 bf_get(lpfc_rsrc_desc_fcfcoe_type, desc)) {
8517 phba->sli4_hba.iov.pf_number =
8518 bf_get(lpfc_rsrc_desc_fcfcoe_pfnum, desc);
8519 phba->sli4_hba.iov.vf_number =
8520 bf_get(lpfc_rsrc_desc_fcfcoe_vfnum, desc);
8521 break;
8522 }
8523 }
8524
8525 if (i < LPFC_RSRC_DESC_MAX_NUM)
8526 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
8527 "3027 GET_FUNCTION_CONFIG: pf_number:%d, "
8528 "vf_number:%d\n", phba->sli4_hba.iov.pf_number,
8529 phba->sli4_hba.iov.vf_number);
8530 else
8531 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
8532 "3028 GET_FUNCTION_CONFIG: failed to find "
8533 "Resource Descriptor:x%x\n",
8534 LPFC_RSRC_DESC_TYPE_FCFCOE);
8535
8536read_cfg_out:
8537 mempool_free(pmb, phba->mbox_mem_pool);
8538 return rc;
8539}
8540
8541
8542
8543
8544
8545
8546
8547
8548
8549
8550
8551
8552
8553
8554static int
8555lpfc_setup_endian_order(struct lpfc_hba *phba)
8556{
8557 LPFC_MBOXQ_t *mboxq;
8558 uint32_t if_type, rc = 0;
8559 uint32_t endian_mb_data[2] = {HOST_ENDIAN_LOW_WORD0,
8560 HOST_ENDIAN_HIGH_WORD1};
8561
8562 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
8563 switch (if_type) {
8564 case LPFC_SLI_INTF_IF_TYPE_0:
8565 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
8566 GFP_KERNEL);
8567 if (!mboxq) {
8568 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8569 "0492 Unable to allocate memory for "
8570 "issuing SLI_CONFIG_SPECIAL mailbox "
8571 "command\n");
8572 return -ENOMEM;
8573 }
8574
8575
8576
8577
8578
8579 memset(mboxq, 0, sizeof(LPFC_MBOXQ_t));
8580 memcpy(&mboxq->u.mqe, &endian_mb_data, sizeof(endian_mb_data));
8581 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
8582 if (rc != MBX_SUCCESS) {
8583 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8584 "0493 SLI_CONFIG_SPECIAL mailbox "
8585 "failed with status x%x\n",
8586 rc);
8587 rc = -EIO;
8588 }
8589 mempool_free(mboxq, phba->mbox_mem_pool);
8590 break;
8591 case LPFC_SLI_INTF_IF_TYPE_6:
8592 case LPFC_SLI_INTF_IF_TYPE_2:
8593 case LPFC_SLI_INTF_IF_TYPE_1:
8594 default:
8595 break;
8596 }
8597 return rc;
8598}
8599
8600
8601
8602
8603
8604
8605
8606
8607
8608
8609
8610
8611
8612
8613static int
8614lpfc_sli4_queue_verify(struct lpfc_hba *phba)
8615{
8616
8617
8618
8619
8620
8621 if (phba->nvmet_support) {
8622 if (phba->cfg_irq_chann < phba->cfg_nvmet_mrq)
8623 phba->cfg_nvmet_mrq = phba->cfg_irq_chann;
8624 if (phba->cfg_nvmet_mrq > LPFC_NVMET_MRQ_MAX)
8625 phba->cfg_nvmet_mrq = LPFC_NVMET_MRQ_MAX;
8626 }
8627
8628 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8629 "2574 IO channels: hdwQ %d IRQ %d MRQ: %d\n",
8630 phba->cfg_hdw_queue, phba->cfg_irq_chann,
8631 phba->cfg_nvmet_mrq);
8632
8633
8634 phba->sli4_hba.eq_esize = LPFC_EQE_SIZE_4B;
8635 phba->sli4_hba.eq_ecount = LPFC_EQE_DEF_COUNT;
8636
8637
8638 phba->sli4_hba.cq_esize = LPFC_CQE_SIZE;
8639 phba->sli4_hba.cq_ecount = LPFC_CQE_DEF_COUNT;
8640 return 0;
8641}
8642
8643static int
8644lpfc_alloc_io_wq_cq(struct lpfc_hba *phba, int idx)
8645{
8646 struct lpfc_queue *qdesc;
8647 u32 wqesize;
8648 int cpu;
8649
8650 cpu = lpfc_find_cpu_handle(phba, idx, LPFC_FIND_BY_HDWQ);
8651
8652 if (phba->enab_exp_wqcq_pages)
8653
8654 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_EXPANDED_PAGE_SIZE,
8655 phba->sli4_hba.cq_esize,
8656 LPFC_CQE_EXP_COUNT, cpu);
8657
8658 else
8659 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8660 phba->sli4_hba.cq_esize,
8661 phba->sli4_hba.cq_ecount, cpu);
8662 if (!qdesc) {
8663 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8664 "0499 Failed allocate fast-path IO CQ (%d)\n", idx);
8665 return 1;
8666 }
8667 qdesc->qe_valid = 1;
8668 qdesc->hdwq = idx;
8669 qdesc->chann = cpu;
8670 phba->sli4_hba.hdwq[idx].io_cq = qdesc;
8671
8672
8673 if (phba->enab_exp_wqcq_pages) {
8674
8675 wqesize = (phba->fcp_embed_io) ?
8676 LPFC_WQE128_SIZE : phba->sli4_hba.wq_esize;
8677 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_EXPANDED_PAGE_SIZE,
8678 wqesize,
8679 LPFC_WQE_EXP_COUNT, cpu);
8680 } else
8681 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8682 phba->sli4_hba.wq_esize,
8683 phba->sli4_hba.wq_ecount, cpu);
8684
8685 if (!qdesc) {
8686 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8687 "0503 Failed allocate fast-path IO WQ (%d)\n",
8688 idx);
8689 return 1;
8690 }
8691 qdesc->hdwq = idx;
8692 qdesc->chann = cpu;
8693 phba->sli4_hba.hdwq[idx].io_wq = qdesc;
8694 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
8695 return 0;
8696}
8697
8698
8699
8700
8701
8702
8703
8704
8705
8706
8707
8708
8709
8710
8711
8712int
8713lpfc_sli4_queue_create(struct lpfc_hba *phba)
8714{
8715 struct lpfc_queue *qdesc;
8716 int idx, cpu, eqcpu;
8717 struct lpfc_sli4_hdw_queue *qp;
8718 struct lpfc_vector_map_info *cpup;
8719 struct lpfc_vector_map_info *eqcpup;
8720 struct lpfc_eq_intr_info *eqi;
8721
8722
8723
8724
8725
8726 phba->sli4_hba.mq_esize = LPFC_MQE_SIZE;
8727 phba->sli4_hba.mq_ecount = LPFC_MQE_DEF_COUNT;
8728 phba->sli4_hba.wq_esize = LPFC_WQE_SIZE;
8729 phba->sli4_hba.wq_ecount = LPFC_WQE_DEF_COUNT;
8730 phba->sli4_hba.rq_esize = LPFC_RQE_SIZE;
8731 phba->sli4_hba.rq_ecount = LPFC_RQE_DEF_COUNT;
8732 phba->sli4_hba.eq_esize = LPFC_EQE_SIZE_4B;
8733 phba->sli4_hba.eq_ecount = LPFC_EQE_DEF_COUNT;
8734 phba->sli4_hba.cq_esize = LPFC_CQE_SIZE;
8735 phba->sli4_hba.cq_ecount = LPFC_CQE_DEF_COUNT;
8736
8737 if (!phba->sli4_hba.hdwq) {
8738 phba->sli4_hba.hdwq = kcalloc(
8739 phba->cfg_hdw_queue, sizeof(struct lpfc_sli4_hdw_queue),
8740 GFP_KERNEL);
8741 if (!phba->sli4_hba.hdwq) {
8742 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8743 "6427 Failed allocate memory for "
8744 "fast-path Hardware Queue array\n");
8745 goto out_error;
8746 }
8747
8748 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
8749 qp = &phba->sli4_hba.hdwq[idx];
8750 spin_lock_init(&qp->io_buf_list_get_lock);
8751 spin_lock_init(&qp->io_buf_list_put_lock);
8752 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_get);
8753 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_put);
8754 qp->get_io_bufs = 0;
8755 qp->put_io_bufs = 0;
8756 qp->total_io_bufs = 0;
8757 spin_lock_init(&qp->abts_io_buf_list_lock);
8758 INIT_LIST_HEAD(&qp->lpfc_abts_io_buf_list);
8759 qp->abts_scsi_io_bufs = 0;
8760 qp->abts_nvme_io_bufs = 0;
8761 INIT_LIST_HEAD(&qp->sgl_list);
8762 INIT_LIST_HEAD(&qp->cmd_rsp_buf_list);
8763 spin_lock_init(&qp->hdwq_lock);
8764 }
8765 }
8766
8767 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
8768 if (phba->nvmet_support) {
8769 phba->sli4_hba.nvmet_cqset = kcalloc(
8770 phba->cfg_nvmet_mrq,
8771 sizeof(struct lpfc_queue *),
8772 GFP_KERNEL);
8773 if (!phba->sli4_hba.nvmet_cqset) {
8774 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8775 "3121 Fail allocate memory for "
8776 "fast-path CQ set array\n");
8777 goto out_error;
8778 }
8779 phba->sli4_hba.nvmet_mrq_hdr = kcalloc(
8780 phba->cfg_nvmet_mrq,
8781 sizeof(struct lpfc_queue *),
8782 GFP_KERNEL);
8783 if (!phba->sli4_hba.nvmet_mrq_hdr) {
8784 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8785 "3122 Fail allocate memory for "
8786 "fast-path RQ set hdr array\n");
8787 goto out_error;
8788 }
8789 phba->sli4_hba.nvmet_mrq_data = kcalloc(
8790 phba->cfg_nvmet_mrq,
8791 sizeof(struct lpfc_queue *),
8792 GFP_KERNEL);
8793 if (!phba->sli4_hba.nvmet_mrq_data) {
8794 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8795 "3124 Fail allocate memory for "
8796 "fast-path RQ set data array\n");
8797 goto out_error;
8798 }
8799 }
8800 }
8801
8802 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_wq_list);
8803
8804
8805 for_each_present_cpu(cpu) {
8806
8807
8808
8809
8810 cpup = &phba->sli4_hba.cpu_map[cpu];
8811 if (!(cpup->flag & LPFC_CPU_FIRST_IRQ))
8812 continue;
8813
8814
8815 qp = &phba->sli4_hba.hdwq[cpup->hdwq];
8816
8817
8818 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8819 phba->sli4_hba.eq_esize,
8820 phba->sli4_hba.eq_ecount, cpu);
8821 if (!qdesc) {
8822 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8823 "0497 Failed allocate EQ (%d)\n",
8824 cpup->hdwq);
8825 goto out_error;
8826 }
8827 qdesc->qe_valid = 1;
8828 qdesc->hdwq = cpup->hdwq;
8829 qdesc->chann = cpu;
8830 qdesc->last_cpu = qdesc->chann;
8831
8832
8833 qp->hba_eq = qdesc;
8834
8835 eqi = per_cpu_ptr(phba->sli4_hba.eq_info, qdesc->last_cpu);
8836 list_add(&qdesc->cpu_list, &eqi->list);
8837 }
8838
8839
8840
8841
8842 for_each_present_cpu(cpu) {
8843 cpup = &phba->sli4_hba.cpu_map[cpu];
8844
8845
8846 if (cpup->flag & LPFC_CPU_FIRST_IRQ)
8847 continue;
8848
8849
8850 qp = &phba->sli4_hba.hdwq[cpup->hdwq];
8851 if (qp->hba_eq)
8852 continue;
8853
8854
8855 eqcpu = lpfc_find_cpu_handle(phba, cpup->eq, LPFC_FIND_BY_EQ);
8856 eqcpup = &phba->sli4_hba.cpu_map[eqcpu];
8857 qp->hba_eq = phba->sli4_hba.hdwq[eqcpup->hdwq].hba_eq;
8858 }
8859
8860
8861 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
8862 if (lpfc_alloc_io_wq_cq(phba, idx))
8863 goto out_error;
8864 }
8865
8866 if (phba->nvmet_support) {
8867 for (idx = 0; idx < phba->cfg_nvmet_mrq; idx++) {
8868 cpu = lpfc_find_cpu_handle(phba, idx,
8869 LPFC_FIND_BY_HDWQ);
8870 qdesc = lpfc_sli4_queue_alloc(phba,
8871 LPFC_DEFAULT_PAGE_SIZE,
8872 phba->sli4_hba.cq_esize,
8873 phba->sli4_hba.cq_ecount,
8874 cpu);
8875 if (!qdesc) {
8876 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8877 "3142 Failed allocate NVME "
8878 "CQ Set (%d)\n", idx);
8879 goto out_error;
8880 }
8881 qdesc->qe_valid = 1;
8882 qdesc->hdwq = idx;
8883 qdesc->chann = cpu;
8884 phba->sli4_hba.nvmet_cqset[idx] = qdesc;
8885 }
8886 }
8887
8888
8889
8890
8891
8892 cpu = lpfc_find_cpu_handle(phba, 0, LPFC_FIND_BY_EQ);
8893
8894 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8895 phba->sli4_hba.cq_esize,
8896 phba->sli4_hba.cq_ecount, cpu);
8897 if (!qdesc) {
8898 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8899 "0500 Failed allocate slow-path mailbox CQ\n");
8900 goto out_error;
8901 }
8902 qdesc->qe_valid = 1;
8903 phba->sli4_hba.mbx_cq = qdesc;
8904
8905
8906 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8907 phba->sli4_hba.cq_esize,
8908 phba->sli4_hba.cq_ecount, cpu);
8909 if (!qdesc) {
8910 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8911 "0501 Failed allocate slow-path ELS CQ\n");
8912 goto out_error;
8913 }
8914 qdesc->qe_valid = 1;
8915 qdesc->chann = cpu;
8916 phba->sli4_hba.els_cq = qdesc;
8917
8918
8919
8920
8921
8922
8923
8924
8925 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8926 phba->sli4_hba.mq_esize,
8927 phba->sli4_hba.mq_ecount, cpu);
8928 if (!qdesc) {
8929 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8930 "0505 Failed allocate slow-path MQ\n");
8931 goto out_error;
8932 }
8933 qdesc->chann = cpu;
8934 phba->sli4_hba.mbx_wq = qdesc;
8935
8936
8937
8938
8939
8940
8941 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8942 phba->sli4_hba.wq_esize,
8943 phba->sli4_hba.wq_ecount, cpu);
8944 if (!qdesc) {
8945 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8946 "0504 Failed allocate slow-path ELS WQ\n");
8947 goto out_error;
8948 }
8949 qdesc->chann = cpu;
8950 phba->sli4_hba.els_wq = qdesc;
8951 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
8952
8953 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
8954
8955 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8956 phba->sli4_hba.cq_esize,
8957 phba->sli4_hba.cq_ecount, cpu);
8958 if (!qdesc) {
8959 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8960 "6079 Failed allocate NVME LS CQ\n");
8961 goto out_error;
8962 }
8963 qdesc->chann = cpu;
8964 qdesc->qe_valid = 1;
8965 phba->sli4_hba.nvmels_cq = qdesc;
8966
8967
8968 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8969 phba->sli4_hba.wq_esize,
8970 phba->sli4_hba.wq_ecount, cpu);
8971 if (!qdesc) {
8972 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8973 "6080 Failed allocate NVME LS WQ\n");
8974 goto out_error;
8975 }
8976 qdesc->chann = cpu;
8977 phba->sli4_hba.nvmels_wq = qdesc;
8978 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
8979 }
8980
8981
8982
8983
8984
8985
8986 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8987 phba->sli4_hba.rq_esize,
8988 phba->sli4_hba.rq_ecount, cpu);
8989 if (!qdesc) {
8990 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8991 "0506 Failed allocate receive HRQ\n");
8992 goto out_error;
8993 }
8994 phba->sli4_hba.hdr_rq = qdesc;
8995
8996
8997 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8998 phba->sli4_hba.rq_esize,
8999 phba->sli4_hba.rq_ecount, cpu);
9000 if (!qdesc) {
9001 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9002 "0507 Failed allocate receive DRQ\n");
9003 goto out_error;
9004 }
9005 phba->sli4_hba.dat_rq = qdesc;
9006
9007 if ((phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) &&
9008 phba->nvmet_support) {
9009 for (idx = 0; idx < phba->cfg_nvmet_mrq; idx++) {
9010 cpu = lpfc_find_cpu_handle(phba, idx,
9011 LPFC_FIND_BY_HDWQ);
9012
9013 qdesc = lpfc_sli4_queue_alloc(phba,
9014 LPFC_DEFAULT_PAGE_SIZE,
9015 phba->sli4_hba.rq_esize,
9016 LPFC_NVMET_RQE_DEF_COUNT,
9017 cpu);
9018 if (!qdesc) {
9019 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9020 "3146 Failed allocate "
9021 "receive HRQ\n");
9022 goto out_error;
9023 }
9024 qdesc->hdwq = idx;
9025 phba->sli4_hba.nvmet_mrq_hdr[idx] = qdesc;
9026
9027
9028 qdesc->rqbp = kzalloc_node(sizeof(*qdesc->rqbp),
9029 GFP_KERNEL,
9030 cpu_to_node(cpu));
9031 if (qdesc->rqbp == NULL) {
9032 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9033 "6131 Failed allocate "
9034 "Header RQBP\n");
9035 goto out_error;
9036 }
9037
9038
9039 INIT_LIST_HEAD(&qdesc->rqbp->rqb_buffer_list);
9040
9041
9042 qdesc = lpfc_sli4_queue_alloc(phba,
9043 LPFC_DEFAULT_PAGE_SIZE,
9044 phba->sli4_hba.rq_esize,
9045 LPFC_NVMET_RQE_DEF_COUNT,
9046 cpu);
9047 if (!qdesc) {
9048 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9049 "3156 Failed allocate "
9050 "receive DRQ\n");
9051 goto out_error;
9052 }
9053 qdesc->hdwq = idx;
9054 phba->sli4_hba.nvmet_mrq_data[idx] = qdesc;
9055 }
9056 }
9057
9058
9059 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
9060 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
9061 memset(&phba->sli4_hba.hdwq[idx].nvme_cstat, 0,
9062 sizeof(phba->sli4_hba.hdwq[idx].nvme_cstat));
9063 }
9064 }
9065
9066
9067 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) {
9068 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
9069 memset(&phba->sli4_hba.hdwq[idx].scsi_cstat, 0,
9070 sizeof(phba->sli4_hba.hdwq[idx].scsi_cstat));
9071 }
9072 }
9073
9074 return 0;
9075
9076out_error:
9077 lpfc_sli4_queue_destroy(phba);
9078 return -ENOMEM;
9079}
9080
9081static inline void
9082__lpfc_sli4_release_queue(struct lpfc_queue **qp)
9083{
9084 if (*qp != NULL) {
9085 lpfc_sli4_queue_free(*qp);
9086 *qp = NULL;
9087 }
9088}
9089
9090static inline void
9091lpfc_sli4_release_queues(struct lpfc_queue ***qs, int max)
9092{
9093 int idx;
9094
9095 if (*qs == NULL)
9096 return;
9097
9098 for (idx = 0; idx < max; idx++)
9099 __lpfc_sli4_release_queue(&(*qs)[idx]);
9100
9101 kfree(*qs);
9102 *qs = NULL;
9103}
9104
9105static inline void
9106lpfc_sli4_release_hdwq(struct lpfc_hba *phba)
9107{
9108 struct lpfc_sli4_hdw_queue *hdwq;
9109 struct lpfc_queue *eq;
9110 uint32_t idx;
9111
9112 hdwq = phba->sli4_hba.hdwq;
9113
9114
9115 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
9116
9117 lpfc_sli4_queue_free(hdwq[idx].io_cq);
9118 lpfc_sli4_queue_free(hdwq[idx].io_wq);
9119 hdwq[idx].io_cq = NULL;
9120 hdwq[idx].io_wq = NULL;
9121 if (phba->cfg_xpsgl && !phba->nvmet_support)
9122 lpfc_free_sgl_per_hdwq(phba, &hdwq[idx]);
9123 lpfc_free_cmd_rsp_buf_per_hdwq(phba, &hdwq[idx]);
9124 }
9125
9126 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
9127
9128 eq = phba->sli4_hba.hba_eq_hdl[idx].eq;
9129 lpfc_sli4_queue_free(eq);
9130 phba->sli4_hba.hba_eq_hdl[idx].eq = NULL;
9131 }
9132}
9133
9134
9135
9136
9137
9138
9139
9140
9141
9142
9143
9144
9145
9146void
9147lpfc_sli4_queue_destroy(struct lpfc_hba *phba)
9148{
9149
9150
9151
9152
9153
9154 spin_lock_irq(&phba->hbalock);
9155 phba->sli.sli_flag |= LPFC_QUEUE_FREE_INIT;
9156 while (phba->sli.sli_flag & LPFC_QUEUE_FREE_WAIT) {
9157 spin_unlock_irq(&phba->hbalock);
9158 msleep(20);
9159 spin_lock_irq(&phba->hbalock);
9160 }
9161 spin_unlock_irq(&phba->hbalock);
9162
9163
9164 if (phba->sli4_hba.hdwq)
9165 lpfc_sli4_release_hdwq(phba);
9166
9167 if (phba->nvmet_support) {
9168 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_cqset,
9169 phba->cfg_nvmet_mrq);
9170
9171 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_mrq_hdr,
9172 phba->cfg_nvmet_mrq);
9173 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_mrq_data,
9174 phba->cfg_nvmet_mrq);
9175 }
9176
9177
9178 __lpfc_sli4_release_queue(&phba->sli4_hba.mbx_wq);
9179
9180
9181 __lpfc_sli4_release_queue(&phba->sli4_hba.els_wq);
9182
9183
9184 __lpfc_sli4_release_queue(&phba->sli4_hba.nvmels_wq);
9185
9186
9187 __lpfc_sli4_release_queue(&phba->sli4_hba.hdr_rq);
9188 __lpfc_sli4_release_queue(&phba->sli4_hba.dat_rq);
9189
9190
9191 __lpfc_sli4_release_queue(&phba->sli4_hba.els_cq);
9192
9193
9194 __lpfc_sli4_release_queue(&phba->sli4_hba.nvmels_cq);
9195
9196
9197 __lpfc_sli4_release_queue(&phba->sli4_hba.mbx_cq);
9198
9199
9200 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_wq_list);
9201
9202
9203 spin_lock_irq(&phba->hbalock);
9204 phba->sli.sli_flag &= ~LPFC_QUEUE_FREE_INIT;
9205 spin_unlock_irq(&phba->hbalock);
9206}
9207
9208int
9209lpfc_free_rq_buffer(struct lpfc_hba *phba, struct lpfc_queue *rq)
9210{
9211 struct lpfc_rqb *rqbp;
9212 struct lpfc_dmabuf *h_buf;
9213 struct rqb_dmabuf *rqb_buffer;
9214
9215 rqbp = rq->rqbp;
9216 while (!list_empty(&rqbp->rqb_buffer_list)) {
9217 list_remove_head(&rqbp->rqb_buffer_list, h_buf,
9218 struct lpfc_dmabuf, list);
9219
9220 rqb_buffer = container_of(h_buf, struct rqb_dmabuf, hbuf);
9221 (rqbp->rqb_free_buffer)(phba, rqb_buffer);
9222 rqbp->buffer_count--;
9223 }
9224 return 1;
9225}
9226
9227static int
9228lpfc_create_wq_cq(struct lpfc_hba *phba, struct lpfc_queue *eq,
9229 struct lpfc_queue *cq, struct lpfc_queue *wq, uint16_t *cq_map,
9230 int qidx, uint32_t qtype)
9231{
9232 struct lpfc_sli_ring *pring;
9233 int rc;
9234
9235 if (!eq || !cq || !wq) {
9236 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9237 "6085 Fast-path %s (%d) not allocated\n",
9238 ((eq) ? ((cq) ? "WQ" : "CQ") : "EQ"), qidx);
9239 return -ENOMEM;
9240 }
9241
9242
9243 rc = lpfc_cq_create(phba, cq, eq,
9244 (qtype == LPFC_MBOX) ? LPFC_MCQ : LPFC_WCQ, qtype);
9245 if (rc) {
9246 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9247 "6086 Failed setup of CQ (%d), rc = 0x%x\n",
9248 qidx, (uint32_t)rc);
9249 return rc;
9250 }
9251
9252 if (qtype != LPFC_MBOX) {
9253
9254 if (cq_map)
9255 *cq_map = cq->queue_id;
9256
9257 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9258 "6087 CQ setup: cq[%d]-id=%d, parent eq[%d]-id=%d\n",
9259 qidx, cq->queue_id, qidx, eq->queue_id);
9260
9261
9262 rc = lpfc_wq_create(phba, wq, cq, qtype);
9263 if (rc) {
9264 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9265 "4618 Fail setup fastpath WQ (%d), rc = 0x%x\n",
9266 qidx, (uint32_t)rc);
9267
9268 return rc;
9269 }
9270
9271
9272 pring = wq->pring;
9273 pring->sli.sli4.wqp = (void *)wq;
9274 cq->pring = pring;
9275
9276 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9277 "2593 WQ setup: wq[%d]-id=%d assoc=%d, cq[%d]-id=%d\n",
9278 qidx, wq->queue_id, wq->assoc_qid, qidx, cq->queue_id);
9279 } else {
9280 rc = lpfc_mq_create(phba, wq, cq, LPFC_MBOX);
9281 if (rc) {
9282 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9283 "0539 Failed setup of slow-path MQ: "
9284 "rc = 0x%x\n", rc);
9285
9286 return rc;
9287 }
9288
9289 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9290 "2589 MBX MQ setup: wq-id=%d, parent cq-id=%d\n",
9291 phba->sli4_hba.mbx_wq->queue_id,
9292 phba->sli4_hba.mbx_cq->queue_id);
9293 }
9294
9295 return 0;
9296}
9297
9298
9299
9300
9301
9302
9303
9304
9305static void
9306lpfc_setup_cq_lookup(struct lpfc_hba *phba)
9307{
9308 struct lpfc_queue *eq, *childq;
9309 int qidx;
9310
9311 memset(phba->sli4_hba.cq_lookup, 0,
9312 (sizeof(struct lpfc_queue *) * (phba->sli4_hba.cq_max + 1)));
9313
9314 for (qidx = 0; qidx < phba->cfg_irq_chann; qidx++) {
9315
9316 eq = phba->sli4_hba.hba_eq_hdl[qidx].eq;
9317 if (!eq)
9318 continue;
9319
9320 list_for_each_entry(childq, &eq->child_list, list) {
9321 if (childq->queue_id > phba->sli4_hba.cq_max)
9322 continue;
9323 if (childq->subtype == LPFC_IO)
9324 phba->sli4_hba.cq_lookup[childq->queue_id] =
9325 childq;
9326 }
9327 }
9328}
9329
9330
9331
9332
9333
9334
9335
9336
9337
9338
9339
9340
9341
9342int
9343lpfc_sli4_queue_setup(struct lpfc_hba *phba)
9344{
9345 uint32_t shdr_status, shdr_add_status;
9346 union lpfc_sli4_cfg_shdr *shdr;
9347 struct lpfc_vector_map_info *cpup;
9348 struct lpfc_sli4_hdw_queue *qp;
9349 LPFC_MBOXQ_t *mboxq;
9350 int qidx, cpu;
9351 uint32_t length, usdelay;
9352 int rc = -ENOMEM;
9353
9354
9355 mboxq = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
9356 if (!mboxq) {
9357 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9358 "3249 Unable to allocate memory for "
9359 "QUERY_FW_CFG mailbox command\n");
9360 return -ENOMEM;
9361 }
9362 length = (sizeof(struct lpfc_mbx_query_fw_config) -
9363 sizeof(struct lpfc_sli4_cfg_mhdr));
9364 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
9365 LPFC_MBOX_OPCODE_QUERY_FW_CFG,
9366 length, LPFC_SLI4_MBX_EMBED);
9367
9368 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
9369
9370 shdr = (union lpfc_sli4_cfg_shdr *)
9371 &mboxq->u.mqe.un.sli4_config.header.cfg_shdr;
9372 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
9373 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &shdr->response);
9374 if (shdr_status || shdr_add_status || rc) {
9375 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9376 "3250 QUERY_FW_CFG mailbox failed with status "
9377 "x%x add_status x%x, mbx status x%x\n",
9378 shdr_status, shdr_add_status, rc);
9379 if (rc != MBX_TIMEOUT)
9380 mempool_free(mboxq, phba->mbox_mem_pool);
9381 rc = -ENXIO;
9382 goto out_error;
9383 }
9384
9385 phba->sli4_hba.fw_func_mode =
9386 mboxq->u.mqe.un.query_fw_cfg.rsp.function_mode;
9387 phba->sli4_hba.ulp0_mode = mboxq->u.mqe.un.query_fw_cfg.rsp.ulp0_mode;
9388 phba->sli4_hba.ulp1_mode = mboxq->u.mqe.un.query_fw_cfg.rsp.ulp1_mode;
9389 phba->sli4_hba.physical_port =
9390 mboxq->u.mqe.un.query_fw_cfg.rsp.physical_port;
9391 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9392 "3251 QUERY_FW_CFG: func_mode:x%x, ulp0_mode:x%x, "
9393 "ulp1_mode:x%x\n", phba->sli4_hba.fw_func_mode,
9394 phba->sli4_hba.ulp0_mode, phba->sli4_hba.ulp1_mode);
9395
9396 if (rc != MBX_TIMEOUT)
9397 mempool_free(mboxq, phba->mbox_mem_pool);
9398
9399
9400
9401
9402 qp = phba->sli4_hba.hdwq;
9403
9404
9405 if (!qp) {
9406 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9407 "3147 Fast-path EQs not allocated\n");
9408 rc = -ENOMEM;
9409 goto out_error;
9410 }
9411
9412
9413 for (qidx = 0; qidx < phba->cfg_irq_chann; qidx++) {
9414
9415 for_each_present_cpu(cpu) {
9416 cpup = &phba->sli4_hba.cpu_map[cpu];
9417
9418
9419
9420
9421 if (!(cpup->flag & LPFC_CPU_FIRST_IRQ))
9422 continue;
9423 if (qidx != cpup->eq)
9424 continue;
9425
9426
9427 rc = lpfc_eq_create(phba, qp[cpup->hdwq].hba_eq,
9428 phba->cfg_fcp_imax);
9429 if (rc) {
9430 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9431 "0523 Failed setup of fast-path"
9432 " EQ (%d), rc = 0x%x\n",
9433 cpup->eq, (uint32_t)rc);
9434 goto out_destroy;
9435 }
9436
9437
9438 phba->sli4_hba.hba_eq_hdl[cpup->eq].eq =
9439 qp[cpup->hdwq].hba_eq;
9440
9441 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9442 "2584 HBA EQ setup: queue[%d]-id=%d\n",
9443 cpup->eq,
9444 qp[cpup->hdwq].hba_eq->queue_id);
9445 }
9446 }
9447
9448
9449 for (qidx = 0; qidx < phba->cfg_hdw_queue; qidx++) {
9450 cpu = lpfc_find_cpu_handle(phba, qidx, LPFC_FIND_BY_HDWQ);
9451 cpup = &phba->sli4_hba.cpu_map[cpu];
9452
9453
9454 rc = lpfc_create_wq_cq(phba,
9455 phba->sli4_hba.hdwq[cpup->hdwq].hba_eq,
9456 qp[qidx].io_cq,
9457 qp[qidx].io_wq,
9458 &phba->sli4_hba.hdwq[qidx].io_cq_map,
9459 qidx,
9460 LPFC_IO);
9461 if (rc) {
9462 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9463 "0535 Failed to setup fastpath "
9464 "IO WQ/CQ (%d), rc = 0x%x\n",
9465 qidx, (uint32_t)rc);
9466 goto out_destroy;
9467 }
9468 }
9469
9470
9471
9472
9473
9474
9475
9476 if (!phba->sli4_hba.mbx_cq || !phba->sli4_hba.mbx_wq) {
9477 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9478 "0528 %s not allocated\n",
9479 phba->sli4_hba.mbx_cq ?
9480 "Mailbox WQ" : "Mailbox CQ");
9481 rc = -ENOMEM;
9482 goto out_destroy;
9483 }
9484
9485 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
9486 phba->sli4_hba.mbx_cq,
9487 phba->sli4_hba.mbx_wq,
9488 NULL, 0, LPFC_MBOX);
9489 if (rc) {
9490 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9491 "0529 Failed setup of mailbox WQ/CQ: rc = 0x%x\n",
9492 (uint32_t)rc);
9493 goto out_destroy;
9494 }
9495 if (phba->nvmet_support) {
9496 if (!phba->sli4_hba.nvmet_cqset) {
9497 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9498 "3165 Fast-path NVME CQ Set "
9499 "array not allocated\n");
9500 rc = -ENOMEM;
9501 goto out_destroy;
9502 }
9503 if (phba->cfg_nvmet_mrq > 1) {
9504 rc = lpfc_cq_create_set(phba,
9505 phba->sli4_hba.nvmet_cqset,
9506 qp,
9507 LPFC_WCQ, LPFC_NVMET);
9508 if (rc) {
9509 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9510 "3164 Failed setup of NVME CQ "
9511 "Set, rc = 0x%x\n",
9512 (uint32_t)rc);
9513 goto out_destroy;
9514 }
9515 } else {
9516
9517 rc = lpfc_cq_create(phba, phba->sli4_hba.nvmet_cqset[0],
9518 qp[0].hba_eq,
9519 LPFC_WCQ, LPFC_NVMET);
9520 if (rc) {
9521 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9522 "6089 Failed setup NVMET CQ: "
9523 "rc = 0x%x\n", (uint32_t)rc);
9524 goto out_destroy;
9525 }
9526 phba->sli4_hba.nvmet_cqset[0]->chann = 0;
9527
9528 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9529 "6090 NVMET CQ setup: cq-id=%d, "
9530 "parent eq-id=%d\n",
9531 phba->sli4_hba.nvmet_cqset[0]->queue_id,
9532 qp[0].hba_eq->queue_id);
9533 }
9534 }
9535
9536
9537 if (!phba->sli4_hba.els_cq || !phba->sli4_hba.els_wq) {
9538 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9539 "0530 ELS %s not allocated\n",
9540 phba->sli4_hba.els_cq ? "WQ" : "CQ");
9541 rc = -ENOMEM;
9542 goto out_destroy;
9543 }
9544 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
9545 phba->sli4_hba.els_cq,
9546 phba->sli4_hba.els_wq,
9547 NULL, 0, LPFC_ELS);
9548 if (rc) {
9549 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9550 "0525 Failed setup of ELS WQ/CQ: rc = 0x%x\n",
9551 (uint32_t)rc);
9552 goto out_destroy;
9553 }
9554 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9555 "2590 ELS WQ setup: wq-id=%d, parent cq-id=%d\n",
9556 phba->sli4_hba.els_wq->queue_id,
9557 phba->sli4_hba.els_cq->queue_id);
9558
9559 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
9560
9561 if (!phba->sli4_hba.nvmels_cq || !phba->sli4_hba.nvmels_wq) {
9562 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9563 "6091 LS %s not allocated\n",
9564 phba->sli4_hba.nvmels_cq ? "WQ" : "CQ");
9565 rc = -ENOMEM;
9566 goto out_destroy;
9567 }
9568 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
9569 phba->sli4_hba.nvmels_cq,
9570 phba->sli4_hba.nvmels_wq,
9571 NULL, 0, LPFC_NVME_LS);
9572 if (rc) {
9573 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9574 "0526 Failed setup of NVVME LS WQ/CQ: "
9575 "rc = 0x%x\n", (uint32_t)rc);
9576 goto out_destroy;
9577 }
9578
9579 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9580 "6096 ELS WQ setup: wq-id=%d, "
9581 "parent cq-id=%d\n",
9582 phba->sli4_hba.nvmels_wq->queue_id,
9583 phba->sli4_hba.nvmels_cq->queue_id);
9584 }
9585
9586
9587
9588
9589 if (phba->nvmet_support) {
9590 if ((!phba->sli4_hba.nvmet_cqset) ||
9591 (!phba->sli4_hba.nvmet_mrq_hdr) ||
9592 (!phba->sli4_hba.nvmet_mrq_data)) {
9593 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9594 "6130 MRQ CQ Queues not "
9595 "allocated\n");
9596 rc = -ENOMEM;
9597 goto out_destroy;
9598 }
9599 if (phba->cfg_nvmet_mrq > 1) {
9600 rc = lpfc_mrq_create(phba,
9601 phba->sli4_hba.nvmet_mrq_hdr,
9602 phba->sli4_hba.nvmet_mrq_data,
9603 phba->sli4_hba.nvmet_cqset,
9604 LPFC_NVMET);
9605 if (rc) {
9606 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9607 "6098 Failed setup of NVMET "
9608 "MRQ: rc = 0x%x\n",
9609 (uint32_t)rc);
9610 goto out_destroy;
9611 }
9612
9613 } else {
9614 rc = lpfc_rq_create(phba,
9615 phba->sli4_hba.nvmet_mrq_hdr[0],
9616 phba->sli4_hba.nvmet_mrq_data[0],
9617 phba->sli4_hba.nvmet_cqset[0],
9618 LPFC_NVMET);
9619 if (rc) {
9620 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9621 "6057 Failed setup of NVMET "
9622 "Receive Queue: rc = 0x%x\n",
9623 (uint32_t)rc);
9624 goto out_destroy;
9625 }
9626
9627 lpfc_printf_log(
9628 phba, KERN_INFO, LOG_INIT,
9629 "6099 NVMET RQ setup: hdr-rq-id=%d, "
9630 "dat-rq-id=%d parent cq-id=%d\n",
9631 phba->sli4_hba.nvmet_mrq_hdr[0]->queue_id,
9632 phba->sli4_hba.nvmet_mrq_data[0]->queue_id,
9633 phba->sli4_hba.nvmet_cqset[0]->queue_id);
9634
9635 }
9636 }
9637
9638 if (!phba->sli4_hba.hdr_rq || !phba->sli4_hba.dat_rq) {
9639 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9640 "0540 Receive Queue not allocated\n");
9641 rc = -ENOMEM;
9642 goto out_destroy;
9643 }
9644
9645 rc = lpfc_rq_create(phba, phba->sli4_hba.hdr_rq, phba->sli4_hba.dat_rq,
9646 phba->sli4_hba.els_cq, LPFC_USOL);
9647 if (rc) {
9648 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9649 "0541 Failed setup of Receive Queue: "
9650 "rc = 0x%x\n", (uint32_t)rc);
9651 goto out_destroy;
9652 }
9653
9654 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9655 "2592 USL RQ setup: hdr-rq-id=%d, dat-rq-id=%d "
9656 "parent cq-id=%d\n",
9657 phba->sli4_hba.hdr_rq->queue_id,
9658 phba->sli4_hba.dat_rq->queue_id,
9659 phba->sli4_hba.els_cq->queue_id);
9660
9661 if (phba->cfg_fcp_imax)
9662 usdelay = LPFC_SEC_TO_USEC / phba->cfg_fcp_imax;
9663 else
9664 usdelay = 0;
9665
9666 for (qidx = 0; qidx < phba->cfg_irq_chann;
9667 qidx += LPFC_MAX_EQ_DELAY_EQID_CNT)
9668 lpfc_modify_hba_eq_delay(phba, qidx, LPFC_MAX_EQ_DELAY_EQID_CNT,
9669 usdelay);
9670
9671 if (phba->sli4_hba.cq_max) {
9672 kfree(phba->sli4_hba.cq_lookup);
9673 phba->sli4_hba.cq_lookup = kcalloc((phba->sli4_hba.cq_max + 1),
9674 sizeof(struct lpfc_queue *), GFP_KERNEL);
9675 if (!phba->sli4_hba.cq_lookup) {
9676 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9677 "0549 Failed setup of CQ Lookup table: "
9678 "size 0x%x\n", phba->sli4_hba.cq_max);
9679 rc = -ENOMEM;
9680 goto out_destroy;
9681 }
9682 lpfc_setup_cq_lookup(phba);
9683 }
9684 return 0;
9685
9686out_destroy:
9687 lpfc_sli4_queue_unset(phba);
9688out_error:
9689 return rc;
9690}
9691
9692
9693
9694
9695
9696
9697
9698
9699
9700
9701
9702
9703
9704void
9705lpfc_sli4_queue_unset(struct lpfc_hba *phba)
9706{
9707 struct lpfc_sli4_hdw_queue *qp;
9708 struct lpfc_queue *eq;
9709 int qidx;
9710
9711
9712 if (phba->sli4_hba.mbx_wq)
9713 lpfc_mq_destroy(phba, phba->sli4_hba.mbx_wq);
9714
9715
9716 if (phba->sli4_hba.nvmels_wq)
9717 lpfc_wq_destroy(phba, phba->sli4_hba.nvmels_wq);
9718
9719
9720 if (phba->sli4_hba.els_wq)
9721 lpfc_wq_destroy(phba, phba->sli4_hba.els_wq);
9722
9723
9724 if (phba->sli4_hba.hdr_rq)
9725 lpfc_rq_destroy(phba, phba->sli4_hba.hdr_rq,
9726 phba->sli4_hba.dat_rq);
9727
9728
9729 if (phba->sli4_hba.mbx_cq)
9730 lpfc_cq_destroy(phba, phba->sli4_hba.mbx_cq);
9731
9732
9733 if (phba->sli4_hba.els_cq)
9734 lpfc_cq_destroy(phba, phba->sli4_hba.els_cq);
9735
9736
9737 if (phba->sli4_hba.nvmels_cq)
9738 lpfc_cq_destroy(phba, phba->sli4_hba.nvmels_cq);
9739
9740 if (phba->nvmet_support) {
9741
9742 if (phba->sli4_hba.nvmet_mrq_hdr) {
9743 for (qidx = 0; qidx < phba->cfg_nvmet_mrq; qidx++)
9744 lpfc_rq_destroy(
9745 phba,
9746 phba->sli4_hba.nvmet_mrq_hdr[qidx],
9747 phba->sli4_hba.nvmet_mrq_data[qidx]);
9748 }
9749
9750
9751 if (phba->sli4_hba.nvmet_cqset) {
9752 for (qidx = 0; qidx < phba->cfg_nvmet_mrq; qidx++)
9753 lpfc_cq_destroy(
9754 phba, phba->sli4_hba.nvmet_cqset[qidx]);
9755 }
9756 }
9757
9758
9759 if (phba->sli4_hba.hdwq) {
9760
9761 for (qidx = 0; qidx < phba->cfg_hdw_queue; qidx++) {
9762
9763 qp = &phba->sli4_hba.hdwq[qidx];
9764 lpfc_wq_destroy(phba, qp->io_wq);
9765 lpfc_cq_destroy(phba, qp->io_cq);
9766 }
9767
9768 for (qidx = 0; qidx < phba->cfg_irq_chann; qidx++) {
9769
9770 eq = phba->sli4_hba.hba_eq_hdl[qidx].eq;
9771 lpfc_eq_destroy(phba, eq);
9772 }
9773 }
9774
9775 kfree(phba->sli4_hba.cq_lookup);
9776 phba->sli4_hba.cq_lookup = NULL;
9777 phba->sli4_hba.cq_max = 0;
9778}
9779
9780
9781
9782
9783
9784
9785
9786
9787
9788
9789
9790
9791
9792
9793
9794
9795
9796static int
9797lpfc_sli4_cq_event_pool_create(struct lpfc_hba *phba)
9798{
9799 struct lpfc_cq_event *cq_event;
9800 int i;
9801
9802 for (i = 0; i < (4 * phba->sli4_hba.cq_ecount); i++) {
9803 cq_event = kmalloc(sizeof(struct lpfc_cq_event), GFP_KERNEL);
9804 if (!cq_event)
9805 goto out_pool_create_fail;
9806 list_add_tail(&cq_event->list,
9807 &phba->sli4_hba.sp_cqe_event_pool);
9808 }
9809 return 0;
9810
9811out_pool_create_fail:
9812 lpfc_sli4_cq_event_pool_destroy(phba);
9813 return -ENOMEM;
9814}
9815
9816
9817
9818
9819
9820
9821
9822
9823
9824
9825
9826static void
9827lpfc_sli4_cq_event_pool_destroy(struct lpfc_hba *phba)
9828{
9829 struct lpfc_cq_event *cq_event, *next_cq_event;
9830
9831 list_for_each_entry_safe(cq_event, next_cq_event,
9832 &phba->sli4_hba.sp_cqe_event_pool, list) {
9833 list_del(&cq_event->list);
9834 kfree(cq_event);
9835 }
9836}
9837
9838
9839
9840
9841
9842
9843
9844
9845
9846
9847
9848struct lpfc_cq_event *
9849__lpfc_sli4_cq_event_alloc(struct lpfc_hba *phba)
9850{
9851 struct lpfc_cq_event *cq_event = NULL;
9852
9853 list_remove_head(&phba->sli4_hba.sp_cqe_event_pool, cq_event,
9854 struct lpfc_cq_event, list);
9855 return cq_event;
9856}
9857
9858
9859
9860
9861
9862
9863
9864
9865
9866
9867
9868struct lpfc_cq_event *
9869lpfc_sli4_cq_event_alloc(struct lpfc_hba *phba)
9870{
9871 struct lpfc_cq_event *cq_event;
9872 unsigned long iflags;
9873
9874 spin_lock_irqsave(&phba->hbalock, iflags);
9875 cq_event = __lpfc_sli4_cq_event_alloc(phba);
9876 spin_unlock_irqrestore(&phba->hbalock, iflags);
9877 return cq_event;
9878}
9879
9880
9881
9882
9883
9884
9885
9886
9887
9888void
9889__lpfc_sli4_cq_event_release(struct lpfc_hba *phba,
9890 struct lpfc_cq_event *cq_event)
9891{
9892 list_add_tail(&cq_event->list, &phba->sli4_hba.sp_cqe_event_pool);
9893}
9894
9895
9896
9897
9898
9899
9900
9901
9902
9903void
9904lpfc_sli4_cq_event_release(struct lpfc_hba *phba,
9905 struct lpfc_cq_event *cq_event)
9906{
9907 unsigned long iflags;
9908 spin_lock_irqsave(&phba->hbalock, iflags);
9909 __lpfc_sli4_cq_event_release(phba, cq_event);
9910 spin_unlock_irqrestore(&phba->hbalock, iflags);
9911}
9912
9913
9914
9915
9916
9917
9918
9919
9920static void
9921lpfc_sli4_cq_event_release_all(struct lpfc_hba *phba)
9922{
9923 LIST_HEAD(cqelist);
9924 struct lpfc_cq_event *cqe;
9925 unsigned long iflags;
9926
9927
9928 spin_lock_irqsave(&phba->hbalock, iflags);
9929
9930 list_splice_init(&phba->sli4_hba.sp_fcp_xri_aborted_work_queue,
9931 &cqelist);
9932
9933 list_splice_init(&phba->sli4_hba.sp_els_xri_aborted_work_queue,
9934 &cqelist);
9935
9936 list_splice_init(&phba->sli4_hba.sp_asynce_work_queue,
9937 &cqelist);
9938 spin_unlock_irqrestore(&phba->hbalock, iflags);
9939
9940 while (!list_empty(&cqelist)) {
9941 list_remove_head(&cqelist, cqe, struct lpfc_cq_event, list);
9942 lpfc_sli4_cq_event_release(phba, cqe);
9943 }
9944}
9945
9946
9947
9948
9949
9950
9951
9952
9953
9954
9955
9956
9957
9958int
9959lpfc_pci_function_reset(struct lpfc_hba *phba)
9960{
9961 LPFC_MBOXQ_t *mboxq;
9962 uint32_t rc = 0, if_type;
9963 uint32_t shdr_status, shdr_add_status;
9964 uint32_t rdy_chk;
9965 uint32_t port_reset = 0;
9966 union lpfc_sli4_cfg_shdr *shdr;
9967 struct lpfc_register reg_data;
9968 uint16_t devid;
9969
9970 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
9971 switch (if_type) {
9972 case LPFC_SLI_INTF_IF_TYPE_0:
9973 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
9974 GFP_KERNEL);
9975 if (!mboxq) {
9976 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9977 "0494 Unable to allocate memory for "
9978 "issuing SLI_FUNCTION_RESET mailbox "
9979 "command\n");
9980 return -ENOMEM;
9981 }
9982
9983
9984 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
9985 LPFC_MBOX_OPCODE_FUNCTION_RESET, 0,
9986 LPFC_SLI4_MBX_EMBED);
9987 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
9988 shdr = (union lpfc_sli4_cfg_shdr *)
9989 &mboxq->u.mqe.un.sli4_config.header.cfg_shdr;
9990 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
9991 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status,
9992 &shdr->response);
9993 if (rc != MBX_TIMEOUT)
9994 mempool_free(mboxq, phba->mbox_mem_pool);
9995 if (shdr_status || shdr_add_status || rc) {
9996 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9997 "0495 SLI_FUNCTION_RESET mailbox "
9998 "failed with status x%x add_status x%x,"
9999 " mbx status x%x\n",
10000 shdr_status, shdr_add_status, rc);
10001 rc = -ENXIO;
10002 }
10003 break;
10004 case LPFC_SLI_INTF_IF_TYPE_2:
10005 case LPFC_SLI_INTF_IF_TYPE_6:
10006wait:
10007
10008
10009
10010
10011
10012 for (rdy_chk = 0; rdy_chk < 1500; rdy_chk++) {
10013 if (lpfc_readl(phba->sli4_hba.u.if_type2.
10014 STATUSregaddr, ®_data.word0)) {
10015 rc = -ENODEV;
10016 goto out;
10017 }
10018 if (bf_get(lpfc_sliport_status_rdy, ®_data))
10019 break;
10020 msleep(20);
10021 }
10022
10023 if (!bf_get(lpfc_sliport_status_rdy, ®_data)) {
10024 phba->work_status[0] = readl(
10025 phba->sli4_hba.u.if_type2.ERR1regaddr);
10026 phba->work_status[1] = readl(
10027 phba->sli4_hba.u.if_type2.ERR2regaddr);
10028 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10029 "2890 Port not ready, port status reg "
10030 "0x%x error 1=0x%x, error 2=0x%x\n",
10031 reg_data.word0,
10032 phba->work_status[0],
10033 phba->work_status[1]);
10034 rc = -ENODEV;
10035 goto out;
10036 }
10037
10038 if (!port_reset) {
10039
10040
10041
10042 reg_data.word0 = 0;
10043 bf_set(lpfc_sliport_ctrl_end, ®_data,
10044 LPFC_SLIPORT_LITTLE_ENDIAN);
10045 bf_set(lpfc_sliport_ctrl_ip, ®_data,
10046 LPFC_SLIPORT_INIT_PORT);
10047 writel(reg_data.word0, phba->sli4_hba.u.if_type2.
10048 CTRLregaddr);
10049
10050 pci_read_config_word(phba->pcidev,
10051 PCI_DEVICE_ID, &devid);
10052
10053 port_reset = 1;
10054 msleep(20);
10055 goto wait;
10056 } else if (bf_get(lpfc_sliport_status_rn, ®_data)) {
10057 rc = -ENODEV;
10058 goto out;
10059 }
10060 break;
10061
10062 case LPFC_SLI_INTF_IF_TYPE_1:
10063 default:
10064 break;
10065 }
10066
10067out:
10068
10069 if (rc) {
10070 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10071 "3317 HBA not functional: IP Reset Failed "
10072 "try: echo fw_reset > board_mode\n");
10073 rc = -ENODEV;
10074 }
10075
10076 return rc;
10077}
10078
10079
10080
10081
10082
10083
10084
10085
10086
10087
10088
10089
10090static int
10091lpfc_sli4_pci_mem_setup(struct lpfc_hba *phba)
10092{
10093 struct pci_dev *pdev = phba->pcidev;
10094 unsigned long bar0map_len, bar1map_len, bar2map_len;
10095 int error;
10096 uint32_t if_type;
10097
10098 if (!pdev)
10099 return -ENODEV;
10100
10101
10102 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
10103 if (error)
10104 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10105 if (error)
10106 return error;
10107
10108
10109
10110
10111
10112 if (pci_read_config_dword(pdev, LPFC_SLI_INTF,
10113 &phba->sli4_hba.sli_intf.word0)) {
10114 return -ENODEV;
10115 }
10116
10117
10118 if (bf_get(lpfc_sli_intf_valid, &phba->sli4_hba.sli_intf) !=
10119 LPFC_SLI_INTF_VALID) {
10120 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10121 "2894 SLI_INTF reg contents invalid "
10122 "sli_intf reg 0x%x\n",
10123 phba->sli4_hba.sli_intf.word0);
10124 return -ENODEV;
10125 }
10126
10127 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
10128
10129
10130
10131
10132
10133
10134 if (pci_resource_start(pdev, PCI_64BIT_BAR0)) {
10135 phba->pci_bar0_map = pci_resource_start(pdev, PCI_64BIT_BAR0);
10136 bar0map_len = pci_resource_len(pdev, PCI_64BIT_BAR0);
10137
10138
10139
10140
10141
10142 phba->sli4_hba.conf_regs_memmap_p =
10143 ioremap(phba->pci_bar0_map, bar0map_len);
10144 if (!phba->sli4_hba.conf_regs_memmap_p) {
10145 dev_printk(KERN_ERR, &pdev->dev,
10146 "ioremap failed for SLI4 PCI config "
10147 "registers.\n");
10148 return -ENODEV;
10149 }
10150 phba->pci_bar0_memmap_p = phba->sli4_hba.conf_regs_memmap_p;
10151
10152 lpfc_sli4_bar0_register_memmap(phba, if_type);
10153 } else {
10154 phba->pci_bar0_map = pci_resource_start(pdev, 1);
10155 bar0map_len = pci_resource_len(pdev, 1);
10156 if (if_type >= LPFC_SLI_INTF_IF_TYPE_2) {
10157 dev_printk(KERN_ERR, &pdev->dev,
10158 "FATAL - No BAR0 mapping for SLI4, if_type 2\n");
10159 return -ENODEV;
10160 }
10161 phba->sli4_hba.conf_regs_memmap_p =
10162 ioremap(phba->pci_bar0_map, bar0map_len);
10163 if (!phba->sli4_hba.conf_regs_memmap_p) {
10164 dev_printk(KERN_ERR, &pdev->dev,
10165 "ioremap failed for SLI4 PCI config "
10166 "registers.\n");
10167 return -ENODEV;
10168 }
10169 lpfc_sli4_bar0_register_memmap(phba, if_type);
10170 }
10171
10172 if (if_type == LPFC_SLI_INTF_IF_TYPE_0) {
10173 if (pci_resource_start(pdev, PCI_64BIT_BAR2)) {
10174
10175
10176
10177
10178 phba->pci_bar1_map = pci_resource_start(pdev,
10179 PCI_64BIT_BAR2);
10180 bar1map_len = pci_resource_len(pdev, PCI_64BIT_BAR2);
10181 phba->sli4_hba.ctrl_regs_memmap_p =
10182 ioremap(phba->pci_bar1_map,
10183 bar1map_len);
10184 if (!phba->sli4_hba.ctrl_regs_memmap_p) {
10185 dev_err(&pdev->dev,
10186 "ioremap failed for SLI4 HBA "
10187 "control registers.\n");
10188 error = -ENOMEM;
10189 goto out_iounmap_conf;
10190 }
10191 phba->pci_bar2_memmap_p =
10192 phba->sli4_hba.ctrl_regs_memmap_p;
10193 lpfc_sli4_bar1_register_memmap(phba, if_type);
10194 } else {
10195 error = -ENOMEM;
10196 goto out_iounmap_conf;
10197 }
10198 }
10199
10200 if ((if_type == LPFC_SLI_INTF_IF_TYPE_6) &&
10201 (pci_resource_start(pdev, PCI_64BIT_BAR2))) {
10202
10203
10204
10205
10206 phba->pci_bar1_map = pci_resource_start(pdev, PCI_64BIT_BAR2);
10207 bar1map_len = pci_resource_len(pdev, PCI_64BIT_BAR2);
10208 phba->sli4_hba.drbl_regs_memmap_p =
10209 ioremap(phba->pci_bar1_map, bar1map_len);
10210 if (!phba->sli4_hba.drbl_regs_memmap_p) {
10211 dev_err(&pdev->dev,
10212 "ioremap failed for SLI4 HBA doorbell registers.\n");
10213 error = -ENOMEM;
10214 goto out_iounmap_conf;
10215 }
10216 phba->pci_bar2_memmap_p = phba->sli4_hba.drbl_regs_memmap_p;
10217 lpfc_sli4_bar1_register_memmap(phba, if_type);
10218 }
10219
10220 if (if_type == LPFC_SLI_INTF_IF_TYPE_0) {
10221 if (pci_resource_start(pdev, PCI_64BIT_BAR4)) {
10222
10223
10224
10225
10226 phba->pci_bar2_map = pci_resource_start(pdev,
10227 PCI_64BIT_BAR4);
10228 bar2map_len = pci_resource_len(pdev, PCI_64BIT_BAR4);
10229 phba->sli4_hba.drbl_regs_memmap_p =
10230 ioremap(phba->pci_bar2_map,
10231 bar2map_len);
10232 if (!phba->sli4_hba.drbl_regs_memmap_p) {
10233 dev_err(&pdev->dev,
10234 "ioremap failed for SLI4 HBA"
10235 " doorbell registers.\n");
10236 error = -ENOMEM;
10237 goto out_iounmap_ctrl;
10238 }
10239 phba->pci_bar4_memmap_p =
10240 phba->sli4_hba.drbl_regs_memmap_p;
10241 error = lpfc_sli4_bar2_register_memmap(phba, LPFC_VF0);
10242 if (error)
10243 goto out_iounmap_all;
10244 } else {
10245 error = -ENOMEM;
10246 goto out_iounmap_all;
10247 }
10248 }
10249
10250 if (if_type == LPFC_SLI_INTF_IF_TYPE_6 &&
10251 pci_resource_start(pdev, PCI_64BIT_BAR4)) {
10252
10253
10254
10255
10256 phba->pci_bar2_map = pci_resource_start(pdev, PCI_64BIT_BAR4);
10257 bar2map_len = pci_resource_len(pdev, PCI_64BIT_BAR4);
10258 phba->sli4_hba.dpp_regs_memmap_p =
10259 ioremap(phba->pci_bar2_map, bar2map_len);
10260 if (!phba->sli4_hba.dpp_regs_memmap_p) {
10261 dev_err(&pdev->dev,
10262 "ioremap failed for SLI4 HBA dpp registers.\n");
10263 error = -ENOMEM;
10264 goto out_iounmap_ctrl;
10265 }
10266 phba->pci_bar4_memmap_p = phba->sli4_hba.dpp_regs_memmap_p;
10267 }
10268
10269
10270 switch (if_type) {
10271 case LPFC_SLI_INTF_IF_TYPE_0:
10272 case LPFC_SLI_INTF_IF_TYPE_2:
10273 phba->sli4_hba.sli4_eq_clr_intr = lpfc_sli4_eq_clr_intr;
10274 phba->sli4_hba.sli4_write_eq_db = lpfc_sli4_write_eq_db;
10275 phba->sli4_hba.sli4_write_cq_db = lpfc_sli4_write_cq_db;
10276 break;
10277 case LPFC_SLI_INTF_IF_TYPE_6:
10278 phba->sli4_hba.sli4_eq_clr_intr = lpfc_sli4_if6_eq_clr_intr;
10279 phba->sli4_hba.sli4_write_eq_db = lpfc_sli4_if6_write_eq_db;
10280 phba->sli4_hba.sli4_write_cq_db = lpfc_sli4_if6_write_cq_db;
10281 break;
10282 default:
10283 break;
10284 }
10285
10286 return 0;
10287
10288out_iounmap_all:
10289 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
10290out_iounmap_ctrl:
10291 iounmap(phba->sli4_hba.ctrl_regs_memmap_p);
10292out_iounmap_conf:
10293 iounmap(phba->sli4_hba.conf_regs_memmap_p);
10294
10295 return error;
10296}
10297
10298
10299
10300
10301
10302
10303
10304
10305static void
10306lpfc_sli4_pci_mem_unset(struct lpfc_hba *phba)
10307{
10308 uint32_t if_type;
10309 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
10310
10311 switch (if_type) {
10312 case LPFC_SLI_INTF_IF_TYPE_0:
10313 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
10314 iounmap(phba->sli4_hba.ctrl_regs_memmap_p);
10315 iounmap(phba->sli4_hba.conf_regs_memmap_p);
10316 break;
10317 case LPFC_SLI_INTF_IF_TYPE_2:
10318 iounmap(phba->sli4_hba.conf_regs_memmap_p);
10319 break;
10320 case LPFC_SLI_INTF_IF_TYPE_6:
10321 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
10322 iounmap(phba->sli4_hba.conf_regs_memmap_p);
10323 break;
10324 case LPFC_SLI_INTF_IF_TYPE_1:
10325 default:
10326 dev_printk(KERN_ERR, &phba->pcidev->dev,
10327 "FATAL - unsupported SLI4 interface type - %d\n",
10328 if_type);
10329 break;
10330 }
10331}
10332
10333
10334
10335
10336
10337
10338
10339
10340
10341
10342
10343
10344static int
10345lpfc_sli_enable_msix(struct lpfc_hba *phba)
10346{
10347 int rc;
10348 LPFC_MBOXQ_t *pmb;
10349
10350
10351 rc = pci_alloc_irq_vectors(phba->pcidev,
10352 LPFC_MSIX_VECTORS, LPFC_MSIX_VECTORS, PCI_IRQ_MSIX);
10353 if (rc < 0) {
10354 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10355 "0420 PCI enable MSI-X failed (%d)\n", rc);
10356 goto vec_fail_out;
10357 }
10358
10359
10360
10361
10362
10363
10364 rc = request_irq(pci_irq_vector(phba->pcidev, 0),
10365 &lpfc_sli_sp_intr_handler, 0,
10366 LPFC_SP_DRIVER_HANDLER_NAME, phba);
10367 if (rc) {
10368 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
10369 "0421 MSI-X slow-path request_irq failed "
10370 "(%d)\n", rc);
10371 goto msi_fail_out;
10372 }
10373
10374
10375 rc = request_irq(pci_irq_vector(phba->pcidev, 1),
10376 &lpfc_sli_fp_intr_handler, 0,
10377 LPFC_FP_DRIVER_HANDLER_NAME, phba);
10378
10379 if (rc) {
10380 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
10381 "0429 MSI-X fast-path request_irq failed "
10382 "(%d)\n", rc);
10383 goto irq_fail_out;
10384 }
10385
10386
10387
10388
10389 pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
10390
10391 if (!pmb) {
10392 rc = -ENOMEM;
10393 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10394 "0474 Unable to allocate memory for issuing "
10395 "MBOX_CONFIG_MSI command\n");
10396 goto mem_fail_out;
10397 }
10398 rc = lpfc_config_msi(phba, pmb);
10399 if (rc)
10400 goto mbx_fail_out;
10401 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
10402 if (rc != MBX_SUCCESS) {
10403 lpfc_printf_log(phba, KERN_WARNING, LOG_MBOX,
10404 "0351 Config MSI mailbox command failed, "
10405 "mbxCmd x%x, mbxStatus x%x\n",
10406 pmb->u.mb.mbxCommand, pmb->u.mb.mbxStatus);
10407 goto mbx_fail_out;
10408 }
10409
10410
10411 mempool_free(pmb, phba->mbox_mem_pool);
10412 return rc;
10413
10414mbx_fail_out:
10415
10416 mempool_free(pmb, phba->mbox_mem_pool);
10417
10418mem_fail_out:
10419
10420 free_irq(pci_irq_vector(phba->pcidev, 1), phba);
10421
10422irq_fail_out:
10423
10424 free_irq(pci_irq_vector(phba->pcidev, 0), phba);
10425
10426msi_fail_out:
10427
10428 pci_free_irq_vectors(phba->pcidev);
10429
10430vec_fail_out:
10431 return rc;
10432}
10433
10434
10435
10436
10437
10438
10439
10440
10441
10442
10443
10444
10445
10446
10447
10448static int
10449lpfc_sli_enable_msi(struct lpfc_hba *phba)
10450{
10451 int rc;
10452
10453 rc = pci_enable_msi(phba->pcidev);
10454 if (!rc)
10455 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10456 "0462 PCI enable MSI mode success.\n");
10457 else {
10458 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10459 "0471 PCI enable MSI mode failed (%d)\n", rc);
10460 return rc;
10461 }
10462
10463 rc = request_irq(phba->pcidev->irq, lpfc_sli_intr_handler,
10464 0, LPFC_DRIVER_NAME, phba);
10465 if (rc) {
10466 pci_disable_msi(phba->pcidev);
10467 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
10468 "0478 MSI request_irq failed (%d)\n", rc);
10469 }
10470 return rc;
10471}
10472
10473
10474
10475
10476
10477
10478
10479
10480
10481
10482
10483
10484
10485
10486
10487
10488
10489static uint32_t
10490lpfc_sli_enable_intr(struct lpfc_hba *phba, uint32_t cfg_mode)
10491{
10492 uint32_t intr_mode = LPFC_INTR_ERROR;
10493 int retval;
10494
10495 if (cfg_mode == 2) {
10496
10497 retval = lpfc_sli_config_port(phba, LPFC_SLI_REV3);
10498 if (!retval) {
10499
10500 retval = lpfc_sli_enable_msix(phba);
10501 if (!retval) {
10502
10503 phba->intr_type = MSIX;
10504 intr_mode = 2;
10505 }
10506 }
10507 }
10508
10509
10510 if (cfg_mode >= 1 && phba->intr_type == NONE) {
10511 retval = lpfc_sli_enable_msi(phba);
10512 if (!retval) {
10513
10514 phba->intr_type = MSI;
10515 intr_mode = 1;
10516 }
10517 }
10518
10519
10520 if (phba->intr_type == NONE) {
10521 retval = request_irq(phba->pcidev->irq, lpfc_sli_intr_handler,
10522 IRQF_SHARED, LPFC_DRIVER_NAME, phba);
10523 if (!retval) {
10524
10525 phba->intr_type = INTx;
10526 intr_mode = 0;
10527 }
10528 }
10529 return intr_mode;
10530}
10531
10532
10533
10534
10535
10536
10537
10538
10539
10540
10541static void
10542lpfc_sli_disable_intr(struct lpfc_hba *phba)
10543{
10544 int nr_irqs, i;
10545
10546 if (phba->intr_type == MSIX)
10547 nr_irqs = LPFC_MSIX_VECTORS;
10548 else
10549 nr_irqs = 1;
10550
10551 for (i = 0; i < nr_irqs; i++)
10552 free_irq(pci_irq_vector(phba->pcidev, i), phba);
10553 pci_free_irq_vectors(phba->pcidev);
10554
10555
10556 phba->intr_type = NONE;
10557 phba->sli.slistat.sli_intr = 0;
10558}
10559
10560
10561
10562
10563
10564
10565
10566
10567
10568static uint16_t
10569lpfc_find_cpu_handle(struct lpfc_hba *phba, uint16_t id, int match)
10570{
10571 struct lpfc_vector_map_info *cpup;
10572 int cpu;
10573
10574
10575 for_each_present_cpu(cpu) {
10576 cpup = &phba->sli4_hba.cpu_map[cpu];
10577
10578
10579
10580
10581
10582 if ((match == LPFC_FIND_BY_EQ) &&
10583 (cpup->flag & LPFC_CPU_FIRST_IRQ) &&
10584 (cpup->irq != LPFC_VECTOR_MAP_EMPTY) &&
10585 (cpup->eq == id))
10586 return cpu;
10587
10588
10589 if ((match == LPFC_FIND_BY_HDWQ) && (cpup->hdwq == id))
10590 return cpu;
10591 }
10592 return 0;
10593}
10594
10595#ifdef CONFIG_X86
10596
10597
10598
10599
10600
10601
10602
10603static int
10604lpfc_find_hyper(struct lpfc_hba *phba, int cpu,
10605 uint16_t phys_id, uint16_t core_id)
10606{
10607 struct lpfc_vector_map_info *cpup;
10608 int idx;
10609
10610 for_each_present_cpu(idx) {
10611 cpup = &phba->sli4_hba.cpu_map[idx];
10612
10613 if ((cpup->phys_id == phys_id) &&
10614 (cpup->core_id == core_id) &&
10615 (cpu != idx))
10616 return 1;
10617 }
10618 return 0;
10619}
10620#endif
10621
10622
10623
10624
10625
10626
10627
10628
10629
10630
10631
10632static void
10633lpfc_cpu_affinity_check(struct lpfc_hba *phba, int vectors)
10634{
10635 int i, cpu, idx, next_idx, new_cpu, start_cpu, first_cpu;
10636 int max_phys_id, min_phys_id;
10637 int max_core_id, min_core_id;
10638 struct lpfc_vector_map_info *cpup;
10639 struct lpfc_vector_map_info *new_cpup;
10640 const struct cpumask *maskp;
10641#ifdef CONFIG_X86
10642 struct cpuinfo_x86 *cpuinfo;
10643#endif
10644
10645
10646 for_each_possible_cpu(cpu) {
10647 cpup = &phba->sli4_hba.cpu_map[cpu];
10648 cpup->phys_id = LPFC_VECTOR_MAP_EMPTY;
10649 cpup->core_id = LPFC_VECTOR_MAP_EMPTY;
10650 cpup->hdwq = LPFC_VECTOR_MAP_EMPTY;
10651 cpup->eq = LPFC_VECTOR_MAP_EMPTY;
10652 cpup->irq = LPFC_VECTOR_MAP_EMPTY;
10653 cpup->flag = 0;
10654 }
10655
10656 max_phys_id = 0;
10657 min_phys_id = LPFC_VECTOR_MAP_EMPTY;
10658 max_core_id = 0;
10659 min_core_id = LPFC_VECTOR_MAP_EMPTY;
10660
10661
10662 for_each_present_cpu(cpu) {
10663 cpup = &phba->sli4_hba.cpu_map[cpu];
10664#ifdef CONFIG_X86
10665 cpuinfo = &cpu_data(cpu);
10666 cpup->phys_id = cpuinfo->phys_proc_id;
10667 cpup->core_id = cpuinfo->cpu_core_id;
10668 if (lpfc_find_hyper(phba, cpu, cpup->phys_id, cpup->core_id))
10669 cpup->flag |= LPFC_CPU_MAP_HYPER;
10670#else
10671
10672 cpup->phys_id = 0;
10673 cpup->core_id = cpu;
10674#endif
10675
10676 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10677 "3328 CPU %d physid %d coreid %d flag x%x\n",
10678 cpu, cpup->phys_id, cpup->core_id, cpup->flag);
10679
10680 if (cpup->phys_id > max_phys_id)
10681 max_phys_id = cpup->phys_id;
10682 if (cpup->phys_id < min_phys_id)
10683 min_phys_id = cpup->phys_id;
10684
10685 if (cpup->core_id > max_core_id)
10686 max_core_id = cpup->core_id;
10687 if (cpup->core_id < min_core_id)
10688 min_core_id = cpup->core_id;
10689 }
10690
10691 for_each_possible_cpu(i) {
10692 struct lpfc_eq_intr_info *eqi =
10693 per_cpu_ptr(phba->sli4_hba.eq_info, i);
10694
10695 INIT_LIST_HEAD(&eqi->list);
10696 eqi->icnt = 0;
10697 }
10698
10699
10700
10701
10702
10703
10704
10705
10706
10707
10708
10709 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
10710
10711 maskp = pci_irq_get_affinity(phba->pcidev, idx);
10712 if (!maskp) {
10713 if (phba->cfg_irq_chann > 1)
10714 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10715 "3329 No affinity mask found "
10716 "for vector %d (%d)\n",
10717 idx, phba->cfg_irq_chann);
10718 if (!idx) {
10719 cpu = cpumask_first(cpu_present_mask);
10720 cpup = &phba->sli4_hba.cpu_map[cpu];
10721 cpup->eq = idx;
10722 cpup->irq = pci_irq_vector(phba->pcidev, idx);
10723 cpup->flag |= LPFC_CPU_FIRST_IRQ;
10724 }
10725 break;
10726 }
10727
10728 i = 0;
10729
10730 for_each_cpu_and(cpu, maskp, cpu_present_mask) {
10731
10732 cpup = &phba->sli4_hba.cpu_map[cpu];
10733 cpup->eq = idx;
10734 cpup->irq = pci_irq_vector(phba->pcidev, idx);
10735
10736
10737
10738
10739 if (!i)
10740 cpup->flag |= LPFC_CPU_FIRST_IRQ;
10741 i++;
10742
10743 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10744 "3336 Set Affinity: CPU %d "
10745 "irq %d eq %d flag x%x\n",
10746 cpu, cpup->irq, cpup->eq, cpup->flag);
10747 }
10748 }
10749
10750
10751
10752
10753
10754
10755 first_cpu = cpumask_first(cpu_present_mask);
10756 start_cpu = first_cpu;
10757
10758 for_each_present_cpu(cpu) {
10759 cpup = &phba->sli4_hba.cpu_map[cpu];
10760
10761
10762 if (cpup->eq == LPFC_VECTOR_MAP_EMPTY) {
10763
10764 cpup->flag |= LPFC_CPU_MAP_UNASSIGN;
10765
10766
10767
10768
10769
10770
10771 new_cpu = start_cpu;
10772 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
10773 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
10774 if (!(new_cpup->flag & LPFC_CPU_MAP_UNASSIGN) &&
10775 (new_cpup->irq != LPFC_VECTOR_MAP_EMPTY) &&
10776 (new_cpup->phys_id == cpup->phys_id))
10777 goto found_same;
10778 new_cpu = cpumask_next(
10779 new_cpu, cpu_present_mask);
10780 if (new_cpu == nr_cpumask_bits)
10781 new_cpu = first_cpu;
10782 }
10783
10784 continue;
10785found_same:
10786
10787 cpup->eq = new_cpup->eq;
10788 cpup->irq = new_cpup->irq;
10789
10790
10791
10792
10793
10794 start_cpu = cpumask_next(new_cpu, cpu_present_mask);
10795 if (start_cpu == nr_cpumask_bits)
10796 start_cpu = first_cpu;
10797
10798 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10799 "3337 Set Affinity: CPU %d "
10800 "irq %d from id %d same "
10801 "phys_id (%d)\n",
10802 cpu, cpup->irq, new_cpu, cpup->phys_id);
10803 }
10804 }
10805
10806
10807 start_cpu = first_cpu;
10808
10809 for_each_present_cpu(cpu) {
10810 cpup = &phba->sli4_hba.cpu_map[cpu];
10811
10812
10813 if (cpup->eq == LPFC_VECTOR_MAP_EMPTY) {
10814
10815 cpup->flag |= LPFC_CPU_MAP_UNASSIGN;
10816
10817
10818
10819
10820
10821
10822 new_cpu = start_cpu;
10823 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
10824 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
10825 if (!(new_cpup->flag & LPFC_CPU_MAP_UNASSIGN) &&
10826 (new_cpup->irq != LPFC_VECTOR_MAP_EMPTY))
10827 goto found_any;
10828 new_cpu = cpumask_next(
10829 new_cpu, cpu_present_mask);
10830 if (new_cpu == nr_cpumask_bits)
10831 new_cpu = first_cpu;
10832 }
10833
10834 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10835 "3339 Set Affinity: CPU %d "
10836 "irq %d UNASSIGNED\n",
10837 cpup->hdwq, cpup->irq);
10838 continue;
10839found_any:
10840
10841 cpup->eq = new_cpup->eq;
10842 cpup->irq = new_cpup->irq;
10843
10844
10845
10846
10847
10848 start_cpu = cpumask_next(new_cpu, cpu_present_mask);
10849 if (start_cpu == nr_cpumask_bits)
10850 start_cpu = first_cpu;
10851
10852 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10853 "3338 Set Affinity: CPU %d "
10854 "irq %d from id %d (%d/%d)\n",
10855 cpu, cpup->irq, new_cpu,
10856 new_cpup->phys_id, new_cpup->core_id);
10857 }
10858 }
10859
10860
10861
10862
10863 idx = 0;
10864 for_each_present_cpu(cpu) {
10865 cpup = &phba->sli4_hba.cpu_map[cpu];
10866
10867
10868 if (!(cpup->flag & LPFC_CPU_FIRST_IRQ))
10869 continue;
10870
10871
10872 cpup->hdwq = idx;
10873 idx++;
10874 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10875 "3333 Set Affinity: CPU %d (phys %d core %d): "
10876 "hdwq %d eq %d irq %d flg x%x\n",
10877 cpu, cpup->phys_id, cpup->core_id,
10878 cpup->hdwq, cpup->eq, cpup->irq, cpup->flag);
10879 }
10880
10881
10882
10883
10884
10885
10886
10887
10888 next_idx = idx;
10889 start_cpu = 0;
10890 idx = 0;
10891 for_each_present_cpu(cpu) {
10892 cpup = &phba->sli4_hba.cpu_map[cpu];
10893
10894
10895 if (cpup->flag & LPFC_CPU_FIRST_IRQ)
10896 continue;
10897
10898
10899
10900
10901
10902 if (next_idx < phba->cfg_hdw_queue) {
10903 cpup->hdwq = next_idx;
10904 next_idx++;
10905 continue;
10906 }
10907
10908
10909
10910
10911
10912
10913 new_cpu = start_cpu;
10914 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
10915 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
10916 if (new_cpup->hdwq != LPFC_VECTOR_MAP_EMPTY &&
10917 new_cpup->phys_id == cpup->phys_id &&
10918 new_cpup->core_id == cpup->core_id) {
10919 goto found_hdwq;
10920 }
10921 new_cpu = cpumask_next(new_cpu, cpu_present_mask);
10922 if (new_cpu == nr_cpumask_bits)
10923 new_cpu = first_cpu;
10924 }
10925
10926
10927
10928
10929 new_cpu = start_cpu;
10930 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
10931 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
10932 if (new_cpup->hdwq != LPFC_VECTOR_MAP_EMPTY &&
10933 new_cpup->phys_id == cpup->phys_id)
10934 goto found_hdwq;
10935
10936 new_cpu = cpumask_next(new_cpu, cpu_present_mask);
10937 if (new_cpu == nr_cpumask_bits)
10938 new_cpu = first_cpu;
10939 }
10940
10941
10942 cpup->hdwq = idx % phba->cfg_hdw_queue;
10943 idx++;
10944 goto logit;
10945 found_hdwq:
10946
10947 start_cpu = cpumask_next(new_cpu, cpu_present_mask);
10948 if (start_cpu == nr_cpumask_bits)
10949 start_cpu = first_cpu;
10950 cpup->hdwq = new_cpup->hdwq;
10951 logit:
10952 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10953 "3335 Set Affinity: CPU %d (phys %d core %d): "
10954 "hdwq %d eq %d irq %d flg x%x\n",
10955 cpu, cpup->phys_id, cpup->core_id,
10956 cpup->hdwq, cpup->eq, cpup->irq, cpup->flag);
10957 }
10958
10959
10960
10961
10962 return;
10963}
10964
10965
10966
10967
10968
10969
10970
10971
10972
10973
10974
10975
10976static int
10977lpfc_sli4_enable_msix(struct lpfc_hba *phba)
10978{
10979 int vectors, rc, index;
10980 char *name;
10981
10982
10983 vectors = phba->cfg_irq_chann;
10984
10985 rc = pci_alloc_irq_vectors(phba->pcidev,
10986 1,
10987 vectors, PCI_IRQ_MSIX | PCI_IRQ_AFFINITY);
10988 if (rc < 0) {
10989 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10990 "0484 PCI enable MSI-X failed (%d)\n", rc);
10991 goto vec_fail_out;
10992 }
10993 vectors = rc;
10994
10995
10996 for (index = 0; index < vectors; index++) {
10997 name = phba->sli4_hba.hba_eq_hdl[index].handler_name;
10998 memset(name, 0, LPFC_SLI4_HANDLER_NAME_SZ);
10999 snprintf(name, LPFC_SLI4_HANDLER_NAME_SZ,
11000 LPFC_DRIVER_HANDLER_NAME"%d", index);
11001
11002 phba->sli4_hba.hba_eq_hdl[index].idx = index;
11003 phba->sli4_hba.hba_eq_hdl[index].phba = phba;
11004 rc = request_irq(pci_irq_vector(phba->pcidev, index),
11005 &lpfc_sli4_hba_intr_handler, 0,
11006 name,
11007 &phba->sli4_hba.hba_eq_hdl[index]);
11008 if (rc) {
11009 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
11010 "0486 MSI-X fast-path (%d) "
11011 "request_irq failed (%d)\n", index, rc);
11012 goto cfg_fail_out;
11013 }
11014 }
11015
11016 if (vectors != phba->cfg_irq_chann) {
11017 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11018 "3238 Reducing IO channels to match number of "
11019 "MSI-X vectors, requested %d got %d\n",
11020 phba->cfg_irq_chann, vectors);
11021 if (phba->cfg_irq_chann > vectors)
11022 phba->cfg_irq_chann = vectors;
11023 if (phba->nvmet_support && (phba->cfg_nvmet_mrq > vectors))
11024 phba->cfg_nvmet_mrq = vectors;
11025 }
11026
11027 return rc;
11028
11029cfg_fail_out:
11030
11031 for (--index; index >= 0; index--)
11032 free_irq(pci_irq_vector(phba->pcidev, index),
11033 &phba->sli4_hba.hba_eq_hdl[index]);
11034
11035
11036 pci_free_irq_vectors(phba->pcidev);
11037
11038vec_fail_out:
11039 return rc;
11040}
11041
11042
11043
11044
11045
11046
11047
11048
11049
11050
11051
11052
11053
11054
11055
11056static int
11057lpfc_sli4_enable_msi(struct lpfc_hba *phba)
11058{
11059 int rc, index;
11060
11061 rc = pci_alloc_irq_vectors(phba->pcidev, 1, 1,
11062 PCI_IRQ_MSI | PCI_IRQ_AFFINITY);
11063 if (rc > 0)
11064 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11065 "0487 PCI enable MSI mode success.\n");
11066 else {
11067 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11068 "0488 PCI enable MSI mode failed (%d)\n", rc);
11069 return rc ? rc : -1;
11070 }
11071
11072 rc = request_irq(phba->pcidev->irq, lpfc_sli4_intr_handler,
11073 0, LPFC_DRIVER_NAME, phba);
11074 if (rc) {
11075 pci_free_irq_vectors(phba->pcidev);
11076 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
11077 "0490 MSI request_irq failed (%d)\n", rc);
11078 return rc;
11079 }
11080
11081 for (index = 0; index < phba->cfg_irq_chann; index++) {
11082 phba->sli4_hba.hba_eq_hdl[index].idx = index;
11083 phba->sli4_hba.hba_eq_hdl[index].phba = phba;
11084 }
11085
11086 return 0;
11087}
11088
11089
11090
11091
11092
11093
11094
11095
11096
11097
11098
11099
11100
11101
11102
11103
11104
11105static uint32_t
11106lpfc_sli4_enable_intr(struct lpfc_hba *phba, uint32_t cfg_mode)
11107{
11108 uint32_t intr_mode = LPFC_INTR_ERROR;
11109 int retval, idx;
11110
11111 if (cfg_mode == 2) {
11112
11113 retval = 0;
11114 if (!retval) {
11115
11116 retval = lpfc_sli4_enable_msix(phba);
11117 if (!retval) {
11118
11119 phba->intr_type = MSIX;
11120 intr_mode = 2;
11121 }
11122 }
11123 }
11124
11125
11126 if (cfg_mode >= 1 && phba->intr_type == NONE) {
11127 retval = lpfc_sli4_enable_msi(phba);
11128 if (!retval) {
11129
11130 phba->intr_type = MSI;
11131 intr_mode = 1;
11132 }
11133 }
11134
11135
11136 if (phba->intr_type == NONE) {
11137 retval = request_irq(phba->pcidev->irq, lpfc_sli4_intr_handler,
11138 IRQF_SHARED, LPFC_DRIVER_NAME, phba);
11139 if (!retval) {
11140 struct lpfc_hba_eq_hdl *eqhdl;
11141
11142
11143 phba->intr_type = INTx;
11144 intr_mode = 0;
11145
11146 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
11147 eqhdl = &phba->sli4_hba.hba_eq_hdl[idx];
11148 eqhdl->idx = idx;
11149 eqhdl->phba = phba;
11150 }
11151 }
11152 }
11153 return intr_mode;
11154}
11155
11156
11157
11158
11159
11160
11161
11162
11163
11164
11165static void
11166lpfc_sli4_disable_intr(struct lpfc_hba *phba)
11167{
11168
11169 if (phba->intr_type == MSIX) {
11170 int index;
11171
11172
11173 for (index = 0; index < phba->cfg_irq_chann; index++) {
11174 irq_set_affinity_hint(
11175 pci_irq_vector(phba->pcidev, index),
11176 NULL);
11177 free_irq(pci_irq_vector(phba->pcidev, index),
11178 &phba->sli4_hba.hba_eq_hdl[index]);
11179 }
11180 } else {
11181 free_irq(phba->pcidev->irq, phba);
11182 }
11183
11184 pci_free_irq_vectors(phba->pcidev);
11185
11186
11187 phba->intr_type = NONE;
11188 phba->sli.slistat.sli_intr = 0;
11189}
11190
11191
11192
11193
11194
11195
11196
11197
11198static void
11199lpfc_unset_hba(struct lpfc_hba *phba)
11200{
11201 struct lpfc_vport *vport = phba->pport;
11202 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
11203
11204 spin_lock_irq(shost->host_lock);
11205 vport->load_flag |= FC_UNLOADING;
11206 spin_unlock_irq(shost->host_lock);
11207
11208 kfree(phba->vpi_bmask);
11209 kfree(phba->vpi_ids);
11210
11211 lpfc_stop_hba_timers(phba);
11212
11213 phba->pport->work_port_events = 0;
11214
11215 lpfc_sli_hba_down(phba);
11216
11217 lpfc_sli_brdrestart(phba);
11218
11219 lpfc_sli_disable_intr(phba);
11220
11221 return;
11222}
11223
11224
11225
11226
11227
11228
11229
11230
11231
11232
11233
11234
11235
11236
11237static void
11238lpfc_sli4_xri_exchange_busy_wait(struct lpfc_hba *phba)
11239{
11240 struct lpfc_sli4_hdw_queue *qp;
11241 int idx, ccnt;
11242 int wait_time = 0;
11243 int io_xri_cmpl = 1;
11244 int nvmet_xri_cmpl = 1;
11245 int els_xri_cmpl = list_empty(&phba->sli4_hba.lpfc_abts_els_sgl_list);
11246
11247
11248
11249
11250
11251 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T1 * 5);
11252
11253
11254 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
11255 lpfc_nvme_wait_for_io_drain(phba);
11256
11257 ccnt = 0;
11258 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
11259 qp = &phba->sli4_hba.hdwq[idx];
11260 io_xri_cmpl = list_empty(&qp->lpfc_abts_io_buf_list);
11261 if (!io_xri_cmpl)
11262 ccnt++;
11263 }
11264 if (ccnt)
11265 io_xri_cmpl = 0;
11266
11267 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
11268 nvmet_xri_cmpl =
11269 list_empty(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
11270 }
11271
11272 while (!els_xri_cmpl || !io_xri_cmpl || !nvmet_xri_cmpl) {
11273 if (wait_time > LPFC_XRI_EXCH_BUSY_WAIT_TMO) {
11274 if (!nvmet_xri_cmpl)
11275 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11276 "6424 NVMET XRI exchange busy "
11277 "wait time: %d seconds.\n",
11278 wait_time/1000);
11279 if (!io_xri_cmpl)
11280 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11281 "6100 IO XRI exchange busy "
11282 "wait time: %d seconds.\n",
11283 wait_time/1000);
11284 if (!els_xri_cmpl)
11285 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11286 "2878 ELS XRI exchange busy "
11287 "wait time: %d seconds.\n",
11288 wait_time/1000);
11289 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T2);
11290 wait_time += LPFC_XRI_EXCH_BUSY_WAIT_T2;
11291 } else {
11292 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T1);
11293 wait_time += LPFC_XRI_EXCH_BUSY_WAIT_T1;
11294 }
11295
11296 ccnt = 0;
11297 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
11298 qp = &phba->sli4_hba.hdwq[idx];
11299 io_xri_cmpl = list_empty(
11300 &qp->lpfc_abts_io_buf_list);
11301 if (!io_xri_cmpl)
11302 ccnt++;
11303 }
11304 if (ccnt)
11305 io_xri_cmpl = 0;
11306
11307 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
11308 nvmet_xri_cmpl = list_empty(
11309 &phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
11310 }
11311 els_xri_cmpl =
11312 list_empty(&phba->sli4_hba.lpfc_abts_els_sgl_list);
11313
11314 }
11315}
11316
11317
11318
11319
11320
11321
11322
11323
11324
11325
11326
11327static void
11328lpfc_sli4_hba_unset(struct lpfc_hba *phba)
11329{
11330 int wait_cnt = 0;
11331 LPFC_MBOXQ_t *mboxq;
11332 struct pci_dev *pdev = phba->pcidev;
11333
11334 lpfc_stop_hba_timers(phba);
11335 if (phba->pport)
11336 phba->sli4_hba.intr_enable = 0;
11337
11338
11339
11340
11341
11342
11343
11344 spin_lock_irq(&phba->hbalock);
11345 phba->sli.sli_flag |= LPFC_SLI_ASYNC_MBX_BLK;
11346 spin_unlock_irq(&phba->hbalock);
11347
11348 while (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) {
11349 msleep(10);
11350 if (++wait_cnt > LPFC_ACTIVE_MBOX_WAIT_CNT)
11351 break;
11352 }
11353
11354 if (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) {
11355 spin_lock_irq(&phba->hbalock);
11356 mboxq = phba->sli.mbox_active;
11357 mboxq->u.mb.mbxStatus = MBX_NOT_FINISHED;
11358 __lpfc_mbox_cmpl_put(phba, mboxq);
11359 phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
11360 phba->sli.mbox_active = NULL;
11361 spin_unlock_irq(&phba->hbalock);
11362 }
11363
11364
11365 lpfc_sli_hba_iocb_abort(phba);
11366
11367
11368 lpfc_sli4_xri_exchange_busy_wait(phba);
11369
11370
11371 lpfc_sli4_disable_intr(phba);
11372
11373
11374 if (phba->cfg_sriov_nr_virtfn)
11375 pci_disable_sriov(pdev);
11376
11377
11378 kthread_stop(phba->worker_thread);
11379
11380
11381 lpfc_ras_stop_fwlog(phba);
11382
11383
11384
11385
11386 lpfc_sli4_queue_unset(phba);
11387 lpfc_sli4_queue_destroy(phba);
11388
11389
11390 lpfc_pci_function_reset(phba);
11391
11392
11393 if (phba->ras_fwlog.ras_enabled)
11394 lpfc_sli4_ras_dma_free(phba);
11395
11396
11397 if (phba->pport)
11398 phba->pport->work_port_events = 0;
11399}
11400
11401
11402
11403
11404
11405
11406
11407
11408
11409
11410
11411
11412
11413int
11414lpfc_pc_sli4_params_get(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq)
11415{
11416 int rc;
11417 struct lpfc_mqe *mqe;
11418 struct lpfc_pc_sli4_params *sli4_params;
11419 uint32_t mbox_tmo;
11420
11421 rc = 0;
11422 mqe = &mboxq->u.mqe;
11423
11424
11425 lpfc_pc_sli4_params(mboxq);
11426 if (!phba->sli4_hba.intr_enable)
11427 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
11428 else {
11429 mbox_tmo = lpfc_mbox_tmo_val(phba, mboxq);
11430 rc = lpfc_sli_issue_mbox_wait(phba, mboxq, mbox_tmo);
11431 }
11432
11433 if (unlikely(rc))
11434 return 1;
11435
11436 sli4_params = &phba->sli4_hba.pc_sli4_params;
11437 sli4_params->if_type = bf_get(if_type, &mqe->un.sli4_params);
11438 sli4_params->sli_rev = bf_get(sli_rev, &mqe->un.sli4_params);
11439 sli4_params->sli_family = bf_get(sli_family, &mqe->un.sli4_params);
11440 sli4_params->featurelevel_1 = bf_get(featurelevel_1,
11441 &mqe->un.sli4_params);
11442 sli4_params->featurelevel_2 = bf_get(featurelevel_2,
11443 &mqe->un.sli4_params);
11444 sli4_params->proto_types = mqe->un.sli4_params.word3;
11445 sli4_params->sge_supp_len = mqe->un.sli4_params.sge_supp_len;
11446 sli4_params->if_page_sz = bf_get(if_page_sz, &mqe->un.sli4_params);
11447 sli4_params->rq_db_window = bf_get(rq_db_window, &mqe->un.sli4_params);
11448 sli4_params->loopbk_scope = bf_get(loopbk_scope, &mqe->un.sli4_params);
11449 sli4_params->eq_pages_max = bf_get(eq_pages, &mqe->un.sli4_params);
11450 sli4_params->eqe_size = bf_get(eqe_size, &mqe->un.sli4_params);
11451 sli4_params->cq_pages_max = bf_get(cq_pages, &mqe->un.sli4_params);
11452 sli4_params->cqe_size = bf_get(cqe_size, &mqe->un.sli4_params);
11453 sli4_params->mq_pages_max = bf_get(mq_pages, &mqe->un.sli4_params);
11454 sli4_params->mqe_size = bf_get(mqe_size, &mqe->un.sli4_params);
11455 sli4_params->mq_elem_cnt = bf_get(mq_elem_cnt, &mqe->un.sli4_params);
11456 sli4_params->wq_pages_max = bf_get(wq_pages, &mqe->un.sli4_params);
11457 sli4_params->wqe_size = bf_get(wqe_size, &mqe->un.sli4_params);
11458 sli4_params->rq_pages_max = bf_get(rq_pages, &mqe->un.sli4_params);
11459 sli4_params->rqe_size = bf_get(rqe_size, &mqe->un.sli4_params);
11460 sli4_params->hdr_pages_max = bf_get(hdr_pages, &mqe->un.sli4_params);
11461 sli4_params->hdr_size = bf_get(hdr_size, &mqe->un.sli4_params);
11462 sli4_params->hdr_pp_align = bf_get(hdr_pp_align, &mqe->un.sli4_params);
11463 sli4_params->sgl_pages_max = bf_get(sgl_pages, &mqe->un.sli4_params);
11464 sli4_params->sgl_pp_align = bf_get(sgl_pp_align, &mqe->un.sli4_params);
11465
11466
11467 if (sli4_params->sge_supp_len > LPFC_MAX_SGE_SIZE)
11468 sli4_params->sge_supp_len = LPFC_MAX_SGE_SIZE;
11469
11470 return rc;
11471}
11472
11473
11474
11475
11476
11477
11478
11479
11480
11481
11482
11483
11484
11485int
11486lpfc_get_sli4_parameters(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq)
11487{
11488 int rc;
11489 struct lpfc_mqe *mqe = &mboxq->u.mqe;
11490 struct lpfc_pc_sli4_params *sli4_params;
11491 uint32_t mbox_tmo;
11492 int length;
11493 bool exp_wqcq_pages = true;
11494 struct lpfc_sli4_parameters *mbx_sli4_parameters;
11495
11496
11497
11498
11499
11500
11501 phba->sli4_hba.rpi_hdrs_in_use = 1;
11502
11503
11504 length = (sizeof(struct lpfc_mbx_get_sli4_parameters) -
11505 sizeof(struct lpfc_sli4_cfg_mhdr));
11506 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
11507 LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS,
11508 length, LPFC_SLI4_MBX_EMBED);
11509 if (!phba->sli4_hba.intr_enable)
11510 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
11511 else {
11512 mbox_tmo = lpfc_mbox_tmo_val(phba, mboxq);
11513 rc = lpfc_sli_issue_mbox_wait(phba, mboxq, mbox_tmo);
11514 }
11515 if (unlikely(rc))
11516 return rc;
11517 sli4_params = &phba->sli4_hba.pc_sli4_params;
11518 mbx_sli4_parameters = &mqe->un.get_sli4_parameters.sli4_parameters;
11519 sli4_params->if_type = bf_get(cfg_if_type, mbx_sli4_parameters);
11520 sli4_params->sli_rev = bf_get(cfg_sli_rev, mbx_sli4_parameters);
11521 sli4_params->sli_family = bf_get(cfg_sli_family, mbx_sli4_parameters);
11522 sli4_params->featurelevel_1 = bf_get(cfg_sli_hint_1,
11523 mbx_sli4_parameters);
11524 sli4_params->featurelevel_2 = bf_get(cfg_sli_hint_2,
11525 mbx_sli4_parameters);
11526 if (bf_get(cfg_phwq, mbx_sli4_parameters))
11527 phba->sli3_options |= LPFC_SLI4_PHWQ_ENABLED;
11528 else
11529 phba->sli3_options &= ~LPFC_SLI4_PHWQ_ENABLED;
11530 sli4_params->sge_supp_len = mbx_sli4_parameters->sge_supp_len;
11531 sli4_params->loopbk_scope = bf_get(loopbk_scope, mbx_sli4_parameters);
11532 sli4_params->oas_supported = bf_get(cfg_oas, mbx_sli4_parameters);
11533 sli4_params->cqv = bf_get(cfg_cqv, mbx_sli4_parameters);
11534 sli4_params->mqv = bf_get(cfg_mqv, mbx_sli4_parameters);
11535 sli4_params->wqv = bf_get(cfg_wqv, mbx_sli4_parameters);
11536 sli4_params->rqv = bf_get(cfg_rqv, mbx_sli4_parameters);
11537 sli4_params->eqav = bf_get(cfg_eqav, mbx_sli4_parameters);
11538 sli4_params->cqav = bf_get(cfg_cqav, mbx_sli4_parameters);
11539 sli4_params->wqsize = bf_get(cfg_wqsize, mbx_sli4_parameters);
11540 sli4_params->bv1s = bf_get(cfg_bv1s, mbx_sli4_parameters);
11541 sli4_params->sgl_pages_max = bf_get(cfg_sgl_page_cnt,
11542 mbx_sli4_parameters);
11543 sli4_params->wqpcnt = bf_get(cfg_wqpcnt, mbx_sli4_parameters);
11544 sli4_params->sgl_pp_align = bf_get(cfg_sgl_pp_align,
11545 mbx_sli4_parameters);
11546 phba->sli4_hba.extents_in_use = bf_get(cfg_ext, mbx_sli4_parameters);
11547 phba->sli4_hba.rpi_hdrs_in_use = bf_get(cfg_hdrr, mbx_sli4_parameters);
11548
11549
11550 phba->cfg_xpsgl = bf_get(cfg_xpsgl, mbx_sli4_parameters);
11551
11552
11553 rc = (bf_get(cfg_nvme, mbx_sli4_parameters) &&
11554 bf_get(cfg_xib, mbx_sli4_parameters));
11555
11556 if (rc) {
11557
11558 sli4_params->nvme = 1;
11559
11560
11561 if (phba->cfg_enable_fc4_type == LPFC_ENABLE_FCP) {
11562 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_NVME,
11563 "6133 Disabling NVME support: "
11564 "FC4 type not supported: x%x\n",
11565 phba->cfg_enable_fc4_type);
11566 goto fcponly;
11567 }
11568 } else {
11569
11570 sli4_params->nvme = 0;
11571 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
11572 lpfc_printf_log(phba, KERN_ERR, LOG_INIT | LOG_NVME,
11573 "6101 Disabling NVME support: Not "
11574 "supported by firmware (%d %d) x%x\n",
11575 bf_get(cfg_nvme, mbx_sli4_parameters),
11576 bf_get(cfg_xib, mbx_sli4_parameters),
11577 phba->cfg_enable_fc4_type);
11578fcponly:
11579 phba->nvme_support = 0;
11580 phba->nvmet_support = 0;
11581 phba->cfg_nvmet_mrq = 0;
11582 phba->cfg_nvme_seg_cnt = 0;
11583
11584
11585 if (!(phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP))
11586 return -ENODEV;
11587 phba->cfg_enable_fc4_type = LPFC_ENABLE_FCP;
11588 }
11589 }
11590
11591
11592
11593
11594
11595 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
11596 phba->cfg_sg_seg_cnt = LPFC_MAX_NVME_SEG_CNT;
11597 phba->cfg_iocb_cnt = 5;
11598 }
11599
11600
11601 if ((bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) !=
11602 LPFC_SLI_INTF_IF_TYPE_6) || (!bf_get(cfg_xib, mbx_sli4_parameters)))
11603 phba->cfg_enable_pbde = 0;
11604
11605
11606
11607
11608
11609
11610
11611
11612
11613 if (phba->cfg_suppress_rsp && bf_get(cfg_xib, mbx_sli4_parameters) &&
11614 !(bf_get(cfg_nosr, mbx_sli4_parameters)))
11615 phba->sli.sli_flag |= LPFC_SLI_SUPPRESS_RSP;
11616 else
11617 phba->cfg_suppress_rsp = 0;
11618
11619 if (bf_get(cfg_eqdr, mbx_sli4_parameters))
11620 phba->sli.sli_flag |= LPFC_SLI_USE_EQDR;
11621
11622
11623 if (sli4_params->sge_supp_len > LPFC_MAX_SGE_SIZE)
11624 sli4_params->sge_supp_len = LPFC_MAX_SGE_SIZE;
11625
11626
11627
11628
11629
11630
11631 if (bf_get(cfg_ext_embed_cb, mbx_sli4_parameters))
11632 phba->fcp_embed_io = 1;
11633 else
11634 phba->fcp_embed_io = 0;
11635
11636 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_NVME,
11637 "6422 XIB %d PBDE %d: FCP %d NVME %d %d %d\n",
11638 bf_get(cfg_xib, mbx_sli4_parameters),
11639 phba->cfg_enable_pbde,
11640 phba->fcp_embed_io, phba->nvme_support,
11641 phba->cfg_nvme_embed_cmd, phba->cfg_suppress_rsp);
11642
11643 if ((bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
11644 LPFC_SLI_INTF_IF_TYPE_2) &&
11645 (bf_get(lpfc_sli_intf_sli_family, &phba->sli4_hba.sli_intf) ==
11646 LPFC_SLI_INTF_FAMILY_LNCR_A0))
11647 exp_wqcq_pages = false;
11648
11649 if ((bf_get(cfg_cqpsize, mbx_sli4_parameters) & LPFC_CQ_16K_PAGE_SZ) &&
11650 (bf_get(cfg_wqpsize, mbx_sli4_parameters) & LPFC_WQ_16K_PAGE_SZ) &&
11651 exp_wqcq_pages &&
11652 (sli4_params->wqsize & LPFC_WQ_SZ128_SUPPORT))
11653 phba->enab_exp_wqcq_pages = 1;
11654 else
11655 phba->enab_exp_wqcq_pages = 0;
11656
11657
11658
11659 if (bf_get(cfg_mds_diags, mbx_sli4_parameters))
11660 phba->mds_diags_support = 1;
11661 else
11662 phba->mds_diags_support = 0;
11663
11664
11665
11666
11667 if (bf_get(cfg_nsler, mbx_sli4_parameters))
11668 phba->nsler = 1;
11669 else
11670 phba->nsler = 0;
11671
11672 return 0;
11673}
11674
11675
11676
11677
11678
11679
11680
11681
11682
11683
11684
11685
11686
11687
11688
11689
11690
11691
11692static int
11693lpfc_pci_probe_one_s3(struct pci_dev *pdev, const struct pci_device_id *pid)
11694{
11695 struct lpfc_hba *phba;
11696 struct lpfc_vport *vport = NULL;
11697 struct Scsi_Host *shost = NULL;
11698 int error;
11699 uint32_t cfg_mode, intr_mode;
11700
11701
11702 phba = lpfc_hba_alloc(pdev);
11703 if (!phba)
11704 return -ENOMEM;
11705
11706
11707 error = lpfc_enable_pci_dev(phba);
11708 if (error)
11709 goto out_free_phba;
11710
11711
11712 error = lpfc_api_table_setup(phba, LPFC_PCI_DEV_LP);
11713 if (error)
11714 goto out_disable_pci_dev;
11715
11716
11717 error = lpfc_sli_pci_mem_setup(phba);
11718 if (error) {
11719 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11720 "1402 Failed to set up pci memory space.\n");
11721 goto out_disable_pci_dev;
11722 }
11723
11724
11725 error = lpfc_sli_driver_resource_setup(phba);
11726 if (error) {
11727 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11728 "1404 Failed to set up driver resource.\n");
11729 goto out_unset_pci_mem_s3;
11730 }
11731
11732
11733
11734 error = lpfc_init_iocb_list(phba, LPFC_IOCB_LIST_CNT);
11735 if (error) {
11736 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11737 "1405 Failed to initialize iocb list.\n");
11738 goto out_unset_driver_resource_s3;
11739 }
11740
11741
11742 error = lpfc_setup_driver_resource_phase2(phba);
11743 if (error) {
11744 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11745 "1406 Failed to set up driver resource.\n");
11746 goto out_free_iocb_list;
11747 }
11748
11749
11750 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
11751
11752
11753 error = lpfc_create_shost(phba);
11754 if (error) {
11755 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11756 "1407 Failed to create scsi host.\n");
11757 goto out_unset_driver_resource;
11758 }
11759
11760
11761 vport = phba->pport;
11762 error = lpfc_alloc_sysfs_attr(vport);
11763 if (error) {
11764 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11765 "1476 Failed to allocate sysfs attr\n");
11766 goto out_destroy_shost;
11767 }
11768
11769 shost = lpfc_shost_from_vport(vport);
11770
11771 cfg_mode = phba->cfg_use_msi;
11772 while (true) {
11773
11774 lpfc_stop_port(phba);
11775
11776 intr_mode = lpfc_sli_enable_intr(phba, cfg_mode);
11777 if (intr_mode == LPFC_INTR_ERROR) {
11778 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11779 "0431 Failed to enable interrupt.\n");
11780 error = -ENODEV;
11781 goto out_free_sysfs_attr;
11782 }
11783
11784 if (lpfc_sli_hba_setup(phba)) {
11785 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11786 "1477 Failed to set up hba\n");
11787 error = -ENODEV;
11788 goto out_remove_device;
11789 }
11790
11791
11792 msleep(50);
11793
11794 if (intr_mode == 0 ||
11795 phba->sli.slistat.sli_intr > LPFC_MSIX_VECTORS) {
11796
11797 phba->intr_mode = intr_mode;
11798 lpfc_log_intr_mode(phba, intr_mode);
11799 break;
11800 } else {
11801 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11802 "0447 Configure interrupt mode (%d) "
11803 "failed active interrupt test.\n",
11804 intr_mode);
11805
11806 lpfc_sli_disable_intr(phba);
11807
11808 cfg_mode = --intr_mode;
11809 }
11810 }
11811
11812
11813 lpfc_post_init_setup(phba);
11814
11815
11816 lpfc_create_static_vport(phba);
11817
11818 return 0;
11819
11820out_remove_device:
11821 lpfc_unset_hba(phba);
11822out_free_sysfs_attr:
11823 lpfc_free_sysfs_attr(vport);
11824out_destroy_shost:
11825 lpfc_destroy_shost(phba);
11826out_unset_driver_resource:
11827 lpfc_unset_driver_resource_phase2(phba);
11828out_free_iocb_list:
11829 lpfc_free_iocb_list(phba);
11830out_unset_driver_resource_s3:
11831 lpfc_sli_driver_resource_unset(phba);
11832out_unset_pci_mem_s3:
11833 lpfc_sli_pci_mem_unset(phba);
11834out_disable_pci_dev:
11835 lpfc_disable_pci_dev(phba);
11836 if (shost)
11837 scsi_host_put(shost);
11838out_free_phba:
11839 lpfc_hba_free(phba);
11840 return error;
11841}
11842
11843
11844
11845
11846
11847
11848
11849
11850
11851
11852static void
11853lpfc_pci_remove_one_s3(struct pci_dev *pdev)
11854{
11855 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11856 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
11857 struct lpfc_vport **vports;
11858 struct lpfc_hba *phba = vport->phba;
11859 int i;
11860
11861 spin_lock_irq(&phba->hbalock);
11862 vport->load_flag |= FC_UNLOADING;
11863 spin_unlock_irq(&phba->hbalock);
11864
11865 lpfc_free_sysfs_attr(vport);
11866
11867
11868 vports = lpfc_create_vport_work_array(phba);
11869 if (vports != NULL)
11870 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
11871 if (vports[i]->port_type == LPFC_PHYSICAL_PORT)
11872 continue;
11873 fc_vport_terminate(vports[i]->fc_vport);
11874 }
11875 lpfc_destroy_vport_work_array(phba, vports);
11876
11877
11878 fc_remove_host(shost);
11879 scsi_remove_host(shost);
11880
11881 lpfc_cleanup(vport);
11882
11883
11884
11885
11886
11887
11888
11889
11890 lpfc_sli_hba_down(phba);
11891
11892 kthread_stop(phba->worker_thread);
11893
11894 lpfc_sli_brdrestart(phba);
11895
11896 kfree(phba->vpi_bmask);
11897 kfree(phba->vpi_ids);
11898
11899 lpfc_stop_hba_timers(phba);
11900 spin_lock_irq(&phba->port_list_lock);
11901 list_del_init(&vport->listentry);
11902 spin_unlock_irq(&phba->port_list_lock);
11903
11904 lpfc_debugfs_terminate(vport);
11905
11906
11907 if (phba->cfg_sriov_nr_virtfn)
11908 pci_disable_sriov(pdev);
11909
11910
11911 lpfc_sli_disable_intr(phba);
11912
11913 scsi_host_put(shost);
11914
11915
11916
11917
11918
11919 lpfc_scsi_free(phba);
11920 lpfc_free_iocb_list(phba);
11921
11922 lpfc_mem_free_all(phba);
11923
11924 dma_free_coherent(&pdev->dev, lpfc_sli_hbq_size(),
11925 phba->hbqslimp.virt, phba->hbqslimp.phys);
11926
11927
11928 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
11929 phba->slim2p.virt, phba->slim2p.phys);
11930
11931
11932 iounmap(phba->ctrl_regs_memmap_p);
11933 iounmap(phba->slim_memmap_p);
11934
11935 lpfc_hba_free(phba);
11936
11937 pci_release_mem_regions(pdev);
11938 pci_disable_device(pdev);
11939}
11940
11941
11942
11943
11944
11945
11946
11947
11948
11949
11950
11951
11952
11953
11954
11955
11956
11957
11958
11959
11960
11961
11962static int
11963lpfc_pci_suspend_one_s3(struct pci_dev *pdev, pm_message_t msg)
11964{
11965 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11966 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
11967
11968 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11969 "0473 PCI device Power Management suspend.\n");
11970
11971
11972 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
11973 lpfc_offline(phba);
11974 kthread_stop(phba->worker_thread);
11975
11976
11977 lpfc_sli_disable_intr(phba);
11978
11979
11980 pci_save_state(pdev);
11981 pci_set_power_state(pdev, PCI_D3hot);
11982
11983 return 0;
11984}
11985
11986
11987
11988
11989
11990
11991
11992
11993
11994
11995
11996
11997
11998
11999
12000
12001
12002
12003
12004
12005static int
12006lpfc_pci_resume_one_s3(struct pci_dev *pdev)
12007{
12008 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12009 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12010 uint32_t intr_mode;
12011 int error;
12012
12013 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
12014 "0452 PCI device Power Management resume.\n");
12015
12016
12017 pci_set_power_state(pdev, PCI_D0);
12018 pci_restore_state(pdev);
12019
12020
12021
12022
12023
12024 pci_save_state(pdev);
12025
12026 if (pdev->is_busmaster)
12027 pci_set_master(pdev);
12028
12029
12030 phba->worker_thread = kthread_run(lpfc_do_work, phba,
12031 "lpfc_worker_%d", phba->brd_no);
12032 if (IS_ERR(phba->worker_thread)) {
12033 error = PTR_ERR(phba->worker_thread);
12034 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12035 "0434 PM resume failed to start worker "
12036 "thread: error=x%x.\n", error);
12037 return error;
12038 }
12039
12040
12041 intr_mode = lpfc_sli_enable_intr(phba, phba->intr_mode);
12042 if (intr_mode == LPFC_INTR_ERROR) {
12043 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12044 "0430 PM resume Failed to enable interrupt\n");
12045 return -EIO;
12046 } else
12047 phba->intr_mode = intr_mode;
12048
12049
12050 lpfc_sli_brdrestart(phba);
12051 lpfc_online(phba);
12052
12053
12054 lpfc_log_intr_mode(phba, phba->intr_mode);
12055
12056 return 0;
12057}
12058
12059
12060
12061
12062
12063
12064
12065
12066static void
12067lpfc_sli_prep_dev_for_recover(struct lpfc_hba *phba)
12068{
12069 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12070 "2723 PCI channel I/O abort preparing for recovery\n");
12071
12072
12073
12074
12075
12076 lpfc_sli_abort_fcp_rings(phba);
12077}
12078
12079
12080
12081
12082
12083
12084
12085
12086
12087static void
12088lpfc_sli_prep_dev_for_reset(struct lpfc_hba *phba)
12089{
12090 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12091 "2710 PCI channel disable preparing for reset\n");
12092
12093
12094 lpfc_block_mgmt_io(phba, LPFC_MBX_WAIT);
12095
12096
12097 lpfc_scsi_dev_block(phba);
12098
12099
12100 lpfc_sli_flush_io_rings(phba);
12101
12102
12103 lpfc_stop_hba_timers(phba);
12104
12105
12106 lpfc_sli_disable_intr(phba);
12107 pci_disable_device(phba->pcidev);
12108}
12109
12110
12111
12112
12113
12114
12115
12116
12117
12118static void
12119lpfc_sli_prep_dev_for_perm_failure(struct lpfc_hba *phba)
12120{
12121 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12122 "2711 PCI channel permanent disable for failure\n");
12123
12124 lpfc_scsi_dev_block(phba);
12125
12126
12127 lpfc_stop_hba_timers(phba);
12128
12129
12130 lpfc_sli_flush_io_rings(phba);
12131}
12132
12133
12134
12135
12136
12137
12138
12139
12140
12141
12142
12143
12144
12145
12146
12147
12148
12149
12150
12151static pci_ers_result_t
12152lpfc_io_error_detected_s3(struct pci_dev *pdev, pci_channel_state_t state)
12153{
12154 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12155 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12156
12157 switch (state) {
12158 case pci_channel_io_normal:
12159
12160 lpfc_sli_prep_dev_for_recover(phba);
12161 return PCI_ERS_RESULT_CAN_RECOVER;
12162 case pci_channel_io_frozen:
12163
12164 lpfc_sli_prep_dev_for_reset(phba);
12165 return PCI_ERS_RESULT_NEED_RESET;
12166 case pci_channel_io_perm_failure:
12167
12168 lpfc_sli_prep_dev_for_perm_failure(phba);
12169 return PCI_ERS_RESULT_DISCONNECT;
12170 default:
12171
12172 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12173 "0472 Unknown PCI error state: x%x\n", state);
12174 lpfc_sli_prep_dev_for_reset(phba);
12175 return PCI_ERS_RESULT_NEED_RESET;
12176 }
12177}
12178
12179
12180
12181
12182
12183
12184
12185
12186
12187
12188
12189
12190
12191
12192
12193
12194
12195
12196
12197static pci_ers_result_t
12198lpfc_io_slot_reset_s3(struct pci_dev *pdev)
12199{
12200 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12201 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12202 struct lpfc_sli *psli = &phba->sli;
12203 uint32_t intr_mode;
12204
12205 dev_printk(KERN_INFO, &pdev->dev, "recovering from a slot reset.\n");
12206 if (pci_enable_device_mem(pdev)) {
12207 printk(KERN_ERR "lpfc: Cannot re-enable "
12208 "PCI device after reset.\n");
12209 return PCI_ERS_RESULT_DISCONNECT;
12210 }
12211
12212 pci_restore_state(pdev);
12213
12214
12215
12216
12217
12218 pci_save_state(pdev);
12219
12220 if (pdev->is_busmaster)
12221 pci_set_master(pdev);
12222
12223 spin_lock_irq(&phba->hbalock);
12224 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
12225 spin_unlock_irq(&phba->hbalock);
12226
12227
12228 intr_mode = lpfc_sli_enable_intr(phba, phba->intr_mode);
12229 if (intr_mode == LPFC_INTR_ERROR) {
12230 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12231 "0427 Cannot re-enable interrupt after "
12232 "slot reset.\n");
12233 return PCI_ERS_RESULT_DISCONNECT;
12234 } else
12235 phba->intr_mode = intr_mode;
12236
12237
12238 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
12239 lpfc_offline(phba);
12240 lpfc_sli_brdrestart(phba);
12241
12242
12243 lpfc_log_intr_mode(phba, phba->intr_mode);
12244
12245 return PCI_ERS_RESULT_RECOVERED;
12246}
12247
12248
12249
12250
12251
12252
12253
12254
12255
12256
12257
12258static void
12259lpfc_io_resume_s3(struct pci_dev *pdev)
12260{
12261 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12262 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12263
12264
12265 lpfc_online(phba);
12266}
12267
12268
12269
12270
12271
12272
12273
12274int
12275lpfc_sli4_get_els_iocb_cnt(struct lpfc_hba *phba)
12276{
12277 int max_xri = phba->sli4_hba.max_cfg_param.max_xri;
12278
12279 if (phba->sli_rev == LPFC_SLI_REV4) {
12280 if (max_xri <= 100)
12281 return 10;
12282 else if (max_xri <= 256)
12283 return 25;
12284 else if (max_xri <= 512)
12285 return 50;
12286 else if (max_xri <= 1024)
12287 return 100;
12288 else if (max_xri <= 1536)
12289 return 150;
12290 else if (max_xri <= 2048)
12291 return 200;
12292 else
12293 return 250;
12294 } else
12295 return 0;
12296}
12297
12298
12299
12300
12301
12302
12303
12304int
12305lpfc_sli4_get_iocb_cnt(struct lpfc_hba *phba)
12306{
12307 int max_xri = lpfc_sli4_get_els_iocb_cnt(phba);
12308
12309 if (phba->nvmet_support)
12310 max_xri += LPFC_NVMET_BUF_POST;
12311 return max_xri;
12312}
12313
12314
12315static void
12316lpfc_log_write_firmware_error(struct lpfc_hba *phba, uint32_t offset,
12317 uint32_t magic_number, uint32_t ftype, uint32_t fid, uint32_t fsize,
12318 const struct firmware *fw)
12319{
12320 if ((offset == ADD_STATUS_FW_NOT_SUPPORTED) ||
12321 (phba->pcidev->device == PCI_DEVICE_ID_LANCER_G6_FC &&
12322 magic_number != MAGIC_NUMER_G6) ||
12323 (phba->pcidev->device == PCI_DEVICE_ID_LANCER_G7_FC &&
12324 magic_number != MAGIC_NUMER_G7))
12325 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12326 "3030 This firmware version is not supported on "
12327 "this HBA model. Device:%x Magic:%x Type:%x "
12328 "ID:%x Size %d %zd\n",
12329 phba->pcidev->device, magic_number, ftype, fid,
12330 fsize, fw->size);
12331 else
12332 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12333 "3022 FW Download failed. Device:%x Magic:%x Type:%x "
12334 "ID:%x Size %d %zd\n",
12335 phba->pcidev->device, magic_number, ftype, fid,
12336 fsize, fw->size);
12337}
12338
12339
12340
12341
12342
12343
12344
12345
12346static void
12347lpfc_write_firmware(const struct firmware *fw, void *context)
12348{
12349 struct lpfc_hba *phba = (struct lpfc_hba *)context;
12350 char fwrev[FW_REV_STR_SIZE];
12351 struct lpfc_grp_hdr *image;
12352 struct list_head dma_buffer_list;
12353 int i, rc = 0;
12354 struct lpfc_dmabuf *dmabuf, *next;
12355 uint32_t offset = 0, temp_offset = 0;
12356 uint32_t magic_number, ftype, fid, fsize;
12357
12358
12359 if (!fw) {
12360 rc = -ENXIO;
12361 goto out;
12362 }
12363 image = (struct lpfc_grp_hdr *)fw->data;
12364
12365 magic_number = be32_to_cpu(image->magic_number);
12366 ftype = bf_get_be32(lpfc_grp_hdr_file_type, image);
12367 fid = bf_get_be32(lpfc_grp_hdr_id, image);
12368 fsize = be32_to_cpu(image->size);
12369
12370 INIT_LIST_HEAD(&dma_buffer_list);
12371 lpfc_decode_firmware_rev(phba, fwrev, 1);
12372 if (strncmp(fwrev, image->revision, strnlen(image->revision, 16))) {
12373 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12374 "3023 Updating Firmware, Current Version:%s "
12375 "New Version:%s\n",
12376 fwrev, image->revision);
12377 for (i = 0; i < LPFC_MBX_WR_CONFIG_MAX_BDE; i++) {
12378 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf),
12379 GFP_KERNEL);
12380 if (!dmabuf) {
12381 rc = -ENOMEM;
12382 goto release_out;
12383 }
12384 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev,
12385 SLI4_PAGE_SIZE,
12386 &dmabuf->phys,
12387 GFP_KERNEL);
12388 if (!dmabuf->virt) {
12389 kfree(dmabuf);
12390 rc = -ENOMEM;
12391 goto release_out;
12392 }
12393 list_add_tail(&dmabuf->list, &dma_buffer_list);
12394 }
12395 while (offset < fw->size) {
12396 temp_offset = offset;
12397 list_for_each_entry(dmabuf, &dma_buffer_list, list) {
12398 if (temp_offset + SLI4_PAGE_SIZE > fw->size) {
12399 memcpy(dmabuf->virt,
12400 fw->data + temp_offset,
12401 fw->size - temp_offset);
12402 temp_offset = fw->size;
12403 break;
12404 }
12405 memcpy(dmabuf->virt, fw->data + temp_offset,
12406 SLI4_PAGE_SIZE);
12407 temp_offset += SLI4_PAGE_SIZE;
12408 }
12409 rc = lpfc_wr_object(phba, &dma_buffer_list,
12410 (fw->size - offset), &offset);
12411 if (rc) {
12412 lpfc_log_write_firmware_error(phba, offset,
12413 magic_number, ftype, fid, fsize, fw);
12414 goto release_out;
12415 }
12416 }
12417 rc = offset;
12418 } else
12419 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12420 "3029 Skipped Firmware update, Current "
12421 "Version:%s New Version:%s\n",
12422 fwrev, image->revision);
12423
12424release_out:
12425 list_for_each_entry_safe(dmabuf, next, &dma_buffer_list, list) {
12426 list_del(&dmabuf->list);
12427 dma_free_coherent(&phba->pcidev->dev, SLI4_PAGE_SIZE,
12428 dmabuf->virt, dmabuf->phys);
12429 kfree(dmabuf);
12430 }
12431 release_firmware(fw);
12432out:
12433 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12434 "3024 Firmware update done: %d.\n", rc);
12435 return;
12436}
12437
12438
12439
12440
12441
12442
12443
12444
12445int
12446lpfc_sli4_request_firmware_update(struct lpfc_hba *phba, uint8_t fw_upgrade)
12447{
12448 uint8_t file_name[ELX_MODEL_NAME_SIZE];
12449 int ret;
12450 const struct firmware *fw;
12451
12452
12453 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) <
12454 LPFC_SLI_INTF_IF_TYPE_2)
12455 return -EPERM;
12456
12457 snprintf(file_name, ELX_MODEL_NAME_SIZE, "%s.grp", phba->ModelName);
12458
12459 if (fw_upgrade == INT_FW_UPGRADE) {
12460 ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
12461 file_name, &phba->pcidev->dev,
12462 GFP_KERNEL, (void *)phba,
12463 lpfc_write_firmware);
12464 } else if (fw_upgrade == RUN_FW_UPGRADE) {
12465 ret = request_firmware(&fw, file_name, &phba->pcidev->dev);
12466 if (!ret)
12467 lpfc_write_firmware(fw, (void *)phba);
12468 } else {
12469 ret = -EINVAL;
12470 }
12471
12472 return ret;
12473}
12474
12475
12476
12477
12478
12479
12480
12481
12482
12483
12484
12485
12486
12487
12488
12489
12490
12491
12492
12493static int
12494lpfc_pci_probe_one_s4(struct pci_dev *pdev, const struct pci_device_id *pid)
12495{
12496 struct lpfc_hba *phba;
12497 struct lpfc_vport *vport = NULL;
12498 struct Scsi_Host *shost = NULL;
12499 int error;
12500 uint32_t cfg_mode, intr_mode;
12501
12502
12503 phba = lpfc_hba_alloc(pdev);
12504 if (!phba)
12505 return -ENOMEM;
12506
12507
12508 error = lpfc_enable_pci_dev(phba);
12509 if (error)
12510 goto out_free_phba;
12511
12512
12513 error = lpfc_api_table_setup(phba, LPFC_PCI_DEV_OC);
12514 if (error)
12515 goto out_disable_pci_dev;
12516
12517
12518 error = lpfc_sli4_pci_mem_setup(phba);
12519 if (error) {
12520 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12521 "1410 Failed to set up pci memory space.\n");
12522 goto out_disable_pci_dev;
12523 }
12524
12525
12526 error = lpfc_sli4_driver_resource_setup(phba);
12527 if (error) {
12528 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12529 "1412 Failed to set up driver resource.\n");
12530 goto out_unset_pci_mem_s4;
12531 }
12532
12533 INIT_LIST_HEAD(&phba->active_rrq_list);
12534 INIT_LIST_HEAD(&phba->fcf.fcf_pri_list);
12535
12536
12537 error = lpfc_setup_driver_resource_phase2(phba);
12538 if (error) {
12539 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12540 "1414 Failed to set up driver resource.\n");
12541 goto out_unset_driver_resource_s4;
12542 }
12543
12544
12545 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
12546
12547
12548 cfg_mode = phba->cfg_use_msi;
12549
12550
12551 phba->pport = NULL;
12552 lpfc_stop_port(phba);
12553
12554
12555 intr_mode = lpfc_sli4_enable_intr(phba, cfg_mode);
12556 if (intr_mode == LPFC_INTR_ERROR) {
12557 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12558 "0426 Failed to enable interrupt.\n");
12559 error = -ENODEV;
12560 goto out_unset_driver_resource;
12561 }
12562
12563 if (phba->intr_type != MSIX) {
12564 phba->cfg_irq_chann = 1;
12565 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
12566 if (phba->nvmet_support)
12567 phba->cfg_nvmet_mrq = 1;
12568 }
12569 }
12570 lpfc_cpu_affinity_check(phba, phba->cfg_irq_chann);
12571
12572
12573 error = lpfc_create_shost(phba);
12574 if (error) {
12575 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12576 "1415 Failed to create scsi host.\n");
12577 goto out_disable_intr;
12578 }
12579 vport = phba->pport;
12580 shost = lpfc_shost_from_vport(vport);
12581
12582
12583 error = lpfc_alloc_sysfs_attr(vport);
12584 if (error) {
12585 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12586 "1416 Failed to allocate sysfs attr\n");
12587 goto out_destroy_shost;
12588 }
12589
12590
12591 if (lpfc_sli4_hba_setup(phba)) {
12592 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12593 "1421 Failed to set up hba\n");
12594 error = -ENODEV;
12595 goto out_free_sysfs_attr;
12596 }
12597
12598
12599 phba->intr_mode = intr_mode;
12600 lpfc_log_intr_mode(phba, intr_mode);
12601
12602
12603 lpfc_post_init_setup(phba);
12604
12605
12606
12607
12608 if (phba->nvmet_support == 0) {
12609 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
12610
12611
12612
12613
12614
12615 error = lpfc_nvme_create_localport(vport);
12616 if (error) {
12617 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12618 "6004 NVME registration "
12619 "failed, error x%x\n",
12620 error);
12621 }
12622 }
12623 }
12624
12625
12626 if (phba->cfg_request_firmware_upgrade)
12627 lpfc_sli4_request_firmware_update(phba, INT_FW_UPGRADE);
12628
12629
12630 lpfc_create_static_vport(phba);
12631
12632
12633 lpfc_sli4_ras_setup(phba);
12634
12635 return 0;
12636
12637out_free_sysfs_attr:
12638 lpfc_free_sysfs_attr(vport);
12639out_destroy_shost:
12640 lpfc_destroy_shost(phba);
12641out_disable_intr:
12642 lpfc_sli4_disable_intr(phba);
12643out_unset_driver_resource:
12644 lpfc_unset_driver_resource_phase2(phba);
12645out_unset_driver_resource_s4:
12646 lpfc_sli4_driver_resource_unset(phba);
12647out_unset_pci_mem_s4:
12648 lpfc_sli4_pci_mem_unset(phba);
12649out_disable_pci_dev:
12650 lpfc_disable_pci_dev(phba);
12651 if (shost)
12652 scsi_host_put(shost);
12653out_free_phba:
12654 lpfc_hba_free(phba);
12655 return error;
12656}
12657
12658
12659
12660
12661
12662
12663
12664
12665
12666
12667static void
12668lpfc_pci_remove_one_s4(struct pci_dev *pdev)
12669{
12670 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12671 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
12672 struct lpfc_vport **vports;
12673 struct lpfc_hba *phba = vport->phba;
12674 int i;
12675
12676
12677 spin_lock_irq(&phba->hbalock);
12678 vport->load_flag |= FC_UNLOADING;
12679 spin_unlock_irq(&phba->hbalock);
12680
12681
12682 lpfc_free_sysfs_attr(vport);
12683
12684
12685 vports = lpfc_create_vport_work_array(phba);
12686 if (vports != NULL)
12687 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
12688 if (vports[i]->port_type == LPFC_PHYSICAL_PORT)
12689 continue;
12690 fc_vport_terminate(vports[i]->fc_vport);
12691 }
12692 lpfc_destroy_vport_work_array(phba, vports);
12693
12694
12695 fc_remove_host(shost);
12696 scsi_remove_host(shost);
12697
12698
12699
12700
12701 lpfc_cleanup(vport);
12702 lpfc_nvmet_destroy_targetport(phba);
12703 lpfc_nvme_destroy_localport(vport);
12704
12705
12706 if (phba->cfg_xri_rebalancing)
12707 lpfc_destroy_multixri_pools(phba);
12708
12709
12710
12711
12712
12713
12714 lpfc_debugfs_terminate(vport);
12715
12716 lpfc_stop_hba_timers(phba);
12717 spin_lock_irq(&phba->port_list_lock);
12718 list_del_init(&vport->listentry);
12719 spin_unlock_irq(&phba->port_list_lock);
12720
12721
12722
12723
12724 lpfc_io_free(phba);
12725 lpfc_free_iocb_list(phba);
12726 lpfc_sli4_hba_unset(phba);
12727
12728 lpfc_unset_driver_resource_phase2(phba);
12729 lpfc_sli4_driver_resource_unset(phba);
12730
12731
12732 lpfc_sli4_pci_mem_unset(phba);
12733
12734
12735 scsi_host_put(shost);
12736 lpfc_disable_pci_dev(phba);
12737
12738
12739 lpfc_hba_free(phba);
12740
12741 return;
12742}
12743
12744
12745
12746
12747
12748
12749
12750
12751
12752
12753
12754
12755
12756
12757
12758
12759
12760
12761
12762
12763
12764
12765static int
12766lpfc_pci_suspend_one_s4(struct pci_dev *pdev, pm_message_t msg)
12767{
12768 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12769 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12770
12771 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
12772 "2843 PCI device Power Management suspend.\n");
12773
12774
12775 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
12776 lpfc_offline(phba);
12777 kthread_stop(phba->worker_thread);
12778
12779
12780 lpfc_sli4_disable_intr(phba);
12781 lpfc_sli4_queue_destroy(phba);
12782
12783
12784 pci_save_state(pdev);
12785 pci_set_power_state(pdev, PCI_D3hot);
12786
12787 return 0;
12788}
12789
12790
12791
12792
12793
12794
12795
12796
12797
12798
12799
12800
12801
12802
12803
12804
12805
12806
12807
12808
12809static int
12810lpfc_pci_resume_one_s4(struct pci_dev *pdev)
12811{
12812 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12813 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12814 uint32_t intr_mode;
12815 int error;
12816
12817 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
12818 "0292 PCI device Power Management resume.\n");
12819
12820
12821 pci_set_power_state(pdev, PCI_D0);
12822 pci_restore_state(pdev);
12823
12824
12825
12826
12827
12828 pci_save_state(pdev);
12829
12830 if (pdev->is_busmaster)
12831 pci_set_master(pdev);
12832
12833
12834 phba->worker_thread = kthread_run(lpfc_do_work, phba,
12835 "lpfc_worker_%d", phba->brd_no);
12836 if (IS_ERR(phba->worker_thread)) {
12837 error = PTR_ERR(phba->worker_thread);
12838 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12839 "0293 PM resume failed to start worker "
12840 "thread: error=x%x.\n", error);
12841 return error;
12842 }
12843
12844
12845 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
12846 if (intr_mode == LPFC_INTR_ERROR) {
12847 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12848 "0294 PM resume Failed to enable interrupt\n");
12849 return -EIO;
12850 } else
12851 phba->intr_mode = intr_mode;
12852
12853
12854 lpfc_sli_brdrestart(phba);
12855 lpfc_online(phba);
12856
12857
12858 lpfc_log_intr_mode(phba, phba->intr_mode);
12859
12860 return 0;
12861}
12862
12863
12864
12865
12866
12867
12868
12869
12870static void
12871lpfc_sli4_prep_dev_for_recover(struct lpfc_hba *phba)
12872{
12873 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12874 "2828 PCI channel I/O abort preparing for recovery\n");
12875
12876
12877
12878
12879 lpfc_sli_abort_fcp_rings(phba);
12880}
12881
12882
12883
12884
12885
12886
12887
12888
12889
12890static void
12891lpfc_sli4_prep_dev_for_reset(struct lpfc_hba *phba)
12892{
12893 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12894 "2826 PCI channel disable preparing for reset\n");
12895
12896
12897 lpfc_block_mgmt_io(phba, LPFC_MBX_NO_WAIT);
12898
12899
12900 lpfc_scsi_dev_block(phba);
12901
12902
12903 lpfc_sli_flush_io_rings(phba);
12904
12905
12906 lpfc_stop_hba_timers(phba);
12907
12908
12909 lpfc_sli4_disable_intr(phba);
12910 lpfc_sli4_queue_destroy(phba);
12911 pci_disable_device(phba->pcidev);
12912}
12913
12914
12915
12916
12917
12918
12919
12920
12921
12922static void
12923lpfc_sli4_prep_dev_for_perm_failure(struct lpfc_hba *phba)
12924{
12925 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12926 "2827 PCI channel permanent disable for failure\n");
12927
12928
12929 lpfc_scsi_dev_block(phba);
12930
12931
12932 lpfc_stop_hba_timers(phba);
12933
12934
12935 lpfc_sli_flush_io_rings(phba);
12936}
12937
12938
12939
12940
12941
12942
12943
12944
12945
12946
12947
12948
12949
12950
12951
12952
12953
12954static pci_ers_result_t
12955lpfc_io_error_detected_s4(struct pci_dev *pdev, pci_channel_state_t state)
12956{
12957 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12958 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12959
12960 switch (state) {
12961 case pci_channel_io_normal:
12962
12963 lpfc_sli4_prep_dev_for_recover(phba);
12964 return PCI_ERS_RESULT_CAN_RECOVER;
12965 case pci_channel_io_frozen:
12966
12967 lpfc_sli4_prep_dev_for_reset(phba);
12968 return PCI_ERS_RESULT_NEED_RESET;
12969 case pci_channel_io_perm_failure:
12970
12971 lpfc_sli4_prep_dev_for_perm_failure(phba);
12972 return PCI_ERS_RESULT_DISCONNECT;
12973 default:
12974
12975 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12976 "2825 Unknown PCI error state: x%x\n", state);
12977 lpfc_sli4_prep_dev_for_reset(phba);
12978 return PCI_ERS_RESULT_NEED_RESET;
12979 }
12980}
12981
12982
12983
12984
12985
12986
12987
12988
12989
12990
12991
12992
12993
12994
12995
12996
12997
12998
12999
13000static pci_ers_result_t
13001lpfc_io_slot_reset_s4(struct pci_dev *pdev)
13002{
13003 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13004 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13005 struct lpfc_sli *psli = &phba->sli;
13006 uint32_t intr_mode;
13007
13008 dev_printk(KERN_INFO, &pdev->dev, "recovering from a slot reset.\n");
13009 if (pci_enable_device_mem(pdev)) {
13010 printk(KERN_ERR "lpfc: Cannot re-enable "
13011 "PCI device after reset.\n");
13012 return PCI_ERS_RESULT_DISCONNECT;
13013 }
13014
13015 pci_restore_state(pdev);
13016
13017
13018
13019
13020
13021 pci_save_state(pdev);
13022
13023 if (pdev->is_busmaster)
13024 pci_set_master(pdev);
13025
13026 spin_lock_irq(&phba->hbalock);
13027 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
13028 spin_unlock_irq(&phba->hbalock);
13029
13030
13031 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
13032 if (intr_mode == LPFC_INTR_ERROR) {
13033 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13034 "2824 Cannot re-enable interrupt after "
13035 "slot reset.\n");
13036 return PCI_ERS_RESULT_DISCONNECT;
13037 } else
13038 phba->intr_mode = intr_mode;
13039
13040
13041 lpfc_log_intr_mode(phba, phba->intr_mode);
13042
13043 return PCI_ERS_RESULT_RECOVERED;
13044}
13045
13046
13047
13048
13049
13050
13051
13052
13053
13054
13055
13056static void
13057lpfc_io_resume_s4(struct pci_dev *pdev)
13058{
13059 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13060 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13061
13062
13063
13064
13065
13066
13067
13068 if (!(phba->sli.sli_flag & LPFC_SLI_ACTIVE)) {
13069
13070 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
13071 lpfc_offline(phba);
13072 lpfc_sli_brdrestart(phba);
13073
13074 lpfc_online(phba);
13075 }
13076}
13077
13078
13079
13080
13081
13082
13083
13084
13085
13086
13087
13088
13089
13090
13091
13092
13093
13094
13095
13096static int
13097lpfc_pci_probe_one(struct pci_dev *pdev, const struct pci_device_id *pid)
13098{
13099 int rc;
13100 struct lpfc_sli_intf intf;
13101
13102 if (pci_read_config_dword(pdev, LPFC_SLI_INTF, &intf.word0))
13103 return -ENODEV;
13104
13105 if ((bf_get(lpfc_sli_intf_valid, &intf) == LPFC_SLI_INTF_VALID) &&
13106 (bf_get(lpfc_sli_intf_slirev, &intf) == LPFC_SLI_INTF_REV_SLI4))
13107 rc = lpfc_pci_probe_one_s4(pdev, pid);
13108 else
13109 rc = lpfc_pci_probe_one_s3(pdev, pid);
13110
13111 return rc;
13112}
13113
13114
13115
13116
13117
13118
13119
13120
13121
13122
13123
13124static void
13125lpfc_pci_remove_one(struct pci_dev *pdev)
13126{
13127 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13128 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13129
13130 switch (phba->pci_dev_grp) {
13131 case LPFC_PCI_DEV_LP:
13132 lpfc_pci_remove_one_s3(pdev);
13133 break;
13134 case LPFC_PCI_DEV_OC:
13135 lpfc_pci_remove_one_s4(pdev);
13136 break;
13137 default:
13138 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13139 "1424 Invalid PCI device group: 0x%x\n",
13140 phba->pci_dev_grp);
13141 break;
13142 }
13143 return;
13144}
13145
13146
13147
13148
13149
13150
13151
13152
13153
13154
13155
13156
13157
13158
13159
13160static int
13161lpfc_pci_suspend_one(struct pci_dev *pdev, pm_message_t msg)
13162{
13163 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13164 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13165 int rc = -ENODEV;
13166
13167 switch (phba->pci_dev_grp) {
13168 case LPFC_PCI_DEV_LP:
13169 rc = lpfc_pci_suspend_one_s3(pdev, msg);
13170 break;
13171 case LPFC_PCI_DEV_OC:
13172 rc = lpfc_pci_suspend_one_s4(pdev, msg);
13173 break;
13174 default:
13175 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13176 "1425 Invalid PCI device group: 0x%x\n",
13177 phba->pci_dev_grp);
13178 break;
13179 }
13180 return rc;
13181}
13182
13183
13184
13185
13186
13187
13188
13189
13190
13191
13192
13193
13194
13195
13196static int
13197lpfc_pci_resume_one(struct pci_dev *pdev)
13198{
13199 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13200 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13201 int rc = -ENODEV;
13202
13203 switch (phba->pci_dev_grp) {
13204 case LPFC_PCI_DEV_LP:
13205 rc = lpfc_pci_resume_one_s3(pdev);
13206 break;
13207 case LPFC_PCI_DEV_OC:
13208 rc = lpfc_pci_resume_one_s4(pdev);
13209 break;
13210 default:
13211 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13212 "1426 Invalid PCI device group: 0x%x\n",
13213 phba->pci_dev_grp);
13214 break;
13215 }
13216 return rc;
13217}
13218
13219
13220
13221
13222
13223
13224
13225
13226
13227
13228
13229
13230
13231
13232
13233
13234static pci_ers_result_t
13235lpfc_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
13236{
13237 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13238 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13239 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
13240
13241 switch (phba->pci_dev_grp) {
13242 case LPFC_PCI_DEV_LP:
13243 rc = lpfc_io_error_detected_s3(pdev, state);
13244 break;
13245 case LPFC_PCI_DEV_OC:
13246 rc = lpfc_io_error_detected_s4(pdev, state);
13247 break;
13248 default:
13249 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13250 "1427 Invalid PCI device group: 0x%x\n",
13251 phba->pci_dev_grp);
13252 break;
13253 }
13254 return rc;
13255}
13256
13257
13258
13259
13260
13261
13262
13263
13264
13265
13266
13267
13268
13269
13270
13271static pci_ers_result_t
13272lpfc_io_slot_reset(struct pci_dev *pdev)
13273{
13274 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13275 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13276 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
13277
13278 switch (phba->pci_dev_grp) {
13279 case LPFC_PCI_DEV_LP:
13280 rc = lpfc_io_slot_reset_s3(pdev);
13281 break;
13282 case LPFC_PCI_DEV_OC:
13283 rc = lpfc_io_slot_reset_s4(pdev);
13284 break;
13285 default:
13286 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13287 "1428 Invalid PCI device group: 0x%x\n",
13288 phba->pci_dev_grp);
13289 break;
13290 }
13291 return rc;
13292}
13293
13294
13295
13296
13297
13298
13299
13300
13301
13302
13303
13304static void
13305lpfc_io_resume(struct pci_dev *pdev)
13306{
13307 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13308 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13309
13310 switch (phba->pci_dev_grp) {
13311 case LPFC_PCI_DEV_LP:
13312 lpfc_io_resume_s3(pdev);
13313 break;
13314 case LPFC_PCI_DEV_OC:
13315 lpfc_io_resume_s4(pdev);
13316 break;
13317 default:
13318 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13319 "1429 Invalid PCI device group: 0x%x\n",
13320 phba->pci_dev_grp);
13321 break;
13322 }
13323 return;
13324}
13325
13326
13327
13328
13329
13330
13331
13332
13333
13334
13335
13336static void
13337lpfc_sli4_oas_verify(struct lpfc_hba *phba)
13338{
13339
13340 if (!phba->cfg_EnableXLane)
13341 return;
13342
13343 if (phba->sli4_hba.pc_sli4_params.oas_supported) {
13344 phba->cfg_fof = 1;
13345 } else {
13346 phba->cfg_fof = 0;
13347 if (phba->device_data_mem_pool)
13348 mempool_destroy(phba->device_data_mem_pool);
13349 phba->device_data_mem_pool = NULL;
13350 }
13351
13352 return;
13353}
13354
13355
13356
13357
13358
13359
13360
13361
13362void
13363lpfc_sli4_ras_init(struct lpfc_hba *phba)
13364{
13365 switch (phba->pcidev->device) {
13366 case PCI_DEVICE_ID_LANCER_G6_FC:
13367 case PCI_DEVICE_ID_LANCER_G7_FC:
13368 phba->ras_fwlog.ras_hwsupport = true;
13369 if (phba->cfg_ras_fwlog_func == PCI_FUNC(phba->pcidev->devfn) &&
13370 phba->cfg_ras_fwlog_buffsize)
13371 phba->ras_fwlog.ras_enabled = true;
13372 else
13373 phba->ras_fwlog.ras_enabled = false;
13374 break;
13375 default:
13376 phba->ras_fwlog.ras_hwsupport = false;
13377 }
13378}
13379
13380
13381MODULE_DEVICE_TABLE(pci, lpfc_id_table);
13382
13383static const struct pci_error_handlers lpfc_err_handler = {
13384 .error_detected = lpfc_io_error_detected,
13385 .slot_reset = lpfc_io_slot_reset,
13386 .resume = lpfc_io_resume,
13387};
13388
13389static struct pci_driver lpfc_driver = {
13390 .name = LPFC_DRIVER_NAME,
13391 .id_table = lpfc_id_table,
13392 .probe = lpfc_pci_probe_one,
13393 .remove = lpfc_pci_remove_one,
13394 .shutdown = lpfc_pci_remove_one,
13395 .suspend = lpfc_pci_suspend_one,
13396 .resume = lpfc_pci_resume_one,
13397 .err_handler = &lpfc_err_handler,
13398};
13399
13400static const struct file_operations lpfc_mgmt_fop = {
13401 .owner = THIS_MODULE,
13402};
13403
13404static struct miscdevice lpfc_mgmt_dev = {
13405 .minor = MISC_DYNAMIC_MINOR,
13406 .name = "lpfcmgmt",
13407 .fops = &lpfc_mgmt_fop,
13408};
13409
13410
13411
13412
13413
13414
13415
13416
13417
13418
13419
13420
13421
13422static int __init
13423lpfc_init(void)
13424{
13425 int error = 0;
13426
13427 printk(LPFC_MODULE_DESC "\n");
13428 printk(LPFC_COPYRIGHT "\n");
13429
13430 error = misc_register(&lpfc_mgmt_dev);
13431 if (error)
13432 printk(KERN_ERR "Could not register lpfcmgmt device, "
13433 "misc_register returned with status %d", error);
13434
13435 lpfc_transport_functions.vport_create = lpfc_vport_create;
13436 lpfc_transport_functions.vport_delete = lpfc_vport_delete;
13437 lpfc_transport_template =
13438 fc_attach_transport(&lpfc_transport_functions);
13439 if (lpfc_transport_template == NULL)
13440 return -ENOMEM;
13441 lpfc_vport_transport_template =
13442 fc_attach_transport(&lpfc_vport_transport_functions);
13443 if (lpfc_vport_transport_template == NULL) {
13444 fc_release_transport(lpfc_transport_template);
13445 return -ENOMEM;
13446 }
13447 lpfc_nvme_cmd_template();
13448 lpfc_nvmet_cmd_template();
13449
13450
13451 lpfc_present_cpu = num_present_cpus();
13452
13453 error = pci_register_driver(&lpfc_driver);
13454 if (error) {
13455 fc_release_transport(lpfc_transport_template);
13456 fc_release_transport(lpfc_vport_transport_template);
13457 }
13458
13459 return error;
13460}
13461
13462
13463
13464
13465
13466
13467
13468
13469static void __exit
13470lpfc_exit(void)
13471{
13472 misc_deregister(&lpfc_mgmt_dev);
13473 pci_unregister_driver(&lpfc_driver);
13474 fc_release_transport(lpfc_transport_template);
13475 fc_release_transport(lpfc_vport_transport_template);
13476 idr_destroy(&lpfc_hba_index);
13477}
13478
13479module_init(lpfc_init);
13480module_exit(lpfc_exit);
13481MODULE_LICENSE("GPL");
13482MODULE_DESCRIPTION(LPFC_MODULE_DESC);
13483MODULE_AUTHOR("Broadcom");
13484MODULE_VERSION("0:" LPFC_DRIVER_VERSION);
13485