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13#ifndef __XILINX_DMA_APF_H
14#define __XILINX_DMA_APF_H
15
16
17#include <linux/ioctl.h>
18
19
20#include <linux/interrupt.h>
21
22
23#include <linux/dma-mapping.h>
24
25
26#include "xlnk.h"
27#include "xlnk-sysdef.h"
28
29#define XDMA_IOC_MAGIC 'X'
30#define XDMA_IOCRESET _IO(XDMA_IOC_MAGIC, 0)
31#define XDMA_IOCREQUEST _IOWR(XDMA_IOC_MAGIC, 1, unsigned long)
32#define XDMA_IOCRELEASE _IOWR(XDMA_IOC_MAGIC, 2, unsigned long)
33#define XDMA_IOCSUBMIT _IOWR(XDMA_IOC_MAGIC, 3, unsigned long)
34#define XDMA_IOCWAIT _IOWR(XDMA_IOC_MAGIC, 4, unsigned long)
35#define XDMA_IOCGETCONFIG _IOWR(XDMA_IOC_MAGIC, 5, unsigned long)
36#define XDMA_IOCSETCONFIG _IOWR(XDMA_IOC_MAGIC, 6, unsigned long)
37#define XDMA_IOC_MAXNR 6
38
39
40
41#define XDMA_RESET_LOOP 1000000
42#define XDMA_HALT_LOOP 1000000
43#define XDMA_NO_CHANGE 0xFFFF
44
45
46
47#define XDMA_CR_RESET_MASK 0x00000004
48#define XDMA_CR_RUNSTOP_MASK 0x00000001
49
50#define XDMA_SR_HALTED_MASK 0x00000001
51#define XDMA_SR_IDLE_MASK 0x00000002
52
53#define XDMA_SR_ERR_INTERNAL_MASK 0x00000010
54#define XDMA_SR_ERR_SLAVE_MASK 0x00000020
55#define XDMA_SR_ERR_DECODE_MASK 0x00000040
56#define XDMA_SR_ERR_SG_INT_MASK 0x00000100
57#define XDMA_SR_ERR_SG_SLV_MASK 0x00000200
58#define XDMA_SR_ERR_SG_DEC_MASK 0x00000400
59#define XDMA_SR_ERR_ALL_MASK 0x00000770
60
61#define XDMA_XR_IRQ_IOC_MASK 0x00001000
62#define XDMA_XR_IRQ_DELAY_MASK 0x00002000
63#define XDMA_XR_IRQ_ERROR_MASK 0x00004000
64#define XDMA_XR_IRQ_ALL_MASK 0x00007000
65
66#define XDMA_XR_DELAY_MASK 0xFF000000
67#define XDMA_XR_COALESCE_MASK 0x00FF0000
68
69#define XDMA_DELAY_SHIFT 24
70#define XDMA_COALESCE_SHIFT 16
71
72#define XDMA_DELAY_MAX 0xFF
73#define XDMA_COALESCE_MAX 0xFF
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75
76
77#define XDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF
78#define XDMA_BD_STS_COMPL_MASK 0x80000000
79#define XDMA_BD_STS_ERR_MASK 0x70000000
80#define XDMA_BD_STS_ALL_MASK 0xF0000000
81
82
83
84#define XDMA_BD_SOP 0x08000000
85#define XDMA_BD_EOP 0x04000000
86
87
88
89#define XDMA_BD_SF_POLL_MODE_MASK 0x00000002
90#define XDMA_BD_SF_SW_DONE_MASK 0x00000001
91
92
93#define XDMA_MAX_BD_CNT 16384
94#define XDMA_MAX_CHANS_PER_DEVICE 2
95#define XDMA_MAX_TRANS_LEN 0x7FF000
96#define XDMA_MAX_APPWORDS 5
97#define XDMA_BD_CLEANUP_THRESHOLD ((XDMA_MAX_BD_CNT * 8) / 10)
98
99#define XDMA_FLAGS_WAIT_COMPLETE 1
100#define XDMA_FLAGS_TRYWAIT 2
101
102
103struct xdma_channel_config {
104 char *type;
105 unsigned int include_dre;
106 unsigned int datawidth;
107 unsigned int max_burst_len;
108 unsigned int irq;
109 unsigned int poll_mode;
110 unsigned int lite_mode;
111};
112
113struct xdma_device_config {
114 char *type;
115 char *name;
116 unsigned int include_sg;
117 unsigned int sg_include_stscntrl_strm;
118 unsigned int channel_count;
119 struct xdma_channel_config *channel_config;
120};
121
122struct xdma_desc_hw {
123 xlnk_intptr_type next_desc;
124#if XLNK_SYS_BIT_WIDTH == 32
125 u32 pad1;
126#endif
127 xlnk_intptr_type src_addr;
128#if XLNK_SYS_BIT_WIDTH == 32
129 u32 pad2;
130#endif
131 u32 addr_vsize;
132 u32 hsize;
133 u32 control;
134 u32 status;
135 u32 app[5];
136 xlnk_intptr_type dmahead;
137#if XLNK_SYS_BIT_WIDTH == 32
138 u32 Reserved0;
139#endif
140 u32 sw_flag;
141} __aligned(64);
142
143
144struct xdma_regs {
145 u32 cr;
146 u32 sr;
147 u32 cdr;
148 u32 cdr_hi;
149 u32 tdr;
150 u32 tdr_hi;
151 u32 src;
152 u32 src_hi;
153 u32 dst;
154 u32 dst_hi;
155 u32 btt_ref;
156
157
158 u32 version;
159};
160
161
162struct xdma_chan {
163 char name[64];
164 struct xdma_regs __iomem *regs;
165 struct device *dev;
166 struct xdma_desc_hw *bds[XDMA_MAX_BD_CNT];
167 dma_addr_t bd_phys_addr;
168 u32 bd_chain_size;
169 int bd_cur;
170 int bd_tail;
171 unsigned int bd_used;
172 enum dma_data_direction direction;
173 int id;
174 int irq;
175 int poll_mode;
176 spinlock_t lock;
177 struct tasklet_struct tasklet;
178 struct tasklet_struct dma_err_tasklet;
179 int max_len;
180 int err;
181 int client_count;
182};
183
184struct xdma_device {
185 void __iomem *regs;
186 struct device *dev;
187 struct list_head node;
188 struct xdma_chan *chan[XDMA_MAX_CHANS_PER_DEVICE];
189 u8 channel_count;
190};
191
192struct xdma_head {
193 xlnk_intptr_type userbuf;
194 unsigned int size;
195 unsigned int dmaflag;
196 enum dma_data_direction dmadir;
197 struct scatterlist *sglist;
198 unsigned int sgcnt;
199 struct scatterlist *pagelist;
200 unsigned int pagecnt;
201 struct completion cmp;
202 struct xdma_chan *chan;
203 unsigned int nappwords_o;
204 u32 appwords_o[XDMA_MAX_APPWORDS];
205 unsigned int userflag;
206 u32 last_bd_index;
207 struct xlnk_dmabuf_reg *dmabuf;
208};
209
210struct xdma_chan *xdma_request_channel(char *name);
211void xdma_release_channel(struct xdma_chan *chan);
212void xdma_release_all_channels(void);
213int xdma_submit(struct xdma_chan *chan,
214 xlnk_intptr_type userbuf,
215 void *kaddr,
216 unsigned int size,
217 unsigned int nappwords_i,
218 u32 *appwords_i,
219 unsigned int nappwords_o,
220 unsigned int user_flags,
221 struct xdma_head **dmaheadpp,
222 struct xlnk_dmabuf_reg *dp);
223int xdma_wait(struct xdma_head *dmahead,
224 unsigned int user_flags,
225 unsigned int *operating_flags);
226int xdma_getconfig(struct xdma_chan *chan,
227 unsigned char *irq_thresh,
228 unsigned char *irq_delay);
229int xdma_setconfig(struct xdma_chan *chan,
230 unsigned char irq_thresh,
231 unsigned char irq_delay);
232unsigned int xlate_irq(unsigned int hwirq);
233
234#endif
235