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7#ifndef R8180_HW
8#define R8180_HW
9
10enum baseband_config {
11 BaseBand_Config_PHY_REG = 0,
12 BaseBand_Config_AGC_TAB = 1,
13};
14
15#define RTL8187_REQT_READ 0xc0
16#define RTL8187_REQT_WRITE 0x40
17#define RTL8187_REQ_GET_REGS 0x05
18#define RTL8187_REQ_SET_REGS 0x05
19
20#define MAX_TX_URB 5
21#define MAX_RX_URB 16
22#define RX_URB_SIZE 9100
23
24#define BB_ANTATTEN_CHAN14 0x0c
25#define BB_ANTENNA_B 0x40
26
27#define BB_HOST_BANG (1<<30)
28#define BB_HOST_BANG_EN (1<<2)
29#define BB_HOST_BANG_CLK (1<<1)
30#define BB_HOST_BANG_RW (1<<3)
31#define BB_HOST_BANG_DATA 1
32
33#define RTL8190_EEPROM_ID 0x8129
34#define EEPROM_VID 0x02
35#define EEPROM_DID 0x04
36#define EEPROM_NODE_ADDRESS_BYTE_0 0x0C
37
38#define EEPROM_TxPowerDiff 0x1F
39
40
41#define EEPROM_PwDiff 0x21
42#define EEPROM_CrystalCap 0x22
43
44
45
46#define EEPROM_TxPwIndex_CCK_V1 0x29
47#define EEPROM_TxPwIndex_OFDM_24G_V1 0x2C
48#define EEPROM_TxPwIndex_Ver 0x27
49
50#define EEPROM_Default_TxPowerDiff 0x0
51#define EEPROM_Default_ThermalMeter 0x77
52#define EEPROM_Default_AntTxPowerDiff 0x0
53#define EEPROM_Default_TxPwDiff_CrystalCap 0x5
54#define EEPROM_Default_PwDiff 0x4
55#define EEPROM_Default_CrystalCap 0x5
56#define EEPROM_Default_TxPower 0x1010
57#define EEPROM_ICVersion_ChannelPlan 0x7C
58#define EEPROM_Customer_ID 0x7B
59#define EEPROM_RFInd_PowerDiff 0x28
60#define EEPROM_ThermalMeter 0x29
61#define EEPROM_TxPwDiff_CrystalCap 0x2A
62#define EEPROM_TxPwIndex_CCK 0x2C
63#define EEPROM_TxPwIndex_OFDM_24G 0x3A
64#define EEPROM_Default_TxPowerLevel 0x10
65#define EEPROM_IC_VER 0x7d
66#define EEPROM_CRC 0x7e
67
68#define EEPROM_CID_DEFAULT 0x0
69#define EEPROM_CID_CAMEO 0x1
70#define EEPROM_CID_RUNTOP 0x2
71#define EEPROM_CID_Senao 0x3
72#define EEPROM_CID_TOSHIBA 0x4
73#define EEPROM_CID_NetCore 0x5
74#define EEPROM_CID_Nettronix 0x6
75#define EEPROM_CID_Pronet 0x7
76#define EEPROM_CID_DLINK 0x8
77#define EEPROM_CID_WHQL 0xFE
78enum _RTL8192Pci_HW {
79 MAC0 = 0x000,
80 MAC1 = 0x001,
81 MAC2 = 0x002,
82 MAC3 = 0x003,
83 MAC4 = 0x004,
84 MAC5 = 0x005,
85 PCIF = 0x009,
86#define MXDMA2_16bytes 0x000
87#define MXDMA2_32bytes 0x001
88#define MXDMA2_64bytes 0x010
89#define MXDMA2_128bytes 0x011
90#define MXDMA2_256bytes 0x100
91#define MXDMA2_512bytes 0x101
92#define MXDMA2_1024bytes 0x110
93#define MXDMA2_NoLimit 0x7
94
95#define MULRW_SHIFT 3
96#define MXDMA2_RX_SHIFT 4
97#define MXDMA2_TX_SHIFT 0
98 PMR = 0x00c,
99 EPROM_CMD = 0x00e,
100#define EPROM_CMD_RESERVED_MASK BIT5
101#define EPROM_CMD_9356SEL BIT4
102#define EPROM_CMD_OPERATING_MODE_SHIFT 6
103#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))
104#define EPROM_CMD_CONFIG 0x3
105#define EPROM_CMD_NORMAL 0
106#define EPROM_CMD_LOAD 1
107#define EPROM_CMD_PROGRAM 2
108#define EPROM_CS_BIT 3
109#define EPROM_CK_BIT 2
110#define EPROM_W_BIT 1
111#define EPROM_R_BIT 0
112
113 AFR = 0x010,
114#define AFR_CardBEn (1<<0)
115#define AFR_CLKRUN_SEL (1<<1)
116#define AFR_FuncRegEn (1<<2)
117
118 ANAPAR = 0x17,
119#define BB_GLOBAL_RESET_BIT 0x1
120 BB_GLOBAL_RESET = 0x020,
121 BSSIDR = 0x02E,
122 CMDR = 0x037,
123#define CR_RST 0x10
124#define CR_RE 0x08
125#define CR_TE 0x04
126#define CR_MulRW 0x01
127 SIFS = 0x03E,
128 TCR = 0x040,
129 RCR = 0x044,
130#define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
131 BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23)
132#define RCR_ONLYERLPKT BIT31
133#define RCR_ENCS2 BIT30
134#define RCR_ENCS1 BIT29
135#define RCR_ENMBID BIT27
136#define RCR_ACKTXBW (BIT24|BIT25)
137#define RCR_CBSSID BIT23
138#define RCR_APWRMGT BIT22
139#define RCR_ADD3 BIT21
140#define RCR_AMF BIT20
141#define RCR_ACF BIT19
142#define RCR_ADF BIT18
143#define RCR_RXFTH BIT13
144#define RCR_AICV BIT12
145#define RCR_ACRC32 BIT5
146#define RCR_AB BIT3
147#define RCR_AM BIT2
148#define RCR_APM BIT1
149#define RCR_AAP BIT0
150#define RCR_MXDMA_OFFSET 8
151#define RCR_FIFO_OFFSET 13
152 SLOT_TIME = 0x049,
153 ACK_TIMEOUT = 0x04c,
154 PIFS_TIME = 0x04d,
155 USTIME = 0x04e,
156 EDCAPARA_BE = 0x050,
157 EDCAPARA_BK = 0x054,
158 EDCAPARA_VO = 0x058,
159 EDCAPARA_VI = 0x05C,
160#define AC_PARAM_TXOP_LIMIT_OFFSET 16
161#define AC_PARAM_ECW_MAX_OFFSET 12
162#define AC_PARAM_ECW_MIN_OFFSET 8
163#define AC_PARAM_AIFS_OFFSET 0
164 RFPC = 0x05F,
165 CWRR = 0x060,
166 BCN_TCFG = 0x062,
167#define BCN_TCFG_CW_SHIFT 8
168#define BCN_TCFG_IFS 0
169 BCN_INTERVAL = 0x070,
170 ATIMWND = 0x072,
171 BCN_DRV_EARLY_INT = 0x074,
172#define BCN_DRV_EARLY_INT_SWBCN_SHIFT 8
173#define BCN_DRV_EARLY_INT_TIME_SHIFT 0
174 BCN_DMATIME = 0x076,
175 BCN_ERR_THRESH = 0x078,
176 RWCAM = 0x0A0,
177#define CAM_CM_SecCAMPolling BIT31
178#define CAM_CM_SecCAMClr BIT30
179#define CAM_CM_SecCAMWE BIT16
180#define CAM_VALID BIT15
181#define CAM_NOTVALID 0x0000
182#define CAM_USEDK BIT5
183
184#define CAM_NONE 0x0
185#define CAM_WEP40 0x01
186#define CAM_TKIP 0x02
187#define CAM_AES 0x04
188#define CAM_WEP104 0x05
189
190#define TOTAL_CAM_ENTRY 32
191
192#define CAM_CONFIG_USEDK true
193#define CAM_CONFIG_NO_USEDK false
194#define CAM_WRITE BIT16
195#define CAM_READ 0x00000000
196#define CAM_POLLINIG BIT31
197#define SCR_UseDK 0x01
198 WCAMI = 0x0A4,
199 RCAMO = 0x0A8,
200 SECR = 0x0B0,
201#define SCR_TxUseDK BIT0
202#define SCR_RxUseDK BIT1
203#define SCR_TxEncEnable BIT2
204#define SCR_RxDecEnable BIT3
205#define SCR_SKByA2 BIT4
206#define SCR_NoSKMC BIT5
207 SWREGULATOR = 0x0BD,
208 INTA_MASK = 0x0f4,
209#define IMR8190_DISABLED 0x0
210#define IMR_ATIMEND BIT28
211#define IMR_TBDOK BIT27
212#define IMR_TBDER BIT26
213#define IMR_TXFOVW BIT15
214#define IMR_TIMEOUT0 BIT14
215#define IMR_BcnInt BIT13
216#define IMR_RXFOVW BIT12
217#define IMR_RDU BIT11
218#define IMR_RXCMDOK BIT10
219#define IMR_BDOK BIT9
220#define IMR_HIGHDOK BIT8
221#define IMR_COMDOK BIT7
222#define IMR_MGNTDOK BIT6
223#define IMR_HCCADOK BIT5
224#define IMR_BKDOK BIT4
225#define IMR_BEDOK BIT3
226#define IMR_VIDOK BIT2
227#define IMR_VODOK BIT1
228#define IMR_ROK BIT0
229 ISR = 0x0f8,
230 TPPoll = 0x0fd,
231#define TPPoll_BKQ BIT0
232#define TPPoll_BEQ BIT1
233#define TPPoll_VIQ BIT2
234#define TPPoll_VOQ BIT3
235#define TPPoll_BQ BIT4
236#define TPPoll_CQ BIT5
237#define TPPoll_MQ BIT6
238#define TPPoll_HQ BIT7
239#define TPPoll_HCCAQ BIT8
240#define TPPoll_StopBK BIT9
241#define TPPoll_StopBE BIT10
242#define TPPoll_StopVI BIT11
243#define TPPoll_StopVO BIT12
244#define TPPoll_StopMgt BIT13
245#define TPPoll_StopHigh BIT14
246#define TPPoll_StopHCCA BIT15
247#define TPPoll_SHIFT 8
248
249 PSR = 0x0ff,
250#define PSR_GEN 0x0
251#define PSR_CPU 0x1
252 CPU_GEN = 0x100,
253 BB_RESET = 0x101,
254#define CPU_CCK_LOOPBACK 0x00030000
255#define CPU_GEN_SYSTEM_RESET 0x00000001
256#define CPU_GEN_FIRMWARE_RESET 0x00000008
257#define CPU_GEN_BOOT_RDY 0x00000010
258#define CPU_GEN_FIRM_RDY 0x00000020
259#define CPU_GEN_PUT_CODE_OK 0x00000080
260#define CPU_GEN_BB_RST 0x00000100
261#define CPU_GEN_PWR_STB_CPU 0x00000004
262#define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF
263#define CPU_GEN_NO_LOOPBACK_SET 0x00080000
264#define CPU_GEN_GPIO_UART 0x00007000
265
266 LED1Cfg = 0x154,
267 LED0Cfg = 0x155,
268
269 AcmAvg = 0x170,
270 AcmHwCtrl = 0x171,
271#define AcmHw_HwEn BIT0
272#define AcmHw_BeqEn BIT1
273#define AcmHw_ViqEn BIT2
274#define AcmHw_VoqEn BIT3
275#define AcmHw_BeqStatus BIT4
276#define AcmHw_ViqStatus BIT5
277#define AcmHw_VoqStatus BIT6
278 AcmFwCtrl = 0x172,
279#define AcmFw_BeqStatus BIT0
280#define AcmFw_ViqStatus BIT1
281#define AcmFw_VoqStatus BIT2
282 VOAdmTime = 0x174,
283 VIAdmTime = 0x178,
284 BEAdmTime = 0x17C,
285 RQPN1 = 0x180,
286 RQPN2 = 0x184,
287 RQPN3 = 0x188,
288 QPRR = 0x1E0,
289 QPNR = 0x1F0,
290 BQDA = 0x200,
291 HQDA = 0x204,
292 CQDA = 0x208,
293 MQDA = 0x20C,
294 HCCAQDA = 0x210,
295 VOQDA = 0x214,
296 VIQDA = 0x218,
297 BEQDA = 0x21C,
298 BKQDA = 0x220,
299 RCQDA = 0x224,
300 RDQDA = 0x228,
301
302 MAR0 = 0x240,
303 MAR4 = 0x244,
304
305 CCX_PERIOD = 0x250,
306 CLM_RESULT = 0x251,
307 NHM_PERIOD = 0x252,
308
309 NHM_THRESHOLD0 = 0x253,
310 NHM_THRESHOLD1 = 0x254,
311 NHM_THRESHOLD2 = 0x255,
312 NHM_THRESHOLD3 = 0x256,
313 NHM_THRESHOLD4 = 0x257,
314 NHM_THRESHOLD5 = 0x258,
315 NHM_THRESHOLD6 = 0x259,
316
317 MCTRL = 0x25A,
318
319 NHM_RPI_COUNTER0 = 0x264,
320 NHM_RPI_COUNTER1 = 0x265,
321 NHM_RPI_COUNTER2 = 0x266,
322 NHM_RPI_COUNTER3 = 0x267,
323 NHM_RPI_COUNTER4 = 0x268,
324 NHM_RPI_COUNTER5 = 0x269,
325 NHM_RPI_COUNTER6 = 0x26A,
326 NHM_RPI_COUNTER7 = 0x26B,
327 WFCRC0 = 0x2f0,
328 WFCRC1 = 0x2f4,
329 WFCRC2 = 0x2f8,
330
331 BW_OPMODE = 0x300,
332#define BW_OPMODE_11J BIT0
333#define BW_OPMODE_5G BIT1
334#define BW_OPMODE_20MHZ BIT2
335 IC_VERRSION = 0x301,
336 MSR = 0x303,
337#define MSR_LINK_MASK ((1<<0)|(1<<1))
338#define MSR_LINK_MANAGED 2
339#define MSR_LINK_NONE 0
340#define MSR_LINK_SHIFT 0
341#define MSR_LINK_ADHOC 1
342#define MSR_LINK_MASTER 3
343#define MSR_LINK_ENEDCA (1<<4)
344
345#define MSR_NOLINK 0x00
346#define MSR_ADHOC 0x01
347#define MSR_INFRA 0x02
348#define MSR_AP 0x03
349
350 RETRY_LIMIT = 0x304,
351#define RETRY_LIMIT_SHORT_SHIFT 8
352#define RETRY_LIMIT_LONG_SHIFT 0
353 TSFR = 0x308,
354 RRSR = 0x310,
355#define RRSR_RSC_OFFSET 21
356#define RRSR_SHORT_OFFSET 23
357#define RRSR_RSC_DUPLICATE 0x600000
358#define RRSR_RSC_UPSUBCHNL 0x400000
359#define RRSR_RSC_LOWSUBCHNL 0x200000
360#define RRSR_SHORT 0x800000
361#define RRSR_1M BIT0
362#define RRSR_2M BIT1
363#define RRSR_5_5M BIT2
364#define RRSR_11M BIT3
365#define RRSR_6M BIT4
366#define RRSR_9M BIT5
367#define RRSR_12M BIT6
368#define RRSR_18M BIT7
369#define RRSR_24M BIT8
370#define RRSR_36M BIT9
371#define RRSR_48M BIT10
372#define RRSR_54M BIT11
373#define RRSR_MCS0 BIT12
374#define RRSR_MCS1 BIT13
375#define RRSR_MCS2 BIT14
376#define RRSR_MCS3 BIT15
377#define RRSR_MCS4 BIT16
378#define RRSR_MCS5 BIT17
379#define RRSR_MCS6 BIT18
380#define RRSR_MCS7 BIT19
381#define BRSR_AckShortPmb BIT23
382 UFWP = 0x318,
383 RATR0 = 0x320,
384#define RATR_1M 0x00000001
385#define RATR_2M 0x00000002
386#define RATR_55M 0x00000004
387#define RATR_11M 0x00000008
388#define RATR_6M 0x00000010
389#define RATR_9M 0x00000020
390#define RATR_12M 0x00000040
391#define RATR_18M 0x00000080
392#define RATR_24M 0x00000100
393#define RATR_36M 0x00000200
394#define RATR_48M 0x00000400
395#define RATR_54M 0x00000800
396#define RATR_MCS0 0x00001000
397#define RATR_MCS1 0x00002000
398#define RATR_MCS2 0x00004000
399#define RATR_MCS3 0x00008000
400#define RATR_MCS4 0x00010000
401#define RATR_MCS5 0x00020000
402#define RATR_MCS6 0x00040000
403#define RATR_MCS7 0x00080000
404#define RATR_MCS8 0x00100000
405#define RATR_MCS9 0x00200000
406#define RATR_MCS10 0x00400000
407#define RATR_MCS11 0x00800000
408#define RATR_MCS12 0x01000000
409#define RATR_MCS13 0x02000000
410#define RATR_MCS14 0x04000000
411#define RATR_MCS15 0x08000000
412#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M)
413#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M | \
414 RATR_24M | RATR_36M | RATR_48M | RATR_54M)
415#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \
416 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \
417 RATR_MCS6 | RATR_MCS7)
418#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \
419 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \
420 RATR_MCS14|RATR_MCS15)
421
422
423 DRIVER_RSSI = 0x32c,
424 MCS_TXAGC = 0x340,
425 CCK_TXAGC = 0x348,
426 MacBlkCtrl = 0x403,
427
428}
429;
430
431#define GPI 0x108
432#define GPO 0x109
433#define GPE 0x10a
434
435#define HWSET_MAX_SIZE_92S 128
436
437#define ANAPAR_FOR_8192PciE 0x17
438
439#endif
440
