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15#if defined(CONFIG_SERIAL_TXX9_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
16#define SUPPORT_SYSRQ
17#endif
18
19#include <linux/module.h>
20#include <linux/ioport.h>
21#include <linux/init.h>
22#include <linux/console.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/pci.h>
26#include <linux/serial_core.h>
27#include <linux/serial.h>
28#include <linux/tty.h>
29#include <linux/tty_flip.h>
30
31#include <asm/io.h>
32
33static char *serial_version = "1.11";
34static char *serial_name = "TX39/49 Serial driver";
35
36#define PASS_LIMIT 256
37
38#if !defined(CONFIG_SERIAL_TXX9_STDSERIAL)
39
40#define TXX9_TTY_NAME "ttyTX"
41#define TXX9_TTY_MINOR_START 196
42#define TXX9_TTY_MAJOR 204
43#else
44
45#define TXX9_TTY_NAME "ttyS"
46#define TXX9_TTY_MINOR_START 64
47#define TXX9_TTY_MAJOR TTY_MAJOR
48#endif
49
50
51#define UPF_TXX9_HAVE_CTS_LINE UPF_BUGGY_UART
52#define UPF_TXX9_USE_SCLK UPF_MAGIC_MULTIPLIER
53
54#ifdef CONFIG_PCI
55
56#define ENABLE_SERIAL_TXX9_PCI
57#endif
58
59
60
61
62#define UART_NR CONFIG_SERIAL_TXX9_NR_UARTS
63
64struct uart_txx9_port {
65 struct uart_port port;
66
67};
68
69#define TXX9_REGION_SIZE 0x24
70
71
72#define TXX9_SILCR 0x00
73#define TXX9_SIDICR 0x04
74#define TXX9_SIDISR 0x08
75#define TXX9_SICISR 0x0c
76#define TXX9_SIFCR 0x10
77#define TXX9_SIFLCR 0x14
78#define TXX9_SIBGR 0x18
79#define TXX9_SITFIFO 0x1c
80#define TXX9_SIRFIFO 0x20
81
82
83#define TXX9_SILCR_SCS_MASK 0x00000060
84#define TXX9_SILCR_SCS_IMCLK 0x00000000
85#define TXX9_SILCR_SCS_IMCLK_BG 0x00000020
86#define TXX9_SILCR_SCS_SCLK 0x00000040
87#define TXX9_SILCR_SCS_SCLK_BG 0x00000060
88#define TXX9_SILCR_UEPS 0x00000010
89#define TXX9_SILCR_UPEN 0x00000008
90#define TXX9_SILCR_USBL_MASK 0x00000004
91#define TXX9_SILCR_USBL_1BIT 0x00000000
92#define TXX9_SILCR_USBL_2BIT 0x00000004
93#define TXX9_SILCR_UMODE_MASK 0x00000003
94#define TXX9_SILCR_UMODE_8BIT 0x00000000
95#define TXX9_SILCR_UMODE_7BIT 0x00000001
96
97
98#define TXX9_SIDICR_TDE 0x00008000
99#define TXX9_SIDICR_RDE 0x00004000
100#define TXX9_SIDICR_TIE 0x00002000
101#define TXX9_SIDICR_RIE 0x00001000
102#define TXX9_SIDICR_SPIE 0x00000800
103#define TXX9_SIDICR_CTSAC 0x00000600
104#define TXX9_SIDICR_STIE_MASK 0x0000003f
105#define TXX9_SIDICR_STIE_OERS 0x00000020
106#define TXX9_SIDICR_STIE_CTSS 0x00000010
107#define TXX9_SIDICR_STIE_RBRKD 0x00000008
108#define TXX9_SIDICR_STIE_TRDY 0x00000004
109#define TXX9_SIDICR_STIE_TXALS 0x00000002
110#define TXX9_SIDICR_STIE_UBRKD 0x00000001
111
112
113#define TXX9_SIDISR_UBRK 0x00008000
114#define TXX9_SIDISR_UVALID 0x00004000
115#define TXX9_SIDISR_UFER 0x00002000
116#define TXX9_SIDISR_UPER 0x00001000
117#define TXX9_SIDISR_UOER 0x00000800
118#define TXX9_SIDISR_ERI 0x00000400
119#define TXX9_SIDISR_TOUT 0x00000200
120#define TXX9_SIDISR_TDIS 0x00000100
121#define TXX9_SIDISR_RDIS 0x00000080
122#define TXX9_SIDISR_STIS 0x00000040
123#define TXX9_SIDISR_RFDN_MASK 0x0000001f
124
125
126#define TXX9_SICISR_OERS 0x00000020
127#define TXX9_SICISR_CTSS 0x00000010
128#define TXX9_SICISR_RBRKD 0x00000008
129#define TXX9_SICISR_TRDY 0x00000004
130#define TXX9_SICISR_TXALS 0x00000002
131#define TXX9_SICISR_UBRKD 0x00000001
132
133
134#define TXX9_SIFCR_SWRST 0x00008000
135#define TXX9_SIFCR_RDIL_MASK 0x00000180
136#define TXX9_SIFCR_RDIL_1 0x00000000
137#define TXX9_SIFCR_RDIL_4 0x00000080
138#define TXX9_SIFCR_RDIL_8 0x00000100
139#define TXX9_SIFCR_RDIL_12 0x00000180
140#define TXX9_SIFCR_RDIL_MAX 0x00000180
141#define TXX9_SIFCR_TDIL_MASK 0x00000018
142#define TXX9_SIFCR_TDIL_1 0x00000000
143#define TXX9_SIFCR_TDIL_4 0x00000001
144#define TXX9_SIFCR_TDIL_8 0x00000010
145#define TXX9_SIFCR_TDIL_MAX 0x00000010
146#define TXX9_SIFCR_TFRST 0x00000004
147#define TXX9_SIFCR_RFRST 0x00000002
148#define TXX9_SIFCR_FRSTE 0x00000001
149#define TXX9_SIO_TX_FIFO 8
150#define TXX9_SIO_RX_FIFO 16
151
152
153#define TXX9_SIFLCR_RCS 0x00001000
154#define TXX9_SIFLCR_TES 0x00000800
155#define TXX9_SIFLCR_RTSSC 0x00000200
156#define TXX9_SIFLCR_RSDE 0x00000100
157#define TXX9_SIFLCR_TSDE 0x00000080
158#define TXX9_SIFLCR_RTSTL_MASK 0x0000001e
159#define TXX9_SIFLCR_RTSTL_MAX 0x0000001e
160#define TXX9_SIFLCR_TBRK 0x00000001
161
162
163#define TXX9_SIBGR_BCLK_MASK 0x00000300
164#define TXX9_SIBGR_BCLK_T0 0x00000000
165#define TXX9_SIBGR_BCLK_T2 0x00000100
166#define TXX9_SIBGR_BCLK_T4 0x00000200
167#define TXX9_SIBGR_BCLK_T6 0x00000300
168#define TXX9_SIBGR_BRD_MASK 0x000000ff
169
170static inline unsigned int sio_in(struct uart_txx9_port *up, int offset)
171{
172 switch (up->port.iotype) {
173 default:
174 return __raw_readl(up->port.membase + offset);
175 case UPIO_PORT:
176 return inl(up->port.iobase + offset);
177 }
178}
179
180static inline void
181sio_out(struct uart_txx9_port *up, int offset, int value)
182{
183 switch (up->port.iotype) {
184 default:
185 __raw_writel(value, up->port.membase + offset);
186 break;
187 case UPIO_PORT:
188 outl(value, up->port.iobase + offset);
189 break;
190 }
191}
192
193static inline void
194sio_mask(struct uart_txx9_port *up, int offset, unsigned int value)
195{
196 sio_out(up, offset, sio_in(up, offset) & ~value);
197}
198static inline void
199sio_set(struct uart_txx9_port *up, int offset, unsigned int value)
200{
201 sio_out(up, offset, sio_in(up, offset) | value);
202}
203
204static inline void
205sio_quot_set(struct uart_txx9_port *up, int quot)
206{
207 quot >>= 1;
208 if (quot < 256)
209 sio_out(up, TXX9_SIBGR, quot | TXX9_SIBGR_BCLK_T0);
210 else if (quot < (256 << 2))
211 sio_out(up, TXX9_SIBGR, (quot >> 2) | TXX9_SIBGR_BCLK_T2);
212 else if (quot < (256 << 4))
213 sio_out(up, TXX9_SIBGR, (quot >> 4) | TXX9_SIBGR_BCLK_T4);
214 else if (quot < (256 << 6))
215 sio_out(up, TXX9_SIBGR, (quot >> 6) | TXX9_SIBGR_BCLK_T6);
216 else
217 sio_out(up, TXX9_SIBGR, 0xff | TXX9_SIBGR_BCLK_T6);
218}
219
220static struct uart_txx9_port *to_uart_txx9_port(struct uart_port *port)
221{
222 return container_of(port, struct uart_txx9_port, port);
223}
224
225static void serial_txx9_stop_tx(struct uart_port *port)
226{
227 struct uart_txx9_port *up = to_uart_txx9_port(port);
228 sio_mask(up, TXX9_SIDICR, TXX9_SIDICR_TIE);
229}
230
231static void serial_txx9_start_tx(struct uart_port *port)
232{
233 struct uart_txx9_port *up = to_uart_txx9_port(port);
234 sio_set(up, TXX9_SIDICR, TXX9_SIDICR_TIE);
235}
236
237static void serial_txx9_stop_rx(struct uart_port *port)
238{
239 struct uart_txx9_port *up = to_uart_txx9_port(port);
240 up->port.read_status_mask &= ~TXX9_SIDISR_RDIS;
241}
242
243static void serial_txx9_initialize(struct uart_port *port)
244{
245 struct uart_txx9_port *up = to_uart_txx9_port(port);
246 unsigned int tmout = 10000;
247
248 sio_out(up, TXX9_SIFCR, TXX9_SIFCR_SWRST);
249
250
251 udelay(1);
252 while ((sio_in(up, TXX9_SIFCR) & TXX9_SIFCR_SWRST) && --tmout)
253 udelay(1);
254
255 sio_set(up, TXX9_SIFCR,
256 TXX9_SIFCR_TDIL_MAX | TXX9_SIFCR_RDIL_1);
257
258 sio_out(up, TXX9_SILCR,
259 TXX9_SILCR_UMODE_8BIT | TXX9_SILCR_USBL_1BIT |
260 ((up->port.flags & UPF_TXX9_USE_SCLK) ?
261 TXX9_SILCR_SCS_SCLK_BG : TXX9_SILCR_SCS_IMCLK_BG));
262 sio_quot_set(up, uart_get_divisor(port, 9600));
263 sio_out(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSTL_MAX );
264 sio_out(up, TXX9_SIDICR, 0);
265}
266
267static inline void
268receive_chars(struct uart_txx9_port *up, unsigned int *status)
269{
270 unsigned char ch;
271 unsigned int disr = *status;
272 int max_count = 256;
273 char flag;
274 unsigned int next_ignore_status_mask;
275
276 do {
277 ch = sio_in(up, TXX9_SIRFIFO);
278 flag = TTY_NORMAL;
279 up->port.icount.rx++;
280
281
282 next_ignore_status_mask =
283 up->port.ignore_status_mask & ~TXX9_SIDISR_RFDN_MASK;
284 if (unlikely(disr & (TXX9_SIDISR_UBRK | TXX9_SIDISR_UPER |
285 TXX9_SIDISR_UFER | TXX9_SIDISR_UOER))) {
286
287
288
289 if (disr & TXX9_SIDISR_UBRK) {
290 disr &= ~(TXX9_SIDISR_UFER | TXX9_SIDISR_UPER);
291 up->port.icount.brk++;
292
293
294
295
296
297
298 if (uart_handle_break(&up->port))
299 goto ignore_char;
300 } else if (disr & TXX9_SIDISR_UPER)
301 up->port.icount.parity++;
302 else if (disr & TXX9_SIDISR_UFER)
303 up->port.icount.frame++;
304 if (disr & TXX9_SIDISR_UOER) {
305 up->port.icount.overrun++;
306
307
308
309
310
311
312 next_ignore_status_mask |=
313 TXX9_SIDISR_RFDN_MASK;
314 }
315
316
317
318
319 disr &= up->port.read_status_mask;
320
321 if (disr & TXX9_SIDISR_UBRK) {
322 flag = TTY_BREAK;
323 } else if (disr & TXX9_SIDISR_UPER)
324 flag = TTY_PARITY;
325 else if (disr & TXX9_SIDISR_UFER)
326 flag = TTY_FRAME;
327 }
328 if (uart_handle_sysrq_char(&up->port, ch))
329 goto ignore_char;
330
331 uart_insert_char(&up->port, disr, TXX9_SIDISR_UOER, ch, flag);
332
333 ignore_char:
334 up->port.ignore_status_mask = next_ignore_status_mask;
335 disr = sio_in(up, TXX9_SIDISR);
336 } while (!(disr & TXX9_SIDISR_UVALID) && (max_count-- > 0));
337 spin_unlock(&up->port.lock);
338 tty_flip_buffer_push(&up->port.state->port);
339 spin_lock(&up->port.lock);
340 *status = disr;
341}
342
343static inline void transmit_chars(struct uart_txx9_port *up)
344{
345 struct circ_buf *xmit = &up->port.state->xmit;
346 int count;
347
348 if (up->port.x_char) {
349 sio_out(up, TXX9_SITFIFO, up->port.x_char);
350 up->port.icount.tx++;
351 up->port.x_char = 0;
352 return;
353 }
354 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
355 serial_txx9_stop_tx(&up->port);
356 return;
357 }
358
359 count = TXX9_SIO_TX_FIFO;
360 do {
361 sio_out(up, TXX9_SITFIFO, xmit->buf[xmit->tail]);
362 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
363 up->port.icount.tx++;
364 if (uart_circ_empty(xmit))
365 break;
366 } while (--count > 0);
367
368 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
369 uart_write_wakeup(&up->port);
370
371 if (uart_circ_empty(xmit))
372 serial_txx9_stop_tx(&up->port);
373}
374
375static irqreturn_t serial_txx9_interrupt(int irq, void *dev_id)
376{
377 int pass_counter = 0;
378 struct uart_txx9_port *up = dev_id;
379 unsigned int status;
380
381 while (1) {
382 spin_lock(&up->port.lock);
383 status = sio_in(up, TXX9_SIDISR);
384 if (!(sio_in(up, TXX9_SIDICR) & TXX9_SIDICR_TIE))
385 status &= ~TXX9_SIDISR_TDIS;
386 if (!(status & (TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS |
387 TXX9_SIDISR_TOUT))) {
388 spin_unlock(&up->port.lock);
389 break;
390 }
391
392 if (status & TXX9_SIDISR_RDIS)
393 receive_chars(up, &status);
394 if (status & TXX9_SIDISR_TDIS)
395 transmit_chars(up);
396
397 sio_mask(up, TXX9_SIDISR,
398 TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS |
399 TXX9_SIDISR_TOUT);
400 spin_unlock(&up->port.lock);
401
402 if (pass_counter++ > PASS_LIMIT)
403 break;
404 }
405
406 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
407}
408
409static unsigned int serial_txx9_tx_empty(struct uart_port *port)
410{
411 struct uart_txx9_port *up = to_uart_txx9_port(port);
412 unsigned long flags;
413 unsigned int ret;
414
415 spin_lock_irqsave(&up->port.lock, flags);
416 ret = (sio_in(up, TXX9_SICISR) & TXX9_SICISR_TXALS) ? TIOCSER_TEMT : 0;
417 spin_unlock_irqrestore(&up->port.lock, flags);
418
419 return ret;
420}
421
422static unsigned int serial_txx9_get_mctrl(struct uart_port *port)
423{
424 struct uart_txx9_port *up = to_uart_txx9_port(port);
425 unsigned int ret;
426
427
428 ret = TIOCM_CAR | TIOCM_DSR;
429 ret |= (sio_in(up, TXX9_SIFLCR) & TXX9_SIFLCR_RTSSC) ? 0 : TIOCM_RTS;
430 ret |= (sio_in(up, TXX9_SICISR) & TXX9_SICISR_CTSS) ? 0 : TIOCM_CTS;
431
432 return ret;
433}
434
435static void serial_txx9_set_mctrl(struct uart_port *port, unsigned int mctrl)
436{
437 struct uart_txx9_port *up = to_uart_txx9_port(port);
438
439 if (mctrl & TIOCM_RTS)
440 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSSC);
441 else
442 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSSC);
443}
444
445static void serial_txx9_break_ctl(struct uart_port *port, int break_state)
446{
447 struct uart_txx9_port *up = to_uart_txx9_port(port);
448 unsigned long flags;
449
450 spin_lock_irqsave(&up->port.lock, flags);
451 if (break_state == -1)
452 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
453 else
454 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
455 spin_unlock_irqrestore(&up->port.lock, flags);
456}
457
458#if defined(CONFIG_SERIAL_TXX9_CONSOLE) || defined(CONFIG_CONSOLE_POLL)
459
460
461
462static void wait_for_xmitr(struct uart_txx9_port *up)
463{
464 unsigned int tmout = 10000;
465
466
467 while (--tmout &&
468 !(sio_in(up, TXX9_SICISR) & TXX9_SICISR_TXALS))
469 udelay(1);
470
471
472 if (up->port.flags & UPF_CONS_FLOW) {
473 tmout = 1000000;
474 while (--tmout &&
475 (sio_in(up, TXX9_SICISR) & TXX9_SICISR_CTSS))
476 udelay(1);
477 }
478}
479#endif
480
481#ifdef CONFIG_CONSOLE_POLL
482
483
484
485
486
487static int serial_txx9_get_poll_char(struct uart_port *port)
488{
489 unsigned int ier;
490 unsigned char c;
491 struct uart_txx9_port *up = to_uart_txx9_port(port);
492
493
494
495
496 ier = sio_in(up, TXX9_SIDICR);
497 sio_out(up, TXX9_SIDICR, 0);
498
499 while (sio_in(up, TXX9_SIDISR) & TXX9_SIDISR_UVALID)
500 ;
501
502 c = sio_in(up, TXX9_SIRFIFO);
503
504
505
506
507
508 sio_mask(up, TXX9_SIDISR, TXX9_SIDISR_RDIS);
509 sio_out(up, TXX9_SIDICR, ier);
510 return c;
511}
512
513
514static void serial_txx9_put_poll_char(struct uart_port *port, unsigned char c)
515{
516 unsigned int ier;
517 struct uart_txx9_port *up = to_uart_txx9_port(port);
518
519
520
521
522 ier = sio_in(up, TXX9_SIDICR);
523 sio_out(up, TXX9_SIDICR, 0);
524
525 wait_for_xmitr(up);
526
527
528
529 sio_out(up, TXX9_SITFIFO, c);
530
531
532
533
534
535 wait_for_xmitr(up);
536 sio_out(up, TXX9_SIDICR, ier);
537}
538
539#endif
540
541static int serial_txx9_startup(struct uart_port *port)
542{
543 struct uart_txx9_port *up = to_uart_txx9_port(port);
544 unsigned long flags;
545 int retval;
546
547
548
549
550
551 sio_set(up, TXX9_SIFCR,
552 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
553
554 sio_mask(up, TXX9_SIFCR,
555 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
556 sio_out(up, TXX9_SIDICR, 0);
557
558
559
560
561 sio_out(up, TXX9_SIDISR, 0);
562
563 retval = request_irq(up->port.irq, serial_txx9_interrupt,
564 IRQF_SHARED, "serial_txx9", up);
565 if (retval)
566 return retval;
567
568
569
570
571 spin_lock_irqsave(&up->port.lock, flags);
572 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
573 spin_unlock_irqrestore(&up->port.lock, flags);
574
575
576 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RSDE | TXX9_SIFLCR_TSDE);
577
578
579
580
581 sio_set(up, TXX9_SIDICR, TXX9_SIDICR_RIE);
582
583 return 0;
584}
585
586static void serial_txx9_shutdown(struct uart_port *port)
587{
588 struct uart_txx9_port *up = to_uart_txx9_port(port);
589 unsigned long flags;
590
591
592
593
594 sio_out(up, TXX9_SIDICR, 0);
595
596 spin_lock_irqsave(&up->port.lock, flags);
597 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
598 spin_unlock_irqrestore(&up->port.lock, flags);
599
600
601
602
603 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
604
605#ifdef CONFIG_SERIAL_TXX9_CONSOLE
606 if (up->port.cons && up->port.line == up->port.cons->index) {
607 free_irq(up->port.irq, up);
608 return;
609 }
610#endif
611
612 sio_set(up, TXX9_SIFCR,
613 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
614
615 sio_mask(up, TXX9_SIFCR,
616 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
617
618
619 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_RSDE | TXX9_SIFLCR_TSDE);
620
621 free_irq(up->port.irq, up);
622}
623
624static void
625serial_txx9_set_termios(struct uart_port *port, struct ktermios *termios,
626 struct ktermios *old)
627{
628 struct uart_txx9_port *up = to_uart_txx9_port(port);
629 unsigned int cval, fcr = 0;
630 unsigned long flags;
631 unsigned int baud, quot;
632
633
634
635
636 termios->c_cflag &= ~(HUPCL | CMSPAR);
637 termios->c_cflag |= CLOCAL;
638
639 cval = sio_in(up, TXX9_SILCR);
640
641 cval &= ~TXX9_SILCR_UMODE_MASK;
642 switch (termios->c_cflag & CSIZE) {
643 case CS7:
644 cval |= TXX9_SILCR_UMODE_7BIT;
645 break;
646 default:
647 case CS5:
648 case CS6:
649 case CS8:
650 cval |= TXX9_SILCR_UMODE_8BIT;
651 break;
652 }
653
654 cval &= ~TXX9_SILCR_USBL_MASK;
655 if (termios->c_cflag & CSTOPB)
656 cval |= TXX9_SILCR_USBL_2BIT;
657 else
658 cval |= TXX9_SILCR_USBL_1BIT;
659 cval &= ~(TXX9_SILCR_UPEN | TXX9_SILCR_UEPS);
660 if (termios->c_cflag & PARENB)
661 cval |= TXX9_SILCR_UPEN;
662 if (!(termios->c_cflag & PARODD))
663 cval |= TXX9_SILCR_UEPS;
664
665
666
667
668 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16/2);
669 quot = uart_get_divisor(port, baud);
670
671
672
673 fcr = TXX9_SIFCR_TDIL_MAX | TXX9_SIFCR_RDIL_1;
674
675
676
677
678
679 spin_lock_irqsave(&up->port.lock, flags);
680
681
682
683
684 uart_update_timeout(port, termios->c_cflag, baud);
685
686 up->port.read_status_mask = TXX9_SIDISR_UOER |
687 TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS;
688 if (termios->c_iflag & INPCK)
689 up->port.read_status_mask |= TXX9_SIDISR_UFER | TXX9_SIDISR_UPER;
690 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
691 up->port.read_status_mask |= TXX9_SIDISR_UBRK;
692
693
694
695
696 up->port.ignore_status_mask = 0;
697 if (termios->c_iflag & IGNPAR)
698 up->port.ignore_status_mask |= TXX9_SIDISR_UPER | TXX9_SIDISR_UFER;
699 if (termios->c_iflag & IGNBRK) {
700 up->port.ignore_status_mask |= TXX9_SIDISR_UBRK;
701
702
703
704
705 if (termios->c_iflag & IGNPAR)
706 up->port.ignore_status_mask |= TXX9_SIDISR_UOER;
707 }
708
709
710
711
712 if ((termios->c_cflag & CREAD) == 0)
713 up->port.ignore_status_mask |= TXX9_SIDISR_RDIS;
714
715
716 if ((termios->c_cflag & CRTSCTS) &&
717 (up->port.flags & UPF_TXX9_HAVE_CTS_LINE)) {
718 sio_set(up, TXX9_SIFLCR,
719 TXX9_SIFLCR_RCS | TXX9_SIFLCR_TES);
720 } else {
721 sio_mask(up, TXX9_SIFLCR,
722 TXX9_SIFLCR_RCS | TXX9_SIFLCR_TES);
723 }
724
725 sio_out(up, TXX9_SILCR, cval);
726 sio_quot_set(up, quot);
727 sio_out(up, TXX9_SIFCR, fcr);
728
729 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
730 spin_unlock_irqrestore(&up->port.lock, flags);
731}
732
733static void
734serial_txx9_pm(struct uart_port *port, unsigned int state,
735 unsigned int oldstate)
736{
737
738
739
740
741
742
743
744
745 if (state == 0 && oldstate != -1)
746 serial_txx9_initialize(port);
747}
748
749static int serial_txx9_request_resource(struct uart_txx9_port *up)
750{
751 unsigned int size = TXX9_REGION_SIZE;
752 int ret = 0;
753
754 switch (up->port.iotype) {
755 default:
756 if (!up->port.mapbase)
757 break;
758
759 if (!request_mem_region(up->port.mapbase, size, "serial_txx9")) {
760 ret = -EBUSY;
761 break;
762 }
763
764 if (up->port.flags & UPF_IOREMAP) {
765 up->port.membase = ioremap(up->port.mapbase, size);
766 if (!up->port.membase) {
767 release_mem_region(up->port.mapbase, size);
768 ret = -ENOMEM;
769 }
770 }
771 break;
772
773 case UPIO_PORT:
774 if (!request_region(up->port.iobase, size, "serial_txx9"))
775 ret = -EBUSY;
776 break;
777 }
778 return ret;
779}
780
781static void serial_txx9_release_resource(struct uart_txx9_port *up)
782{
783 unsigned int size = TXX9_REGION_SIZE;
784
785 switch (up->port.iotype) {
786 default:
787 if (!up->port.mapbase)
788 break;
789
790 if (up->port.flags & UPF_IOREMAP) {
791 iounmap(up->port.membase);
792 up->port.membase = NULL;
793 }
794
795 release_mem_region(up->port.mapbase, size);
796 break;
797
798 case UPIO_PORT:
799 release_region(up->port.iobase, size);
800 break;
801 }
802}
803
804static void serial_txx9_release_port(struct uart_port *port)
805{
806 struct uart_txx9_port *up = to_uart_txx9_port(port);
807 serial_txx9_release_resource(up);
808}
809
810static int serial_txx9_request_port(struct uart_port *port)
811{
812 struct uart_txx9_port *up = to_uart_txx9_port(port);
813 return serial_txx9_request_resource(up);
814}
815
816static void serial_txx9_config_port(struct uart_port *port, int uflags)
817{
818 struct uart_txx9_port *up = to_uart_txx9_port(port);
819 int ret;
820
821
822
823
824
825 ret = serial_txx9_request_resource(up);
826 if (ret < 0)
827 return;
828 port->type = PORT_TXX9;
829 up->port.fifosize = TXX9_SIO_TX_FIFO;
830
831#ifdef CONFIG_SERIAL_TXX9_CONSOLE
832 if (up->port.line == up->port.cons->index)
833 return;
834#endif
835 serial_txx9_initialize(port);
836}
837
838static const char *
839serial_txx9_type(struct uart_port *port)
840{
841 return "txx9";
842}
843
844static const struct uart_ops serial_txx9_pops = {
845 .tx_empty = serial_txx9_tx_empty,
846 .set_mctrl = serial_txx9_set_mctrl,
847 .get_mctrl = serial_txx9_get_mctrl,
848 .stop_tx = serial_txx9_stop_tx,
849 .start_tx = serial_txx9_start_tx,
850 .stop_rx = serial_txx9_stop_rx,
851 .break_ctl = serial_txx9_break_ctl,
852 .startup = serial_txx9_startup,
853 .shutdown = serial_txx9_shutdown,
854 .set_termios = serial_txx9_set_termios,
855 .pm = serial_txx9_pm,
856 .type = serial_txx9_type,
857 .release_port = serial_txx9_release_port,
858 .request_port = serial_txx9_request_port,
859 .config_port = serial_txx9_config_port,
860#ifdef CONFIG_CONSOLE_POLL
861 .poll_get_char = serial_txx9_get_poll_char,
862 .poll_put_char = serial_txx9_put_poll_char,
863#endif
864};
865
866static struct uart_txx9_port serial_txx9_ports[UART_NR];
867
868static void __init serial_txx9_register_ports(struct uart_driver *drv,
869 struct device *dev)
870{
871 int i;
872
873 for (i = 0; i < UART_NR; i++) {
874 struct uart_txx9_port *up = &serial_txx9_ports[i];
875
876 up->port.line = i;
877 up->port.ops = &serial_txx9_pops;
878 up->port.dev = dev;
879 if (up->port.iobase || up->port.mapbase)
880 uart_add_one_port(drv, &up->port);
881 }
882}
883
884#ifdef CONFIG_SERIAL_TXX9_CONSOLE
885
886static void serial_txx9_console_putchar(struct uart_port *port, int ch)
887{
888 struct uart_txx9_port *up = to_uart_txx9_port(port);
889
890 wait_for_xmitr(up);
891 sio_out(up, TXX9_SITFIFO, ch);
892}
893
894
895
896
897
898
899
900static void
901serial_txx9_console_write(struct console *co, const char *s, unsigned int count)
902{
903 struct uart_txx9_port *up = &serial_txx9_ports[co->index];
904 unsigned int ier, flcr;
905
906
907
908
909 ier = sio_in(up, TXX9_SIDICR);
910 sio_out(up, TXX9_SIDICR, 0);
911
912
913
914 flcr = sio_in(up, TXX9_SIFLCR);
915 if (!(up->port.flags & UPF_CONS_FLOW) && (flcr & TXX9_SIFLCR_TES))
916 sio_out(up, TXX9_SIFLCR, flcr & ~TXX9_SIFLCR_TES);
917
918 uart_console_write(&up->port, s, count, serial_txx9_console_putchar);
919
920
921
922
923
924 wait_for_xmitr(up);
925 sio_out(up, TXX9_SIFLCR, flcr);
926 sio_out(up, TXX9_SIDICR, ier);
927}
928
929static int __init serial_txx9_console_setup(struct console *co, char *options)
930{
931 struct uart_port *port;
932 struct uart_txx9_port *up;
933 int baud = 9600;
934 int bits = 8;
935 int parity = 'n';
936 int flow = 'n';
937
938
939
940
941
942
943 if (co->index >= UART_NR)
944 co->index = 0;
945 up = &serial_txx9_ports[co->index];
946 port = &up->port;
947 if (!port->ops)
948 return -ENODEV;
949
950 serial_txx9_initialize(&up->port);
951
952 if (options)
953 uart_parse_options(options, &baud, &parity, &bits, &flow);
954
955 return uart_set_options(port, co, baud, parity, bits, flow);
956}
957
958static struct uart_driver serial_txx9_reg;
959static struct console serial_txx9_console = {
960 .name = TXX9_TTY_NAME,
961 .write = serial_txx9_console_write,
962 .device = uart_console_device,
963 .setup = serial_txx9_console_setup,
964 .flags = CON_PRINTBUFFER,
965 .index = -1,
966 .data = &serial_txx9_reg,
967};
968
969static int __init serial_txx9_console_init(void)
970{
971 register_console(&serial_txx9_console);
972 return 0;
973}
974console_initcall(serial_txx9_console_init);
975
976#define SERIAL_TXX9_CONSOLE &serial_txx9_console
977#else
978#define SERIAL_TXX9_CONSOLE NULL
979#endif
980
981static struct uart_driver serial_txx9_reg = {
982 .owner = THIS_MODULE,
983 .driver_name = "serial_txx9",
984 .dev_name = TXX9_TTY_NAME,
985 .major = TXX9_TTY_MAJOR,
986 .minor = TXX9_TTY_MINOR_START,
987 .nr = UART_NR,
988 .cons = SERIAL_TXX9_CONSOLE,
989};
990
991int __init early_serial_txx9_setup(struct uart_port *port)
992{
993 if (port->line >= ARRAY_SIZE(serial_txx9_ports))
994 return -ENODEV;
995
996 serial_txx9_ports[port->line].port = *port;
997 serial_txx9_ports[port->line].port.ops = &serial_txx9_pops;
998 serial_txx9_ports[port->line].port.flags |=
999 UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
1000 return 0;
1001}
1002
1003static DEFINE_MUTEX(serial_txx9_mutex);
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016static int serial_txx9_register_port(struct uart_port *port)
1017{
1018 int i;
1019 struct uart_txx9_port *uart;
1020 int ret = -ENOSPC;
1021
1022 mutex_lock(&serial_txx9_mutex);
1023 for (i = 0; i < UART_NR; i++) {
1024 uart = &serial_txx9_ports[i];
1025 if (uart_match_port(&uart->port, port)) {
1026 uart_remove_one_port(&serial_txx9_reg, &uart->port);
1027 break;
1028 }
1029 }
1030 if (i == UART_NR) {
1031
1032 for (i = 0; i < UART_NR; i++) {
1033 uart = &serial_txx9_ports[i];
1034 if (!(uart->port.iobase || uart->port.mapbase))
1035 break;
1036 }
1037 }
1038 if (i < UART_NR) {
1039 uart->port.iobase = port->iobase;
1040 uart->port.membase = port->membase;
1041 uart->port.irq = port->irq;
1042 uart->port.uartclk = port->uartclk;
1043 uart->port.iotype = port->iotype;
1044 uart->port.flags = port->flags
1045 | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
1046 uart->port.mapbase = port->mapbase;
1047 if (port->dev)
1048 uart->port.dev = port->dev;
1049 ret = uart_add_one_port(&serial_txx9_reg, &uart->port);
1050 if (ret == 0)
1051 ret = uart->port.line;
1052 }
1053 mutex_unlock(&serial_txx9_mutex);
1054 return ret;
1055}
1056
1057
1058
1059
1060
1061
1062
1063
1064static void serial_txx9_unregister_port(int line)
1065{
1066 struct uart_txx9_port *uart = &serial_txx9_ports[line];
1067
1068 mutex_lock(&serial_txx9_mutex);
1069 uart_remove_one_port(&serial_txx9_reg, &uart->port);
1070 uart->port.flags = 0;
1071 uart->port.type = PORT_UNKNOWN;
1072 uart->port.iobase = 0;
1073 uart->port.mapbase = 0;
1074 uart->port.membase = NULL;
1075 uart->port.dev = NULL;
1076 mutex_unlock(&serial_txx9_mutex);
1077}
1078
1079
1080
1081
1082static int serial_txx9_probe(struct platform_device *dev)
1083{
1084 struct uart_port *p = dev_get_platdata(&dev->dev);
1085 struct uart_port port;
1086 int ret, i;
1087
1088 memset(&port, 0, sizeof(struct uart_port));
1089 for (i = 0; p && p->uartclk != 0; p++, i++) {
1090 port.iobase = p->iobase;
1091 port.membase = p->membase;
1092 port.irq = p->irq;
1093 port.uartclk = p->uartclk;
1094 port.iotype = p->iotype;
1095 port.flags = p->flags;
1096 port.mapbase = p->mapbase;
1097 port.dev = &dev->dev;
1098 ret = serial_txx9_register_port(&port);
1099 if (ret < 0) {
1100 dev_err(&dev->dev, "unable to register port at index %d "
1101 "(IO%lx MEM%llx IRQ%d): %d\n", i,
1102 p->iobase, (unsigned long long)p->mapbase,
1103 p->irq, ret);
1104 }
1105 }
1106 return 0;
1107}
1108
1109
1110
1111
1112static int serial_txx9_remove(struct platform_device *dev)
1113{
1114 int i;
1115
1116 for (i = 0; i < UART_NR; i++) {
1117 struct uart_txx9_port *up = &serial_txx9_ports[i];
1118
1119 if (up->port.dev == &dev->dev)
1120 serial_txx9_unregister_port(i);
1121 }
1122 return 0;
1123}
1124
1125#ifdef CONFIG_PM
1126static int serial_txx9_suspend(struct platform_device *dev, pm_message_t state)
1127{
1128 int i;
1129
1130 for (i = 0; i < UART_NR; i++) {
1131 struct uart_txx9_port *up = &serial_txx9_ports[i];
1132
1133 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1134 uart_suspend_port(&serial_txx9_reg, &up->port);
1135 }
1136
1137 return 0;
1138}
1139
1140static int serial_txx9_resume(struct platform_device *dev)
1141{
1142 int i;
1143
1144 for (i = 0; i < UART_NR; i++) {
1145 struct uart_txx9_port *up = &serial_txx9_ports[i];
1146
1147 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1148 uart_resume_port(&serial_txx9_reg, &up->port);
1149 }
1150
1151 return 0;
1152}
1153#endif
1154
1155static struct platform_driver serial_txx9_plat_driver = {
1156 .probe = serial_txx9_probe,
1157 .remove = serial_txx9_remove,
1158#ifdef CONFIG_PM
1159 .suspend = serial_txx9_suspend,
1160 .resume = serial_txx9_resume,
1161#endif
1162 .driver = {
1163 .name = "serial_txx9",
1164 },
1165};
1166
1167#ifdef ENABLE_SERIAL_TXX9_PCI
1168
1169
1170
1171
1172static int
1173pciserial_txx9_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1174{
1175 struct uart_port port;
1176 int line;
1177 int rc;
1178
1179 rc = pci_enable_device(dev);
1180 if (rc)
1181 return rc;
1182
1183 memset(&port, 0, sizeof(port));
1184 port.ops = &serial_txx9_pops;
1185 port.flags |= UPF_TXX9_HAVE_CTS_LINE;
1186 port.uartclk = 66670000;
1187 port.irq = dev->irq;
1188 port.iotype = UPIO_PORT;
1189 port.iobase = pci_resource_start(dev, 1);
1190 port.dev = &dev->dev;
1191 line = serial_txx9_register_port(&port);
1192 if (line < 0) {
1193 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), line);
1194 pci_disable_device(dev);
1195 return line;
1196 }
1197 pci_set_drvdata(dev, &serial_txx9_ports[line]);
1198
1199 return 0;
1200}
1201
1202static void pciserial_txx9_remove_one(struct pci_dev *dev)
1203{
1204 struct uart_txx9_port *up = pci_get_drvdata(dev);
1205
1206 if (up) {
1207 serial_txx9_unregister_port(up->port.line);
1208 pci_disable_device(dev);
1209 }
1210}
1211
1212#ifdef CONFIG_PM
1213static int pciserial_txx9_suspend_one(struct pci_dev *dev, pm_message_t state)
1214{
1215 struct uart_txx9_port *up = pci_get_drvdata(dev);
1216
1217 if (up)
1218 uart_suspend_port(&serial_txx9_reg, &up->port);
1219 pci_save_state(dev);
1220 pci_set_power_state(dev, pci_choose_state(dev, state));
1221 return 0;
1222}
1223
1224static int pciserial_txx9_resume_one(struct pci_dev *dev)
1225{
1226 struct uart_txx9_port *up = pci_get_drvdata(dev);
1227
1228 pci_set_power_state(dev, PCI_D0);
1229 pci_restore_state(dev);
1230 if (up)
1231 uart_resume_port(&serial_txx9_reg, &up->port);
1232 return 0;
1233}
1234#endif
1235
1236static const struct pci_device_id serial_txx9_pci_tbl[] = {
1237 { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC) },
1238 { 0, }
1239};
1240
1241static struct pci_driver serial_txx9_pci_driver = {
1242 .name = "serial_txx9",
1243 .probe = pciserial_txx9_init_one,
1244 .remove = pciserial_txx9_remove_one,
1245#ifdef CONFIG_PM
1246 .suspend = pciserial_txx9_suspend_one,
1247 .resume = pciserial_txx9_resume_one,
1248#endif
1249 .id_table = serial_txx9_pci_tbl,
1250};
1251
1252MODULE_DEVICE_TABLE(pci, serial_txx9_pci_tbl);
1253#endif
1254
1255static struct platform_device *serial_txx9_plat_devs;
1256
1257static int __init serial_txx9_init(void)
1258{
1259 int ret;
1260
1261 printk(KERN_INFO "%s version %s\n", serial_name, serial_version);
1262
1263 ret = uart_register_driver(&serial_txx9_reg);
1264 if (ret)
1265 goto out;
1266
1267 serial_txx9_plat_devs = platform_device_alloc("serial_txx9", -1);
1268 if (!serial_txx9_plat_devs) {
1269 ret = -ENOMEM;
1270 goto unreg_uart_drv;
1271 }
1272
1273 ret = platform_device_add(serial_txx9_plat_devs);
1274 if (ret)
1275 goto put_dev;
1276
1277 serial_txx9_register_ports(&serial_txx9_reg,
1278 &serial_txx9_plat_devs->dev);
1279
1280 ret = platform_driver_register(&serial_txx9_plat_driver);
1281 if (ret)
1282 goto del_dev;
1283
1284#ifdef ENABLE_SERIAL_TXX9_PCI
1285 ret = pci_register_driver(&serial_txx9_pci_driver);
1286#endif
1287 if (ret == 0)
1288 goto out;
1289
1290 del_dev:
1291 platform_device_del(serial_txx9_plat_devs);
1292 put_dev:
1293 platform_device_put(serial_txx9_plat_devs);
1294 unreg_uart_drv:
1295 uart_unregister_driver(&serial_txx9_reg);
1296 out:
1297 return ret;
1298}
1299
1300static void __exit serial_txx9_exit(void)
1301{
1302 int i;
1303
1304#ifdef ENABLE_SERIAL_TXX9_PCI
1305 pci_unregister_driver(&serial_txx9_pci_driver);
1306#endif
1307 platform_driver_unregister(&serial_txx9_plat_driver);
1308 platform_device_unregister(serial_txx9_plat_devs);
1309 for (i = 0; i < UART_NR; i++) {
1310 struct uart_txx9_port *up = &serial_txx9_ports[i];
1311 if (up->port.iobase || up->port.mapbase)
1312 uart_remove_one_port(&serial_txx9_reg, &up->port);
1313 }
1314
1315 uart_unregister_driver(&serial_txx9_reg);
1316}
1317
1318module_init(serial_txx9_init);
1319module_exit(serial_txx9_exit);
1320
1321MODULE_LICENSE("GPL");
1322MODULE_DESCRIPTION("TX39/49 serial driver");
1323
1324MODULE_ALIAS_CHARDEV_MAJOR(TXX9_TTY_MAJOR);
1325
