1
2
3
4
5
6
7
8
9
10
11
12
13#ifndef __FIRMWARE_ZYNQMP_H__
14#define __FIRMWARE_ZYNQMP_H__
15
16#include <linux/device.h>
17
18#define ZYNQMP_PM_VERSION_MAJOR 1
19#define ZYNQMP_PM_VERSION_MINOR 0
20
21#define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
22 ZYNQMP_PM_VERSION_MINOR)
23
24#define ZYNQMP_TZ_VERSION_MAJOR 1
25#define ZYNQMP_TZ_VERSION_MINOR 0
26
27#define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
28 ZYNQMP_TZ_VERSION_MINOR)
29
30
31#define PM_SIP_SVC 0xC2000000
32
33
34#define PM_GET_TRUSTZONE_VERSION 0xa03
35#define PM_SET_SUSPEND_MODE 0xa02
36#define GET_CALLBACK_DATA 0xa01
37
38
39#define PM_LOAD_PDI 0x701
40
41
42#define PAYLOAD_ARG_CNT 4U
43
44
45#define CB_ARG_CNT 4
46
47
48#define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
49
50#define ZYNQMP_PM_MAX_LATENCY (~0U)
51#define ZYNQMP_PM_MAX_QOS 100U
52
53
54#define PM_USAGE_NO_MASTER 0x0U
55#define PM_USAGE_CURRENT_MASTER 0x1U
56#define PM_USAGE_OTHER_MASTER 0x2U
57#define PM_USAGE_BOTH_MASTERS (PM_USAGE_CURRENT_MASTER | \
58 PM_USAGE_OTHER_MASTER)
59
60#define GSS_NUM_REGS (4)
61
62
63#define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
64#define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
65#define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
66#define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
67
68
69#define PM_FEATURE_INVALID -1
70#define PM_FEATURE_UNCHECKED 0
71
72
73
74
75
76
77#define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
78#define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
79#define XILINX_ZYNQMP_PM_FPGA_AUTHENTICATION_DDR BIT(1)
80#define XILINX_ZYNQMP_PM_FPGA_AUTHENTICATION_OCM BIT(2)
81#define XILINX_ZYNQMP_PM_FPGA_ENCRYPTION_USERKEY BIT(3)
82#define XILINX_ZYNQMP_PM_FPGA_ENCRYPTION_DEVKEY BIT(4)
83
84enum pm_api_id {
85 PM_GET_API_VERSION = 1,
86 PM_SET_CONFIGURATION,
87 PM_GET_NODE_STATUS,
88 PM_GET_OPERATING_CHARACTERISTIC,
89 PM_REGISTER_NOTIFIER,
90
91 PM_REQUEST_SUSPEND,
92 PM_SELF_SUSPEND,
93 PM_FORCE_POWERDOWN,
94 PM_ABORT_SUSPEND,
95 PM_REQUEST_WAKEUP,
96 PM_SET_WAKEUP_SOURCE,
97 PM_SYSTEM_SHUTDOWN,
98
99 PM_REQUEST_NODE,
100 PM_RELEASE_NODE,
101 PM_SET_REQUIREMENT,
102 PM_SET_MAX_LATENCY,
103
104 PM_RESET_ASSERT,
105 PM_RESET_GET_STATUS,
106 PM_PM_INIT_FINALIZE = 21,
107 PM_FPGA_LOAD,
108 PM_FPGA_GET_STATUS,
109 PM_GET_CHIPID = 24,
110
111
112 PM_SECURE_SHA = 26,
113 PM_SECURE_RSA,
114
115 PM_PINCTRL_REQUEST,
116 PM_PINCTRL_RELEASE,
117 PM_PINCTRL_GET_FUNCTION,
118 PM_PINCTRL_SET_FUNCTION,
119 PM_PINCTRL_CONFIG_PARAM_GET,
120 PM_PINCTRL_CONFIG_PARAM_SET,
121 PM_IOCTL,
122 PM_QUERY_DATA,
123 PM_CLOCK_ENABLE,
124 PM_CLOCK_DISABLE,
125 PM_CLOCK_GETSTATE,
126 PM_CLOCK_SETDIVIDER,
127 PM_CLOCK_GETDIVIDER,
128 PM_CLOCK_SETRATE,
129 PM_CLOCK_GETRATE,
130 PM_CLOCK_SETPARENT,
131 PM_CLOCK_GETPARENT,
132 PM_SECURE_IMAGE,
133 PM_FPGA_READ = 46,
134 PM_SECURE_AES,
135
136 PM_REGISTER_ACCESS = 52,
137 PM_EFUSE_ACCESS = 53,
138 PM_FEATURE_CHECK = 63,
139 PM_API_MAX,
140};
141
142
143enum pm_ret_status {
144 XST_PM_SUCCESS = 0,
145 XST_PM_NO_FEATURE = 19,
146 XST_PM_INTERNAL = 2000,
147 XST_PM_CONFLICT,
148 XST_PM_NO_ACCESS,
149 XST_PM_INVALID_NODE,
150 XST_PM_DOUBLE_REQ,
151 XST_PM_ABORT_SUSPEND,
152 XST_PM_MULT_USER = 2008,
153};
154
155enum pm_ioctl_id {
156 IOCTL_GET_RPU_OPER_MODE,
157 IOCTL_SET_RPU_OPER_MODE,
158 IOCTL_RPU_BOOT_ADDR_CONFIG,
159 IOCTL_TCM_COMB_CONFIG,
160 IOCTL_SET_TAPDELAY_BYPASS,
161 IOCTL_SET_SGMII_MODE,
162 IOCTL_SD_DLL_RESET,
163 IOCTL_SET_SD_TAPDELAY,
164 IOCTL_SET_PLL_FRAC_MODE,
165 IOCTL_GET_PLL_FRAC_MODE,
166 IOCTL_SET_PLL_FRAC_DATA,
167 IOCTL_GET_PLL_FRAC_DATA,
168 IOCTL_WRITE_GGS,
169 IOCTL_READ_GGS,
170 IOCTL_WRITE_PGGS,
171 IOCTL_READ_PGGS,
172
173 IOCTL_ULPI_RESET,
174
175 IOCTL_SET_BOOT_HEALTH_STATUS,
176 IOCTL_AFI,
177
178 IOCTL_PROBE_COUNTER_READ,
179 IOCTL_PROBE_COUNTER_WRITE,
180 IOCTL_OSPI_MUX_SELECT,
181
182 IOCTL_USB_SET_STATE,
183
184 IOCTL_GET_LAST_RESET_REASON,
185
186 IOCTL_AIE_ISR_CLEAR,
187};
188
189enum pm_query_id {
190 PM_QID_INVALID,
191 PM_QID_CLOCK_GET_NAME,
192 PM_QID_CLOCK_GET_TOPOLOGY,
193 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
194 PM_QID_CLOCK_GET_PARENTS,
195 PM_QID_CLOCK_GET_ATTRIBUTES,
196 PM_QID_PINCTRL_GET_NUM_PINS,
197 PM_QID_PINCTRL_GET_NUM_FUNCTIONS,
198 PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS,
199 PM_QID_PINCTRL_GET_FUNCTION_NAME,
200 PM_QID_PINCTRL_GET_FUNCTION_GROUPS,
201 PM_QID_PINCTRL_GET_PIN_GROUPS,
202 PM_QID_CLOCK_GET_NUM_CLOCKS,
203 PM_QID_CLOCK_GET_MAX_DIVISOR,
204 PM_QID_PLD_GET_PARENT,
205};
206
207enum zynqmp_pm_reset_action {
208 PM_RESET_ACTION_RELEASE,
209 PM_RESET_ACTION_ASSERT,
210 PM_RESET_ACTION_PULSE,
211};
212
213enum zynqmp_pm_reset {
214 ZYNQMP_PM_RESET_START = 1000,
215 ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
216 ZYNQMP_PM_RESET_PCIE_BRIDGE,
217 ZYNQMP_PM_RESET_PCIE_CTRL,
218 ZYNQMP_PM_RESET_DP,
219 ZYNQMP_PM_RESET_SWDT_CRF,
220 ZYNQMP_PM_RESET_AFI_FM5,
221 ZYNQMP_PM_RESET_AFI_FM4,
222 ZYNQMP_PM_RESET_AFI_FM3,
223 ZYNQMP_PM_RESET_AFI_FM2,
224 ZYNQMP_PM_RESET_AFI_FM1,
225 ZYNQMP_PM_RESET_AFI_FM0,
226 ZYNQMP_PM_RESET_GDMA,
227 ZYNQMP_PM_RESET_GPU_PP1,
228 ZYNQMP_PM_RESET_GPU_PP0,
229 ZYNQMP_PM_RESET_GPU,
230 ZYNQMP_PM_RESET_GT,
231 ZYNQMP_PM_RESET_SATA,
232 ZYNQMP_PM_RESET_ACPU3_PWRON,
233 ZYNQMP_PM_RESET_ACPU2_PWRON,
234 ZYNQMP_PM_RESET_ACPU1_PWRON,
235 ZYNQMP_PM_RESET_ACPU0_PWRON,
236 ZYNQMP_PM_RESET_APU_L2,
237 ZYNQMP_PM_RESET_ACPU3,
238 ZYNQMP_PM_RESET_ACPU2,
239 ZYNQMP_PM_RESET_ACPU1,
240 ZYNQMP_PM_RESET_ACPU0,
241 ZYNQMP_PM_RESET_DDR,
242 ZYNQMP_PM_RESET_APM_FPD,
243 ZYNQMP_PM_RESET_SOFT,
244 ZYNQMP_PM_RESET_GEM0,
245 ZYNQMP_PM_RESET_GEM1,
246 ZYNQMP_PM_RESET_GEM2,
247 ZYNQMP_PM_RESET_GEM3,
248 ZYNQMP_PM_RESET_QSPI,
249 ZYNQMP_PM_RESET_UART0,
250 ZYNQMP_PM_RESET_UART1,
251 ZYNQMP_PM_RESET_SPI0,
252 ZYNQMP_PM_RESET_SPI1,
253 ZYNQMP_PM_RESET_SDIO0,
254 ZYNQMP_PM_RESET_SDIO1,
255 ZYNQMP_PM_RESET_CAN0,
256 ZYNQMP_PM_RESET_CAN1,
257 ZYNQMP_PM_RESET_I2C0,
258 ZYNQMP_PM_RESET_I2C1,
259 ZYNQMP_PM_RESET_TTC0,
260 ZYNQMP_PM_RESET_TTC1,
261 ZYNQMP_PM_RESET_TTC2,
262 ZYNQMP_PM_RESET_TTC3,
263 ZYNQMP_PM_RESET_SWDT_CRL,
264 ZYNQMP_PM_RESET_NAND,
265 ZYNQMP_PM_RESET_ADMA,
266 ZYNQMP_PM_RESET_GPIO,
267 ZYNQMP_PM_RESET_IOU_CC,
268 ZYNQMP_PM_RESET_TIMESTAMP,
269 ZYNQMP_PM_RESET_RPU_R50,
270 ZYNQMP_PM_RESET_RPU_R51,
271 ZYNQMP_PM_RESET_RPU_AMBA,
272 ZYNQMP_PM_RESET_OCM,
273 ZYNQMP_PM_RESET_RPU_PGE,
274 ZYNQMP_PM_RESET_USB0_CORERESET,
275 ZYNQMP_PM_RESET_USB1_CORERESET,
276 ZYNQMP_PM_RESET_USB0_HIBERRESET,
277 ZYNQMP_PM_RESET_USB1_HIBERRESET,
278 ZYNQMP_PM_RESET_USB0_APB,
279 ZYNQMP_PM_RESET_USB1_APB,
280 ZYNQMP_PM_RESET_IPI,
281 ZYNQMP_PM_RESET_APM_LPD,
282 ZYNQMP_PM_RESET_RTC,
283 ZYNQMP_PM_RESET_SYSMON,
284 ZYNQMP_PM_RESET_AFI_FM6,
285 ZYNQMP_PM_RESET_LPD_SWDT,
286 ZYNQMP_PM_RESET_FPD,
287 ZYNQMP_PM_RESET_RPU_DBG1,
288 ZYNQMP_PM_RESET_RPU_DBG0,
289 ZYNQMP_PM_RESET_DBG_LPD,
290 ZYNQMP_PM_RESET_DBG_FPD,
291 ZYNQMP_PM_RESET_APLL,
292 ZYNQMP_PM_RESET_DPLL,
293 ZYNQMP_PM_RESET_VPLL,
294 ZYNQMP_PM_RESET_IOPLL,
295 ZYNQMP_PM_RESET_RPLL,
296 ZYNQMP_PM_RESET_GPO3_PL_0,
297 ZYNQMP_PM_RESET_GPO3_PL_1,
298 ZYNQMP_PM_RESET_GPO3_PL_2,
299 ZYNQMP_PM_RESET_GPO3_PL_3,
300 ZYNQMP_PM_RESET_GPO3_PL_4,
301 ZYNQMP_PM_RESET_GPO3_PL_5,
302 ZYNQMP_PM_RESET_GPO3_PL_6,
303 ZYNQMP_PM_RESET_GPO3_PL_7,
304 ZYNQMP_PM_RESET_GPO3_PL_8,
305 ZYNQMP_PM_RESET_GPO3_PL_9,
306 ZYNQMP_PM_RESET_GPO3_PL_10,
307 ZYNQMP_PM_RESET_GPO3_PL_11,
308 ZYNQMP_PM_RESET_GPO3_PL_12,
309 ZYNQMP_PM_RESET_GPO3_PL_13,
310 ZYNQMP_PM_RESET_GPO3_PL_14,
311 ZYNQMP_PM_RESET_GPO3_PL_15,
312 ZYNQMP_PM_RESET_GPO3_PL_16,
313 ZYNQMP_PM_RESET_GPO3_PL_17,
314 ZYNQMP_PM_RESET_GPO3_PL_18,
315 ZYNQMP_PM_RESET_GPO3_PL_19,
316 ZYNQMP_PM_RESET_GPO3_PL_20,
317 ZYNQMP_PM_RESET_GPO3_PL_21,
318 ZYNQMP_PM_RESET_GPO3_PL_22,
319 ZYNQMP_PM_RESET_GPO3_PL_23,
320 ZYNQMP_PM_RESET_GPO3_PL_24,
321 ZYNQMP_PM_RESET_GPO3_PL_25,
322 ZYNQMP_PM_RESET_GPO3_PL_26,
323 ZYNQMP_PM_RESET_GPO3_PL_27,
324 ZYNQMP_PM_RESET_GPO3_PL_28,
325 ZYNQMP_PM_RESET_GPO3_PL_29,
326 ZYNQMP_PM_RESET_GPO3_PL_30,
327 ZYNQMP_PM_RESET_GPO3_PL_31,
328 ZYNQMP_PM_RESET_RPU_LS,
329 ZYNQMP_PM_RESET_PS_ONLY,
330 ZYNQMP_PM_RESET_PL,
331 ZYNQMP_PM_RESET_PS_PL0,
332 ZYNQMP_PM_RESET_PS_PL1,
333 ZYNQMP_PM_RESET_PS_PL2,
334 ZYNQMP_PM_RESET_PS_PL3,
335 ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
336};
337
338enum zynqmp_pm_abort_reason {
339 ZYNQMP_PM_ABORT_REASON_WAKEUP_EVENT = 100,
340 ZYNQMP_PM_ABORT_REASON_POWER_UNIT_BUSY,
341 ZYNQMP_PM_ABORT_REASON_NO_POWERDOWN,
342 ZYNQMP_PM_ABORT_REASON_UNKNOWN,
343};
344
345enum zynqmp_pm_suspend_reason {
346 SUSPEND_POWER_REQUEST = 201,
347 SUSPEND_ALERT,
348 SUSPEND_SYSTEM_SHUTDOWN,
349};
350
351enum zynqmp_pm_request_ack {
352 ZYNQMP_PM_REQUEST_ACK_NO = 1,
353 ZYNQMP_PM_REQUEST_ACK_BLOCKING,
354 ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING,
355};
356
357enum tap_delay_type {
358 PM_TAPDELAY_INPUT = 0,
359 PM_TAPDELAY_OUTPUT,
360};
361
362enum dll_reset_type {
363 PM_DLL_RESET_ASSERT,
364 PM_DLL_RESET_RELEASE,
365 PM_DLL_RESET_PULSE,
366};
367
368enum pm_pinctrl_config_param {
369 PM_PINCTRL_CONFIG_SLEW_RATE,
370 PM_PINCTRL_CONFIG_BIAS_STATUS,
371 PM_PINCTRL_CONFIG_PULL_CTRL,
372 PM_PINCTRL_CONFIG_SCHMITT_CMOS,
373 PM_PINCTRL_CONFIG_DRIVE_STRENGTH,
374 PM_PINCTRL_CONFIG_VOLTAGE_STATUS,
375 PM_PINCTRL_CONFIG_TRI_STATE,
376 PM_PINCTRL_CONFIG_MAX,
377};
378
379enum pm_pinctrl_slew_rate {
380 PM_PINCTRL_SLEW_RATE_FAST,
381 PM_PINCTRL_SLEW_RATE_SLOW,
382};
383
384enum pm_pinctrl_bias_status {
385 PM_PINCTRL_BIAS_DISABLE,
386 PM_PINCTRL_BIAS_ENABLE,
387};
388
389enum pm_pinctrl_pull_ctrl {
390 PM_PINCTRL_BIAS_PULL_DOWN,
391 PM_PINCTRL_BIAS_PULL_UP,
392};
393
394enum pm_pinctrl_schmitt_cmos {
395 PM_PINCTRL_INPUT_TYPE_CMOS,
396 PM_PINCTRL_INPUT_TYPE_SCHMITT,
397};
398
399enum zynqmp_pm_opchar_type {
400 ZYNQMP_PM_OPERATING_CHARACTERISTIC_POWER = 1,
401 ZYNQMP_PM_OPERATING_CHARACTERISTIC_ENERGY,
402 ZYNQMP_PM_OPERATING_CHARACTERISTIC_TEMPERATURE,
403};
404
405enum pm_pinctrl_drive_strength {
406 PM_PINCTRL_DRIVE_STRENGTH_2MA,
407 PM_PINCTRL_DRIVE_STRENGTH_4MA,
408 PM_PINCTRL_DRIVE_STRENGTH_8MA,
409 PM_PINCTRL_DRIVE_STRENGTH_12MA,
410};
411
412enum pm_pinctrl_tri_state {
413 PM_PINCTRL_TRI_STATE_DISABLE = 0,
414 PM_PINCTRL_TRI_STATE_ENABLE,
415};
416
417enum zynqmp_pm_shutdown_type {
418 ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN,
419 ZYNQMP_PM_SHUTDOWN_TYPE_RESET,
420 ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY,
421};
422
423enum zynqmp_pm_shutdown_subtype {
424 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM,
425 ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY,
426 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM,
427};
428
429enum rpu_oper_mode {
430 PM_RPU_MODE_LOCKSTEP,
431 PM_RPU_MODE_SPLIT,
432};
433
434enum rpu_boot_mem {
435 PM_RPU_BOOTMEM_LOVEC,
436 PM_RPU_BOOTMEM_HIVEC,
437};
438
439enum rpu_tcm_comb {
440 PM_RPU_TCM_SPLIT,
441 PM_RPU_TCM_COMB,
442};
443
444enum tap_delay_signal_type {
445 PM_TAPDELAY_NAND_DQS_IN,
446 PM_TAPDELAY_NAND_DQS_OUT,
447 PM_TAPDELAY_QSPI,
448 PM_TAPDELAY_MAX,
449};
450
451enum tap_delay_bypass_ctrl {
452 PM_TAPDELAY_BYPASS_DISABLE,
453 PM_TAPDELAY_BYPASS_ENABLE,
454};
455
456enum sgmii_mode {
457 PM_SGMII_DISABLE,
458 PM_SGMII_ENABLE,
459};
460
461enum pm_register_access_id {
462 CONFIG_REG_WRITE,
463 CONFIG_REG_READ,
464};
465
466enum ospi_mux_select_type {
467 PM_OSPI_MUX_SEL_DMA,
468 PM_OSPI_MUX_SEL_LINEAR,
469 PM_OSPI_MUX_GET_MODE,
470};
471
472enum pm_node_id {
473 NODE_UNKNOWN = 0,
474 NODE_APU,
475 NODE_APU_0,
476 NODE_APU_1,
477 NODE_APU_2,
478 NODE_APU_3,
479 NODE_RPU,
480 NODE_RPU_0,
481 NODE_RPU_1,
482 NODE_PLD,
483 NODE_FPD,
484 NODE_OCM_BANK_0,
485 NODE_OCM_BANK_1,
486 NODE_OCM_BANK_2,
487 NODE_OCM_BANK_3,
488 NODE_TCM_0_A,
489 NODE_TCM_0_B,
490 NODE_TCM_1_A,
491 NODE_TCM_1_B,
492 NODE_L2,
493 NODE_GPU_PP_0,
494 NODE_GPU_PP_1,
495 NODE_USB_0,
496 NODE_USB_1,
497 NODE_TTC_0,
498 NODE_TTC_1,
499 NODE_TTC_2,
500 NODE_TTC_3,
501 NODE_SATA,
502 NODE_ETH_0,
503 NODE_ETH_1,
504 NODE_ETH_2,
505 NODE_ETH_3,
506 NODE_UART_0,
507 NODE_UART_1,
508 NODE_SPI_0,
509 NODE_SPI_1,
510 NODE_I2C_0,
511 NODE_I2C_1,
512 NODE_SD_0,
513 NODE_SD_1,
514 NODE_DP,
515 NODE_GDMA,
516 NODE_ADMA,
517 NODE_NAND,
518 NODE_QSPI,
519 NODE_GPIO,
520 NODE_CAN_0,
521 NODE_CAN_1,
522 NODE_EXTERN,
523 NODE_APLL,
524 NODE_VPLL,
525 NODE_DPLL,
526 NODE_RPLL,
527 NODE_IOPLL,
528 NODE_DDR,
529 NODE_IPI_APU,
530 NODE_IPI_RPU_0,
531 NODE_GPU,
532 NODE_PCIE,
533 NODE_PCAP,
534 NODE_RTC,
535 NODE_LPD,
536 NODE_VCU,
537 NODE_IPI_RPU_1,
538 NODE_IPI_PL_0,
539 NODE_IPI_PL_1,
540 NODE_IPI_PL_2,
541 NODE_IPI_PL_3,
542 NODE_PL,
543 NODE_GEM_TSU,
544 NODE_SWDT_0,
545 NODE_SWDT_1,
546 NODE_CSU,
547 NODE_PJTAG,
548 NODE_TRACE,
549 NODE_TESTSCAN,
550 NODE_PMU,
551 NODE_MAX,
552};
553
554enum pm_reset_reason {
555 PM_RESET_REASON_EXT_POR = 0,
556 PM_RESET_REASON_SW_POR = 1,
557 PM_RESET_REASON_SLR_POR = 2,
558 PM_RESET_REASON_ERR_POR = 3,
559 PM_RESET_REASON_DAP_SRST = 7,
560 PM_RESET_REASON_ERR_SRST = 8,
561 PM_RESET_REASON_SW_SRST = 9,
562 PM_RESET_REASON_SLR_SRST = 10,
563};
564
565
566
567
568
569
570
571
572struct zynqmp_pm_query_data {
573 u32 qid;
574 u32 arg1;
575 u32 arg2;
576 u32 arg3;
577};
578
579struct zynqmp_eemi_ops {
580 int (*get_api_version)(u32 *version);
581 int (*get_chipid)(u32 *idcode, u32 *version);
582 int (*fpga_load)(const u64 address, const u32 size, const u32 flags);
583 int (*fpga_get_status)(u32 *value);
584 int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
585 int (*clock_enable)(u32 clock_id);
586 int (*clock_disable)(u32 clock_id);
587 int (*clock_getstate)(u32 clock_id, u32 *state);
588 int (*clock_setdivider)(u32 clock_id, u32 divider);
589 int (*clock_getdivider)(u32 clock_id, u32 *divider);
590 int (*clock_setrate)(u32 clock_id, u64 rate);
591 int (*clock_getrate)(u32 clock_id, u64 *rate);
592 int (*clock_setparent)(u32 clock_id, u32 parent_id);
593 int (*clock_getparent)(u32 clock_id, u32 *parent_id);
594 int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out);
595 int (*reset_assert)(const u32 reset,
596 const enum zynqmp_pm_reset_action assert_flag);
597 int (*reset_get_status)(const u32 reset, u32 *status);
598 int (*init_finalize)(void);
599 int (*set_suspend_mode)(u32 mode);
600 int (*request_node)(const u32 node,
601 const u32 capabilities,
602 const u32 qos,
603 const enum zynqmp_pm_request_ack ack);
604 int (*release_node)(const u32 node);
605 int (*set_requirement)(const u32 node,
606 const u32 capabilities,
607 const u32 qos,
608 const enum zynqmp_pm_request_ack ack);
609 int (*fpga_read)(const u32 reg_numframes, const u64 phys_address,
610 u32 readback_type, u32 *value);
611 int (*sha_hash)(const u64 address, const u32 size, const u32 flags);
612 int (*rsa)(const u64 address, const u32 size, const u32 flags);
613 int (*request_suspend)(const u32 node,
614 const enum zynqmp_pm_request_ack ack,
615 const u32 latency,
616 const u32 state);
617 int (*force_powerdown)(const u32 target,
618 const enum zynqmp_pm_request_ack ack);
619 int (*request_wakeup)(const u32 node,
620 const bool set_addr,
621 const u64 address,
622 const enum zynqmp_pm_request_ack ack);
623 int (*set_wakeup_source)(const u32 target,
624 const u32 wakeup_node,
625 const u32 enable);
626 int (*system_shutdown)(const u32 type, const u32 subtype);
627 int (*set_max_latency)(const u32 node, const u32 latency);
628 int (*set_configuration)(const u32 physical_addr);
629 int (*get_node_status)(const u32 node, u32 *const status,
630 u32 *const requirements, u32 *const usage);
631 int (*get_operating_characteristic)(const u32 node,
632 const enum zynqmp_pm_opchar_type
633 type, u32 *const result);
634 int (*pinctrl_request)(const u32 pin);
635 int (*pinctrl_release)(const u32 pin);
636 int (*pinctrl_get_function)(const u32 pin, u32 *id);
637 int (*pinctrl_set_function)(const u32 pin, const u32 id);
638 int (*pinctrl_get_config)(const u32 pin, const u32 param, u32 *value);
639 int (*pinctrl_set_config)(const u32 pin, const u32 param, u32 value);
640 int (*register_access)(u32 register_access_id, u32 address,
641 u32 mask, u32 value, u32 *out);
642 int (*aes)(const u64 address, u32 *out);
643 int (*efuse_access)(const u64 address, u32 *out);
644 int (*secure_image)(const u64 src_addr, u64 key_addr, u64 *dst);
645 int (*pdi_load)(const u32 src, const u64 address);
646};
647
648int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
649 u32 arg2, u32 arg3, u32 *ret_payload);
650
651int zynqmp_pm_ggs_init(struct kobject *parent_kobj);
652
653#if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
654const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void);
655int zynqmp_pm_get_last_reset_reason(u32 *reset_reason);
656#else
657static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
658{
659 return ERR_PTR(-ENODEV);
660}
661
662static inline int zynqmp_pm_get_last_reset_reason(u32 *reset_reason)
663{
664 return -ENODEV;
665}
666#endif
667
668#endif
669
