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16#ifndef __LINUX_SSP_H
17#define __LINUX_SSP_H
18
19#include <linux/list.h>
20#include <linux/io.h>
21#include <linux/of.h>
22
23
24
25
26
27
28
29
30#define SSCR0 (0x00)
31#define SSCR1 (0x04)
32#define SSSR (0x08)
33#define SSITR (0x0C)
34#define SSDR (0x10)
35
36#define SSTO (0x28)
37#define DDS_RATE (0x28)
38#define SSPSP (0x2C)
39#define SSTSA (0x30)
40#define SSRSA (0x34)
41#define SSTSS (0x38)
42#define SSACD (0x3C)
43#define SSACDD (0x40)
44
45
46#define SSCR0_DSS (0x0000000f)
47#define SSCR0_DataSize(x) ((x) - 1)
48#define SSCR0_FRF (0x00000030)
49#define SSCR0_Motorola (0x0 << 4)
50#define SSCR0_TI (0x1 << 4)
51#define SSCR0_National (0x2 << 4)
52#define SSCR0_ECS (1 << 6)
53#define SSCR0_SSE (1 << 7)
54#define SSCR0_SCR(x) ((x) << 8)
55
56
57#define SSCR0_EDSS (1 << 20)
58#define SSCR0_NCS (1 << 21)
59#define SSCR0_RIM (1 << 22)
60#define SSCR0_TUM (1 << 23)
61#define SSCR0_FRDC (0x07000000)
62#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24)
63#define SSCR0_FPCKE (1 << 29)
64#define SSCR0_ACS (1 << 30)
65#define SSCR0_MOD (1 << 31)
66
67
68#define SSCR1_RIE (1 << 0)
69#define SSCR1_TIE (1 << 1)
70#define SSCR1_LBM (1 << 2)
71#define SSCR1_SPO (1 << 3)
72#define SSCR1_SPH (1 << 4)
73#define SSCR1_MWDS (1 << 5)
74
75#define SSSR_ALT_FRM_MASK 3
76#define SSSR_TNF (1 << 2)
77#define SSSR_RNE (1 << 3)
78#define SSSR_BSY (1 << 4)
79#define SSSR_TFS (1 << 5)
80#define SSSR_RFS (1 << 6)
81#define SSSR_ROR (1 << 7)
82
83#define RX_THRESH_DFLT 8
84#define TX_THRESH_DFLT 8
85
86#define SSSR_TFL_MASK (0xf << 8)
87#define SSSR_RFL_MASK (0xf << 12)
88
89#define SSCR1_TFT (0x000003c0)
90#define SSCR1_TxTresh(x) (((x) - 1) << 6)
91#define SSCR1_RFT (0x00003c00)
92#define SSCR1_RxTresh(x) (((x) - 1) << 10)
93
94#define RX_THRESH_CE4100_DFLT 2
95#define TX_THRESH_CE4100_DFLT 2
96
97#define CE4100_SSSR_TFL_MASK (0x3 << 8)
98#define CE4100_SSSR_RFL_MASK (0x3 << 12)
99
100#define CE4100_SSCR1_TFT (0x000000c0)
101#define CE4100_SSCR1_TxTresh(x) (((x) - 1) << 6)
102#define CE4100_SSCR1_RFT (0x00000c00)
103#define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10)
104
105
106#define QUARK_X1000_SSCR0_DSS (0x1F << 0)
107#define QUARK_X1000_SSCR0_DataSize(x) ((x) - 1)
108#define QUARK_X1000_SSCR0_FRF (0x3 << 5)
109#define QUARK_X1000_SSCR0_Motorola (0x0 << 5)
110
111#define RX_THRESH_QUARK_X1000_DFLT 1
112#define TX_THRESH_QUARK_X1000_DFLT 16
113
114#define QUARK_X1000_SSSR_TFL_MASK (0x1F << 8)
115#define QUARK_X1000_SSSR_RFL_MASK (0x1F << 13)
116
117#define QUARK_X1000_SSCR1_TFT (0x1F << 6)
118#define QUARK_X1000_SSCR1_TxTresh(x) (((x) - 1) << 6)
119#define QUARK_X1000_SSCR1_RFT (0x1F << 11)
120#define QUARK_X1000_SSCR1_RxTresh(x) (((x) - 1) << 11)
121#define QUARK_X1000_SSCR1_STRF (1 << 17)
122#define QUARK_X1000_SSCR1_EFWR (1 << 16)
123
124
125#define SSCR0_TISSP (1 << 4)
126#define SSCR0_PSP (3 << 4)
127#define SSCR1_TTELP (1 << 31)
128#define SSCR1_TTE (1 << 30)
129#define SSCR1_EBCEI (1 << 29)
130#define SSCR1_SCFR (1 << 28)
131#define SSCR1_ECRA (1 << 27)
132#define SSCR1_ECRB (1 << 26)
133#define SSCR1_SCLKDIR (1 << 25)
134#define SSCR1_SFRMDIR (1 << 24)
135#define SSCR1_RWOT (1 << 23)
136#define SSCR1_TRAIL (1 << 22)
137#define SSCR1_TSRE (1 << 21)
138#define SSCR1_RSRE (1 << 20)
139#define SSCR1_TINTE (1 << 19)
140#define SSCR1_PINTE (1 << 18)
141#define SSCR1_IFS (1 << 16)
142#define SSCR1_STRF (1 << 15)
143#define SSCR1_EFWR (1 << 14)
144
145#define SSSR_BCE (1 << 23)
146#define SSSR_CSS (1 << 22)
147#define SSSR_TUR (1 << 21)
148#define SSSR_EOC (1 << 20)
149#define SSSR_TINT (1 << 19)
150#define SSSR_PINT (1 << 18)
151
152
153#define SSPSP_SCMODE(x) ((x) << 0)
154#define SSPSP_SFRMP (1 << 2)
155#define SSPSP_ETDS (1 << 3)
156#define SSPSP_STRTDLY(x) ((x) << 4)
157#define SSPSP_DMYSTRT(x) ((x) << 7)
158#define SSPSP_SFRMDLY(x) ((x) << 9)
159#define SSPSP_SFRMWDTH(x) ((x) << 16)
160#define SSPSP_DMYSTOP(x) ((x) << 23)
161#define SSPSP_FSRT (1 << 25)
162
163
164#define SSPSP_EDMYSTRT(x) ((x) << 26)
165#define SSPSP_EDMYSTOP(x) ((x) << 28)
166#define SSPSP_TIMING_MASK (0x7f8001f0)
167
168#define SSACD_SCDB (1 << 3)
169#define SSACD_ACPS(x) ((x) << 4)
170#define SSACD_ACDS(x) ((x) << 0)
171#define SSACD_ACDS_1 (0)
172#define SSACD_ACDS_2 (1)
173#define SSACD_ACDS_4 (2)
174#define SSACD_ACDS_8 (3)
175#define SSACD_ACDS_16 (4)
176#define SSACD_ACDS_32 (5)
177#define SSACD_SCDB_4X (0)
178#define SSACD_SCDB_1X (1)
179#define SSACD_SCDX8 (1 << 7)
180
181
182#define SSITF 0x44
183#define SSITF_TxLoThresh(x) (((x) - 1) << 8)
184#define SSITF_TxHiThresh(x) ((x) - 1)
185
186#define SSIRF 0x48
187#define SSIRF_RxThresh(x) ((x) - 1)
188
189enum pxa_ssp_type {
190 SSP_UNDEFINED = 0,
191 PXA25x_SSP,
192 PXA25x_NSSP,
193 PXA27x_SSP,
194 PXA3xx_SSP,
195 PXA168_SSP,
196 MMP2_SSP,
197 PXA910_SSP,
198 CE4100_SSP,
199 QUARK_X1000_SSP,
200 LPSS_LPT_SSP,
201 LPSS_BYT_SSP,
202 LPSS_BSW_SSP,
203 LPSS_SPT_SSP,
204 LPSS_BXT_SSP,
205 LPSS_CNL_SSP,
206};
207
208struct ssp_device {
209 struct platform_device *pdev;
210 struct list_head node;
211
212 struct clk *clk;
213 void __iomem *mmio_base;
214 unsigned long phys_base;
215
216 const char *label;
217 int port_id;
218 enum pxa_ssp_type type;
219 int use_count;
220 int irq;
221
222 struct device_node *of_node;
223};
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231
232static inline void pxa_ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val)
233{
234 __raw_writel(val, dev->mmio_base + reg);
235}
236
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242
243static inline u32 pxa_ssp_read_reg(struct ssp_device *dev, u32 reg)
244{
245 return __raw_readl(dev->mmio_base + reg);
246}
247
248#if IS_ENABLED(CONFIG_PXA_SSP)
249struct ssp_device *pxa_ssp_request(int port, const char *label);
250void pxa_ssp_free(struct ssp_device *);
251struct ssp_device *pxa_ssp_request_of(const struct device_node *of_node,
252 const char *label);
253#else
254static inline struct ssp_device *pxa_ssp_request(int port, const char *label)
255{
256 return NULL;
257}
258static inline struct ssp_device *pxa_ssp_request_of(const struct device_node *n,
259 const char *name)
260{
261 return NULL;
262}
263static inline void pxa_ssp_free(struct ssp_device *ssp) {}
264#endif
265
266#endif
267