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33#ifndef __ETH_COMMON__
34#define __ETH_COMMON__
35
36
37
38
39
40#define ETH_HSI_VER_MAJOR 3
41#define ETH_HSI_VER_MINOR 10
42
43#define ETH_HSI_VER_NO_PKT_LEN_TUNN 5
44
45#define ETH_CACHE_LINE_SIZE 64
46#define ETH_RX_CQE_GAP 32
47#define ETH_MAX_RAMROD_PER_CON 8
48#define ETH_TX_BD_PAGE_SIZE_BYTES 4096
49#define ETH_RX_BD_PAGE_SIZE_BYTES 4096
50#define ETH_RX_CQE_PAGE_SIZE_BYTES 4096
51#define ETH_RX_NUM_NEXT_PAGE_BDS 2
52
53#define ETH_MAX_TUNN_LSO_INNER_IPV4_OFFSET 253
54#define ETH_MAX_TUNN_LSO_INNER_IPV6_OFFSET 251
55
56#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1
57#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18
58#define ETH_TX_MAX_BDS_PER_LSO_PACKET 255
59#define ETH_TX_MAX_LSO_HDR_NBD 4
60#define ETH_TX_MIN_BDS_PER_LSO_PKT 3
61#define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3
62#define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2
63#define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2
64#define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 4 + 12 + 8))
65#define ETH_TX_MAX_LSO_HDR_BYTES 510
66#define ETH_TX_LSO_WINDOW_BDS_NUM (18 - 1)
67#define ETH_TX_LSO_WINDOW_MIN_LEN 9700
68#define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFE000
69#define ETH_TX_NUM_SAME_AS_LAST_ENTRIES 320
70#define ETH_TX_INACTIVE_SAME_AS_LAST 0xFFFF
71
72#define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
73#define ETH_NUM_STATISTIC_COUNTERS_DOUBLE_VF_ZONE \
74 (ETH_NUM_STATISTIC_COUNTERS - MAX_NUM_VFS / 2)
75#define ETH_NUM_STATISTIC_COUNTERS_QUAD_VF_ZONE \
76 (ETH_NUM_STATISTIC_COUNTERS - 3 * MAX_NUM_VFS / 4)
77
78
79#define ETH_RX_MAX_BUFF_PER_PKT 5
80#define ETH_RX_BD_THRESHOLD 12
81
82
83#define ETH_NUM_MAC_FILTERS 512
84#define ETH_NUM_VLAN_FILTERS 512
85
86
87#define ETH_MULTICAST_BIN_FROM_MAC_SEED 0
88#define ETH_MULTICAST_MAC_BINS 256
89#define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32)
90
91
92#define ETH_FILTER_RULES_COUNT 10
93#define ETH_RSS_IND_TABLE_ENTRIES_NUM 128
94#define ETH_RSS_KEY_SIZE_REGS 10
95#define ETH_RSS_ENGINE_NUM_K2 207
96#define ETH_RSS_ENGINE_NUM_BB 127
97
98
99#define ETH_TPA_MAX_AGGS_NUM 64
100#define ETH_TPA_CQE_START_LEN_LIST_SIZE ETH_RX_MAX_BUFF_PER_PKT
101#define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6
102#define ETH_TPA_CQE_END_LEN_LIST_SIZE 4
103
104
105#define ETH_CTL_FRAME_ETH_TYPE_NUM 4
106
107
108#define ETH_GFT_TRASHCAN_VPORT 0x1FF
109
110
111enum dest_port_mode {
112 DEST_PORT_PHY,
113 DEST_PORT_LOOPBACK,
114 DEST_PORT_PHY_LOOPBACK,
115 DEST_PORT_DROP,
116 MAX_DEST_PORT_MODE
117};
118
119
120enum eth_addr_type {
121 BROADCAST_ADDRESS,
122 MULTICAST_ADDRESS,
123 UNICAST_ADDRESS,
124 UNKNOWN_ADDRESS,
125 MAX_ETH_ADDR_TYPE
126};
127
128struct eth_tx_1st_bd_flags {
129 u8 bitfields;
130#define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1
131#define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 0
132#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1
133#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1
134#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1
135#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 2
136#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1
137#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 3
138#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1
139#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 4
140#define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1
141#define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 5
142#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1
143#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6
144#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1
145#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7
146};
147
148
149struct eth_tx_data_1st_bd {
150 __le16 vlan;
151 u8 nbds;
152 struct eth_tx_1st_bd_flags bd_flags;
153 __le16 bitfields;
154#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK 0x1
155#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT 0
156#define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1
157#define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1
158#define ETH_TX_DATA_1ST_BD_PKT_LEN_MASK 0x3FFF
159#define ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT 2
160};
161
162
163struct eth_tx_data_2nd_bd {
164 __le16 tunn_ip_size;
165 __le16 bitfields1;
166#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF
167#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
168#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3
169#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4
170#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK 0x3
171#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT 6
172#define ETH_TX_DATA_2ND_BD_START_BD_MASK 0x1
173#define ETH_TX_DATA_2ND_BD_START_BD_SHIFT 8
174#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3
175#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 9
176#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1
177#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 11
178#define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1
179#define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 12
180#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1
181#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 13
182#define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1
183#define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 14
184#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1
185#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 15
186 __le16 bitfields2;
187#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF
188#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0
189#define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7
190#define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13
191};
192
193
194struct eth_edpm_fw_data {
195 struct eth_tx_data_1st_bd data_1st_bd;
196 struct eth_tx_data_2nd_bd data_2nd_bd;
197 __le32 reserved;
198};
199
200
201struct eth_tunnel_parsing_flags {
202 u8 flags;
203#define ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK 0x3
204#define ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT 0
205#define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_MASK 0x1
206#define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_SHIFT 2
207#define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK 0x3
208#define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT 3
209#define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_MASK 0x1
210#define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_SHIFT 5
211#define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK 0x1
212#define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT 6
213#define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_MASK 0x1
214#define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_SHIFT 7
215};
216
217
218struct eth_pmd_flow_flags {
219 u8 flags;
220#define ETH_PMD_FLOW_FLAGS_VALID_MASK 0x1
221#define ETH_PMD_FLOW_FLAGS_VALID_SHIFT 0
222#define ETH_PMD_FLOW_FLAGS_TOGGLE_MASK 0x1
223#define ETH_PMD_FLOW_FLAGS_TOGGLE_SHIFT 1
224#define ETH_PMD_FLOW_FLAGS_RESERVED_MASK 0x3F
225#define ETH_PMD_FLOW_FLAGS_RESERVED_SHIFT 2
226};
227
228
229struct eth_fast_path_rx_reg_cqe {
230 u8 type;
231 u8 bitfields;
232#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7
233#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0
234#define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF
235#define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3
236#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1
237#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7
238 __le16 pkt_len;
239 struct parsing_and_err_flags pars_flags;
240 __le16 vlan_tag;
241 __le32 rss_hash;
242 __le16 len_on_first_bd;
243 u8 placement_offset;
244 struct eth_tunnel_parsing_flags tunnel_pars_flags;
245 u8 bd_num;
246 u8 reserved;
247 __le16 flow_id;
248 u8 reserved1[11];
249 struct eth_pmd_flow_flags pmd_flags;
250};
251
252
253struct eth_fast_path_rx_tpa_cont_cqe {
254 u8 type;
255 u8 tpa_agg_index;
256 __le16 len_list[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
257 u8 reserved;
258 u8 reserved1;
259 __le16 reserved2[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
260 u8 reserved3[3];
261 struct eth_pmd_flow_flags pmd_flags;
262};
263
264
265struct eth_fast_path_rx_tpa_end_cqe {
266 u8 type;
267 u8 tpa_agg_index;
268 __le16 total_packet_len;
269 u8 num_of_bds;
270 u8 end_reason;
271 __le16 num_of_coalesced_segs;
272 __le32 ts_delta;
273 __le16 len_list[ETH_TPA_CQE_END_LEN_LIST_SIZE];
274 __le16 reserved3[ETH_TPA_CQE_END_LEN_LIST_SIZE];
275 __le16 reserved1;
276 u8 reserved2;
277 struct eth_pmd_flow_flags pmd_flags;
278};
279
280
281struct eth_fast_path_rx_tpa_start_cqe {
282 u8 type;
283 u8 bitfields;
284#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7
285#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0
286#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF
287#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3
288#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1
289#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7
290 __le16 seg_len;
291 struct parsing_and_err_flags pars_flags;
292 __le16 vlan_tag;
293 __le32 rss_hash;
294 __le16 len_on_first_bd;
295 u8 placement_offset;
296 struct eth_tunnel_parsing_flags tunnel_pars_flags;
297 u8 tpa_agg_index;
298 u8 header_len;
299 __le16 ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE];
300 __le16 flow_id;
301 u8 reserved;
302 struct eth_pmd_flow_flags pmd_flags;
303};
304
305
306enum eth_l4_pseudo_checksum_mode {
307 ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH,
308 ETH_L4_PSEUDO_CSUM_ZERO_LENGTH,
309 MAX_ETH_L4_PSEUDO_CHECKSUM_MODE
310};
311
312struct eth_rx_bd {
313 struct regpair addr;
314};
315
316
317struct eth_slow_path_rx_cqe {
318 u8 type;
319 u8 ramrod_cmd_id;
320 u8 error_flag;
321 u8 reserved[25];
322 __le16 echo;
323 u8 reserved1;
324 struct eth_pmd_flow_flags pmd_flags;
325};
326
327
328union eth_rx_cqe {
329 struct eth_fast_path_rx_reg_cqe fast_path_regular;
330 struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start;
331 struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont;
332 struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end;
333 struct eth_slow_path_rx_cqe slow_path;
334};
335
336
337enum eth_rx_cqe_type {
338 ETH_RX_CQE_TYPE_UNUSED,
339 ETH_RX_CQE_TYPE_REGULAR,
340 ETH_RX_CQE_TYPE_SLOW_PATH,
341 ETH_RX_CQE_TYPE_TPA_START,
342 ETH_RX_CQE_TYPE_TPA_CONT,
343 ETH_RX_CQE_TYPE_TPA_END,
344 MAX_ETH_RX_CQE_TYPE
345};
346
347struct eth_rx_pmd_cqe {
348 union eth_rx_cqe cqe;
349 u8 reserved[ETH_RX_CQE_GAP];
350};
351
352enum eth_rx_tunn_type {
353 ETH_RX_NO_TUNN,
354 ETH_RX_TUNN_GENEVE,
355 ETH_RX_TUNN_GRE,
356 ETH_RX_TUNN_VXLAN,
357 MAX_ETH_RX_TUNN_TYPE
358};
359
360
361enum eth_tpa_end_reason {
362 ETH_AGG_END_UNUSED,
363 ETH_AGG_END_SP_UPDATE,
364 ETH_AGG_END_MAX_LEN,
365 ETH_AGG_END_LAST_SEG,
366 ETH_AGG_END_TIMEOUT,
367 ETH_AGG_END_NOT_CONSISTENT,
368 ETH_AGG_END_OUT_OF_ORDER,
369 ETH_AGG_END_NON_TPA_SEG,
370 MAX_ETH_TPA_END_REASON
371};
372
373
374struct eth_tx_1st_bd {
375 struct regpair addr;
376 __le16 nbytes;
377 struct eth_tx_data_1st_bd data;
378};
379
380
381struct eth_tx_2nd_bd {
382 struct regpair addr;
383 __le16 nbytes;
384 struct eth_tx_data_2nd_bd data;
385};
386
387
388struct eth_tx_data_3rd_bd {
389 __le16 lso_mss;
390 __le16 bitfields;
391#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF
392#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0
393#define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF
394#define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4
395#define ETH_TX_DATA_3RD_BD_START_BD_MASK 0x1
396#define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8
397#define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F
398#define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9
399 u8 tunn_l4_hdr_start_offset_w;
400 u8 tunn_hdr_size_w;
401};
402
403
404struct eth_tx_3rd_bd {
405 struct regpair addr;
406 __le16 nbytes;
407 struct eth_tx_data_3rd_bd data;
408};
409
410
411struct eth_tx_data_bd {
412 __le16 reserved0;
413 __le16 bitfields;
414#define ETH_TX_DATA_BD_RESERVED1_MASK 0xFF
415#define ETH_TX_DATA_BD_RESERVED1_SHIFT 0
416#define ETH_TX_DATA_BD_START_BD_MASK 0x1
417#define ETH_TX_DATA_BD_START_BD_SHIFT 8
418#define ETH_TX_DATA_BD_RESERVED2_MASK 0x7F
419#define ETH_TX_DATA_BD_RESERVED2_SHIFT 9
420 __le16 reserved3;
421};
422
423
424struct eth_tx_bd {
425 struct regpair addr;
426 __le16 nbytes;
427 struct eth_tx_data_bd data;
428};
429
430union eth_tx_bd_types {
431 struct eth_tx_1st_bd first_bd;
432 struct eth_tx_2nd_bd second_bd;
433 struct eth_tx_3rd_bd third_bd;
434 struct eth_tx_bd reg_bd;
435};
436
437
438enum eth_tx_tunn_type {
439 ETH_TX_TUNN_GENEVE,
440 ETH_TX_TUNN_TTAG,
441 ETH_TX_TUNN_GRE,
442 ETH_TX_TUNN_VXLAN,
443 MAX_ETH_TX_TUNN_TYPE
444};
445
446
447struct xstorm_eth_queue_zone {
448 struct coalescing_timeset int_coalescing_timeset;
449 u8 reserved[7];
450};
451
452
453struct eth_db_data {
454 u8 params;
455#define ETH_DB_DATA_DEST_MASK 0x3
456#define ETH_DB_DATA_DEST_SHIFT 0
457#define ETH_DB_DATA_AGG_CMD_MASK 0x3
458#define ETH_DB_DATA_AGG_CMD_SHIFT 2
459#define ETH_DB_DATA_BYPASS_EN_MASK 0x1
460#define ETH_DB_DATA_BYPASS_EN_SHIFT 4
461#define ETH_DB_DATA_RESERVED_MASK 0x1
462#define ETH_DB_DATA_RESERVED_SHIFT 5
463#define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3
464#define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6
465 u8 agg_flags;
466 __le16 bd_prod;
467};
468
469
470enum rss_hash_type {
471 RSS_HASH_TYPE_DEFAULT = 0,
472 RSS_HASH_TYPE_IPV4 = 1,
473 RSS_HASH_TYPE_TCP_IPV4 = 2,
474 RSS_HASH_TYPE_IPV6 = 3,
475 RSS_HASH_TYPE_TCP_IPV6 = 4,
476 RSS_HASH_TYPE_UDP_IPV4 = 5,
477 RSS_HASH_TYPE_UDP_IPV6 = 6,
478 MAX_RSS_HASH_TYPE
479};
480
481#endif
482