LXR linux/drivers/fpga/Kconfig

   1# SPDX-License-Identifier: GPL-2.0-only
   2#
   3# FPGA framework configuration
   4#
   5
   6menuconfig FPGA
   7        tristate "FPGA Configuration Framework"
   8        help
   9          Say Y here if you want support for configuring FPGAs from the
  10          kernel.  The FPGA framework adds a FPGA manager class and FPGA
  11          manager drivers.
  12
  13if FPGA
  14
  15config FPGA_MGR_DEBUG_FS
  16        tristate "FPGA debug fs"
  17        select DEBUG_FS
  18        help
  19          Say Y here if you want to expose a DebugFS interface for the
  20          FPGA Manager Framework. FPGA manager DebugFS provides a user
  21          interface to read the fpga specific configuration information.
  22
  23          If unsure, say N.
  24
  25config FPGA_MGR_SOCFPGA
  26        tristate "Altera SOCFPGA FPGA Manager"
  27        depends on ARCH_SOCFPGA || COMPILE_TEST
  28        help
  29          FPGA manager driver support for Altera SOCFPGA.
  30
  31config FPGA_MGR_SOCFPGA_A10
  32        tristate "Altera SoCFPGA Arria10"
  33        depends on ARCH_SOCFPGA || COMPILE_TEST
  34        select REGMAP_MMIO
  35        help
  36          FPGA manager driver support for Altera Arria10 SoCFPGA.
  37
  38config ALTERA_PR_IP_CORE
  39        tristate "Altera Partial Reconfiguration IP Core"
  40        help
  41          Core driver support for Altera Partial Reconfiguration IP component
  42
  43config ALTERA_PR_IP_CORE_PLAT
  44        tristate "Platform support of Altera Partial Reconfiguration IP Core"
  45        depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM
  46        help
  47          Platform driver support for Altera Partial Reconfiguration IP
  48          component
  49
  50config FPGA_MGR_ALTERA_PS_SPI
  51        tristate "Altera FPGA Passive Serial over SPI"
  52        depends on SPI
  53        select BITREVERSE
  54        help
  55          FPGA manager driver support for Altera Arria/Cyclone/Stratix
  56          using the passive serial interface over SPI.
  57
  58config FPGA_MGR_ALTERA_CVP
  59        tristate "Altera CvP FPGA Manager"
  60        depends on PCI
  61        help
  62          FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
  63          Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe.
  64
  65config FPGA_MGR_ZYNQ_FPGA
  66        tristate "Xilinx Zynq FPGA"
  67        depends on ARCH_ZYNQ || COMPILE_TEST
  68        help
  69          FPGA manager driver support for Xilinx Zynq FPGAs.
  70
  71config FPGA_MGR_STRATIX10_SOC
  72        tristate "Intel Stratix10 SoC FPGA Manager"
  73        depends on (ARCH_STRATIX10 && INTEL_STRATIX10_SERVICE)
  74        help
  75          FPGA manager driver support for the Intel Stratix10 SoC.
  76
  77config FPGA_MGR_XILINX_SPI
  78        tristate "Xilinx Configuration over Slave Serial (SPI)"
  79        depends on SPI
  80        help
  81          FPGA manager driver support for Xilinx FPGA configuration
  82          over slave serial interface.
  83
  84config FPGA_MGR_ICE40_SPI
  85        tristate "Lattice iCE40 SPI"
  86        depends on OF && SPI
  87        help
  88          FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
  89
  90config FPGA_MGR_MACHXO2_SPI
  91        tristate "Lattice MachXO2 SPI"
  92        depends on SPI
  93        help
  94          FPGA manager driver support for Lattice MachXO2 configuration
  95          over slave SPI interface.
  96
  97config FPGA_MGR_TS73XX
  98        tristate "Technologic Systems TS-73xx SBC FPGA Manager"
  99        depends on ARCH_EP93XX && MACH_TS72XX
 100        help
 101          FPGA manager driver support for the Altera Cyclone II FPGA
 102          present on the TS-73xx SBC boards.
 103
 104config FPGA_MGR_ZYNQ_AFI_FPGA
 105        bool "Xilinx AFI FPGA"
 106        depends on FPGA_MGR_ZYNQ_FPGA
 107        help
 108          Zynq AFI driver support for writing to the AFI registers
 109          for configuring the PS_PL interface. For some of the bitstream
 110          or designs to work the PS to PL interfaces need to be configured
 111          like the data bus-width etc.
 112
 113config XILINX_AFI_FPGA
 114        bool "Xilinx AFI FPGA"
 115        depends on FPGA_MGR_ZYNQMP_FPGA || COMPILE_TEST
 116        help
 117          FPGA manager driver support for writing to the AFI registers
 118          for configuring the PS_PL interface. For some of the bitstream
 119          or designs to work the PS to PL interfaces need to be configured
 120          like the datawidth etc.
 121
 122config FPGA_BRIDGE
 123        tristate "FPGA Bridge Framework"
 124        help
 125          Say Y here if you want to support bridges connected between host
 126          processors and FPGAs or between FPGAs.
 127
 128config SOCFPGA_FPGA_BRIDGE
 129        tristate "Altera SoCFPGA FPGA Bridges"
 130        depends on ARCH_SOCFPGA && FPGA_BRIDGE
 131        help
 132          Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
 133          devices.
 134
 135config ALTERA_FREEZE_BRIDGE
 136        tristate "Altera FPGA Freeze Bridge"
 137        depends on FPGA_BRIDGE && HAS_IOMEM
 138        help
 139          Say Y to enable drivers for Altera FPGA Freeze bridges.  A
 140          freeze bridge is a bridge that exists in the FPGA fabric to
 141          isolate one region of the FPGA from the busses while that
 142          region is being reprogrammed.
 143
 144config XILINX_PR_DECOUPLER
 145        tristate "Xilinx LogiCORE PR Decoupler"
 146        depends on FPGA_BRIDGE
 147        depends on HAS_IOMEM
 148        help
 149          Say Y to enable drivers for Xilinx LogiCORE PR Decoupler.
 150          The PR Decoupler exists in the FPGA fabric to isolate one
 151          region of the FPGA from the busses while that region is
 152          being reprogrammed during partial reconfig.
 153
 154config FPGA_REGION
 155        tristate "FPGA Region"
 156        depends on FPGA_BRIDGE
 157        help
 158          FPGA Region common code.  A FPGA Region controls a FPGA Manager
 159          and the FPGA Bridges associated with either a reconfigurable
 160          region of an FPGA or a whole FPGA.
 161
 162config OF_FPGA_REGION
 163        tristate "FPGA Region Device Tree Overlay Support"
 164        depends on OF && FPGA_REGION
 165        help
 166          Support for loading FPGA images by applying a Device Tree
 167          overlay.
 168
 169config FPGA_DFL
 170        tristate "FPGA Device Feature List (DFL) support"
 171        select FPGA_BRIDGE
 172        select FPGA_REGION
 173        depends on HAS_IOMEM
 174        help
 175          Device Feature List (DFL) defines a feature list structure that
 176          creates a linked list of feature headers within the MMIO space
 177          to provide an extensible way of adding features for FPGA.
 178          Driver can walk through the feature headers to enumerate feature
 179          devices (e.g. FPGA Management Engine, Port and Accelerator
 180          Function Unit) and their private features for target FPGA devices.
 181
 182          Select this option to enable common support for Field-Programmable
 183          Gate Array (FPGA) solutions which implement Device Feature List.
 184          It provides enumeration APIs and feature device infrastructure.
 185
 186config FPGA_DFL_FME
 187        tristate "FPGA DFL FME Driver"
 188        depends on FPGA_DFL && HWMON && PERF_EVENTS
 189        help
 190          The FPGA Management Engine (FME) is a feature device implemented
 191          under Device Feature List (DFL) framework. Select this option to
 192          enable the platform device driver for FME which implements all
 193          FPGA platform level management features. There shall be one FME
 194          per DFL based FPGA device.
 195
 196config FPGA_DFL_FME_MGR
 197        tristate "FPGA DFL FME Manager Driver"
 198        depends on FPGA_DFL_FME && HAS_IOMEM
 199        help
 200          Say Y to enable FPGA Manager driver for FPGA Management Engine.
 201
 202config FPGA_DFL_FME_BRIDGE
 203        tristate "FPGA DFL FME Bridge Driver"
 204        depends on FPGA_DFL_FME && HAS_IOMEM
 205        help
 206          Say Y to enable FPGA Bridge driver for FPGA Management Engine.
 207
 208config FPGA_DFL_FME_REGION
 209        tristate "FPGA DFL FME Region Driver"
 210        depends on FPGA_DFL_FME && HAS_IOMEM
 211        help
 212          Say Y to enable FPGA Region driver for FPGA Management Engine.
 213
 214config FPGA_DFL_AFU
 215        tristate "FPGA DFL AFU Driver"
 216        depends on FPGA_DFL
 217        help
 218          This is the driver for FPGA Accelerated Function Unit (AFU) which
 219          implements AFU and Port management features. A User AFU connects
 220          to the FPGA infrastructure via a Port. There may be more than one
 221          Port/AFU per DFL based FPGA device.
 222
 223config FPGA_DFL_PCI
 224        tristate "FPGA DFL PCIe Device Driver"
 225        depends on PCI && FPGA_DFL
 226        help
 227          Select this option to enable PCIe driver for PCIe-based
 228          Field-Programmable Gate Array (FPGA) solutions which implement
 229          the Device Feature List (DFL). This driver provides interfaces
 230          for userspace applications to configure, enumerate, open and access
 231          FPGA accelerators on the FPGA DFL devices, enables system level
 232          management functions such as FPGA partial reconfiguration, power
 233          management and virtualization with DFL framework and DFL feature
 234          device drivers.
 235
 236          To compile this as a module, choose M here.
 237
 238config FPGA_MGR_ZYNQMP_FPGA
 239        tristate "Xilinx ZynqMP FPGA"
 240        depends on ZYNQMP_FIRMWARE || (!ZYNQMP_FIRMWARE && COMPILE_TEST)
 241        help
 242          FPGA manager driver support for Xilinx ZynqMP FPGAs.
 243          This driver uses the processor configuration port(PCAP)
 244          to configure the programmable logic(PL) through PS
 245          on ZynqMP SoC.
 246
 247config FPGA_MGR_VERSAL_FPGA
 248        tristate "Xilinx Versal FPGA"
 249        depends on ARCH_ZYNQMP || COMPILE_TEST
 250        help
 251          Select this option to enable FPGA manager driver support for
 252          Xilinx Versal SOC. This driver uses the versal soc firmware
 253          interface to load programmable logic(PL) images
 254          on versal soc.
 255
 256endif # FPGA
 257