linux/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
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   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3* Analogix DP (Display Port) core interface driver.
   4*
   5* Copyright (C) 2012 Samsung Electronics Co., Ltd.
   6* Author: Jingoo Han <jg1.han@samsung.com>
   7*/
   8
   9#include <linux/clk.h>
  10#include <linux/component.h>
  11#include <linux/err.h>
  12#include <linux/gpio/consumer.h>
  13#include <linux/interrupt.h>
  14#include <linux/io.h>
  15#include <linux/iopoll.h>
  16#include <linux/module.h>
  17#include <linux/of.h>
  18#include <linux/phy/phy.h>
  19#include <linux/platform_device.h>
  20
  21#include <drm/bridge/analogix_dp.h>
  22#include <drm/drm_atomic.h>
  23#include <drm/drm_atomic_helper.h>
  24#include <drm/drm_bridge.h>
  25#include <drm/drm_crtc.h>
  26#include <drm/drm_device.h>
  27#include <drm/drm_panel.h>
  28#include <drm/drm_print.h>
  29#include <drm/drm_probe_helper.h>
  30
  31#include "analogix_dp_core.h"
  32#include "analogix_dp_reg.h"
  33
  34#define to_dp(nm)       container_of(nm, struct analogix_dp_device, nm)
  35
  36static const bool verify_fast_training;
  37
  38struct bridge_init {
  39        struct i2c_client *client;
  40        struct device_node *node;
  41};
  42
  43static int analogix_dp_init_dp(struct analogix_dp_device *dp)
  44{
  45        int ret;
  46
  47        analogix_dp_reset(dp);
  48
  49        analogix_dp_swreset(dp);
  50
  51        analogix_dp_init_analog_param(dp);
  52        analogix_dp_init_interrupt(dp);
  53
  54        /* SW defined function Normal operation */
  55        analogix_dp_enable_sw_function(dp);
  56
  57        analogix_dp_config_interrupt(dp);
  58        ret = analogix_dp_init_analog_func(dp);
  59        if (ret)
  60                return ret;
  61
  62        analogix_dp_init_hpd(dp);
  63        analogix_dp_init_aux(dp);
  64        return 0;
  65}
  66
  67static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
  68{
  69        int timeout_loop = 0;
  70
  71        while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
  72                if (analogix_dp_get_plug_in_status(dp) == 0)
  73                        return 0;
  74
  75                timeout_loop++;
  76                usleep_range(1000, 1100);
  77        }
  78
  79        /*
  80         * Some edp screen do not have hpd signal, so we can't just
  81         * return failed when hpd plug in detect failed, DT property
  82         * "force-hpd" would indicate whether driver need this.
  83         */
  84        if (!dp->force_hpd)
  85                return -ETIMEDOUT;
  86
  87        /*
  88         * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
  89         * will not work, so we need to give a force hpd action to
  90         * set HPD_STATUS manually.
  91         */
  92        dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
  93
  94        analogix_dp_force_hpd(dp);
  95
  96        if (analogix_dp_get_plug_in_status(dp) != 0) {
  97                dev_err(dp->dev, "failed to get hpd plug in status\n");
  98                return -EINVAL;
  99        }
 100
 101        dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
 102
 103        return 0;
 104}
 105
 106static bool analogix_dp_detect_sink_psr(struct analogix_dp_device *dp)
 107{
 108        unsigned char psr_version;
 109        int ret;
 110
 111        ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version);
 112        if (ret != 1) {
 113                dev_err(dp->dev, "failed to get PSR version, disable it\n");
 114                return false;
 115        }
 116
 117        dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version);
 118        return psr_version & DP_PSR_IS_SUPPORTED;
 119}
 120
 121static int analogix_dp_enable_sink_psr(struct analogix_dp_device *dp)
 122{
 123        unsigned char psr_en;
 124        int ret;
 125
 126        /* Disable psr function */
 127        ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en);
 128        if (ret != 1) {
 129                dev_err(dp->dev, "failed to get psr config\n");
 130                goto end;
 131        }
 132
 133        psr_en &= ~DP_PSR_ENABLE;
 134        ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
 135        if (ret != 1) {
 136                dev_err(dp->dev, "failed to disable panel psr\n");
 137                goto end;
 138        }
 139
 140        /* Main-Link transmitter remains active during PSR active states */
 141        psr_en = DP_PSR_CRC_VERIFICATION;
 142        ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
 143        if (ret != 1) {
 144                dev_err(dp->dev, "failed to set panel psr\n");
 145                goto end;
 146        }
 147
 148        /* Enable psr function */
 149        psr_en = DP_PSR_ENABLE | DP_PSR_CRC_VERIFICATION;
 150        ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
 151        if (ret != 1) {
 152                dev_err(dp->dev, "failed to set panel psr\n");
 153                goto end;
 154        }
 155
 156        analogix_dp_enable_psr_crc(dp);
 157
 158        dp->psr_supported = true;
 159
 160        return 0;
 161end:
 162        dev_err(dp->dev, "enable psr fail, force to disable psr\n");
 163
 164        return ret;
 165}
 166
 167static int
 168analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
 169                                       bool enable)
 170{
 171        u8 data;
 172        int ret;
 173
 174        ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data);
 175        if (ret != 1)
 176                return ret;
 177
 178        if (enable)
 179                ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
 180                                         DP_LANE_COUNT_ENHANCED_FRAME_EN |
 181                                         DPCD_LANE_COUNT_SET(data));
 182        else
 183                ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
 184                                         DPCD_LANE_COUNT_SET(data));
 185
 186        return ret < 0 ? ret : 0;
 187}
 188
 189static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp,
 190                                                  u8 *enhanced_mode_support)
 191{
 192        u8 data;
 193        int ret;
 194
 195        ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
 196        if (ret != 1) {
 197                *enhanced_mode_support = 0;
 198                return ret;
 199        }
 200
 201        *enhanced_mode_support = DPCD_ENHANCED_FRAME_CAP(data);
 202
 203        return 0;
 204}
 205
 206static int analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
 207{
 208        u8 data;
 209        int ret;
 210
 211        ret = analogix_dp_is_enhanced_mode_available(dp, &data);
 212        if (ret < 0)
 213                return ret;
 214
 215        ret = analogix_dp_enable_rx_to_enhanced_mode(dp, data);
 216        if (ret < 0)
 217                return ret;
 218
 219        analogix_dp_enable_enhanced_mode(dp, data);
 220
 221        return 0;
 222}
 223
 224static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
 225{
 226        int ret;
 227
 228        analogix_dp_set_training_pattern(dp, DP_NONE);
 229
 230        ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 231                                 DP_TRAINING_PATTERN_DISABLE);
 232
 233        return ret < 0 ? ret : 0;
 234}
 235
 236static void
 237analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
 238                                       int pre_emphasis, int lane)
 239{
 240        switch (lane) {
 241        case 0:
 242                analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
 243                break;
 244        case 1:
 245                analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
 246                break;
 247
 248        case 2:
 249                analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
 250                break;
 251
 252        case 3:
 253                analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
 254                break;
 255        }
 256}
 257
 258static int analogix_dp_link_start(struct analogix_dp_device *dp)
 259{
 260        u8 buf[4];
 261        int lane, lane_count, pll_tries, retval;
 262
 263        lane_count = dp->link_train.lane_count;
 264
 265        dp->link_train.lt_state = CLOCK_RECOVERY;
 266        dp->link_train.eq_loop = 0;
 267
 268        for (lane = 0; lane < lane_count; lane++)
 269                dp->link_train.cr_loop[lane] = 0;
 270
 271        /* Set link rate and count as you want to establish*/
 272        analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
 273        analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
 274
 275        /* Setup RX configuration */
 276        buf[0] = dp->link_train.link_rate;
 277        buf[1] = dp->link_train.lane_count;
 278        retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2);
 279        if (retval < 0)
 280                return retval;
 281        /* set enhanced mode if available */
 282        retval = analogix_dp_set_enhanced_mode(dp);
 283        if (retval < 0) {
 284                dev_err(dp->dev, "failed to set enhance mode\n");
 285                return retval;
 286        }
 287
 288        /* Set TX pre-emphasis to minimum */
 289        for (lane = 0; lane < lane_count; lane++)
 290                analogix_dp_set_lane_lane_pre_emphasis(dp,
 291                        PRE_EMPHASIS_LEVEL_0, lane);
 292
 293        /* Wait for PLL lock */
 294        pll_tries = 0;
 295        while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 296                if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
 297                        dev_err(dp->dev, "Wait for PLL lock timed out\n");
 298                        return -ETIMEDOUT;
 299                }
 300
 301                pll_tries++;
 302                usleep_range(90, 120);
 303        }
 304
 305        /* Set training pattern 1 */
 306        analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
 307
 308        /* Set RX training pattern */
 309        retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 310                                    DP_LINK_SCRAMBLING_DISABLE |
 311                                        DP_TRAINING_PATTERN_1);
 312        if (retval < 0)
 313                return retval;
 314
 315        for (lane = 0; lane < lane_count; lane++)
 316                buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
 317                            DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 318
 319        retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf,
 320                                   lane_count);
 321        if (retval < 0)
 322                return retval;
 323
 324        return 0;
 325}
 326
 327static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
 328{
 329        int shift = (lane & 1) * 4;
 330        u8 link_value = link_status[lane >> 1];
 331
 332        return (link_value >> shift) & 0xf;
 333}
 334
 335static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
 336{
 337        int lane;
 338        u8 lane_status;
 339
 340        for (lane = 0; lane < lane_count; lane++) {
 341                lane_status = analogix_dp_get_lane_status(link_status, lane);
 342                if ((lane_status & DP_LANE_CR_DONE) == 0)
 343                        return -EINVAL;
 344        }
 345        return 0;
 346}
 347
 348static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 349                                     int lane_count)
 350{
 351        int lane;
 352        u8 lane_status;
 353
 354        if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
 355                return -EINVAL;
 356
 357        for (lane = 0; lane < lane_count; lane++) {
 358                lane_status = analogix_dp_get_lane_status(link_status, lane);
 359                lane_status &= DP_CHANNEL_EQ_BITS;
 360                if (lane_status != DP_CHANNEL_EQ_BITS)
 361                        return -EINVAL;
 362        }
 363
 364        return 0;
 365}
 366
 367static unsigned char
 368analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
 369{
 370        int shift = (lane & 1) * 4;
 371        u8 link_value = adjust_request[lane >> 1];
 372
 373        return (link_value >> shift) & 0x3;
 374}
 375
 376static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
 377                                        u8 adjust_request[2],
 378                                        int lane)
 379{
 380        int shift = (lane & 1) * 4;
 381        u8 link_value = adjust_request[lane >> 1];
 382
 383        return ((link_value >> shift) & 0xc) >> 2;
 384}
 385
 386static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
 387                                               u8 training_lane_set, int lane)
 388{
 389        switch (lane) {
 390        case 0:
 391                analogix_dp_set_lane0_link_training(dp, training_lane_set);
 392                break;
 393        case 1:
 394                analogix_dp_set_lane1_link_training(dp, training_lane_set);
 395                break;
 396
 397        case 2:
 398                analogix_dp_set_lane2_link_training(dp, training_lane_set);
 399                break;
 400
 401        case 3:
 402                analogix_dp_set_lane3_link_training(dp, training_lane_set);
 403                break;
 404        }
 405}
 406
 407static unsigned int
 408analogix_dp_get_lane_link_training(struct analogix_dp_device *dp,
 409                                   int lane)
 410{
 411        u32 reg;
 412
 413        switch (lane) {
 414        case 0:
 415                reg = analogix_dp_get_lane0_link_training(dp);
 416                break;
 417        case 1:
 418                reg = analogix_dp_get_lane1_link_training(dp);
 419                break;
 420        case 2:
 421                reg = analogix_dp_get_lane2_link_training(dp);
 422                break;
 423        case 3:
 424                reg = analogix_dp_get_lane3_link_training(dp);
 425                break;
 426        default:
 427                WARN_ON(1);
 428                return 0;
 429        }
 430
 431        return reg;
 432}
 433
 434static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
 435{
 436        analogix_dp_training_pattern_dis(dp);
 437        analogix_dp_set_enhanced_mode(dp);
 438
 439        dp->link_train.lt_state = FAILED;
 440}
 441
 442static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
 443                                                 u8 adjust_request[2])
 444{
 445        int lane, lane_count;
 446        u8 voltage_swing, pre_emphasis, training_lane;
 447
 448        lane_count = dp->link_train.lane_count;
 449        for (lane = 0; lane < lane_count; lane++) {
 450                voltage_swing = analogix_dp_get_adjust_request_voltage(
 451                                                adjust_request, lane);
 452                pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
 453                                                adjust_request, lane);
 454                training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 455                                DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 456
 457                if (voltage_swing == VOLTAGE_LEVEL_3)
 458                        training_lane |= DP_TRAIN_MAX_SWING_REACHED;
 459                if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 460                        training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 461
 462                dp->link_train.training_lane[lane] = training_lane;
 463        }
 464}
 465
 466static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
 467{
 468        int lane, lane_count, retval;
 469        u8 voltage_swing, pre_emphasis, training_lane;
 470        u8 link_status[2], adjust_request[2];
 471
 472        usleep_range(100, 101);
 473
 474        lane_count = dp->link_train.lane_count;
 475
 476        retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
 477        if (retval < 0)
 478                return retval;
 479
 480        retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
 481                                  adjust_request, 2);
 482        if (retval < 0)
 483                return retval;
 484
 485        if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
 486                /* set training pattern 2 for EQ */
 487                analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
 488
 489                retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 490                                            DP_LINK_SCRAMBLING_DISABLE |
 491                                                DP_TRAINING_PATTERN_2);
 492                if (retval < 0)
 493                        return retval;
 494
 495                dev_dbg(dp->dev, "Link Training Clock Recovery success\n");
 496                dp->link_train.lt_state = EQUALIZER_TRAINING;
 497        } else {
 498                for (lane = 0; lane < lane_count; lane++) {
 499                        training_lane = analogix_dp_get_lane_link_training(
 500                                                        dp, lane);
 501                        voltage_swing = analogix_dp_get_adjust_request_voltage(
 502                                                        adjust_request, lane);
 503                        pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
 504                                                        adjust_request, lane);
 505
 506                        if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
 507                                        voltage_swing &&
 508                            DPCD_PRE_EMPHASIS_GET(training_lane) ==
 509                                        pre_emphasis)
 510                                dp->link_train.cr_loop[lane]++;
 511
 512                        if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
 513                            voltage_swing == VOLTAGE_LEVEL_3 ||
 514                            pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 515                                dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
 516                                        dp->link_train.cr_loop[lane],
 517                                        voltage_swing, pre_emphasis);
 518                                analogix_dp_reduce_link_rate(dp);
 519                                return -EIO;
 520                        }
 521                }
 522        }
 523
 524        analogix_dp_get_adjust_training_lane(dp, adjust_request);
 525
 526        for (lane = 0; lane < lane_count; lane++)
 527                analogix_dp_set_lane_link_training(dp,
 528                        dp->link_train.training_lane[lane], lane);
 529
 530        retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
 531                                   dp->link_train.training_lane, lane_count);
 532        if (retval < 0)
 533                return retval;
 534
 535        return 0;
 536}
 537
 538static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
 539{
 540        int lane, lane_count, retval;
 541        u32 reg;
 542        u8 link_align, link_status[2], adjust_request[2];
 543
 544        usleep_range(400, 401);
 545
 546        lane_count = dp->link_train.lane_count;
 547
 548        retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
 549        if (retval < 0)
 550                return retval;
 551
 552        if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
 553                analogix_dp_reduce_link_rate(dp);
 554                return -EIO;
 555        }
 556
 557        retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
 558                                  adjust_request, 2);
 559        if (retval < 0)
 560                return retval;
 561
 562        retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
 563                                   &link_align);
 564        if (retval < 0)
 565                return retval;
 566
 567        analogix_dp_get_adjust_training_lane(dp, adjust_request);
 568
 569        if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
 570                /* traing pattern Set to Normal */
 571                retval = analogix_dp_training_pattern_dis(dp);
 572                if (retval < 0)
 573                        return retval;
 574
 575                dev_dbg(dp->dev, "Link Training success!\n");
 576                analogix_dp_get_link_bandwidth(dp, &reg);
 577                dp->link_train.link_rate = reg;
 578                dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 579                        dp->link_train.link_rate);
 580
 581                analogix_dp_get_lane_count(dp, &reg);
 582                dp->link_train.lane_count = reg;
 583                dev_dbg(dp->dev, "final lane count = %.2x\n",
 584                        dp->link_train.lane_count);
 585
 586                dp->link_train.lt_state = FINISHED;
 587
 588                return 0;
 589        }
 590
 591        /* not all locked */
 592        dp->link_train.eq_loop++;
 593
 594        if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
 595                dev_err(dp->dev, "EQ Max loop\n");
 596                analogix_dp_reduce_link_rate(dp);
 597                return -EIO;
 598        }
 599
 600        for (lane = 0; lane < lane_count; lane++)
 601                analogix_dp_set_lane_link_training(dp,
 602                        dp->link_train.training_lane[lane], lane);
 603
 604        retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
 605                                   dp->link_train.training_lane, lane_count);
 606        if (retval < 0)
 607                return retval;
 608
 609        return 0;
 610}
 611
 612static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 613                                             u8 *bandwidth)
 614{
 615        u8 data;
 616
 617        /*
 618         * For DP rev.1.1, Maximum link rate of Main Link lanes
 619         * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 620         * For DP rev.1.2, Maximum link rate of Main Link lanes
 621         * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
 622         */
 623        drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data);
 624        *bandwidth = data;
 625}
 626
 627static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
 628                                              u8 *lane_count)
 629{
 630        u8 data;
 631
 632        /*
 633         * For DP rev.1.1, Maximum number of Main Link lanes
 634         * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 635         */
 636        drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
 637        *lane_count = DPCD_MAX_LANE_COUNT(data);
 638}
 639
 640static int analogix_dp_full_link_train(struct analogix_dp_device *dp,
 641                                       u32 max_lanes, u32 max_rate)
 642{
 643        int retval = 0;
 644        bool training_finished = false;
 645
 646        /*
 647         * MACRO_RST must be applied after the PLL_LOCK to avoid
 648         * the DP inter pair skew issue for at least 10 us
 649         */
 650        analogix_dp_reset_macro(dp);
 651
 652        /* Initialize by reading RX's DPCD */
 653        analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
 654        analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 655
 656        if ((dp->link_train.link_rate != DP_LINK_BW_1_62) &&
 657            (dp->link_train.link_rate != DP_LINK_BW_2_7) &&
 658            (dp->link_train.link_rate != DP_LINK_BW_5_4)) {
 659                dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 660                        dp->link_train.link_rate);
 661                dp->link_train.link_rate = DP_LINK_BW_1_62;
 662        }
 663
 664        if (dp->link_train.lane_count == 0) {
 665                dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
 666                        dp->link_train.lane_count);
 667                dp->link_train.lane_count = (u8)LANE_COUNT1;
 668        }
 669
 670        /* Setup TX lane count & rate */
 671        if (dp->link_train.lane_count > max_lanes)
 672                dp->link_train.lane_count = max_lanes;
 673        if (dp->link_train.link_rate > max_rate)
 674                dp->link_train.link_rate = max_rate;
 675
 676        /* All DP analog module power up */
 677        analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
 678
 679        dp->link_train.lt_state = START;
 680
 681        /* Process here */
 682        while (!retval && !training_finished) {
 683                switch (dp->link_train.lt_state) {
 684                case START:
 685                        retval = analogix_dp_link_start(dp);
 686                        if (retval)
 687                                dev_err(dp->dev, "LT link start failed!\n");
 688                        break;
 689                case CLOCK_RECOVERY:
 690                        retval = analogix_dp_process_clock_recovery(dp);
 691                        if (retval)
 692                                dev_err(dp->dev, "LT CR failed!\n");
 693                        break;
 694                case EQUALIZER_TRAINING:
 695                        retval = analogix_dp_process_equalizer_training(dp);
 696                        if (retval)
 697                                dev_err(dp->dev, "LT EQ failed!\n");
 698                        break;
 699                case FINISHED:
 700                        training_finished = 1;
 701                        break;
 702                case FAILED:
 703                        return -EREMOTEIO;
 704                }
 705        }
 706        if (retval)
 707                dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
 708
 709        return retval;
 710}
 711
 712static int analogix_dp_fast_link_train(struct analogix_dp_device *dp)
 713{
 714        int i, ret;
 715        u8 link_align, link_status[2];
 716        enum pll_status status;
 717
 718        analogix_dp_reset_macro(dp);
 719
 720        analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
 721        analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
 722
 723        for (i = 0; i < dp->link_train.lane_count; i++) {
 724                analogix_dp_set_lane_link_training(dp,
 725                        dp->link_train.training_lane[i], i);
 726        }
 727
 728        ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status,
 729                                 status != PLL_UNLOCKED, 120,
 730                                 120 * DP_TIMEOUT_LOOP_COUNT);
 731        if (ret) {
 732                DRM_DEV_ERROR(dp->dev, "Wait for pll lock failed %d\n", ret);
 733                return ret;
 734        }
 735
 736        /* source Set training pattern 1 */
 737        analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
 738        /* From DP spec, pattern must be on-screen for a minimum 500us */
 739        usleep_range(500, 600);
 740
 741        analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
 742        /* From DP spec, pattern must be on-screen for a minimum 500us */
 743        usleep_range(500, 600);
 744
 745        /* TODO: enhanced_mode?*/
 746        analogix_dp_set_training_pattern(dp, DP_NONE);
 747
 748        /*
 749         * Useful for debugging issues with fast link training, disable for more
 750         * speed
 751         */
 752        if (verify_fast_training) {
 753                ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
 754                                        &link_align);
 755                if (ret < 0) {
 756                        DRM_DEV_ERROR(dp->dev, "Read align status failed %d\n",
 757                                      ret);
 758                        return ret;
 759                }
 760
 761                ret = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status,
 762                                       2);
 763                if (ret < 0) {
 764                        DRM_DEV_ERROR(dp->dev, "Read link status failed %d\n",
 765                                      ret);
 766                        return ret;
 767                }
 768
 769                if (analogix_dp_clock_recovery_ok(link_status,
 770                                                  dp->link_train.lane_count)) {
 771                        DRM_DEV_ERROR(dp->dev, "Clock recovery failed\n");
 772                        analogix_dp_reduce_link_rate(dp);
 773                        return -EIO;
 774                }
 775
 776                if (analogix_dp_channel_eq_ok(link_status, link_align,
 777                                              dp->link_train.lane_count)) {
 778                        DRM_DEV_ERROR(dp->dev, "Channel EQ failed\n");
 779                        analogix_dp_reduce_link_rate(dp);
 780                        return -EIO;
 781                }
 782        }
 783
 784        return 0;
 785}
 786
 787static int analogix_dp_train_link(struct analogix_dp_device *dp)
 788{
 789        if (dp->fast_train_enable)
 790                return analogix_dp_fast_link_train(dp);
 791
 792        return analogix_dp_full_link_train(dp, dp->video_info.max_lane_count,
 793                                           dp->video_info.max_link_rate);
 794}
 795
 796static int analogix_dp_config_video(struct analogix_dp_device *dp)
 797{
 798        int timeout_loop = 0;
 799        int done_count = 0;
 800
 801        analogix_dp_config_video_slave_mode(dp);
 802
 803        analogix_dp_set_video_color_format(dp);
 804
 805        if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 806                dev_err(dp->dev, "PLL is not locked yet.\n");
 807                return -EINVAL;
 808        }
 809
 810        for (;;) {
 811                timeout_loop++;
 812                if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
 813                        break;
 814                if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 815                        dev_err(dp->dev, "Timeout of slave video streamclk ok\n");
 816                        return -ETIMEDOUT;
 817                }
 818                usleep_range(1000, 1001);
 819        }
 820
 821        /* Set to use the register calculated M/N video */
 822        analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
 823
 824        /* For video bist, Video timing must be generated by register */
 825        analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
 826
 827        /* Disable video mute */
 828        analogix_dp_enable_video_mute(dp, 0);
 829
 830        /* Configure video slave mode */
 831        analogix_dp_enable_video_master(dp, 0);
 832
 833        /* Enable video */
 834        analogix_dp_start_video(dp);
 835
 836        timeout_loop = 0;
 837
 838        for (;;) {
 839                timeout_loop++;
 840                if (analogix_dp_is_video_stream_on(dp) == 0) {
 841                        done_count++;
 842                        if (done_count > 10)
 843                                break;
 844                } else if (done_count) {
 845                        done_count = 0;
 846                }
 847                if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 848                        dev_warn(dp->dev,
 849                                 "Ignoring timeout of video streamclk ok\n");
 850                        break;
 851                }
 852
 853                usleep_range(1000, 1001);
 854        }
 855
 856        return 0;
 857}
 858
 859static int analogix_dp_enable_scramble(struct analogix_dp_device *dp,
 860                                       bool enable)
 861{
 862        u8 data;
 863        int ret;
 864
 865        if (enable) {
 866                analogix_dp_enable_scrambling(dp);
 867
 868                ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
 869                                        &data);
 870                if (ret != 1)
 871                        return ret;
 872                ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 873                                   (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
 874        } else {
 875                analogix_dp_disable_scrambling(dp);
 876
 877                ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
 878                                        &data);
 879                if (ret != 1)
 880                        return ret;
 881                ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 882                                   (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
 883        }
 884        return ret < 0 ? ret : 0;
 885}
 886
 887static irqreturn_t analogix_dp_hardirq(int irq, void *arg)
 888{
 889        struct analogix_dp_device *dp = arg;
 890        irqreturn_t ret = IRQ_NONE;
 891        enum dp_irq_type irq_type;
 892
 893        irq_type = analogix_dp_get_irq_type(dp);
 894        if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
 895                analogix_dp_mute_hpd_interrupt(dp);
 896                ret = IRQ_WAKE_THREAD;
 897        }
 898
 899        return ret;
 900}
 901
 902static irqreturn_t analogix_dp_irq_thread(int irq, void *arg)
 903{
 904        struct analogix_dp_device *dp = arg;
 905        enum dp_irq_type irq_type;
 906
 907        irq_type = analogix_dp_get_irq_type(dp);
 908        if (irq_type & DP_IRQ_TYPE_HP_CABLE_IN ||
 909            irq_type & DP_IRQ_TYPE_HP_CABLE_OUT) {
 910                dev_dbg(dp->dev, "Detected cable status changed!\n");
 911                if (dp->drm_dev)
 912                        drm_helper_hpd_irq_event(dp->drm_dev);
 913        }
 914
 915        if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
 916                analogix_dp_clear_hotplug_interrupts(dp);
 917                analogix_dp_unmute_hpd_interrupt(dp);
 918        }
 919
 920        return IRQ_HANDLED;
 921}
 922
 923static int analogix_dp_fast_link_train_detection(struct analogix_dp_device *dp)
 924{
 925        int ret;
 926        u8 spread;
 927
 928        ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &spread);
 929        if (ret != 1) {
 930                dev_err(dp->dev, "failed to read downspread %d\n", ret);
 931                return ret;
 932        }
 933        dp->fast_train_enable = !!(spread & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
 934        dev_dbg(dp->dev, "fast link training %s\n",
 935                dp->fast_train_enable ? "supported" : "unsupported");
 936        return 0;
 937}
 938
 939static int analogix_dp_commit(struct analogix_dp_device *dp)
 940{
 941        int ret;
 942
 943        /* Keep the panel disabled while we configure video */
 944        if (dp->plat_data->panel) {
 945                if (drm_panel_disable(dp->plat_data->panel))
 946                        DRM_ERROR("failed to disable the panel\n");
 947        }
 948
 949        ret = analogix_dp_train_link(dp);
 950        if (ret) {
 951                dev_err(dp->dev, "unable to do link train, ret=%d\n", ret);
 952                return ret;
 953        }
 954
 955        ret = analogix_dp_enable_scramble(dp, 1);
 956        if (ret < 0) {
 957                dev_err(dp->dev, "can not enable scramble\n");
 958                return ret;
 959        }
 960
 961        analogix_dp_init_video(dp);
 962        ret = analogix_dp_config_video(dp);
 963        if (ret) {
 964                dev_err(dp->dev, "unable to config video\n");
 965                return ret;
 966        }
 967
 968        /* Safe to enable the panel now */
 969        if (dp->plat_data->panel) {
 970                ret = drm_panel_enable(dp->plat_data->panel);
 971                if (ret) {
 972                        DRM_ERROR("failed to enable the panel\n");
 973                        return ret;
 974                }
 975        }
 976
 977        /* Check whether panel supports fast training */
 978        ret = analogix_dp_fast_link_train_detection(dp);
 979        if (ret)
 980                return ret;
 981
 982        if (analogix_dp_detect_sink_psr(dp)) {
 983                ret = analogix_dp_enable_sink_psr(dp);
 984                if (ret)
 985                        return ret;
 986        }
 987
 988        return ret;
 989}
 990
 991static int analogix_dp_enable_psr(struct analogix_dp_device *dp)
 992{
 993        struct dp_sdp psr_vsc;
 994        int ret;
 995        u8 sink;
 996
 997        ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink);
 998        if (ret != 1)
 999                DRM_DEV_ERROR(dp->dev, "Failed to read psr status %d\n", ret);
1000        else if (sink == DP_PSR_SINK_ACTIVE_RFB)
1001                return 0;
1002
1003        /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
1004        memset(&psr_vsc, 0, sizeof(psr_vsc));
1005        psr_vsc.sdp_header.HB0 = 0;
1006        psr_vsc.sdp_header.HB1 = 0x7;
1007        psr_vsc.sdp_header.HB2 = 0x2;
1008        psr_vsc.sdp_header.HB3 = 0x8;
1009        psr_vsc.db[0] = 0;
1010        psr_vsc.db[1] = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID;
1011
1012        ret = analogix_dp_send_psr_spd(dp, &psr_vsc, true);
1013        if (!ret)
1014                analogix_dp_set_analog_power_down(dp, POWER_ALL, true);
1015
1016        return ret;
1017}
1018
1019static int analogix_dp_disable_psr(struct analogix_dp_device *dp)
1020{
1021        struct dp_sdp psr_vsc;
1022        int ret;
1023        u8 sink;
1024
1025        analogix_dp_set_analog_power_down(dp, POWER_ALL, false);
1026
1027        ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
1028        if (ret != 1) {
1029                DRM_DEV_ERROR(dp->dev, "Failed to set DP Power0 %d\n", ret);
1030                return ret;
1031        }
1032
1033        ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink);
1034        if (ret != 1) {
1035                DRM_DEV_ERROR(dp->dev, "Failed to read psr status %d\n", ret);
1036                return ret;
1037        } else if (sink == DP_PSR_SINK_INACTIVE) {
1038                DRM_DEV_ERROR(dp->dev, "sink inactive, skip disable psr");
1039                return 0;
1040        }
1041
1042        ret = analogix_dp_train_link(dp);
1043        if (ret) {
1044                DRM_DEV_ERROR(dp->dev, "Failed to train the link %d\n", ret);
1045                return ret;
1046        }
1047
1048        /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
1049        memset(&psr_vsc, 0, sizeof(psr_vsc));
1050        psr_vsc.sdp_header.HB0 = 0;
1051        psr_vsc.sdp_header.HB1 = 0x7;
1052        psr_vsc.sdp_header.HB2 = 0x2;
1053        psr_vsc.sdp_header.HB3 = 0x8;
1054
1055        psr_vsc.db[0] = 0;
1056        psr_vsc.db[1] = 0;
1057
1058        return analogix_dp_send_psr_spd(dp, &psr_vsc, true);
1059}
1060
1061/*
1062 * This function is a bit of a catch-all for panel preparation, hopefully
1063 * simplifying the logic of functions that need to prepare/unprepare the panel
1064 * below.
1065 *
1066 * If @prepare is true, this function will prepare the panel. Conversely, if it
1067 * is false, the panel will be unprepared.
1068 *
1069 * If @is_modeset_prepare is true, the function will disregard the current state
1070 * of the panel and either prepare/unprepare the panel based on @prepare. Once
1071 * it finishes, it will update dp->panel_is_modeset to reflect the current state
1072 * of the panel.
1073 */
1074static int analogix_dp_prepare_panel(struct analogix_dp_device *dp,
1075                                     bool prepare, bool is_modeset_prepare)
1076{
1077        int ret = 0;
1078
1079        if (!dp->plat_data->panel)
1080                return 0;
1081
1082        mutex_lock(&dp->panel_lock);
1083
1084        /*
1085         * Exit early if this is a temporary prepare/unprepare and we're already
1086         * modeset (since we neither want to prepare twice or unprepare early).
1087         */
1088        if (dp->panel_is_modeset && !is_modeset_prepare)
1089                goto out;
1090
1091        if (prepare)
1092                ret = drm_panel_prepare(dp->plat_data->panel);
1093        else
1094                ret = drm_panel_unprepare(dp->plat_data->panel);
1095
1096        if (ret)
1097                goto out;
1098
1099        if (is_modeset_prepare)
1100                dp->panel_is_modeset = prepare;
1101
1102out:
1103        mutex_unlock(&dp->panel_lock);
1104        return ret;
1105}
1106
1107static int analogix_dp_get_modes(struct drm_connector *connector)
1108{
1109        struct analogix_dp_device *dp = to_dp(connector);
1110        struct edid *edid;
1111        int ret, num_modes = 0;
1112
1113        if (dp->plat_data->panel) {
1114                num_modes += drm_panel_get_modes(dp->plat_data->panel, connector);
1115        } else {
1116                ret = analogix_dp_prepare_panel(dp, true, false);
1117                if (ret) {
1118                        DRM_ERROR("Failed to prepare panel (%d)\n", ret);
1119                        return 0;
1120                }
1121
1122                pm_runtime_get_sync(dp->dev);
1123                edid = drm_get_edid(connector, &dp->aux.ddc);
1124                pm_runtime_put(dp->dev);
1125                if (edid) {
1126                        drm_connector_update_edid_property(&dp->connector,
1127                                                           edid);
1128                        num_modes += drm_add_edid_modes(&dp->connector, edid);
1129                        kfree(edid);
1130                }
1131
1132                ret = analogix_dp_prepare_panel(dp, false, false);
1133                if (ret)
1134                        DRM_ERROR("Failed to unprepare panel (%d)\n", ret);
1135        }
1136
1137        if (dp->plat_data->get_modes)
1138                num_modes += dp->plat_data->get_modes(dp->plat_data, connector);
1139
1140        return num_modes;
1141}
1142
1143static struct drm_encoder *
1144analogix_dp_best_encoder(struct drm_connector *connector)
1145{
1146        struct analogix_dp_device *dp = to_dp(connector);
1147
1148        return dp->encoder;
1149}
1150
1151
1152static int analogix_dp_atomic_check(struct drm_connector *connector,
1153                                    struct drm_atomic_state *state)
1154{
1155        struct analogix_dp_device *dp = to_dp(connector);
1156        struct drm_connector_state *conn_state;
1157        struct drm_crtc_state *crtc_state;
1158
1159        conn_state = drm_atomic_get_new_connector_state(state, connector);
1160        if (WARN_ON(!conn_state))
1161                return -ENODEV;
1162
1163        conn_state->self_refresh_aware = true;
1164
1165        if (!conn_state->crtc)
1166                return 0;
1167
1168        crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
1169        if (!crtc_state)
1170                return 0;
1171
1172        if (crtc_state->self_refresh_active && !dp->psr_supported)
1173                return -EINVAL;
1174
1175        return 0;
1176}
1177
1178static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
1179        .get_modes = analogix_dp_get_modes,
1180        .best_encoder = analogix_dp_best_encoder,
1181        .atomic_check = analogix_dp_atomic_check,
1182};
1183
1184static enum drm_connector_status
1185analogix_dp_detect(struct drm_connector *connector, bool force)
1186{
1187        struct analogix_dp_device *dp = to_dp(connector);
1188        enum drm_connector_status status = connector_status_disconnected;
1189        int ret;
1190
1191        if (dp->plat_data->panel)
1192                return connector_status_connected;
1193
1194        ret = analogix_dp_prepare_panel(dp, true, false);
1195        if (ret) {
1196                DRM_ERROR("Failed to prepare panel (%d)\n", ret);
1197                return connector_status_disconnected;
1198        }
1199
1200        if (!analogix_dp_detect_hpd(dp))
1201                status = connector_status_connected;
1202
1203        ret = analogix_dp_prepare_panel(dp, false, false);
1204        if (ret)
1205                DRM_ERROR("Failed to unprepare panel (%d)\n", ret);
1206
1207        return status;
1208}
1209
1210static const struct drm_connector_funcs analogix_dp_connector_funcs = {
1211        .fill_modes = drm_helper_probe_single_connector_modes,
1212        .detect = analogix_dp_detect,
1213        .destroy = drm_connector_cleanup,
1214        .reset = drm_atomic_helper_connector_reset,
1215        .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1216        .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1217};
1218
1219static int analogix_dp_bridge_attach(struct drm_bridge *bridge,
1220                                     enum drm_bridge_attach_flags flags)
1221{
1222        struct analogix_dp_device *dp = bridge->driver_private;
1223        struct drm_encoder *encoder = dp->encoder;
1224        struct drm_connector *connector = NULL;
1225        int ret = 0;
1226
1227        if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
1228                DRM_ERROR("Fix bridge driver to make connector optional!");
1229                return -EINVAL;
1230        }
1231
1232        if (!bridge->encoder) {
1233                DRM_ERROR("Parent encoder object not found");
1234                return -ENODEV;
1235        }
1236
1237        if (!dp->plat_data->skip_connector) {
1238                connector = &dp->connector;
1239                connector->polled = DRM_CONNECTOR_POLL_HPD;
1240
1241                ret = drm_connector_init(dp->drm_dev, connector,
1242                                         &analogix_dp_connector_funcs,
1243                                         DRM_MODE_CONNECTOR_eDP);
1244                if (ret) {
1245                        DRM_ERROR("Failed to initialize connector with drm\n");
1246                        return ret;
1247                }
1248
1249                drm_connector_helper_add(connector,
1250                                         &analogix_dp_connector_helper_funcs);
1251                drm_connector_attach_encoder(connector, encoder);
1252        }
1253
1254        /*
1255         * NOTE: the connector registration is implemented in analogix
1256         * platform driver, that to say connector would be exist after
1257         * plat_data->attch return, that's why we record the connector
1258         * point after plat attached.
1259         */
1260        if (dp->plat_data->attach) {
1261                ret = dp->plat_data->attach(dp->plat_data, bridge, connector);
1262                if (ret) {
1263                        DRM_ERROR("Failed at platform attach func\n");
1264                        return ret;
1265                }
1266        }
1267
1268        return 0;
1269}
1270
1271static
1272struct drm_crtc *analogix_dp_get_new_crtc(struct analogix_dp_device *dp,
1273                                          struct drm_atomic_state *state)
1274{
1275        struct drm_encoder *encoder = dp->encoder;
1276        struct drm_connector *connector;
1277        struct drm_connector_state *conn_state;
1278
1279        connector = drm_atomic_get_new_connector_for_encoder(state, encoder);
1280        if (!connector)
1281                return NULL;
1282
1283        conn_state = drm_atomic_get_new_connector_state(state, connector);
1284        if (!conn_state)
1285                return NULL;
1286
1287        return conn_state->crtc;
1288}
1289
1290static void
1291analogix_dp_bridge_atomic_pre_enable(struct drm_bridge *bridge,
1292                                     struct drm_bridge_state *old_bridge_state)
1293{
1294        struct drm_atomic_state *old_state = old_bridge_state->base.state;
1295        struct analogix_dp_device *dp = bridge->driver_private;
1296        struct drm_crtc *crtc;
1297        struct drm_crtc_state *old_crtc_state;
1298        int ret;
1299
1300        crtc = analogix_dp_get_new_crtc(dp, old_state);
1301        if (!crtc)
1302                return;
1303
1304        old_crtc_state = drm_atomic_get_old_crtc_state(old_state, crtc);
1305        /* Don't touch the panel if we're coming back from PSR */
1306        if (old_crtc_state && old_crtc_state->self_refresh_active)
1307                return;
1308
1309        ret = analogix_dp_prepare_panel(dp, true, true);
1310        if (ret)
1311                DRM_ERROR("failed to setup the panel ret = %d\n", ret);
1312}
1313
1314static int analogix_dp_set_bridge(struct analogix_dp_device *dp)
1315{
1316        int ret;
1317
1318        pm_runtime_get_sync(dp->dev);
1319
1320        ret = clk_prepare_enable(dp->clock);
1321        if (ret < 0) {
1322                DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
1323                goto out_dp_clk_pre;
1324        }
1325
1326        if (dp->plat_data->power_on_start)
1327                dp->plat_data->power_on_start(dp->plat_data);
1328
1329        phy_power_on(dp->phy);
1330
1331        ret = analogix_dp_init_dp(dp);
1332        if (ret)
1333                goto out_dp_init;
1334
1335        /*
1336         * According to DP spec v1.3 chap 3.5.1.2 Link Training,
1337         * We should first make sure the HPD signal is asserted high by device
1338         * when we want to establish a link with it.
1339         */
1340        ret = analogix_dp_detect_hpd(dp);
1341        if (ret) {
1342                DRM_ERROR("failed to get hpd single ret = %d\n", ret);
1343                goto out_dp_init;
1344        }
1345
1346        ret = analogix_dp_commit(dp);
1347        if (ret) {
1348                DRM_ERROR("dp commit error, ret = %d\n", ret);
1349                goto out_dp_init;
1350        }
1351
1352        if (dp->plat_data->power_on_end)
1353                dp->plat_data->power_on_end(dp->plat_data);
1354
1355        enable_irq(dp->irq);
1356        return 0;
1357
1358out_dp_init:
1359        phy_power_off(dp->phy);
1360        if (dp->plat_data->power_off)
1361                dp->plat_data->power_off(dp->plat_data);
1362        clk_disable_unprepare(dp->clock);
1363out_dp_clk_pre:
1364        pm_runtime_put_sync(dp->dev);
1365
1366        return ret;
1367}
1368
1369static void
1370analogix_dp_bridge_atomic_enable(struct drm_bridge *bridge,
1371                                 struct drm_bridge_state *old_bridge_state)
1372{
1373        struct drm_atomic_state *old_state = old_bridge_state->base.state;
1374        struct analogix_dp_device *dp = bridge->driver_private;
1375        struct drm_crtc *crtc;
1376        struct drm_crtc_state *old_crtc_state;
1377        int timeout_loop = 0;
1378        int ret;
1379
1380        crtc = analogix_dp_get_new_crtc(dp, old_state);
1381        if (!crtc)
1382                return;
1383
1384        old_crtc_state = drm_atomic_get_old_crtc_state(old_state, crtc);
1385        /* Not a full enable, just disable PSR and continue */
1386        if (old_crtc_state && old_crtc_state->self_refresh_active) {
1387                ret = analogix_dp_disable_psr(dp);
1388                if (ret)
1389                        DRM_ERROR("Failed to disable psr %d\n", ret);
1390                return;
1391        }
1392
1393        if (dp->dpms_mode == DRM_MODE_DPMS_ON)
1394                return;
1395
1396        while (timeout_loop < MAX_PLL_LOCK_LOOP) {
1397                if (analogix_dp_set_bridge(dp) == 0) {
1398                        dp->dpms_mode = DRM_MODE_DPMS_ON;
1399                        return;
1400                }
1401                dev_err(dp->dev, "failed to set bridge, retry: %d\n",
1402                        timeout_loop);
1403                timeout_loop++;
1404                usleep_range(10, 11);
1405        }
1406        dev_err(dp->dev, "too many times retry set bridge, give it up\n");
1407}
1408
1409static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
1410{
1411        struct analogix_dp_device *dp = bridge->driver_private;
1412        int ret;
1413
1414        if (dp->dpms_mode != DRM_MODE_DPMS_ON)
1415                return;
1416
1417        if (dp->plat_data->panel) {
1418                if (drm_panel_disable(dp->plat_data->panel)) {
1419                        DRM_ERROR("failed to disable the panel\n");
1420                        return;
1421                }
1422        }
1423
1424        disable_irq(dp->irq);
1425
1426        if (dp->plat_data->power_off)
1427                dp->plat_data->power_off(dp->plat_data);
1428
1429        analogix_dp_set_analog_power_down(dp, POWER_ALL, 1);
1430        phy_power_off(dp->phy);
1431
1432        clk_disable_unprepare(dp->clock);
1433
1434        pm_runtime_put_sync(dp->dev);
1435
1436        ret = analogix_dp_prepare_panel(dp, false, true);
1437        if (ret)
1438                DRM_ERROR("failed to setup the panel ret = %d\n", ret);
1439
1440        dp->fast_train_enable = false;
1441        dp->psr_supported = false;
1442        dp->dpms_mode = DRM_MODE_DPMS_OFF;
1443}
1444
1445static void
1446analogix_dp_bridge_atomic_disable(struct drm_bridge *bridge,
1447                                  struct drm_bridge_state *old_bridge_state)
1448{
1449        struct drm_atomic_state *old_state = old_bridge_state->base.state;
1450        struct analogix_dp_device *dp = bridge->driver_private;
1451        struct drm_crtc *crtc;
1452        struct drm_crtc_state *new_crtc_state = NULL;
1453
1454        crtc = analogix_dp_get_new_crtc(dp, old_state);
1455        if (!crtc)
1456                goto out;
1457
1458        new_crtc_state = drm_atomic_get_new_crtc_state(old_state, crtc);
1459        if (!new_crtc_state)
1460                goto out;
1461
1462        /* Don't do a full disable on PSR transitions */
1463        if (new_crtc_state->self_refresh_active)
1464                return;
1465
1466out:
1467        analogix_dp_bridge_disable(bridge);
1468}
1469
1470static void
1471analogix_dp_bridge_atomic_post_disable(struct drm_bridge *bridge,
1472                                struct drm_bridge_state *old_bridge_state)
1473{
1474        struct drm_atomic_state *old_state = old_bridge_state->base.state;
1475        struct analogix_dp_device *dp = bridge->driver_private;
1476        struct drm_crtc *crtc;
1477        struct drm_crtc_state *new_crtc_state;
1478        int ret;
1479
1480        crtc = analogix_dp_get_new_crtc(dp, old_state);
1481        if (!crtc)
1482                return;
1483
1484        new_crtc_state = drm_atomic_get_new_crtc_state(old_state, crtc);
1485        if (!new_crtc_state || !new_crtc_state->self_refresh_active)
1486                return;
1487
1488        ret = analogix_dp_enable_psr(dp);
1489        if (ret)
1490                DRM_ERROR("Failed to enable psr (%d)\n", ret);
1491}
1492
1493static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
1494                                const struct drm_display_mode *orig_mode,
1495                                const struct drm_display_mode *mode)
1496{
1497        struct analogix_dp_device *dp = bridge->driver_private;
1498        struct drm_display_info *display_info = &dp->connector.display_info;
1499        struct video_info *video = &dp->video_info;
1500        struct device_node *dp_node = dp->dev->of_node;
1501        int vic;
1502
1503        /* Input video interlaces & hsync pol & vsync pol */
1504        video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1505        video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
1506        video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
1507
1508        /* Input video dynamic_range & colorimetry */
1509        vic = drm_match_cea_mode(mode);
1510        if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
1511            (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
1512                video->dynamic_range = CEA;
1513                video->ycbcr_coeff = COLOR_YCBCR601;
1514        } else if (vic) {
1515                video->dynamic_range = CEA;
1516                video->ycbcr_coeff = COLOR_YCBCR709;
1517        } else {
1518                video->dynamic_range = VESA;
1519                video->ycbcr_coeff = COLOR_YCBCR709;
1520        }
1521
1522        /* Input vide bpc and color_formats */
1523        switch (display_info->bpc) {
1524        case 12:
1525                video->color_depth = COLOR_12;
1526                break;
1527        case 10:
1528                video->color_depth = COLOR_10;
1529                break;
1530        case 8:
1531                video->color_depth = COLOR_8;
1532                break;
1533        case 6:
1534                video->color_depth = COLOR_6;
1535                break;
1536        default:
1537                video->color_depth = COLOR_8;
1538                break;
1539        }
1540        if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
1541                video->color_space = COLOR_YCBCR444;
1542        else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
1543                video->color_space = COLOR_YCBCR422;
1544        else
1545                video->color_space = COLOR_RGB;
1546
1547        /*
1548         * NOTE: those property parsing code is used for providing backward
1549         * compatibility for samsung platform.
1550         * Due to we used the "of_property_read_u32" interfaces, when this
1551         * property isn't present, the "video_info" can keep the original
1552         * values and wouldn't be modified.
1553         */
1554        of_property_read_u32(dp_node, "samsung,color-space",
1555                             &video->color_space);
1556        of_property_read_u32(dp_node, "samsung,dynamic-range",
1557                             &video->dynamic_range);
1558        of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
1559                             &video->ycbcr_coeff);
1560        of_property_read_u32(dp_node, "samsung,color-depth",
1561                             &video->color_depth);
1562        if (of_property_read_bool(dp_node, "hsync-active-high"))
1563                video->h_sync_polarity = true;
1564        if (of_property_read_bool(dp_node, "vsync-active-high"))
1565                video->v_sync_polarity = true;
1566        if (of_property_read_bool(dp_node, "interlaced"))
1567                video->interlaced = true;
1568}
1569
1570static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
1571        .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1572        .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1573        .atomic_reset = drm_atomic_helper_bridge_reset,
1574        .atomic_pre_enable = analogix_dp_bridge_atomic_pre_enable,
1575        .atomic_enable = analogix_dp_bridge_atomic_enable,
1576        .atomic_disable = analogix_dp_bridge_atomic_disable,
1577        .atomic_post_disable = analogix_dp_bridge_atomic_post_disable,
1578        .mode_set = analogix_dp_bridge_mode_set,
1579        .attach = analogix_dp_bridge_attach,
1580};
1581
1582static int analogix_dp_create_bridge(struct drm_device *drm_dev,
1583                                     struct analogix_dp_device *dp)
1584{
1585        struct drm_bridge *bridge;
1586        int ret;
1587
1588        bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
1589        if (!bridge) {
1590                DRM_ERROR("failed to allocate for drm bridge\n");
1591                return -ENOMEM;
1592        }
1593
1594        dp->bridge = bridge;
1595
1596        bridge->driver_private = dp;
1597        bridge->funcs = &analogix_dp_bridge_funcs;
1598
1599        ret = drm_bridge_attach(dp->encoder, bridge, NULL, 0);
1600        if (ret) {
1601                DRM_ERROR("failed to attach drm bridge\n");
1602                return -EINVAL;
1603        }
1604
1605        return 0;
1606}
1607
1608static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
1609{
1610        struct device_node *dp_node = dp->dev->of_node;
1611        struct video_info *video_info = &dp->video_info;
1612
1613        switch (dp->plat_data->dev_type) {
1614        case RK3288_DP:
1615        case RK3399_EDP:
1616                /*
1617                 * Like Rk3288 DisplayPort TRM indicate that "Main link
1618                 * containing 4 physical lanes of 2.7/1.62 Gbps/lane".
1619                 */
1620                video_info->max_link_rate = 0x0A;
1621                video_info->max_lane_count = 0x04;
1622                break;
1623        case EXYNOS_DP:
1624                /*
1625                 * NOTE: those property parseing code is used for
1626                 * providing backward compatibility for samsung platform.
1627                 */
1628                of_property_read_u32(dp_node, "samsung,link-rate",
1629                                     &video_info->max_link_rate);
1630                of_property_read_u32(dp_node, "samsung,lane-count",
1631                                     &video_info->max_lane_count);
1632                break;
1633        }
1634
1635        return 0;
1636}
1637
1638static ssize_t analogix_dpaux_transfer(struct drm_dp_aux *aux,
1639                                       struct drm_dp_aux_msg *msg)
1640{
1641        struct analogix_dp_device *dp = to_dp(aux);
1642
1643        return analogix_dp_transfer(dp, msg);
1644}
1645
1646struct analogix_dp_device *
1647analogix_dp_probe(struct device *dev, struct analogix_dp_plat_data *plat_data)
1648{
1649        struct platform_device *pdev = to_platform_device(dev);
1650        struct analogix_dp_device *dp;
1651        struct resource *res;
1652        unsigned int irq_flags;
1653        int ret;
1654
1655        if (!plat_data) {
1656                dev_err(dev, "Invalided input plat_data\n");
1657                return ERR_PTR(-EINVAL);
1658        }
1659
1660        dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
1661        if (!dp)
1662                return ERR_PTR(-ENOMEM);
1663
1664        dp->dev = &pdev->dev;
1665        dp->dpms_mode = DRM_MODE_DPMS_OFF;
1666
1667        mutex_init(&dp->panel_lock);
1668        dp->panel_is_modeset = false;
1669
1670        /*
1671         * platform dp driver need containor_of the plat_data to get
1672         * the driver private data, so we need to store the point of
1673         * plat_data, not the context of plat_data.
1674         */
1675        dp->plat_data = plat_data;
1676
1677        ret = analogix_dp_dt_parse_pdata(dp);
1678        if (ret)
1679                return ERR_PTR(ret);
1680
1681        dp->phy = devm_phy_get(dp->dev, "dp");
1682        if (IS_ERR(dp->phy)) {
1683                dev_err(dp->dev, "no DP phy configured\n");
1684                ret = PTR_ERR(dp->phy);
1685                if (ret) {
1686                        /*
1687                         * phy itself is not enabled, so we can move forward
1688                         * assigning NULL to phy pointer.
1689                         */
1690                        if (ret == -ENOSYS || ret == -ENODEV)
1691                                dp->phy = NULL;
1692                        else
1693                                return ERR_PTR(ret);
1694                }
1695        }
1696
1697        dp->clock = devm_clk_get(&pdev->dev, "dp");
1698        if (IS_ERR(dp->clock)) {
1699                dev_err(&pdev->dev, "failed to get clock\n");
1700                return ERR_CAST(dp->clock);
1701        }
1702
1703        clk_prepare_enable(dp->clock);
1704
1705        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1706
1707        dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
1708        if (IS_ERR(dp->reg_base))
1709                return ERR_CAST(dp->reg_base);
1710
1711        dp->force_hpd = of_property_read_bool(dev->of_node, "force-hpd");
1712
1713        /* Try two different names */
1714        dp->hpd_gpiod = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
1715        if (!dp->hpd_gpiod)
1716                dp->hpd_gpiod = devm_gpiod_get_optional(dev, "samsung,hpd",
1717                                                        GPIOD_IN);
1718        if (IS_ERR(dp->hpd_gpiod)) {
1719                dev_err(dev, "error getting HDP GPIO: %ld\n",
1720                        PTR_ERR(dp->hpd_gpiod));
1721                return ERR_CAST(dp->hpd_gpiod);
1722        }
1723
1724        if (dp->hpd_gpiod) {
1725                /*
1726                 * Set up the hotplug GPIO from the device tree as an interrupt.
1727                 * Simply specifying a different interrupt in the device tree
1728                 * doesn't work since we handle hotplug rather differently when
1729                 * using a GPIO.  We also need the actual GPIO specifier so
1730                 * that we can get the current state of the GPIO.
1731                 */
1732                dp->irq = gpiod_to_irq(dp->hpd_gpiod);
1733                irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
1734        } else {
1735                dp->irq = platform_get_irq(pdev, 0);
1736                irq_flags = 0;
1737        }
1738
1739        if (dp->irq == -ENXIO) {
1740                dev_err(&pdev->dev, "failed to get irq\n");
1741                return ERR_PTR(-ENODEV);
1742        }
1743
1744        ret = devm_request_threaded_irq(&pdev->dev, dp->irq,
1745                                        analogix_dp_hardirq,
1746                                        analogix_dp_irq_thread,
1747                                        irq_flags, "analogix-dp", dp);
1748        if (ret) {
1749                dev_err(&pdev->dev, "failed to request irq\n");
1750                return ERR_PTR(ret);
1751        }
1752        disable_irq(dp->irq);
1753
1754        return dp;
1755}
1756EXPORT_SYMBOL_GPL(analogix_dp_probe);
1757
1758int analogix_dp_bind(struct analogix_dp_device *dp, struct drm_device *drm_dev)
1759{
1760        int ret;
1761
1762        dp->drm_dev = drm_dev;
1763        dp->encoder = dp->plat_data->encoder;
1764
1765        dp->aux.name = "DP-AUX";
1766        dp->aux.transfer = analogix_dpaux_transfer;
1767        dp->aux.dev = dp->dev;
1768
1769        ret = drm_dp_aux_register(&dp->aux);
1770        if (ret)
1771                return ret;
1772
1773        pm_runtime_enable(dp->dev);
1774
1775        ret = analogix_dp_create_bridge(drm_dev, dp);
1776        if (ret) {
1777                DRM_ERROR("failed to create bridge (%d)\n", ret);
1778                goto err_disable_pm_runtime;
1779        }
1780
1781        return 0;
1782
1783err_disable_pm_runtime:
1784        pm_runtime_disable(dp->dev);
1785
1786        return ret;
1787}
1788EXPORT_SYMBOL_GPL(analogix_dp_bind);
1789
1790void analogix_dp_unbind(struct analogix_dp_device *dp)
1791{
1792        analogix_dp_bridge_disable(dp->bridge);
1793        dp->connector.funcs->destroy(&dp->connector);
1794
1795        if (dp->plat_data->panel) {
1796                if (drm_panel_unprepare(dp->plat_data->panel))
1797                        DRM_ERROR("failed to turnoff the panel\n");
1798        }
1799
1800        drm_dp_aux_unregister(&dp->aux);
1801        pm_runtime_disable(dp->dev);
1802}
1803EXPORT_SYMBOL_GPL(analogix_dp_unbind);
1804
1805void analogix_dp_remove(struct analogix_dp_device *dp)
1806{
1807        clk_disable_unprepare(dp->clock);
1808}
1809EXPORT_SYMBOL_GPL(analogix_dp_remove);
1810
1811#ifdef CONFIG_PM
1812int analogix_dp_suspend(struct analogix_dp_device *dp)
1813{
1814        clk_disable_unprepare(dp->clock);
1815
1816        if (dp->plat_data->panel) {
1817                if (drm_panel_unprepare(dp->plat_data->panel))
1818                        DRM_ERROR("failed to turnoff the panel\n");
1819        }
1820
1821        return 0;
1822}
1823EXPORT_SYMBOL_GPL(analogix_dp_suspend);
1824
1825int analogix_dp_resume(struct analogix_dp_device *dp)
1826{
1827        int ret;
1828
1829        ret = clk_prepare_enable(dp->clock);
1830        if (ret < 0) {
1831                DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
1832                return ret;
1833        }
1834
1835        if (dp->plat_data->panel) {
1836                if (drm_panel_prepare(dp->plat_data->panel)) {
1837                        DRM_ERROR("failed to setup the panel\n");
1838                        return -EBUSY;
1839                }
1840        }
1841
1842        return 0;
1843}
1844EXPORT_SYMBOL_GPL(analogix_dp_resume);
1845#endif
1846
1847int analogix_dp_start_crc(struct drm_connector *connector)
1848{
1849        struct analogix_dp_device *dp = to_dp(connector);
1850
1851        if (!connector->state->crtc) {
1852                DRM_ERROR("Connector %s doesn't currently have a CRTC.\n",
1853                          connector->name);
1854                return -EINVAL;
1855        }
1856
1857        return drm_dp_start_crc(&dp->aux, connector->state->crtc);
1858}
1859EXPORT_SYMBOL_GPL(analogix_dp_start_crc);
1860
1861int analogix_dp_stop_crc(struct drm_connector *connector)
1862{
1863        struct analogix_dp_device *dp = to_dp(connector);
1864
1865        return drm_dp_stop_crc(&dp->aux);
1866}
1867EXPORT_SYMBOL_GPL(analogix_dp_stop_crc);
1868
1869MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1870MODULE_DESCRIPTION("Analogix DP Core Driver");
1871MODULE_LICENSE("GPL v2");
1872