LXR linux/drivers/mailbox/sun6i-msgbox.c

   1// SPDX-License-Identifier: GPL-2.0
   2//
   3// Copyright (c) 2017-2019 Samuel Holland <samuel@sholland.org>
   4
   5#include <linux/bitops.h>
   6#include <linux/clk.h>
   7#include <linux/device.h>
   8#include <linux/err.h>
   9#include <linux/interrupt.h>
  10#include <linux/io.h>
  11#include <linux/kernel.h>
  12#include <linux/mailbox_controller.h>
  13#include <linux/module.h>
  14#include <linux/of.h>
  15#include <linux/of_irq.h>
  16#include <linux/platform_device.h>
  17#include <linux/reset.h>
  18#include <linux/spinlock.h>
  19
  20#define NUM_CHANS               8
  21
  22#define CTRL_REG(n)             (0x0000 + 0x4 * ((n) / 4))
  23#define CTRL_RX(n)              BIT(0 + 8 * ((n) % 4))
  24#define CTRL_TX(n)              BIT(4 + 8 * ((n) % 4))
  25
  26#define REMOTE_IRQ_EN_REG       0x0040
  27#define REMOTE_IRQ_STAT_REG     0x0050
  28#define LOCAL_IRQ_EN_REG        0x0060
  29#define LOCAL_IRQ_STAT_REG      0x0070
  30
  31#define RX_IRQ(n)               BIT(0 + 2 * (n))
  32#define RX_IRQ_MASK             0x5555
  33#define TX_IRQ(n)               BIT(1 + 2 * (n))
  34#define TX_IRQ_MASK             0xaaaa
  35
  36#define FIFO_STAT_REG(n)        (0x0100 + 0x4 * (n))
  37#define FIFO_STAT_MASK          GENMASK(0, 0)
  38
  39#define MSG_STAT_REG(n)         (0x0140 + 0x4 * (n))
  40#define MSG_STAT_MASK           GENMASK(2, 0)
  41
  42#define MSG_DATA_REG(n)         (0x0180 + 0x4 * (n))
  43
  44#define mbox_dbg(mbox, ...)     dev_dbg((mbox)->controller.dev, __VA_ARGS__)
  45
  46struct sun6i_msgbox {
  47        struct mbox_controller controller;
  48        struct clk *clk;
  49        spinlock_t lock;
  50        void __iomem *regs;
  51};
  52
  53static bool sun6i_msgbox_last_tx_done(struct mbox_chan *chan);
  54static bool sun6i_msgbox_peek_data(struct mbox_chan *chan);
  55
  56static inline int channel_number(struct mbox_chan *chan)
  57{
  58        return chan - chan->mbox->chans;
  59}
  60
  61static inline struct sun6i_msgbox *to_sun6i_msgbox(struct mbox_chan *chan)
  62{
  63        return chan->con_priv;
  64}
  65
  66static irqreturn_t sun6i_msgbox_irq(int irq, void *dev_id)
  67{
  68        struct sun6i_msgbox *mbox = dev_id;
  69        uint32_t status;
  70        int n;
  71
  72        /* Only examine channels that are currently enabled. */
  73        status = readl(mbox->regs + LOCAL_IRQ_EN_REG) &
  74                 readl(mbox->regs + LOCAL_IRQ_STAT_REG);
  75
  76        if (!(status & RX_IRQ_MASK))
  77                return IRQ_NONE;
  78
  79        for (n = 0; n < NUM_CHANS; ++n) {
  80                struct mbox_chan *chan = &mbox->controller.chans[n];
  81
  82                if (!(status & RX_IRQ(n)))
  83                        continue;
  84
  85                while (sun6i_msgbox_peek_data(chan)) {
  86                        uint32_t msg = readl(mbox->regs + MSG_DATA_REG(n));
  87
  88                        mbox_dbg(mbox, "Channel %d received 0x%08x\n", n, msg);
  89                        mbox_chan_received_data(chan, &msg);
  90                }
  91
  92                /* The IRQ can be cleared only once the FIFO is empty. */
  93                writel(RX_IRQ(n), mbox->regs + LOCAL_IRQ_STAT_REG);
  94        }
  95
  96        return IRQ_HANDLED;
  97}
  98
  99static int sun6i_msgbox_send_data(struct mbox_chan *chan, void *data)
 100{
 101        struct sun6i_msgbox *mbox = to_sun6i_msgbox(chan);
 102        int n = channel_number(chan);
 103        uint32_t msg = *(uint32_t *)data;
 104
 105        /* Using a channel backwards gets the hardware into a bad state. */
 106        if (WARN_ON_ONCE(!(readl(mbox->regs + CTRL_REG(n)) & CTRL_TX(n))))
 107                return 0;
 108
 109        writel(msg, mbox->regs + MSG_DATA_REG(n));
 110        mbox_dbg(mbox, "Channel %d sent 0x%08x\n", n, msg);
 111
 112        return 0;
 113}
 114
 115static int sun6i_msgbox_startup(struct mbox_chan *chan)
 116{
 117        struct sun6i_msgbox *mbox = to_sun6i_msgbox(chan);
 118        int n = channel_number(chan);
 119
 120        /* The coprocessor is responsible for setting channel directions. */
 121        if (readl(mbox->regs + CTRL_REG(n)) & CTRL_RX(n)) {
 122                /* Flush the receive FIFO. */
 123                while (sun6i_msgbox_peek_data(chan))
 124                        readl(mbox->regs + MSG_DATA_REG(n));
 125                writel(RX_IRQ(n), mbox->regs + LOCAL_IRQ_STAT_REG);
 126
 127                /* Enable the receive IRQ. */
 128                spin_lock(&mbox->lock);
 129                writel(readl(mbox->regs + LOCAL_IRQ_EN_REG) | RX_IRQ(n),
 130                       mbox->regs + LOCAL_IRQ_EN_REG);
 131                spin_unlock(&mbox->lock);
 132        }
 133
 134        mbox_dbg(mbox, "Channel %d startup complete\n", n);
 135
 136        return 0;
 137}
 138
 139static void sun6i_msgbox_shutdown(struct mbox_chan *chan)
 140{
 141        struct sun6i_msgbox *mbox = to_sun6i_msgbox(chan);
 142        int n = channel_number(chan);
 143
 144        if (readl(mbox->regs + CTRL_REG(n)) & CTRL_RX(n)) {
 145                /* Disable the receive IRQ. */
 146                spin_lock(&mbox->lock);
 147                writel(readl(mbox->regs + LOCAL_IRQ_EN_REG) & ~RX_IRQ(n),
 148                       mbox->regs + LOCAL_IRQ_EN_REG);
 149                spin_unlock(&mbox->lock);
 150
 151                /* Attempt to flush the FIFO until the IRQ is cleared. */
 152                do {
 153                        while (sun6i_msgbox_peek_data(chan))
 154                                readl(mbox->regs + MSG_DATA_REG(n));
 155                        writel(RX_IRQ(n), mbox->regs + LOCAL_IRQ_STAT_REG);
 156                } while (readl(mbox->regs + LOCAL_IRQ_STAT_REG) & RX_IRQ(n));
 157        }
 158
 159        mbox_dbg(mbox, "Channel %d shutdown complete\n", n);
 160}
 161
 162static bool sun6i_msgbox_last_tx_done(struct mbox_chan *chan)
 163{
 164        struct sun6i_msgbox *mbox = to_sun6i_msgbox(chan);
 165        int n = channel_number(chan);
 166
 167        /*
 168         * The hardware allows snooping on the remote user's IRQ statuses.
 169         * We consider a message to be acknowledged only once the receive IRQ
 170         * for that channel is cleared. Since the receive IRQ for a channel
 171         * cannot be cleared until the FIFO for that channel is empty, this
 172         * ensures that the message has actually been read. It also gives the
 173         * recipient an opportunity to perform minimal processing before
 174         * acknowledging the message.
 175         */
 176        return !(readl(mbox->regs + REMOTE_IRQ_STAT_REG) & RX_IRQ(n));
 177}
 178
 179static bool sun6i_msgbox_peek_data(struct mbox_chan *chan)
 180{
 181        struct sun6i_msgbox *mbox = to_sun6i_msgbox(chan);
 182        int n = channel_number(chan);
 183
 184        return readl(mbox->regs + MSG_STAT_REG(n)) & MSG_STAT_MASK;
 185}
 186
 187static const struct mbox_chan_ops sun6i_msgbox_chan_ops = {
 188        .send_data    = sun6i_msgbox_send_data,
 189        .startup      = sun6i_msgbox_startup,
 190        .shutdown     = sun6i_msgbox_shutdown,
 191        .last_tx_done = sun6i_msgbox_last_tx_done,
 192        .peek_data    = sun6i_msgbox_peek_data,
 193};
 194
 195static int sun6i_msgbox_probe(struct platform_device *pdev)
 196{
 197        struct device *dev = &pdev->dev;
 198        struct mbox_chan *chans;
 199        struct reset_control *reset;
 200        struct resource *res;
 201        struct sun6i_msgbox *mbox;
 202        int i, ret;
 203
 204        mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL);
 205        if (!mbox)
 206                return -ENOMEM;
 207
 208        chans = devm_kcalloc(dev, NUM_CHANS, sizeof(*chans), GFP_KERNEL);
 209        if (!chans)
 210                return -ENOMEM;
 211
 212        for (i = 0; i < NUM_CHANS; ++i)
 213                chans[i].con_priv = mbox;
 214
 215        mbox->clk = devm_clk_get(dev, NULL);
 216        if (IS_ERR(mbox->clk)) {
 217                ret = PTR_ERR(mbox->clk);
 218                dev_err(dev, "Failed to get clock: %d\n", ret);
 219                return ret;
 220        }
 221
 222        ret = clk_prepare_enable(mbox->clk);
 223        if (ret) {
 224                dev_err(dev, "Failed to enable clock: %d\n", ret);
 225                return ret;
 226        }
 227
 228        reset = devm_reset_control_get_exclusive(dev, NULL);
 229        if (IS_ERR(reset)) {
 230                ret = PTR_ERR(reset);
 231                dev_err(dev, "Failed to get reset control: %d\n", ret);
 232                goto err_disable_unprepare;
 233        }
 234
 235        /*
 236         * NOTE: We rely on platform firmware to preconfigure the channel
 237         * directions, and we share this hardware block with other firmware
 238         * that runs concurrently with Linux (e.g. a trusted monitor).
 239         *
 240         * Therefore, we do *not* assert the reset line if probing fails or
 241         * when removing the device.
 242         */
 243        ret = reset_control_deassert(reset);
 244        if (ret) {
 245                dev_err(dev, "Failed to deassert reset: %d\n", ret);
 246                goto err_disable_unprepare;
 247        }
 248
 249        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 250        if (!res) {
 251                ret = -ENODEV;
 252                goto err_disable_unprepare;
 253        }
 254
 255        mbox->regs = devm_ioremap_resource(&pdev->dev, res);
 256        if (IS_ERR(mbox->regs)) {
 257                ret = PTR_ERR(mbox->regs);
 258                dev_err(dev, "Failed to map MMIO resource: %d\n", ret);
 259                goto err_disable_unprepare;
 260        }
 261
 262        /* Disable all IRQs for this end of the msgbox. */
 263        writel(0, mbox->regs + LOCAL_IRQ_EN_REG);
 264
 265        ret = devm_request_irq(dev, irq_of_parse_and_map(dev->of_node, 0),
 266                               sun6i_msgbox_irq, 0, dev_name(dev), mbox);
 267        if (ret) {
 268                dev_err(dev, "Failed to register IRQ handler: %d\n", ret);
 269                goto err_disable_unprepare;
 270        }
 271
 272        mbox->controller.dev           = dev;
 273        mbox->controller.ops           = &sun6i_msgbox_chan_ops;
 274        mbox->controller.chans         = chans;
 275        mbox->controller.num_chans     = NUM_CHANS;
 276        mbox->controller.txdone_irq    = false;
 277        mbox->controller.txdone_poll   = true;
 278        mbox->controller.txpoll_period = 5;
 279
 280        spin_lock_init(&mbox->lock);
 281        platform_set_drvdata(pdev, mbox);
 282
 283        ret = mbox_controller_register(&mbox->controller);
 284        if (ret) {
 285                dev_err(dev, "Failed to register controller: %d\n", ret);
 286                goto err_disable_unprepare;
 287        }
 288
 289        return 0;
 290
 291err_disable_unprepare:
 292        clk_disable_unprepare(mbox->clk);
 293
 294        return ret;
 295}
 296
 297static int sun6i_msgbox_remove(struct platform_device *pdev)
 298{
 299        struct sun6i_msgbox *mbox = platform_get_drvdata(pdev);
 300
 301        mbox_controller_unregister(&mbox->controller);
 302        /* See the comment in sun6i_msgbox_probe about the reset line. */
 303        clk_disable_unprepare(mbox->clk);
 304
 305        return 0;
 306}
 307
 308static const struct of_device_id sun6i_msgbox_of_match[] = {
 309        { .compatible = "allwinner,sun6i-a31-msgbox", },
 310        {},
 311};
 312MODULE_DEVICE_TABLE(of, sun6i_msgbox_of_match);
 313
 314static struct platform_driver sun6i_msgbox_driver = {
 315        .driver = {
 316                .name = "sun6i-msgbox",
 317                .of_match_table = sun6i_msgbox_of_match,
 318        },
 319        .probe  = sun6i_msgbox_probe,
 320        .remove = sun6i_msgbox_remove,
 321};
 322module_platform_driver(sun6i_msgbox_driver);
 323
 324MODULE_AUTHOR("Samuel Holland <samuel@sholland.org>");
 325MODULE_DESCRIPTION("Allwinner sun6i/sun8i/sun9i/sun50i Message Box");
 326MODULE_LICENSE("GPL v2");
 327