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25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/sched.h>
28#include <linux/string.h>
29#include <linux/timer.h>
30#include <linux/delay.h>
31#include <linux/errno.h>
32#include <linux/slab.h>
33#include <linux/videodev2.h>
34#include <linux/i2c.h>
35#include <linux/init.h>
36#include <linux/kthread.h>
37#include <linux/freezer.h>
38
39#include <media/i2c/tvaudio.h>
40#include <media/v4l2-device.h>
41#include <media/v4l2-ctrls.h>
42
43
44
45
46static int debug;
47module_param(debug, int, 0644);
48
49MODULE_DESCRIPTION("device driver for various i2c TV sound decoder / audiomux chips");
50MODULE_AUTHOR("Eric Sandeen, Steve VanDeBogart, Greg Alexander, Gerd Knorr");
51MODULE_LICENSE("GPL");
52
53#define UNSET (-1U)
54
55
56
57
58#define MAXREGS 256
59
60struct CHIPSTATE;
61typedef int (*getvalue)(int);
62typedef int (*checkit)(struct CHIPSTATE*);
63typedef int (*initialize)(struct CHIPSTATE*);
64typedef int (*getrxsubchans)(struct CHIPSTATE *);
65typedef void (*setaudmode)(struct CHIPSTATE*, int mode);
66
67
68typedef struct AUDIOCMD {
69 int count;
70 unsigned char bytes[MAXREGS+1];
71} audiocmd;
72
73
74struct CHIPDESC {
75 char *name;
76 int addr_lo, addr_hi;
77 int registers;
78
79 int *insmodopt;
80 checkit checkit;
81 initialize initialize;
82 int flags;
83#define CHIP_HAS_VOLUME 1
84#define CHIP_HAS_BASSTREBLE 2
85#define CHIP_HAS_INPUTSEL 4
86#define CHIP_NEED_CHECKMODE 8
87
88
89 audiocmd init;
90
91
92 int leftreg, rightreg, treblereg, bassreg;
93
94
95 int volinit, trebleinit, bassinit;
96
97
98 getvalue volfunc, treblefunc, bassfunc;
99
100
101 getrxsubchans getrxsubchans;
102 setaudmode setaudmode;
103
104
105 int inputreg;
106 int inputmap[4];
107 int inputmute;
108 int inputmask;
109};
110
111
112struct CHIPSTATE {
113 struct v4l2_subdev sd;
114 struct v4l2_ctrl_handler hdl;
115 struct {
116
117 struct v4l2_ctrl *volume;
118 struct v4l2_ctrl *balance;
119 };
120
121
122
123 struct CHIPDESC *desc;
124
125
126 audiocmd shadow;
127
128
129 u16 muted;
130 int prevmode;
131 int radio;
132 int input;
133
134
135 struct task_struct *thread;
136 struct timer_list wt;
137 int audmode;
138};
139
140static inline struct CHIPSTATE *to_state(struct v4l2_subdev *sd)
141{
142 return container_of(sd, struct CHIPSTATE, sd);
143}
144
145static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
146{
147 return &container_of(ctrl->handler, struct CHIPSTATE, hdl)->sd;
148}
149
150
151
152
153
154static int chip_write(struct CHIPSTATE *chip, int subaddr, int val)
155{
156 struct v4l2_subdev *sd = &chip->sd;
157 struct i2c_client *c = v4l2_get_subdevdata(sd);
158 unsigned char buffer[2];
159 int rc;
160
161 if (subaddr < 0) {
162 v4l2_dbg(1, debug, sd, "chip_write: 0x%x\n", val);
163 chip->shadow.bytes[1] = val;
164 buffer[0] = val;
165 rc = i2c_master_send(c, buffer, 1);
166 if (rc != 1) {
167 v4l2_warn(sd, "I/O error (write 0x%x)\n", val);
168 if (rc < 0)
169 return rc;
170 return -EIO;
171 }
172 } else {
173 if (subaddr + 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
174 v4l2_info(sd,
175 "Tried to access a non-existent register: %d\n",
176 subaddr);
177 return -EINVAL;
178 }
179
180 v4l2_dbg(1, debug, sd, "chip_write: reg%d=0x%x\n",
181 subaddr, val);
182 chip->shadow.bytes[subaddr+1] = val;
183 buffer[0] = subaddr;
184 buffer[1] = val;
185 rc = i2c_master_send(c, buffer, 2);
186 if (rc != 2) {
187 v4l2_warn(sd, "I/O error (write reg%d=0x%x)\n",
188 subaddr, val);
189 if (rc < 0)
190 return rc;
191 return -EIO;
192 }
193 }
194 return 0;
195}
196
197static int chip_write_masked(struct CHIPSTATE *chip,
198 int subaddr, int val, int mask)
199{
200 struct v4l2_subdev *sd = &chip->sd;
201
202 if (mask != 0) {
203 if (subaddr < 0) {
204 val = (chip->shadow.bytes[1] & ~mask) | (val & mask);
205 } else {
206 if (subaddr + 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
207 v4l2_info(sd,
208 "Tried to access a non-existent register: %d\n",
209 subaddr);
210 return -EINVAL;
211 }
212
213 val = (chip->shadow.bytes[subaddr+1] & ~mask) | (val & mask);
214 }
215 }
216 return chip_write(chip, subaddr, val);
217}
218
219static int chip_read(struct CHIPSTATE *chip)
220{
221 struct v4l2_subdev *sd = &chip->sd;
222 struct i2c_client *c = v4l2_get_subdevdata(sd);
223 unsigned char buffer;
224 int rc;
225
226 rc = i2c_master_recv(c, &buffer, 1);
227 if (rc != 1) {
228 v4l2_warn(sd, "I/O error (read)\n");
229 if (rc < 0)
230 return rc;
231 return -EIO;
232 }
233 v4l2_dbg(1, debug, sd, "chip_read: 0x%x\n", buffer);
234 return buffer;
235}
236
237static int chip_read2(struct CHIPSTATE *chip, int subaddr)
238{
239 struct v4l2_subdev *sd = &chip->sd;
240 struct i2c_client *c = v4l2_get_subdevdata(sd);
241 int rc;
242 unsigned char write[1];
243 unsigned char read[1];
244 struct i2c_msg msgs[2] = {
245 {
246 .addr = c->addr,
247 .len = 1,
248 .buf = write
249 },
250 {
251 .addr = c->addr,
252 .flags = I2C_M_RD,
253 .len = 1,
254 .buf = read
255 }
256 };
257
258 write[0] = subaddr;
259
260 rc = i2c_transfer(c->adapter, msgs, 2);
261 if (rc != 2) {
262 v4l2_warn(sd, "I/O error (read2)\n");
263 if (rc < 0)
264 return rc;
265 return -EIO;
266 }
267 v4l2_dbg(1, debug, sd, "chip_read2: reg%d=0x%x\n",
268 subaddr, read[0]);
269 return read[0];
270}
271
272static int chip_cmd(struct CHIPSTATE *chip, char *name, audiocmd *cmd)
273{
274 struct v4l2_subdev *sd = &chip->sd;
275 struct i2c_client *c = v4l2_get_subdevdata(sd);
276 int i, rc;
277
278 if (0 == cmd->count)
279 return 0;
280
281 if (cmd->count + cmd->bytes[0] - 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
282 v4l2_info(sd,
283 "Tried to access a non-existent register range: %d to %d\n",
284 cmd->bytes[0] + 1, cmd->bytes[0] + cmd->count - 1);
285 return -EINVAL;
286 }
287
288
289
290
291 v4l2_dbg(1, debug, sd, "chip_cmd(%s): reg=%d, data:",
292 name, cmd->bytes[0]);
293 for (i = 1; i < cmd->count; i++) {
294 if (debug)
295 printk(KERN_CONT " 0x%x", cmd->bytes[i]);
296 chip->shadow.bytes[i+cmd->bytes[0]] = cmd->bytes[i];
297 }
298 if (debug)
299 printk(KERN_CONT "\n");
300
301
302 rc = i2c_master_send(c, cmd->bytes, cmd->count);
303 if (rc != cmd->count) {
304 v4l2_warn(sd, "I/O error (%s)\n", name);
305 if (rc < 0)
306 return rc;
307 return -EIO;
308 }
309 return 0;
310}
311
312
313
314
315
316
317
318
319static void chip_thread_wake(struct timer_list *t)
320{
321 struct CHIPSTATE *chip = from_timer(chip, t, wt);
322 wake_up_process(chip->thread);
323}
324
325static int chip_thread(void *data)
326{
327 struct CHIPSTATE *chip = data;
328 struct CHIPDESC *desc = chip->desc;
329 struct v4l2_subdev *sd = &chip->sd;
330 int mode, selected;
331
332 v4l2_dbg(1, debug, sd, "thread started\n");
333 set_freezable();
334 for (;;) {
335 set_current_state(TASK_INTERRUPTIBLE);
336 if (!kthread_should_stop())
337 schedule();
338 set_current_state(TASK_RUNNING);
339 try_to_freeze();
340 if (kthread_should_stop())
341 break;
342 v4l2_dbg(1, debug, sd, "thread wakeup\n");
343
344
345 if (chip->radio)
346 continue;
347
348
349 mode = desc->getrxsubchans(chip);
350 if (mode == chip->prevmode)
351 continue;
352
353
354 v4l2_dbg(1, debug, sd, "thread checkmode\n");
355
356 chip->prevmode = mode;
357
358 selected = V4L2_TUNER_MODE_MONO;
359 switch (chip->audmode) {
360 case V4L2_TUNER_MODE_MONO:
361 if (mode & V4L2_TUNER_SUB_LANG1)
362 selected = V4L2_TUNER_MODE_LANG1;
363 break;
364 case V4L2_TUNER_MODE_STEREO:
365 case V4L2_TUNER_MODE_LANG1:
366 if (mode & V4L2_TUNER_SUB_LANG1)
367 selected = V4L2_TUNER_MODE_LANG1;
368 else if (mode & V4L2_TUNER_SUB_STEREO)
369 selected = V4L2_TUNER_MODE_STEREO;
370 break;
371 case V4L2_TUNER_MODE_LANG2:
372 if (mode & V4L2_TUNER_SUB_LANG2)
373 selected = V4L2_TUNER_MODE_LANG2;
374 else if (mode & V4L2_TUNER_SUB_STEREO)
375 selected = V4L2_TUNER_MODE_STEREO;
376 break;
377 case V4L2_TUNER_MODE_LANG1_LANG2:
378 if (mode & V4L2_TUNER_SUB_LANG2)
379 selected = V4L2_TUNER_MODE_LANG1_LANG2;
380 else if (mode & V4L2_TUNER_SUB_STEREO)
381 selected = V4L2_TUNER_MODE_STEREO;
382 }
383 desc->setaudmode(chip, selected);
384
385
386 mod_timer(&chip->wt, jiffies+msecs_to_jiffies(2000));
387 }
388
389 v4l2_dbg(1, debug, sd, "thread exiting\n");
390 return 0;
391}
392
393
394
395
396#define TDA9840_SW 0x00
397#define TDA9840_LVADJ 0x02
398#define TDA9840_STADJ 0x03
399#define TDA9840_TEST 0x04
400
401#define TDA9840_MONO 0x10
402#define TDA9840_STEREO 0x2a
403#define TDA9840_DUALA 0x12
404#define TDA9840_DUALB 0x1e
405#define TDA9840_DUALAB 0x1a
406#define TDA9840_DUALBA 0x16
407#define TDA9840_EXTERNAL 0x7a
408
409#define TDA9840_DS_DUAL 0x20
410#define TDA9840_ST_STEREO 0x40
411#define TDA9840_PONRES 0x80
412
413#define TDA9840_TEST_INT1SN 0x1
414#define TDA9840_TEST_INTFU 0x02
415
416static int tda9840_getrxsubchans(struct CHIPSTATE *chip)
417{
418 struct v4l2_subdev *sd = &chip->sd;
419 int val, mode;
420
421 mode = V4L2_TUNER_SUB_MONO;
422
423 val = chip_read(chip);
424 if (val < 0)
425 return mode;
426
427 if (val & TDA9840_DS_DUAL)
428 mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
429 if (val & TDA9840_ST_STEREO)
430 mode = V4L2_TUNER_SUB_STEREO;
431
432 v4l2_dbg(1, debug, sd,
433 "tda9840_getrxsubchans(): raw chip read: %d, return: %d\n",
434 val, mode);
435 return mode;
436}
437
438static void tda9840_setaudmode(struct CHIPSTATE *chip, int mode)
439{
440 int update = 1;
441 int t = chip->shadow.bytes[TDA9840_SW + 1] & ~0x7e;
442
443 switch (mode) {
444 case V4L2_TUNER_MODE_MONO:
445 t |= TDA9840_MONO;
446 break;
447 case V4L2_TUNER_MODE_STEREO:
448 t |= TDA9840_STEREO;
449 break;
450 case V4L2_TUNER_MODE_LANG1:
451 t |= TDA9840_DUALA;
452 break;
453 case V4L2_TUNER_MODE_LANG2:
454 t |= TDA9840_DUALB;
455 break;
456 case V4L2_TUNER_MODE_LANG1_LANG2:
457 t |= TDA9840_DUALAB;
458 break;
459 default:
460 update = 0;
461 }
462
463 if (update)
464 chip_write(chip, TDA9840_SW, t);
465}
466
467static int tda9840_checkit(struct CHIPSTATE *chip)
468{
469 int rc;
470
471 rc = chip_read(chip);
472 if (rc < 0)
473 return 0;
474
475
476
477 return ((rc & 0x1f) == 0) ? 1 : 0;
478}
479
480
481
482
483
484#define TDA9855_VR 0x00
485#define TDA9855_VL 0x01
486#define TDA9855_BA 0x02
487#define TDA9855_TR 0x03
488#define TDA9855_SW 0x04
489
490
491#define TDA9850_C4 0x04
492
493
494#define TDA985x_C5 0x05
495#define TDA985x_C6 0x06
496#define TDA985x_C7 0x07
497#define TDA985x_A1 0x08
498#define TDA985x_A2 0x09
499#define TDA985x_A3 0x0a
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530#define TDA9855_MUTE 1<<7
531#define TDA9855_AVL 1<<6
532#define TDA9855_LOUD 1<<5
533#define TDA9855_SUR 1<<3
534
535
536
537#define TDA9855_EXT 1<<2
538#define TDA9855_INT 0
539
540
541
542
543
544
545
546
547#define TDA985x_SAP 3<<6
548#define TDA985x_MONOSAP 2<<6
549#define TDA985x_STEREO 1<<6
550#define TDA985x_MONO 0
551#define TDA985x_LMU 1<<3
552
553
554#define TDA9855_TZCM 1<<5
555#define TDA9855_VZCM 1<<4
556#define TDA9855_LINEAR 0
557#define TDA9855_PSEUDO 1
558#define TDA9855_SPAT_30 2
559#define TDA9855_SPAT_50 3
560#define TDA9855_E_MONO 7
561
562
563
564
565
566
567
568
569
570
571#define TDA985x_STP 1<<5
572#define TDA985x_SAPP 1<<6
573#define TDA985x_STS 1<<7
574
575
576
577
578
579#define TDA985x_ADJ 1<<7
580
581static int tda9855_volume(int val) { return val/0x2e8+0x27; }
582static int tda9855_bass(int val) { return val/0xccc+0x06; }
583static int tda9855_treble(int val) { return (val/0x1c71+0x3)<<1; }
584
585static int tda985x_getrxsubchans(struct CHIPSTATE *chip)
586{
587 int mode, val;
588
589
590
591 mode = V4L2_TUNER_SUB_MONO;
592 val = chip_read(chip);
593 if (val < 0)
594 return mode;
595
596 if (val & TDA985x_STP)
597 mode = V4L2_TUNER_SUB_STEREO;
598 if (val & TDA985x_SAPP)
599 mode |= V4L2_TUNER_SUB_SAP;
600 return mode;
601}
602
603static void tda985x_setaudmode(struct CHIPSTATE *chip, int mode)
604{
605 int update = 1;
606 int c6 = chip->shadow.bytes[TDA985x_C6+1] & 0x3f;
607
608 switch (mode) {
609 case V4L2_TUNER_MODE_MONO:
610 c6 |= TDA985x_MONO;
611 break;
612 case V4L2_TUNER_MODE_STEREO:
613 case V4L2_TUNER_MODE_LANG1:
614 c6 |= TDA985x_STEREO;
615 break;
616 case V4L2_TUNER_MODE_SAP:
617 c6 |= TDA985x_SAP;
618 break;
619 case V4L2_TUNER_MODE_LANG1_LANG2:
620 c6 |= TDA985x_MONOSAP;
621 break;
622 default:
623 update = 0;
624 }
625 if (update)
626 chip_write(chip,TDA985x_C6,c6);
627}
628
629
630
631
632
633
634
635#define TDA9873_SW 0x00
636#define TDA9873_AD 0x01
637#define TDA9873_PT 0x02
638
639
640
641
642
643
644
645
646
647#define TDA9873_INP_MASK 3
648#define TDA9873_INTERNAL 0
649#define TDA9873_EXT_STEREO 2
650#define TDA9873_EXT_MONO 1
651
652
653
654
655
656
657
658
659
660
661
662
663#define TDA9873_TR_MASK (7 << 2)
664#define TDA9873_TR_MONO 4
665#define TDA9873_TR_STEREO 1 << 4
666#define TDA9873_TR_REVERSE ((1 << 3) | (1 << 2))
667#define TDA9873_TR_DUALA 1 << 2
668#define TDA9873_TR_DUALB 1 << 3
669#define TDA9873_TR_DUALAB 0
670
671
672
673
674
675
676
677#define TDA9873_GAIN_NORMAL 1 << 5
678#define TDA9873_MUTE 1 << 6
679#define TDA9873_AUTOMUTE 1 << 7
680
681
682
683
684
685
686
687#define TDA9873_STEREO_ADJ 0x06
688
689
690
691
692
693
694
695
696
697
698#define TDA9873_BG 0
699#define TDA9873_M 1
700#define TDA9873_DK1 2
701#define TDA9873_DK2 3
702#define TDA9873_DK3 4
703#define TDA9873_I 5
704
705
706
707#define TDA9873_IDR_NORM 0
708#define TDA9873_IDR_FAST 1 << 7
709
710
711
712
713
714
715
716
717
718
719
720#define TDA9873_PORTS 3
721
722
723#define TDA9873_TST_PORT 1 << 2
724
725
726
727
728
729
730
731
732#define TDA9873_MOUT_MONO 0
733#define TDA9873_MOUT_FMONO 0
734#define TDA9873_MOUT_DUALA 0
735#define TDA9873_MOUT_DUALB 1 << 3
736#define TDA9873_MOUT_ST 1 << 4
737#define TDA9873_MOUT_EXTM ((1 << 4) | (1 << 3))
738#define TDA9873_MOUT_EXTL 1 << 5
739#define TDA9873_MOUT_EXTR ((1 << 5) | (1 << 3))
740#define TDA9873_MOUT_EXTLR ((1 << 5) | (1 << 4))
741#define TDA9873_MOUT_MUTE ((1 << 5) | (1 << 4) | (1 << 3))
742
743
744#define TDA9873_PONR 0
745#define TDA9873_STEREO 2
746#define TDA9873_DUAL 4
747
748static int tda9873_getrxsubchans(struct CHIPSTATE *chip)
749{
750 struct v4l2_subdev *sd = &chip->sd;
751 int val,mode;
752
753 mode = V4L2_TUNER_SUB_MONO;
754
755 val = chip_read(chip);
756 if (val < 0)
757 return mode;
758
759 if (val & TDA9873_STEREO)
760 mode = V4L2_TUNER_SUB_STEREO;
761 if (val & TDA9873_DUAL)
762 mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
763 v4l2_dbg(1, debug, sd,
764 "tda9873_getrxsubchans(): raw chip read: %d, return: %d\n",
765 val, mode);
766 return mode;
767}
768
769static void tda9873_setaudmode(struct CHIPSTATE *chip, int mode)
770{
771 struct v4l2_subdev *sd = &chip->sd;
772 int sw_data = chip->shadow.bytes[TDA9873_SW+1] & ~ TDA9873_TR_MASK;
773
774
775 if ((sw_data & TDA9873_INP_MASK) != TDA9873_INTERNAL) {
776 v4l2_dbg(1, debug, sd,
777 "tda9873_setaudmode(): external input\n");
778 return;
779 }
780
781 v4l2_dbg(1, debug, sd,
782 "tda9873_setaudmode(): chip->shadow.bytes[%d] = %d\n",
783 TDA9873_SW+1, chip->shadow.bytes[TDA9873_SW+1]);
784 v4l2_dbg(1, debug, sd, "tda9873_setaudmode(): sw_data = %d\n",
785 sw_data);
786
787 switch (mode) {
788 case V4L2_TUNER_MODE_MONO:
789 sw_data |= TDA9873_TR_MONO;
790 break;
791 case V4L2_TUNER_MODE_STEREO:
792 sw_data |= TDA9873_TR_STEREO;
793 break;
794 case V4L2_TUNER_MODE_LANG1:
795 sw_data |= TDA9873_TR_DUALA;
796 break;
797 case V4L2_TUNER_MODE_LANG2:
798 sw_data |= TDA9873_TR_DUALB;
799 break;
800 case V4L2_TUNER_MODE_LANG1_LANG2:
801 sw_data |= TDA9873_TR_DUALAB;
802 break;
803 default:
804 return;
805 }
806
807 chip_write(chip, TDA9873_SW, sw_data);
808 v4l2_dbg(1, debug, sd,
809 "tda9873_setaudmode(): req. mode %d; chip_write: %d\n",
810 mode, sw_data);
811}
812
813static int tda9873_checkit(struct CHIPSTATE *chip)
814{
815 int rc;
816
817 rc = chip_read2(chip, 254);
818 if (rc < 0)
819 return 0;
820 return (rc & ~0x1f) == 0x80;
821}
822
823
824
825
826
827
828
829#define TDA9874A_AGCGR 0x00
830#define TDA9874A_GCONR 0x01
831#define TDA9874A_MSR 0x02
832#define TDA9874A_C1FRA 0x03
833#define TDA9874A_C1FRB 0x04
834#define TDA9874A_C1FRC 0x05
835#define TDA9874A_C2FRA 0x06
836#define TDA9874A_C2FRB 0x07
837#define TDA9874A_C2FRC 0x08
838#define TDA9874A_DCR 0x09
839#define TDA9874A_FMER 0x0a
840#define TDA9874A_FMMR 0x0b
841#define TDA9874A_C1OLAR 0x0c
842#define TDA9874A_C2OLAR 0x0d
843#define TDA9874A_NCONR 0x0e
844#define TDA9874A_NOLAR 0x0f
845#define TDA9874A_NLELR 0x10
846#define TDA9874A_NUELR 0x11
847#define TDA9874A_AMCONR 0x12
848#define TDA9874A_SDACOSR 0x13
849#define TDA9874A_AOSR 0x14
850#define TDA9874A_DAICONR 0x15
851#define TDA9874A_I2SOSR 0x16
852#define TDA9874A_I2SOLAR 0x17
853#define TDA9874A_MDACOSR 0x18
854#define TDA9874A_ESP 0xFF
855
856
857#define TDA9874A_DSR 0x00
858#define TDA9874A_NSR 0x01
859#define TDA9874A_NECR 0x02
860#define TDA9874A_DR1 0x03
861#define TDA9874A_DR2 0x04
862#define TDA9874A_LLRA 0x05
863#define TDA9874A_LLRB 0x06
864#define TDA9874A_SIFLR 0x07
865#define TDA9874A_TR2 252
866#define TDA9874A_TR1 253
867#define TDA9874A_DIC 254
868#define TDA9874A_SIC 255
869
870
871static int tda9874a_mode = 1;
872static int tda9874a_GCONR = 0xc0;
873static int tda9874a_NCONR = 0x01;
874static int tda9874a_ESP = 0x07;
875static int tda9874a_dic = -1;
876
877
878static unsigned int tda9874a_SIF = UNSET;
879static unsigned int tda9874a_AMSEL = UNSET;
880static unsigned int tda9874a_STD = UNSET;
881module_param(tda9874a_SIF, int, 0444);
882module_param(tda9874a_AMSEL, int, 0444);
883module_param(tda9874a_STD, int, 0444);
884
885
886
887
888
889
890
891
892
893static struct tda9874a_MODES {
894 char *name;
895 audiocmd cmd;
896} tda9874a_modelist[9] = {
897 { "A2, B/G",
898 { 9, { TDA9874A_C1FRA, 0x72,0x95,0x55, 0x77,0xA0,0x00, 0x00,0x00 }} },
899 { "A2, M (Korea)",
900 { 9, { TDA9874A_C1FRA, 0x5D,0xC0,0x00, 0x62,0x6A,0xAA, 0x20,0x22 }} },
901 { "A2, D/K (1)",
902 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x82,0x60,0x00, 0x00,0x00 }} },
903 { "A2, D/K (2)",
904 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x8C,0x75,0x55, 0x00,0x00 }} },
905 { "A2, D/K (3)",
906 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x77,0xA0,0x00, 0x00,0x00 }} },
907 { "NICAM, I",
908 { 9, { TDA9874A_C1FRA, 0x7D,0x00,0x00, 0x88,0x8A,0xAA, 0x08,0x33 }} },
909 { "NICAM, B/G",
910 { 9, { TDA9874A_C1FRA, 0x72,0x95,0x55, 0x79,0xEA,0xAA, 0x08,0x33 }} },
911 { "NICAM, D/K",
912 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x79,0xEA,0xAA, 0x08,0x33 }} },
913 { "NICAM, L",
914 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x79,0xEA,0xAA, 0x09,0x33 }} }
915};
916
917static int tda9874a_setup(struct CHIPSTATE *chip)
918{
919 struct v4l2_subdev *sd = &chip->sd;
920
921 chip_write(chip, TDA9874A_AGCGR, 0x00);
922 chip_write(chip, TDA9874A_GCONR, tda9874a_GCONR);
923 chip_write(chip, TDA9874A_MSR, (tda9874a_mode) ? 0x03:0x02);
924 if(tda9874a_dic == 0x11) {
925 chip_write(chip, TDA9874A_FMMR, 0x80);
926 } else {
927 chip_cmd(chip,"tda9874_modelist",&tda9874a_modelist[tda9874a_STD].cmd);
928 chip_write(chip, TDA9874A_FMMR, 0x00);
929 }
930 chip_write(chip, TDA9874A_C1OLAR, 0x00);
931 chip_write(chip, TDA9874A_C2OLAR, 0x00);
932 chip_write(chip, TDA9874A_NCONR, tda9874a_NCONR);
933 chip_write(chip, TDA9874A_NOLAR, 0x00);
934
935
936
937 chip_write(chip, TDA9874A_NLELR, 0x14);
938 chip_write(chip, TDA9874A_NUELR, 0x50);
939
940 if(tda9874a_dic == 0x11) {
941 chip_write(chip, TDA9874A_AMCONR, 0xf9);
942 chip_write(chip, TDA9874A_SDACOSR, (tda9874a_mode) ? 0x81:0x80);
943 chip_write(chip, TDA9874A_AOSR, 0x80);
944 chip_write(chip, TDA9874A_MDACOSR, (tda9874a_mode) ? 0x82:0x80);
945 chip_write(chip, TDA9874A_ESP, tda9874a_ESP);
946 } else {
947 chip_write(chip, TDA9874A_AMCONR, 0xfb);
948 chip_write(chip, TDA9874A_SDACOSR, (tda9874a_mode) ? 0x81:0x80);
949 chip_write(chip, TDA9874A_AOSR, 0x00);
950 }
951 v4l2_dbg(1, debug, sd, "tda9874a_setup(): %s [0x%02X].\n",
952 tda9874a_modelist[tda9874a_STD].name,tda9874a_STD);
953 return 1;
954}
955
956static int tda9874a_getrxsubchans(struct CHIPSTATE *chip)
957{
958 struct v4l2_subdev *sd = &chip->sd;
959 int dsr,nsr,mode;
960 int necr;
961
962 mode = V4L2_TUNER_SUB_MONO;
963
964 dsr = chip_read2(chip, TDA9874A_DSR);
965 if (dsr < 0)
966 return mode;
967 nsr = chip_read2(chip, TDA9874A_NSR);
968 if (nsr < 0)
969 return mode;
970 necr = chip_read2(chip, TDA9874A_NECR);
971 if (necr < 0)
972 return mode;
973
974
975 chip->shadow.bytes[MAXREGS-2] = dsr;
976 chip->shadow.bytes[MAXREGS-1] = nsr;
977
978 if(tda9874a_mode) {
979
980
981
982
983
984
985
986
987 if(nsr & 0x02)
988 mode = V4L2_TUNER_SUB_STEREO;
989 if(nsr & 0x01)
990 mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
991 } else {
992 if(dsr & 0x02)
993 mode = V4L2_TUNER_SUB_STEREO;
994 if(dsr & 0x04)
995 mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
996 }
997
998 v4l2_dbg(1, debug, sd,
999 "tda9874a_getrxsubchans(): DSR=0x%X, NSR=0x%X, NECR=0x%X, return: %d.\n",
1000 dsr, nsr, necr, mode);
1001 return mode;
1002}
1003
1004static void tda9874a_setaudmode(struct CHIPSTATE *chip, int mode)
1005{
1006 struct v4l2_subdev *sd = &chip->sd;
1007
1008
1009
1010 if (tda9874a_mode) {
1011 if(chip->shadow.bytes[MAXREGS-2] & 0x20)
1012 tda9874a_NCONR &= 0xfe;
1013 else
1014 tda9874a_NCONR |= 0x01;
1015 chip_write(chip, TDA9874A_NCONR, tda9874a_NCONR);
1016 }
1017
1018
1019
1020
1021
1022
1023
1024 if(tda9874a_dic == 0x11) {
1025 int aosr = 0x80;
1026 int mdacosr = (tda9874a_mode) ? 0x82:0x80;
1027
1028 switch(mode) {
1029 case V4L2_TUNER_MODE_MONO:
1030 case V4L2_TUNER_MODE_STEREO:
1031 break;
1032 case V4L2_TUNER_MODE_LANG1:
1033 aosr = 0x80;
1034 mdacosr = (tda9874a_mode) ? 0x82:0x80;
1035 break;
1036 case V4L2_TUNER_MODE_LANG2:
1037 aosr = 0xa0;
1038 mdacosr = (tda9874a_mode) ? 0x83:0x81;
1039 break;
1040 case V4L2_TUNER_MODE_LANG1_LANG2:
1041 aosr = 0x00;
1042 mdacosr = (tda9874a_mode) ? 0x82:0x80;
1043 break;
1044 default:
1045 return;
1046 }
1047 chip_write(chip, TDA9874A_AOSR, aosr);
1048 chip_write(chip, TDA9874A_MDACOSR, mdacosr);
1049
1050 v4l2_dbg(1, debug, sd,
1051 "tda9874a_setaudmode(): req. mode %d; AOSR=0x%X, MDACOSR=0x%X.\n",
1052 mode, aosr, mdacosr);
1053
1054 } else {
1055 int fmmr,aosr;
1056
1057 switch(mode) {
1058 case V4L2_TUNER_MODE_MONO:
1059 fmmr = 0x00;
1060 aosr = 0x10;
1061 break;
1062 case V4L2_TUNER_MODE_STEREO:
1063 if(tda9874a_mode) {
1064 fmmr = 0x00;
1065 aosr = 0x00;
1066 } else {
1067 fmmr = (tda9874a_ESP == 1) ? 0x05 : 0x04;
1068 aosr = 0x00;
1069 }
1070 break;
1071 case V4L2_TUNER_MODE_LANG1:
1072 fmmr = 0x02;
1073 aosr = 0x10;
1074 break;
1075 case V4L2_TUNER_MODE_LANG2:
1076 fmmr = 0x02;
1077 aosr = 0x20;
1078 break;
1079 case V4L2_TUNER_MODE_LANG1_LANG2:
1080 fmmr = 0x02;
1081 aosr = 0x00;
1082 break;
1083 default:
1084 return;
1085 }
1086 chip_write(chip, TDA9874A_FMMR, fmmr);
1087 chip_write(chip, TDA9874A_AOSR, aosr);
1088
1089 v4l2_dbg(1, debug, sd,
1090 "tda9874a_setaudmode(): req. mode %d; FMMR=0x%X, AOSR=0x%X.\n",
1091 mode, fmmr, aosr);
1092 }
1093}
1094
1095static int tda9874a_checkit(struct CHIPSTATE *chip)
1096{
1097 struct v4l2_subdev *sd = &chip->sd;
1098 int dic,sic;
1099
1100 dic = chip_read2(chip, TDA9874A_DIC);
1101 if (dic < 0)
1102 return 0;
1103 sic = chip_read2(chip, TDA9874A_SIC);
1104 if (sic < 0)
1105 return 0;
1106
1107 v4l2_dbg(1, debug, sd, "tda9874a_checkit(): DIC=0x%X, SIC=0x%X.\n", dic, sic);
1108
1109 if((dic == 0x11)||(dic == 0x07)) {
1110 v4l2_info(sd, "found tda9874%s.\n", (dic == 0x11) ? "a" : "h");
1111 tda9874a_dic = dic;
1112 return 1;
1113 }
1114 return 0;
1115}
1116
1117static int tda9874a_initialize(struct CHIPSTATE *chip)
1118{
1119 if (tda9874a_SIF > 2)
1120 tda9874a_SIF = 1;
1121 if (tda9874a_STD >= ARRAY_SIZE(tda9874a_modelist))
1122 tda9874a_STD = 0;
1123 if(tda9874a_AMSEL > 1)
1124 tda9874a_AMSEL = 0;
1125
1126 if(tda9874a_SIF == 1)
1127 tda9874a_GCONR = 0xc0;
1128 else
1129 tda9874a_GCONR = 0xc1;
1130
1131 tda9874a_ESP = tda9874a_STD;
1132 tda9874a_mode = (tda9874a_STD < 5) ? 0 : 1;
1133
1134 if(tda9874a_AMSEL == 0)
1135 tda9874a_NCONR = 0x01;
1136 else
1137 tda9874a_NCONR = 0x05;
1138
1139 tda9874a_setup(chip);
1140 return 0;
1141}
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152#define TDA9875_MUT 0x12
1153#define TDA9875_CFG 0x01
1154#define TDA9875_DACOS 0x13
1155#define TDA9875_LOSR 0x16
1156
1157#define TDA9875_CH1V 0x0c
1158#define TDA9875_CH2V 0x0d
1159#define TDA9875_SC1 0x14
1160#define TDA9875_SC2 0x15
1161
1162#define TDA9875_ADCIS 0x17
1163#define TDA9875_AER 0x19
1164#define TDA9875_MCS 0x18
1165#define TDA9875_MVL 0x1a
1166#define TDA9875_MVR 0x1b
1167#define TDA9875_MBA 0x1d
1168#define TDA9875_MTR 0x1e
1169#define TDA9875_ACS 0x1f
1170#define TDA9875_AVL 0x20
1171#define TDA9875_AVR 0x21
1172#define TDA9875_ABA 0x22
1173#define TDA9875_ATR 0x23
1174
1175#define TDA9875_MSR 0x02
1176#define TDA9875_C1MSB 0x03
1177#define TDA9875_C1MIB 0x04
1178#define TDA9875_C1LSB 0x05
1179#define TDA9875_C2MSB 0x06
1180#define TDA9875_C2MIB 0x07
1181#define TDA9875_C2LSB 0x08
1182#define TDA9875_DCR 0x09
1183#define TDA9875_DEEM 0x0a
1184#define TDA9875_FMAT 0x0b
1185
1186
1187#define TDA9875_MUTE_ON 0xff
1188#define TDA9875_MUTE_OFF 0xcc
1189
1190static int tda9875_initialize(struct CHIPSTATE *chip)
1191{
1192 chip_write(chip, TDA9875_CFG, 0xd0);
1193 chip_write(chip, TDA9875_MSR, 0x03);
1194 chip_write(chip, TDA9875_C1MSB, 0x00);
1195 chip_write(chip, TDA9875_C1MIB, 0x00);
1196 chip_write(chip, TDA9875_C1LSB, 0x00);
1197 chip_write(chip, TDA9875_C2MSB, 0x00);
1198 chip_write(chip, TDA9875_C2MIB, 0x00);
1199 chip_write(chip, TDA9875_C2LSB, 0x00);
1200 chip_write(chip, TDA9875_DCR, 0x00);
1201 chip_write(chip, TDA9875_DEEM, 0x44);
1202 chip_write(chip, TDA9875_FMAT, 0x00);
1203 chip_write(chip, TDA9875_SC1, 0x00);
1204 chip_write(chip, TDA9875_SC2, 0x01);
1205
1206 chip_write(chip, TDA9875_CH1V, 0x10);
1207 chip_write(chip, TDA9875_CH2V, 0x10);
1208 chip_write(chip, TDA9875_DACOS, 0x02);
1209 chip_write(chip, TDA9875_ADCIS, 0x6f);
1210 chip_write(chip, TDA9875_LOSR, 0x00);
1211 chip_write(chip, TDA9875_AER, 0x00);
1212 chip_write(chip, TDA9875_MCS, 0x44);
1213 chip_write(chip, TDA9875_MVL, 0x03);
1214 chip_write(chip, TDA9875_MVR, 0x03);
1215 chip_write(chip, TDA9875_MBA, 0x00);
1216 chip_write(chip, TDA9875_MTR, 0x00);
1217 chip_write(chip, TDA9875_ACS, 0x44);
1218 chip_write(chip, TDA9875_AVL, 0x00);
1219 chip_write(chip, TDA9875_AVR, 0x00);
1220 chip_write(chip, TDA9875_ABA, 0x00);
1221 chip_write(chip, TDA9875_ATR, 0x00);
1222
1223 chip_write(chip, TDA9875_MUT, 0xcc);
1224 return 0;
1225}
1226
1227static int tda9875_volume(int val) { return (unsigned char)(val / 602 - 84); }
1228static int tda9875_bass(int val) { return (unsigned char)(max(-12, val / 2115 - 15)); }
1229static int tda9875_treble(int val) { return (unsigned char)(val / 2622 - 12); }
1230
1231
1232
1233
1234
1235
1236
1237
1238static int tda9875_checkit(struct CHIPSTATE *chip)
1239{
1240 struct v4l2_subdev *sd = &chip->sd;
1241 int dic, rev;
1242
1243 dic = chip_read2(chip, 254);
1244 if (dic < 0)
1245 return 0;
1246 rev = chip_read2(chip, 255);
1247 if (rev < 0)
1248 return 0;
1249
1250 if (dic == 0 || dic == 2) {
1251 v4l2_info(sd, "found tda9875%s rev. %d.\n",
1252 dic == 0 ? "" : "A", rev);
1253 return 1;
1254 }
1255 return 0;
1256}
1257
1258
1259
1260
1261#define TEA6300_VL 0x00
1262#define TEA6300_VR 0x01
1263#define TEA6300_BA 0x02
1264#define TEA6300_TR 0x03
1265#define TEA6300_FA 0x04
1266#define TEA6300_S 0x05
1267
1268#define TEA6300_S_SA 0x01
1269#define TEA6300_S_SB 0x02
1270#define TEA6300_S_SC 0x04
1271#define TEA6300_S_GMU 0x80
1272
1273#define TEA6320_V 0x00
1274#define TEA6320_FFR 0x01
1275#define TEA6320_FFL 0x02
1276#define TEA6320_FRR 0x03
1277#define TEA6320_FRL 0x04
1278#define TEA6320_BA 0x05
1279#define TEA6320_TR 0x06
1280#define TEA6320_S 0x07
1281
1282#define TEA6320_S_SA 0x07
1283#define TEA6320_S_SB 0x06
1284#define TEA6320_S_SC 0x05
1285#define TEA6320_S_SD 0x04
1286#define TEA6320_S_GMU 0x80
1287
1288#define TEA6420_S_SA 0x00
1289#define TEA6420_S_SB 0x01
1290#define TEA6420_S_SC 0x02
1291#define TEA6420_S_SD 0x03
1292#define TEA6420_S_SE 0x04
1293#define TEA6420_S_GMU 0x05
1294
1295static int tea6300_shift10(int val) { return val >> 10; }
1296static int tea6300_shift12(int val) { return val >> 12; }
1297
1298
1299
1300static int tea6320_volume(int val) { return (val / (65535/(63-12)) + 12) & 0x3f; }
1301static int tea6320_shift11(int val) { return val >> 11; }
1302static int tea6320_initialize(struct CHIPSTATE * chip)
1303{
1304 chip_write(chip, TEA6320_FFR, 0x3f);
1305 chip_write(chip, TEA6320_FFL, 0x3f);
1306 chip_write(chip, TEA6320_FRR, 0x3f);
1307 chip_write(chip, TEA6320_FRL, 0x3f);
1308
1309 return 0;
1310}
1311
1312
1313
1314
1315
1316#define TDA8425_VL 0x00
1317#define TDA8425_VR 0x01
1318#define TDA8425_BA 0x02
1319#define TDA8425_TR 0x03
1320#define TDA8425_S1 0x08
1321
1322#define TDA8425_S1_OFF 0xEE
1323#define TDA8425_S1_CH1 0xCE
1324#define TDA8425_S1_CH2 0xCF
1325#define TDA8425_S1_MU 0x20
1326#define TDA8425_S1_STEREO 0x18
1327#define TDA8425_S1_STEREO_SPATIAL 0x18
1328#define TDA8425_S1_STEREO_LINEAR 0x08
1329#define TDA8425_S1_STEREO_PSEUDO 0x10
1330#define TDA8425_S1_STEREO_MONO 0x00
1331#define TDA8425_S1_ML 0x06
1332#define TDA8425_S1_ML_SOUND_A 0x02
1333#define TDA8425_S1_ML_SOUND_B 0x04
1334#define TDA8425_S1_ML_STEREO 0x06
1335#define TDA8425_S1_IS 0x01
1336
1337
1338static int tda8425_shift10(int val) { return (val >> 10) | 0xc0; }
1339static int tda8425_shift12(int val) { return (val >> 12) | 0xf0; }
1340
1341static void tda8425_setaudmode(struct CHIPSTATE *chip, int mode)
1342{
1343 int s1 = chip->shadow.bytes[TDA8425_S1+1] & 0xe1;
1344
1345 switch (mode) {
1346 case V4L2_TUNER_MODE_LANG1:
1347 s1 |= TDA8425_S1_ML_SOUND_A;
1348 s1 |= TDA8425_S1_STEREO_PSEUDO;
1349 break;
1350 case V4L2_TUNER_MODE_LANG2:
1351 s1 |= TDA8425_S1_ML_SOUND_B;
1352 s1 |= TDA8425_S1_STEREO_PSEUDO;
1353 break;
1354 case V4L2_TUNER_MODE_LANG1_LANG2:
1355 s1 |= TDA8425_S1_ML_STEREO;
1356 s1 |= TDA8425_S1_STEREO_LINEAR;
1357 break;
1358 case V4L2_TUNER_MODE_MONO:
1359 s1 |= TDA8425_S1_ML_STEREO;
1360 s1 |= TDA8425_S1_STEREO_MONO;
1361 break;
1362 case V4L2_TUNER_MODE_STEREO:
1363 s1 |= TDA8425_S1_ML_STEREO;
1364 s1 |= TDA8425_S1_STEREO_SPATIAL;
1365 break;
1366 default:
1367 return;
1368 }
1369 chip_write(chip,TDA8425_S1,s1);
1370}
1371
1372
1373
1374
1375
1376
1377#define PIC16C54_REG_KEY_CODE 0x01
1378#define PIC16C54_REG_MISC 0x02
1379
1380
1381#define PIC16C54_MISC_RESET_REMOTE_CTL 0x01
1382
1383#define PIC16C54_MISC_MTS_MAIN 0x02
1384#define PIC16C54_MISC_MTS_SAP 0x04
1385#define PIC16C54_MISC_MTS_BOTH 0x08
1386#define PIC16C54_MISC_SND_MUTE 0x10
1387#define PIC16C54_MISC_SND_NOTMUTE 0x20
1388#define PIC16C54_MISC_SWITCH_TUNER 0x40
1389#define PIC16C54_MISC_SWITCH_LINE 0x80
1390
1391
1392
1393
1394
1395#define TA8874Z_LED_STE 0x80
1396#define TA8874Z_LED_BIL 0x40
1397#define TA8874Z_LED_EXT 0x20
1398#define TA8874Z_MONO_SET 0x10
1399#define TA8874Z_MUTE 0x08
1400#define TA8874Z_F_MONO 0x04
1401#define TA8874Z_MODE_SUB 0x02
1402#define TA8874Z_MODE_MAIN 0x01
1403
1404
1405
1406#define TA8874Z_SEPARATION 0x3f
1407#define TA8874Z_SEPARATION_DEFAULT 0x10
1408
1409
1410#define TA8874Z_B1 0x80
1411#define TA8874Z_B0 0x40
1412#define TA8874Z_CHAG_FLAG 0x20
1413
1414
1415
1416
1417
1418
1419
1420static int ta8874z_getrxsubchans(struct CHIPSTATE *chip)
1421{
1422 int val, mode;
1423
1424 mode = V4L2_TUNER_SUB_MONO;
1425
1426 val = chip_read(chip);
1427 if (val < 0)
1428 return mode;
1429
1430 if (val & TA8874Z_B1){
1431 mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
1432 }else if (!(val & TA8874Z_B0)){
1433 mode = V4L2_TUNER_SUB_STEREO;
1434 }
1435
1436
1437
1438 return mode;
1439}
1440
1441static audiocmd ta8874z_stereo = { 2, {0, TA8874Z_SEPARATION_DEFAULT}};
1442static audiocmd ta8874z_mono = {2, { TA8874Z_MONO_SET, TA8874Z_SEPARATION_DEFAULT}};
1443static audiocmd ta8874z_main = {2, { 0, TA8874Z_SEPARATION_DEFAULT}};
1444static audiocmd ta8874z_sub = {2, { TA8874Z_MODE_SUB, TA8874Z_SEPARATION_DEFAULT}};
1445static audiocmd ta8874z_both = {2, { TA8874Z_MODE_MAIN | TA8874Z_MODE_SUB, TA8874Z_SEPARATION_DEFAULT}};
1446
1447static void ta8874z_setaudmode(struct CHIPSTATE *chip, int mode)
1448{
1449 struct v4l2_subdev *sd = &chip->sd;
1450 int update = 1;
1451 audiocmd *t = NULL;
1452
1453 v4l2_dbg(1, debug, sd, "ta8874z_setaudmode(): mode: 0x%02x\n", mode);
1454
1455 switch(mode){
1456 case V4L2_TUNER_MODE_MONO:
1457 t = &ta8874z_mono;
1458 break;
1459 case V4L2_TUNER_MODE_STEREO:
1460 t = &ta8874z_stereo;
1461 break;
1462 case V4L2_TUNER_MODE_LANG1:
1463 t = &ta8874z_main;
1464 break;
1465 case V4L2_TUNER_MODE_LANG2:
1466 t = &ta8874z_sub;
1467 break;
1468 case V4L2_TUNER_MODE_LANG1_LANG2:
1469 t = &ta8874z_both;
1470 break;
1471 default:
1472 update = 0;
1473 }
1474
1475 if(update)
1476 chip_cmd(chip, "TA8874Z", t);
1477}
1478
1479static int ta8874z_checkit(struct CHIPSTATE *chip)
1480{
1481 int rc;
1482
1483 rc = chip_read(chip);
1484 if (rc < 0)
1485 return rc;
1486
1487 return ((rc & 0x1f) == 0x1f) ? 1 : 0;
1488}
1489
1490
1491
1492
1493
1494static int tda8425 = 1;
1495static int tda9840 = 1;
1496static int tda9850 = 1;
1497static int tda9855 = 1;
1498static int tda9873 = 1;
1499static int tda9874a = 1;
1500static int tda9875 = 1;
1501static int tea6300;
1502static int tea6320;
1503static int tea6420 = 1;
1504static int pic16c54 = 1;
1505static int ta8874z;
1506
1507module_param(tda8425, int, 0444);
1508module_param(tda9840, int, 0444);
1509module_param(tda9850, int, 0444);
1510module_param(tda9855, int, 0444);
1511module_param(tda9873, int, 0444);
1512module_param(tda9874a, int, 0444);
1513module_param(tda9875, int, 0444);
1514module_param(tea6300, int, 0444);
1515module_param(tea6320, int, 0444);
1516module_param(tea6420, int, 0444);
1517module_param(pic16c54, int, 0444);
1518module_param(ta8874z, int, 0444);
1519
1520static struct CHIPDESC chiplist[] = {
1521 {
1522 .name = "tda9840",
1523 .insmodopt = &tda9840,
1524 .addr_lo = I2C_ADDR_TDA9840 >> 1,
1525 .addr_hi = I2C_ADDR_TDA9840 >> 1,
1526 .registers = 5,
1527 .flags = CHIP_NEED_CHECKMODE,
1528
1529
1530 .checkit = tda9840_checkit,
1531 .getrxsubchans = tda9840_getrxsubchans,
1532 .setaudmode = tda9840_setaudmode,
1533
1534 .init = { 2, { TDA9840_TEST, TDA9840_TEST_INT1SN
1535 } }
1536 },
1537 {
1538 .name = "tda9873h",
1539 .insmodopt = &tda9873,
1540 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1541 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1542 .registers = 3,
1543 .flags = CHIP_HAS_INPUTSEL | CHIP_NEED_CHECKMODE,
1544
1545
1546 .checkit = tda9873_checkit,
1547 .getrxsubchans = tda9873_getrxsubchans,
1548 .setaudmode = tda9873_setaudmode,
1549
1550 .init = { 4, { TDA9873_SW, 0xa4, 0x06, 0x03 } },
1551 .inputreg = TDA9873_SW,
1552 .inputmute = TDA9873_MUTE | TDA9873_AUTOMUTE,
1553 .inputmap = {0xa0, 0xa2, 0xa0, 0xa0},
1554 .inputmask = TDA9873_INP_MASK|TDA9873_MUTE|TDA9873_AUTOMUTE,
1555
1556 },
1557 {
1558 .name = "tda9874h/a",
1559 .insmodopt = &tda9874a,
1560 .addr_lo = I2C_ADDR_TDA9874 >> 1,
1561 .addr_hi = I2C_ADDR_TDA9874 >> 1,
1562 .flags = CHIP_NEED_CHECKMODE,
1563
1564
1565 .initialize = tda9874a_initialize,
1566 .checkit = tda9874a_checkit,
1567 .getrxsubchans = tda9874a_getrxsubchans,
1568 .setaudmode = tda9874a_setaudmode,
1569 },
1570 {
1571 .name = "tda9875",
1572 .insmodopt = &tda9875,
1573 .addr_lo = I2C_ADDR_TDA9875 >> 1,
1574 .addr_hi = I2C_ADDR_TDA9875 >> 1,
1575 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE,
1576
1577
1578 .initialize = tda9875_initialize,
1579 .checkit = tda9875_checkit,
1580 .volfunc = tda9875_volume,
1581 .bassfunc = tda9875_bass,
1582 .treblefunc = tda9875_treble,
1583 .leftreg = TDA9875_MVL,
1584 .rightreg = TDA9875_MVR,
1585 .bassreg = TDA9875_MBA,
1586 .treblereg = TDA9875_MTR,
1587 .volinit = 58880,
1588 },
1589 {
1590 .name = "tda9850",
1591 .insmodopt = &tda9850,
1592 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1593 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1594 .registers = 11,
1595
1596 .getrxsubchans = tda985x_getrxsubchans,
1597 .setaudmode = tda985x_setaudmode,
1598
1599 .init = { 8, { TDA9850_C4, 0x08, 0x08, TDA985x_STEREO, 0x07, 0x10, 0x10, 0x03 } }
1600 },
1601 {
1602 .name = "tda9855",
1603 .insmodopt = &tda9855,
1604 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1605 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1606 .registers = 11,
1607 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE,
1608
1609 .leftreg = TDA9855_VL,
1610 .rightreg = TDA9855_VR,
1611 .bassreg = TDA9855_BA,
1612 .treblereg = TDA9855_TR,
1613
1614
1615 .volfunc = tda9855_volume,
1616 .bassfunc = tda9855_bass,
1617 .treblefunc = tda9855_treble,
1618 .getrxsubchans = tda985x_getrxsubchans,
1619 .setaudmode = tda985x_setaudmode,
1620
1621 .init = { 12, { 0, 0x6f, 0x6f, 0x0e, 0x07<<1, 0x8<<2,
1622 TDA9855_MUTE | TDA9855_AVL | TDA9855_LOUD | TDA9855_INT,
1623 TDA985x_STEREO | TDA9855_LINEAR | TDA9855_TZCM | TDA9855_VZCM,
1624 0x07, 0x10, 0x10, 0x03 }}
1625 },
1626 {
1627 .name = "tea6300",
1628 .insmodopt = &tea6300,
1629 .addr_lo = I2C_ADDR_TEA6300 >> 1,
1630 .addr_hi = I2C_ADDR_TEA6300 >> 1,
1631 .registers = 6,
1632 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1633
1634 .leftreg = TEA6300_VR,
1635 .rightreg = TEA6300_VL,
1636 .bassreg = TEA6300_BA,
1637 .treblereg = TEA6300_TR,
1638
1639
1640 .volfunc = tea6300_shift10,
1641 .bassfunc = tea6300_shift12,
1642 .treblefunc = tea6300_shift12,
1643
1644 .inputreg = TEA6300_S,
1645 .inputmap = { TEA6300_S_SA, TEA6300_S_SB, TEA6300_S_SC },
1646 .inputmute = TEA6300_S_GMU,
1647 },
1648 {
1649 .name = "tea6320",
1650 .insmodopt = &tea6320,
1651 .addr_lo = I2C_ADDR_TEA6300 >> 1,
1652 .addr_hi = I2C_ADDR_TEA6300 >> 1,
1653 .registers = 8,
1654 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1655
1656 .leftreg = TEA6320_V,
1657 .rightreg = TEA6320_V,
1658 .bassreg = TEA6320_BA,
1659 .treblereg = TEA6320_TR,
1660
1661
1662 .initialize = tea6320_initialize,
1663 .volfunc = tea6320_volume,
1664 .bassfunc = tea6320_shift11,
1665 .treblefunc = tea6320_shift11,
1666
1667 .inputreg = TEA6320_S,
1668 .inputmap = { TEA6320_S_SA, TEA6420_S_SB, TEA6300_S_SC, TEA6320_S_SD },
1669 .inputmute = TEA6300_S_GMU,
1670 },
1671 {
1672 .name = "tea6420",
1673 .insmodopt = &tea6420,
1674 .addr_lo = I2C_ADDR_TEA6420 >> 1,
1675 .addr_hi = I2C_ADDR_TEA6420 >> 1,
1676 .registers = 1,
1677 .flags = CHIP_HAS_INPUTSEL,
1678
1679 .inputreg = -1,
1680 .inputmap = { TEA6420_S_SA, TEA6420_S_SB, TEA6420_S_SC },
1681 .inputmute = TEA6420_S_GMU,
1682 .inputmask = 0x07,
1683 },
1684 {
1685 .name = "tda8425",
1686 .insmodopt = &tda8425,
1687 .addr_lo = I2C_ADDR_TDA8425 >> 1,
1688 .addr_hi = I2C_ADDR_TDA8425 >> 1,
1689 .registers = 9,
1690 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1691
1692 .leftreg = TDA8425_VL,
1693 .rightreg = TDA8425_VR,
1694 .bassreg = TDA8425_BA,
1695 .treblereg = TDA8425_TR,
1696
1697
1698 .volfunc = tda8425_shift10,
1699 .bassfunc = tda8425_shift12,
1700 .treblefunc = tda8425_shift12,
1701 .setaudmode = tda8425_setaudmode,
1702
1703 .inputreg = TDA8425_S1,
1704 .inputmap = { TDA8425_S1_CH1, TDA8425_S1_CH1, TDA8425_S1_CH1 },
1705 .inputmute = TDA8425_S1_OFF,
1706
1707 },
1708 {
1709 .name = "pic16c54 (PV951)",
1710 .insmodopt = &pic16c54,
1711 .addr_lo = I2C_ADDR_PIC16C54 >> 1,
1712 .addr_hi = I2C_ADDR_PIC16C54>> 1,
1713 .registers = 2,
1714 .flags = CHIP_HAS_INPUTSEL,
1715
1716 .inputreg = PIC16C54_REG_MISC,
1717 .inputmap = {PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_TUNER,
1718 PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_LINE,
1719 PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_LINE,
1720 PIC16C54_MISC_SND_MUTE},
1721 .inputmute = PIC16C54_MISC_SND_MUTE,
1722 },
1723 {
1724 .name = "ta8874z",
1725 .checkit = ta8874z_checkit,
1726 .insmodopt = &ta8874z,
1727 .addr_lo = I2C_ADDR_TDA9840 >> 1,
1728 .addr_hi = I2C_ADDR_TDA9840 >> 1,
1729 .registers = 2,
1730
1731
1732 .getrxsubchans = ta8874z_getrxsubchans,
1733 .setaudmode = ta8874z_setaudmode,
1734
1735 .init = {2, { TA8874Z_MONO_SET, TA8874Z_SEPARATION_DEFAULT}},
1736 },
1737 { .name = NULL }
1738};
1739
1740
1741
1742
1743static int tvaudio_s_ctrl(struct v4l2_ctrl *ctrl)
1744{
1745 struct v4l2_subdev *sd = to_sd(ctrl);
1746 struct CHIPSTATE *chip = to_state(sd);
1747 struct CHIPDESC *desc = chip->desc;
1748
1749 switch (ctrl->id) {
1750 case V4L2_CID_AUDIO_MUTE:
1751 chip->muted = ctrl->val;
1752 if (chip->muted)
1753 chip_write_masked(chip,desc->inputreg,desc->inputmute,desc->inputmask);
1754 else
1755 chip_write_masked(chip,desc->inputreg,
1756 desc->inputmap[chip->input],desc->inputmask);
1757 return 0;
1758 case V4L2_CID_AUDIO_VOLUME: {
1759 u32 volume, balance;
1760 u32 left, right;
1761
1762 volume = chip->volume->val;
1763 balance = chip->balance->val;
1764 left = (min(65536U - balance, 32768U) * volume) / 32768U;
1765 right = (min(balance, 32768U) * volume) / 32768U;
1766
1767 chip_write(chip, desc->leftreg, desc->volfunc(left));
1768 chip_write(chip, desc->rightreg, desc->volfunc(right));
1769 return 0;
1770 }
1771 case V4L2_CID_AUDIO_BASS:
1772 chip_write(chip, desc->bassreg, desc->bassfunc(ctrl->val));
1773 return 0;
1774 case V4L2_CID_AUDIO_TREBLE:
1775 chip_write(chip, desc->treblereg, desc->treblefunc(ctrl->val));
1776 return 0;
1777 }
1778 return -EINVAL;
1779}
1780
1781
1782
1783
1784
1785static int tvaudio_s_radio(struct v4l2_subdev *sd)
1786{
1787 struct CHIPSTATE *chip = to_state(sd);
1788
1789 chip->radio = 1;
1790
1791 return 0;
1792}
1793
1794static int tvaudio_s_routing(struct v4l2_subdev *sd,
1795 u32 input, u32 output, u32 config)
1796{
1797 struct CHIPSTATE *chip = to_state(sd);
1798 struct CHIPDESC *desc = chip->desc;
1799
1800 if (!(desc->flags & CHIP_HAS_INPUTSEL))
1801 return 0;
1802 if (input >= 4)
1803 return -EINVAL;
1804
1805 chip->input = input;
1806 if (chip->muted)
1807 return 0;
1808 chip_write_masked(chip, desc->inputreg,
1809 desc->inputmap[chip->input], desc->inputmask);
1810 return 0;
1811}
1812
1813static int tvaudio_s_tuner(struct v4l2_subdev *sd, const struct v4l2_tuner *vt)
1814{
1815 struct CHIPSTATE *chip = to_state(sd);
1816 struct CHIPDESC *desc = chip->desc;
1817
1818 if (!desc->setaudmode)
1819 return 0;
1820 if (chip->radio)
1821 return 0;
1822
1823 switch (vt->audmode) {
1824 case V4L2_TUNER_MODE_MONO:
1825 case V4L2_TUNER_MODE_STEREO:
1826 case V4L2_TUNER_MODE_LANG1:
1827 case V4L2_TUNER_MODE_LANG2:
1828 case V4L2_TUNER_MODE_LANG1_LANG2:
1829 break;
1830 default:
1831 return -EINVAL;
1832 }
1833 chip->audmode = vt->audmode;
1834
1835 if (chip->thread)
1836 wake_up_process(chip->thread);
1837 else
1838 desc->setaudmode(chip, vt->audmode);
1839
1840 return 0;
1841}
1842
1843static int tvaudio_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1844{
1845 struct CHIPSTATE *chip = to_state(sd);
1846 struct CHIPDESC *desc = chip->desc;
1847
1848 if (!desc->getrxsubchans)
1849 return 0;
1850 if (chip->radio)
1851 return 0;
1852
1853 vt->audmode = chip->audmode;
1854 vt->rxsubchans = desc->getrxsubchans(chip);
1855 vt->capability |= V4L2_TUNER_CAP_STEREO |
1856 V4L2_TUNER_CAP_LANG1 | V4L2_TUNER_CAP_LANG2;
1857
1858 return 0;
1859}
1860
1861static int tvaudio_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
1862{
1863 struct CHIPSTATE *chip = to_state(sd);
1864
1865 chip->radio = 0;
1866 return 0;
1867}
1868
1869static int tvaudio_s_frequency(struct v4l2_subdev *sd, const struct v4l2_frequency *freq)
1870{
1871 struct CHIPSTATE *chip = to_state(sd);
1872 struct CHIPDESC *desc = chip->desc;
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882 if (chip->thread) {
1883 desc->setaudmode(chip, V4L2_TUNER_MODE_MONO);
1884 chip->prevmode = -1;
1885 mod_timer(&chip->wt, jiffies+msecs_to_jiffies(2000));
1886 }
1887 return 0;
1888}
1889
1890static int tvaudio_log_status(struct v4l2_subdev *sd)
1891{
1892 struct CHIPSTATE *chip = to_state(sd);
1893 struct CHIPDESC *desc = chip->desc;
1894
1895 v4l2_info(sd, "Chip: %s\n", desc->name);
1896 v4l2_ctrl_handler_log_status(&chip->hdl, sd->name);
1897 return 0;
1898}
1899
1900
1901
1902static const struct v4l2_ctrl_ops tvaudio_ctrl_ops = {
1903 .s_ctrl = tvaudio_s_ctrl,
1904};
1905
1906static const struct v4l2_subdev_core_ops tvaudio_core_ops = {
1907 .log_status = tvaudio_log_status,
1908};
1909
1910static const struct v4l2_subdev_tuner_ops tvaudio_tuner_ops = {
1911 .s_radio = tvaudio_s_radio,
1912 .s_frequency = tvaudio_s_frequency,
1913 .s_tuner = tvaudio_s_tuner,
1914 .g_tuner = tvaudio_g_tuner,
1915};
1916
1917static const struct v4l2_subdev_audio_ops tvaudio_audio_ops = {
1918 .s_routing = tvaudio_s_routing,
1919};
1920
1921static const struct v4l2_subdev_video_ops tvaudio_video_ops = {
1922 .s_std = tvaudio_s_std,
1923};
1924
1925static const struct v4l2_subdev_ops tvaudio_ops = {
1926 .core = &tvaudio_core_ops,
1927 .tuner = &tvaudio_tuner_ops,
1928 .audio = &tvaudio_audio_ops,
1929 .video = &tvaudio_video_ops,
1930};
1931
1932
1933
1934
1935
1936
1937static int tvaudio_probe(struct i2c_client *client, const struct i2c_device_id *id)
1938{
1939 struct CHIPSTATE *chip;
1940 struct CHIPDESC *desc;
1941 struct v4l2_subdev *sd;
1942
1943 if (debug) {
1944 printk(KERN_INFO "tvaudio: TV audio decoder + audio/video mux driver\n");
1945 printk(KERN_INFO "tvaudio: known chips: ");
1946 for (desc = chiplist; desc->name != NULL; desc++)
1947 printk(KERN_CONT "%s%s",
1948 (desc == chiplist) ? "" : ", ", desc->name);
1949 printk(KERN_CONT "\n");
1950 }
1951
1952 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
1953 if (!chip)
1954 return -ENOMEM;
1955 sd = &chip->sd;
1956 v4l2_i2c_subdev_init(sd, client, &tvaudio_ops);
1957
1958
1959 v4l2_dbg(1, debug, sd, "chip found @ 0x%x\n", client->addr<<1);
1960 for (desc = chiplist; desc->name != NULL; desc++) {
1961 if (0 == *(desc->insmodopt))
1962 continue;
1963 if (client->addr < desc->addr_lo ||
1964 client->addr > desc->addr_hi)
1965 continue;
1966 if (desc->checkit && !desc->checkit(chip))
1967 continue;
1968 break;
1969 }
1970 if (desc->name == NULL) {
1971 v4l2_dbg(1, debug, sd, "no matching chip description found\n");
1972 return -EIO;
1973 }
1974 v4l2_info(sd, "%s found @ 0x%x (%s)\n", desc->name, client->addr<<1, client->adapter->name);
1975 if (desc->flags) {
1976 v4l2_dbg(1, debug, sd, "matches:%s%s%s.\n",
1977 (desc->flags & CHIP_HAS_VOLUME) ? " volume" : "",
1978 (desc->flags & CHIP_HAS_BASSTREBLE) ? " bass/treble" : "",
1979 (desc->flags & CHIP_HAS_INPUTSEL) ? " audiomux" : "");
1980 }
1981
1982
1983 if (!id)
1984 strscpy(client->name, desc->name, I2C_NAME_SIZE);
1985 chip->desc = desc;
1986 chip->shadow.count = desc->registers+1;
1987 chip->prevmode = -1;
1988 chip->audmode = V4L2_TUNER_MODE_LANG1;
1989
1990
1991 if (desc->initialize != NULL)
1992 desc->initialize(chip);
1993 else
1994 chip_cmd(chip, "init", &desc->init);
1995
1996 v4l2_ctrl_handler_init(&chip->hdl, 5);
1997 if (desc->flags & CHIP_HAS_INPUTSEL)
1998 v4l2_ctrl_new_std(&chip->hdl, &tvaudio_ctrl_ops,
1999 V4L2_CID_AUDIO_MUTE, 0, 1, 1, 0);
2000 if (desc->flags & CHIP_HAS_VOLUME) {
2001 if (!desc->volfunc) {
2002
2003
2004
2005 v4l2_info(sd, "volume callback undefined!\n");
2006 desc->flags &= ~CHIP_HAS_VOLUME;
2007 } else {
2008 chip->volume = v4l2_ctrl_new_std(&chip->hdl,
2009 &tvaudio_ctrl_ops, V4L2_CID_AUDIO_VOLUME,
2010 0, 65535, 65535 / 100,
2011 desc->volinit ? desc->volinit : 65535);
2012 chip->balance = v4l2_ctrl_new_std(&chip->hdl,
2013 &tvaudio_ctrl_ops, V4L2_CID_AUDIO_BALANCE,
2014 0, 65535, 65535 / 100, 32768);
2015 v4l2_ctrl_cluster(2, &chip->volume);
2016 }
2017 }
2018 if (desc->flags & CHIP_HAS_BASSTREBLE) {
2019 if (!desc->bassfunc || !desc->treblefunc) {
2020
2021
2022
2023 v4l2_info(sd, "bass/treble callbacks undefined!\n");
2024 desc->flags &= ~CHIP_HAS_BASSTREBLE;
2025 } else {
2026 v4l2_ctrl_new_std(&chip->hdl,
2027 &tvaudio_ctrl_ops, V4L2_CID_AUDIO_BASS,
2028 0, 65535, 65535 / 100,
2029 desc->bassinit ? desc->bassinit : 32768);
2030 v4l2_ctrl_new_std(&chip->hdl,
2031 &tvaudio_ctrl_ops, V4L2_CID_AUDIO_TREBLE,
2032 0, 65535, 65535 / 100,
2033 desc->trebleinit ? desc->trebleinit : 32768);
2034 }
2035 }
2036
2037 sd->ctrl_handler = &chip->hdl;
2038 if (chip->hdl.error) {
2039 int err = chip->hdl.error;
2040
2041 v4l2_ctrl_handler_free(&chip->hdl);
2042 return err;
2043 }
2044
2045 v4l2_ctrl_handler_setup(&chip->hdl);
2046
2047 chip->thread = NULL;
2048 timer_setup(&chip->wt, chip_thread_wake, 0);
2049 if (desc->flags & CHIP_NEED_CHECKMODE) {
2050 if (!desc->getrxsubchans || !desc->setaudmode) {
2051
2052
2053
2054 v4l2_info(sd, "set/get mode callbacks undefined!\n");
2055 return 0;
2056 }
2057
2058 chip->thread = kthread_run(chip_thread, chip, "%s",
2059 client->name);
2060 if (IS_ERR(chip->thread)) {
2061 v4l2_warn(sd, "failed to create kthread\n");
2062 chip->thread = NULL;
2063 }
2064 }
2065 return 0;
2066}
2067
2068static int tvaudio_remove(struct i2c_client *client)
2069{
2070 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2071 struct CHIPSTATE *chip = to_state(sd);
2072
2073 del_timer_sync(&chip->wt);
2074 if (chip->thread) {
2075
2076 kthread_stop(chip->thread);
2077 chip->thread = NULL;
2078 }
2079
2080 v4l2_device_unregister_subdev(sd);
2081 v4l2_ctrl_handler_free(&chip->hdl);
2082 return 0;
2083}
2084
2085
2086
2087
2088static const struct i2c_device_id tvaudio_id[] = {
2089 { "tvaudio", 0 },
2090 { }
2091};
2092MODULE_DEVICE_TABLE(i2c, tvaudio_id);
2093
2094static struct i2c_driver tvaudio_driver = {
2095 .driver = {
2096 .name = "tvaudio",
2097 },
2098 .probe = tvaudio_probe,
2099 .remove = tvaudio_remove,
2100 .id_table = tvaudio_id,
2101};
2102
2103module_i2c_driver(tvaudio_driver);
2104