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19#include <linux/i2c.h>
20#include <linux/slab.h>
21#include <linux/delay.h>
22#include <linux/videodev2.h>
23#include <linux/module.h>
24#include <linux/v4l2-mediabus.h>
25#include <linux/of.h>
26#include <linux/of_graph.h>
27
28#include <media/v4l2-async.h>
29#include <media/v4l2-device.h>
30#include <media/v4l2-common.h>
31#include <media/v4l2-mediabus.h>
32#include <media/v4l2-fwnode.h>
33#include <media/v4l2-ctrls.h>
34#include <media/i2c/tvp514x.h>
35#include <media/media-entity.h>
36
37#include "tvp514x_regs.h"
38
39
40#define I2C_RETRY_COUNT (5)
41#define LOCK_RETRY_COUNT (5)
42#define LOCK_RETRY_DELAY (200)
43
44
45static bool debug;
46module_param(debug, bool, 0644);
47MODULE_PARM_DESC(debug, "Debug level (0-1)");
48
49MODULE_AUTHOR("Texas Instruments");
50MODULE_DESCRIPTION("TVP514X linux decoder driver");
51MODULE_LICENSE("GPL");
52
53
54enum tvp514x_std {
55 STD_NTSC_MJ = 0,
56 STD_PAL_BDGHIN,
57 STD_INVALID
58};
59
60
61
62
63
64
65
66
67struct tvp514x_std_info {
68 unsigned long width;
69 unsigned long height;
70 u8 video_std;
71 struct v4l2_standard standard;
72};
73
74static struct tvp514x_reg tvp514x_reg_list_default[0x40];
75
76static int tvp514x_s_stream(struct v4l2_subdev *sd, int enable);
77
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96
97struct tvp514x_decoder {
98 struct v4l2_subdev sd;
99 struct v4l2_ctrl_handler hdl;
100 struct tvp514x_reg tvp514x_regs[ARRAY_SIZE(tvp514x_reg_list_default)];
101 const struct tvp514x_platform_data *pdata;
102
103 int ver;
104 int streaming;
105
106 struct v4l2_pix_format pix;
107 int num_fmts;
108 const struct v4l2_fmtdesc *fmt_list;
109
110 enum tvp514x_std current_std;
111 int num_stds;
112 const struct tvp514x_std_info *std_list;
113
114 u32 input;
115 u32 output;
116
117
118 struct media_pad pad;
119 struct v4l2_mbus_framefmt format;
120
121 struct tvp514x_reg *int_seq;
122};
123
124
125static struct tvp514x_reg tvp514x_reg_list_default[] = {
126
127 {TOK_WRITE, REG_INPUT_SEL, 0x05},
128 {TOK_WRITE, REG_AFE_GAIN_CTRL, 0x0F},
129
130 {TOK_WRITE, REG_VIDEO_STD, 0x00},
131 {TOK_WRITE, REG_OPERATION_MODE, 0x00},
132 {TOK_SKIP, REG_AUTOSWITCH_MASK, 0x3F},
133 {TOK_WRITE, REG_COLOR_KILLER, 0x10},
134 {TOK_WRITE, REG_LUMA_CONTROL1, 0x00},
135 {TOK_WRITE, REG_LUMA_CONTROL2, 0x00},
136 {TOK_WRITE, REG_LUMA_CONTROL3, 0x02},
137 {TOK_WRITE, REG_BRIGHTNESS, 0x80},
138 {TOK_WRITE, REG_CONTRAST, 0x80},
139 {TOK_WRITE, REG_SATURATION, 0x80},
140 {TOK_WRITE, REG_HUE, 0x00},
141 {TOK_WRITE, REG_CHROMA_CONTROL1, 0x00},
142 {TOK_WRITE, REG_CHROMA_CONTROL2, 0x0E},
143
144 {TOK_SKIP, 0x0F, 0x00},
145 {TOK_WRITE, REG_COMP_PR_SATURATION, 0x80},
146 {TOK_WRITE, REG_COMP_Y_CONTRAST, 0x80},
147 {TOK_WRITE, REG_COMP_PB_SATURATION, 0x80},
148
149 {TOK_SKIP, 0x13, 0x00},
150 {TOK_WRITE, REG_COMP_Y_BRIGHTNESS, 0x80},
151
152 {TOK_SKIP, 0x15, 0x00},
153
154 {TOK_SKIP, REG_AVID_START_PIXEL_LSB, 0x55},
155 {TOK_SKIP, REG_AVID_START_PIXEL_MSB, 0x00},
156 {TOK_SKIP, REG_AVID_STOP_PIXEL_LSB, 0x25},
157 {TOK_SKIP, REG_AVID_STOP_PIXEL_MSB, 0x03},
158
159 {TOK_SKIP, REG_HSYNC_START_PIXEL_LSB, 0x00},
160 {TOK_SKIP, REG_HSYNC_START_PIXEL_MSB, 0x00},
161 {TOK_SKIP, REG_HSYNC_STOP_PIXEL_LSB, 0x40},
162 {TOK_SKIP, REG_HSYNC_STOP_PIXEL_MSB, 0x00},
163
164 {TOK_SKIP, REG_VSYNC_START_LINE_LSB, 0x04},
165 {TOK_SKIP, REG_VSYNC_START_LINE_MSB, 0x00},
166 {TOK_SKIP, REG_VSYNC_STOP_LINE_LSB, 0x07},
167 {TOK_SKIP, REG_VSYNC_STOP_LINE_MSB, 0x00},
168
169 {TOK_SKIP, REG_VBLK_START_LINE_LSB, 0x01},
170 {TOK_SKIP, REG_VBLK_START_LINE_MSB, 0x00},
171 {TOK_SKIP, REG_VBLK_STOP_LINE_LSB, 0x15},
172 {TOK_SKIP, REG_VBLK_STOP_LINE_MSB, 0x00},
173
174 {TOK_SKIP, 0x26, 0x00},
175
176 {TOK_SKIP, 0x27, 0x00},
177 {TOK_SKIP, REG_FAST_SWTICH_CONTROL, 0xCC},
178
179 {TOK_SKIP, 0x29, 0x00},
180 {TOK_SKIP, REG_FAST_SWTICH_SCART_DELAY, 0x00},
181
182 {TOK_SKIP, 0x2B, 0x00},
183 {TOK_SKIP, REG_SCART_DELAY, 0x00},
184 {TOK_SKIP, REG_CTI_DELAY, 0x00},
185 {TOK_SKIP, REG_CTI_CONTROL, 0x00},
186
187 {TOK_SKIP, 0x2F, 0x00},
188
189 {TOK_SKIP, 0x30, 0x00},
190
191 {TOK_SKIP, 0x31, 0x00},
192
193 {TOK_WRITE, REG_SYNC_CONTROL, 0x00},
194
195 {TOK_WRITE, REG_OUTPUT_FORMATTER1, 0x00},
196
197 {TOK_WRITE, REG_OUTPUT_FORMATTER2, 0x11},
198
199 {TOK_WRITE, REG_OUTPUT_FORMATTER3, 0xEE},
200
201 {TOK_WRITE, REG_OUTPUT_FORMATTER4, 0xAF},
202 {TOK_WRITE, REG_OUTPUT_FORMATTER5, 0xFF},
203 {TOK_WRITE, REG_OUTPUT_FORMATTER6, 0xFF},
204
205 {TOK_WRITE, REG_CLEAR_LOST_LOCK, 0x01},
206 {TOK_TERM, 0, 0},
207};
208
209
210
211
212
213
214static const struct v4l2_fmtdesc tvp514x_fmt_list[] = {
215 {
216 .index = 0,
217 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
218 .flags = 0,
219 .description = "8-bit UYVY 4:2:2 Format",
220 .pixelformat = V4L2_PIX_FMT_UYVY,
221 },
222};
223
224
225
226
227
228
229
230static const struct tvp514x_std_info tvp514x_std_list[] = {
231
232 [STD_NTSC_MJ] = {
233 .width = NTSC_NUM_ACTIVE_PIXELS,
234 .height = NTSC_NUM_ACTIVE_LINES,
235 .video_std = VIDEO_STD_NTSC_MJ_BIT,
236 .standard = {
237 .index = 0,
238 .id = V4L2_STD_NTSC,
239 .name = "NTSC",
240 .frameperiod = {1001, 30000},
241 .framelines = 525
242 },
243
244 },
245 [STD_PAL_BDGHIN] = {
246 .width = PAL_NUM_ACTIVE_PIXELS,
247 .height = PAL_NUM_ACTIVE_LINES,
248 .video_std = VIDEO_STD_PAL_BDGHIN_BIT,
249 .standard = {
250 .index = 1,
251 .id = V4L2_STD_PAL,
252 .name = "PAL",
253 .frameperiod = {1, 25},
254 .framelines = 625
255 },
256 },
257
258};
259
260
261static inline struct tvp514x_decoder *to_decoder(struct v4l2_subdev *sd)
262{
263 return container_of(sd, struct tvp514x_decoder, sd);
264}
265
266static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
267{
268 return &container_of(ctrl->handler, struct tvp514x_decoder, hdl)->sd;
269}
270
271
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275
276
277
278
279static int tvp514x_read_reg(struct v4l2_subdev *sd, u8 reg)
280{
281 int err, retry = 0;
282 struct i2c_client *client = v4l2_get_subdevdata(sd);
283
284read_again:
285
286 err = i2c_smbus_read_byte_data(client, reg);
287 if (err < 0) {
288 if (retry <= I2C_RETRY_COUNT) {
289 v4l2_warn(sd, "Read: retry ... %d\n", retry);
290 retry++;
291 msleep_interruptible(10);
292 goto read_again;
293 }
294 }
295
296 return err;
297}
298
299
300
301
302
303
304static void dump_reg(struct v4l2_subdev *sd, u8 reg)
305{
306 u32 val;
307
308 val = tvp514x_read_reg(sd, reg);
309 v4l2_info(sd, "Reg(0x%.2X): 0x%.2X\n", reg, val);
310}
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319
320
321static int tvp514x_write_reg(struct v4l2_subdev *sd, u8 reg, u8 val)
322{
323 int err, retry = 0;
324 struct i2c_client *client = v4l2_get_subdevdata(sd);
325
326write_again:
327
328 err = i2c_smbus_write_byte_data(client, reg, val);
329 if (err) {
330 if (retry <= I2C_RETRY_COUNT) {
331 v4l2_warn(sd, "Write: retry ... %d\n", retry);
332 retry++;
333 msleep_interruptible(10);
334 goto write_again;
335 }
336 }
337
338 return err;
339}
340
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351
352
353static int tvp514x_write_regs(struct v4l2_subdev *sd,
354 const struct tvp514x_reg reglist[])
355{
356 int err;
357 const struct tvp514x_reg *next = reglist;
358
359 for (; next->token != TOK_TERM; next++) {
360 if (next->token == TOK_DELAY) {
361 msleep(next->val);
362 continue;
363 }
364
365 if (next->token == TOK_SKIP)
366 continue;
367
368 err = tvp514x_write_reg(sd, next->reg, (u8) next->val);
369 if (err) {
370 v4l2_err(sd, "Write failed. Err[%d]\n", err);
371 return err;
372 }
373 }
374 return 0;
375}
376
377
378
379
380
381
382
383
384static enum tvp514x_std tvp514x_query_current_std(struct v4l2_subdev *sd)
385{
386 u8 std, std_status;
387
388 std = tvp514x_read_reg(sd, REG_VIDEO_STD);
389 if ((std & VIDEO_STD_MASK) == VIDEO_STD_AUTO_SWITCH_BIT)
390
391 std_status = tvp514x_read_reg(sd, REG_VIDEO_STD_STATUS);
392 else
393
394 std_status = std;
395
396 switch (std_status & VIDEO_STD_MASK) {
397 case VIDEO_STD_NTSC_MJ_BIT:
398 return STD_NTSC_MJ;
399
400 case VIDEO_STD_PAL_BDGHIN_BIT:
401 return STD_PAL_BDGHIN;
402
403 default:
404 return STD_INVALID;
405 }
406
407 return STD_INVALID;
408}
409
410
411static void tvp514x_reg_dump(struct v4l2_subdev *sd)
412{
413 dump_reg(sd, REG_INPUT_SEL);
414 dump_reg(sd, REG_AFE_GAIN_CTRL);
415 dump_reg(sd, REG_VIDEO_STD);
416 dump_reg(sd, REG_OPERATION_MODE);
417 dump_reg(sd, REG_COLOR_KILLER);
418 dump_reg(sd, REG_LUMA_CONTROL1);
419 dump_reg(sd, REG_LUMA_CONTROL2);
420 dump_reg(sd, REG_LUMA_CONTROL3);
421 dump_reg(sd, REG_BRIGHTNESS);
422 dump_reg(sd, REG_CONTRAST);
423 dump_reg(sd, REG_SATURATION);
424 dump_reg(sd, REG_HUE);
425 dump_reg(sd, REG_CHROMA_CONTROL1);
426 dump_reg(sd, REG_CHROMA_CONTROL2);
427 dump_reg(sd, REG_COMP_PR_SATURATION);
428 dump_reg(sd, REG_COMP_Y_CONTRAST);
429 dump_reg(sd, REG_COMP_PB_SATURATION);
430 dump_reg(sd, REG_COMP_Y_BRIGHTNESS);
431 dump_reg(sd, REG_AVID_START_PIXEL_LSB);
432 dump_reg(sd, REG_AVID_START_PIXEL_MSB);
433 dump_reg(sd, REG_AVID_STOP_PIXEL_LSB);
434 dump_reg(sd, REG_AVID_STOP_PIXEL_MSB);
435 dump_reg(sd, REG_HSYNC_START_PIXEL_LSB);
436 dump_reg(sd, REG_HSYNC_START_PIXEL_MSB);
437 dump_reg(sd, REG_HSYNC_STOP_PIXEL_LSB);
438 dump_reg(sd, REG_HSYNC_STOP_PIXEL_MSB);
439 dump_reg(sd, REG_VSYNC_START_LINE_LSB);
440 dump_reg(sd, REG_VSYNC_START_LINE_MSB);
441 dump_reg(sd, REG_VSYNC_STOP_LINE_LSB);
442 dump_reg(sd, REG_VSYNC_STOP_LINE_MSB);
443 dump_reg(sd, REG_VBLK_START_LINE_LSB);
444 dump_reg(sd, REG_VBLK_START_LINE_MSB);
445 dump_reg(sd, REG_VBLK_STOP_LINE_LSB);
446 dump_reg(sd, REG_VBLK_STOP_LINE_MSB);
447 dump_reg(sd, REG_SYNC_CONTROL);
448 dump_reg(sd, REG_OUTPUT_FORMATTER1);
449 dump_reg(sd, REG_OUTPUT_FORMATTER2);
450 dump_reg(sd, REG_OUTPUT_FORMATTER3);
451 dump_reg(sd, REG_OUTPUT_FORMATTER4);
452 dump_reg(sd, REG_OUTPUT_FORMATTER5);
453 dump_reg(sd, REG_OUTPUT_FORMATTER6);
454 dump_reg(sd, REG_CLEAR_LOST_LOCK);
455}
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462
463
464static int tvp514x_configure(struct v4l2_subdev *sd,
465 struct tvp514x_decoder *decoder)
466{
467 int err;
468
469
470 err =
471 tvp514x_write_regs(sd, decoder->tvp514x_regs);
472 if (err)
473 return err;
474
475 if (debug)
476 tvp514x_reg_dump(sd);
477
478 return 0;
479}
480
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490
491
492static int tvp514x_detect(struct v4l2_subdev *sd,
493 struct tvp514x_decoder *decoder)
494{
495 u8 chip_id_msb, chip_id_lsb, rom_ver;
496 struct i2c_client *client = v4l2_get_subdevdata(sd);
497
498 chip_id_msb = tvp514x_read_reg(sd, REG_CHIP_ID_MSB);
499 chip_id_lsb = tvp514x_read_reg(sd, REG_CHIP_ID_LSB);
500 rom_ver = tvp514x_read_reg(sd, REG_ROM_VERSION);
501
502 v4l2_dbg(1, debug, sd,
503 "chip id detected msb:0x%x lsb:0x%x rom version:0x%x\n",
504 chip_id_msb, chip_id_lsb, rom_ver);
505 if ((chip_id_msb != TVP514X_CHIP_ID_MSB)
506 || ((chip_id_lsb != TVP5146_CHIP_ID_LSB)
507 && (chip_id_lsb != TVP5147_CHIP_ID_LSB))) {
508
509
510
511 v4l2_err(sd, "chip id mismatch msb:0x%x lsb:0x%x\n",
512 chip_id_msb, chip_id_lsb);
513 return -ENODEV;
514 }
515
516 decoder->ver = rom_ver;
517
518 v4l2_info(sd, "%s (Version - 0x%.2x) found at 0x%x (%s)\n",
519 client->name, decoder->ver,
520 client->addr << 1, client->adapter->name);
521 return 0;
522}
523
524
525
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527
528
529
530
531
532static int tvp514x_querystd(struct v4l2_subdev *sd, v4l2_std_id *std_id)
533{
534 struct tvp514x_decoder *decoder = to_decoder(sd);
535 enum tvp514x_std current_std;
536 enum tvp514x_input input_sel;
537 u8 sync_lock_status, lock_mask;
538
539 if (std_id == NULL)
540 return -EINVAL;
541
542
543 if (!decoder->streaming) {
544 tvp514x_s_stream(sd, 1);
545 msleep(LOCK_RETRY_DELAY);
546 }
547
548
549 current_std = tvp514x_query_current_std(sd);
550 if (current_std == STD_INVALID) {
551 *std_id = V4L2_STD_UNKNOWN;
552 return 0;
553 }
554
555 input_sel = decoder->input;
556
557 switch (input_sel) {
558 case INPUT_CVBS_VI1A:
559 case INPUT_CVBS_VI1B:
560 case INPUT_CVBS_VI1C:
561 case INPUT_CVBS_VI2A:
562 case INPUT_CVBS_VI2B:
563 case INPUT_CVBS_VI2C:
564 case INPUT_CVBS_VI3A:
565 case INPUT_CVBS_VI3B:
566 case INPUT_CVBS_VI3C:
567 case INPUT_CVBS_VI4A:
568 lock_mask = STATUS_CLR_SUBCAR_LOCK_BIT |
569 STATUS_HORZ_SYNC_LOCK_BIT |
570 STATUS_VIRT_SYNC_LOCK_BIT;
571 break;
572
573 case INPUT_SVIDEO_VI2A_VI1A:
574 case INPUT_SVIDEO_VI2B_VI1B:
575 case INPUT_SVIDEO_VI2C_VI1C:
576 case INPUT_SVIDEO_VI2A_VI3A:
577 case INPUT_SVIDEO_VI2B_VI3B:
578 case INPUT_SVIDEO_VI2C_VI3C:
579 case INPUT_SVIDEO_VI4A_VI1A:
580 case INPUT_SVIDEO_VI4A_VI1B:
581 case INPUT_SVIDEO_VI4A_VI1C:
582 case INPUT_SVIDEO_VI4A_VI3A:
583 case INPUT_SVIDEO_VI4A_VI3B:
584 case INPUT_SVIDEO_VI4A_VI3C:
585 lock_mask = STATUS_HORZ_SYNC_LOCK_BIT |
586 STATUS_VIRT_SYNC_LOCK_BIT;
587 break;
588
589 default:
590 return -EINVAL;
591 }
592
593 sync_lock_status = tvp514x_read_reg(sd, REG_STATUS1);
594 if (lock_mask != (sync_lock_status & lock_mask)) {
595 *std_id = V4L2_STD_UNKNOWN;
596 return 0;
597 }
598
599 *std_id &= decoder->std_list[current_std].standard.id;
600
601 v4l2_dbg(1, debug, sd, "Current STD: %s\n",
602 decoder->std_list[current_std].standard.name);
603 return 0;
604}
605
606
607
608
609
610
611
612
613
614static int tvp514x_s_std(struct v4l2_subdev *sd, v4l2_std_id std_id)
615{
616 struct tvp514x_decoder *decoder = to_decoder(sd);
617 int err, i;
618
619 for (i = 0; i < decoder->num_stds; i++)
620 if (std_id & decoder->std_list[i].standard.id)
621 break;
622
623 if ((i == decoder->num_stds) || (i == STD_INVALID))
624 return -EINVAL;
625
626 err = tvp514x_write_reg(sd, REG_VIDEO_STD,
627 decoder->std_list[i].video_std);
628 if (err)
629 return err;
630
631 decoder->current_std = i;
632 decoder->tvp514x_regs[REG_VIDEO_STD].val =
633 decoder->std_list[i].video_std;
634
635 v4l2_dbg(1, debug, sd, "Standard set to: %s\n",
636 decoder->std_list[i].standard.name);
637 return 0;
638}
639
640
641
642
643
644
645
646
647
648
649
650
651static int tvp514x_s_routing(struct v4l2_subdev *sd,
652 u32 input, u32 output, u32 config)
653{
654 struct tvp514x_decoder *decoder = to_decoder(sd);
655 int err;
656 enum tvp514x_input input_sel;
657 enum tvp514x_output output_sel;
658
659 if ((input >= INPUT_INVALID) ||
660 (output >= OUTPUT_INVALID))
661
662 return -EINVAL;
663
664 input_sel = input;
665 output_sel = output;
666
667 err = tvp514x_write_reg(sd, REG_INPUT_SEL, input_sel);
668 if (err)
669 return err;
670
671 output_sel |= tvp514x_read_reg(sd,
672 REG_OUTPUT_FORMATTER1) & 0x7;
673 err = tvp514x_write_reg(sd, REG_OUTPUT_FORMATTER1,
674 output_sel);
675 if (err)
676 return err;
677
678 decoder->tvp514x_regs[REG_INPUT_SEL].val = input_sel;
679 decoder->tvp514x_regs[REG_OUTPUT_FORMATTER1].val = output_sel;
680 decoder->input = input;
681 decoder->output = output;
682
683 v4l2_dbg(1, debug, sd, "Input set to: %d\n", input_sel);
684
685 return 0;
686}
687
688
689
690
691
692
693
694
695static int tvp514x_s_ctrl(struct v4l2_ctrl *ctrl)
696{
697 struct v4l2_subdev *sd = to_sd(ctrl);
698 struct tvp514x_decoder *decoder = to_decoder(sd);
699 int err = -EINVAL, value;
700
701 value = ctrl->val;
702
703 switch (ctrl->id) {
704 case V4L2_CID_BRIGHTNESS:
705 err = tvp514x_write_reg(sd, REG_BRIGHTNESS, value);
706 if (!err)
707 decoder->tvp514x_regs[REG_BRIGHTNESS].val = value;
708 break;
709 case V4L2_CID_CONTRAST:
710 err = tvp514x_write_reg(sd, REG_CONTRAST, value);
711 if (!err)
712 decoder->tvp514x_regs[REG_CONTRAST].val = value;
713 break;
714 case V4L2_CID_SATURATION:
715 err = tvp514x_write_reg(sd, REG_SATURATION, value);
716 if (!err)
717 decoder->tvp514x_regs[REG_SATURATION].val = value;
718 break;
719 case V4L2_CID_HUE:
720 if (value == 180)
721 value = 0x7F;
722 else if (value == -180)
723 value = 0x80;
724 err = tvp514x_write_reg(sd, REG_HUE, value);
725 if (!err)
726 decoder->tvp514x_regs[REG_HUE].val = value;
727 break;
728 case V4L2_CID_AUTOGAIN:
729 err = tvp514x_write_reg(sd, REG_AFE_GAIN_CTRL, value ? 0x0f : 0x0c);
730 if (!err)
731 decoder->tvp514x_regs[REG_AFE_GAIN_CTRL].val = value;
732 break;
733 }
734
735 v4l2_dbg(1, debug, sd, "Set Control: ID - %d - %d\n",
736 ctrl->id, ctrl->val);
737 return err;
738}
739
740
741
742
743
744
745
746
747static int
748tvp514x_g_frame_interval(struct v4l2_subdev *sd,
749 struct v4l2_subdev_frame_interval *ival)
750{
751 struct tvp514x_decoder *decoder = to_decoder(sd);
752 enum tvp514x_std current_std;
753
754
755
756 current_std = decoder->current_std;
757
758 ival->interval =
759 decoder->std_list[current_std].standard.frameperiod;
760
761 return 0;
762}
763
764
765
766
767
768
769
770
771
772static int
773tvp514x_s_frame_interval(struct v4l2_subdev *sd,
774 struct v4l2_subdev_frame_interval *ival)
775{
776 struct tvp514x_decoder *decoder = to_decoder(sd);
777 struct v4l2_fract *timeperframe;
778 enum tvp514x_std current_std;
779
780
781 timeperframe = &ival->interval;
782
783
784 current_std = decoder->current_std;
785
786 *timeperframe =
787 decoder->std_list[current_std].standard.frameperiod;
788
789 return 0;
790}
791
792
793
794
795
796
797
798
799static int tvp514x_s_stream(struct v4l2_subdev *sd, int enable)
800{
801 int err = 0;
802 struct tvp514x_decoder *decoder = to_decoder(sd);
803
804 if (decoder->streaming == enable)
805 return 0;
806
807 switch (enable) {
808 case 0:
809 {
810
811 err = tvp514x_write_reg(sd, REG_OPERATION_MODE, 0x01);
812 if (err) {
813 v4l2_err(sd, "Unable to turn off decoder\n");
814 return err;
815 }
816 decoder->streaming = enable;
817 break;
818 }
819 case 1:
820 {
821
822 err = tvp514x_write_regs(sd, decoder->int_seq);
823 if (err) {
824 v4l2_err(sd, "Unable to turn on decoder\n");
825 return err;
826 }
827
828 err = tvp514x_detect(sd, decoder);
829 if (err) {
830 v4l2_err(sd, "Unable to detect decoder\n");
831 return err;
832 }
833 err = tvp514x_configure(sd, decoder);
834 if (err) {
835 v4l2_err(sd, "Unable to configure decoder\n");
836 return err;
837 }
838 decoder->streaming = enable;
839 break;
840 }
841 default:
842 err = -ENODEV;
843 break;
844 }
845
846 return err;
847}
848
849static const struct v4l2_ctrl_ops tvp514x_ctrl_ops = {
850 .s_ctrl = tvp514x_s_ctrl,
851};
852
853
854
855
856
857
858
859
860
861static int tvp514x_enum_mbus_code(struct v4l2_subdev *sd,
862 struct v4l2_subdev_pad_config *cfg,
863 struct v4l2_subdev_mbus_code_enum *code)
864{
865 u32 pad = code->pad;
866 u32 index = code->index;
867
868 memset(code, 0, sizeof(*code));
869 code->index = index;
870 code->pad = pad;
871
872 if (index != 0)
873 return -EINVAL;
874
875 code->code = MEDIA_BUS_FMT_UYVY8_2X8;
876
877 return 0;
878}
879
880
881
882
883
884
885
886
887
888static int tvp514x_get_pad_format(struct v4l2_subdev *sd,
889 struct v4l2_subdev_pad_config *cfg,
890 struct v4l2_subdev_format *format)
891{
892 struct tvp514x_decoder *decoder = to_decoder(sd);
893 __u32 which = format->which;
894
895 if (format->pad)
896 return -EINVAL;
897
898 if (which == V4L2_SUBDEV_FORMAT_ACTIVE) {
899 format->format = decoder->format;
900 return 0;
901 }
902
903 format->format.code = MEDIA_BUS_FMT_UYVY8_2X8;
904 format->format.width = tvp514x_std_list[decoder->current_std].width;
905 format->format.height = tvp514x_std_list[decoder->current_std].height;
906 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
907 format->format.field = V4L2_FIELD_INTERLACED;
908
909 return 0;
910}
911
912
913
914
915
916
917
918
919
920static int tvp514x_set_pad_format(struct v4l2_subdev *sd,
921 struct v4l2_subdev_pad_config *cfg,
922 struct v4l2_subdev_format *fmt)
923{
924 struct tvp514x_decoder *decoder = to_decoder(sd);
925
926 if (fmt->format.field != V4L2_FIELD_INTERLACED ||
927 fmt->format.code != MEDIA_BUS_FMT_UYVY8_2X8 ||
928 fmt->format.colorspace != V4L2_COLORSPACE_SMPTE170M ||
929 fmt->format.width != tvp514x_std_list[decoder->current_std].width ||
930 fmt->format.height != tvp514x_std_list[decoder->current_std].height)
931 return -EINVAL;
932
933 decoder->format = fmt->format;
934
935 return 0;
936}
937
938static const struct v4l2_subdev_video_ops tvp514x_video_ops = {
939 .s_std = tvp514x_s_std,
940 .s_routing = tvp514x_s_routing,
941 .querystd = tvp514x_querystd,
942 .g_frame_interval = tvp514x_g_frame_interval,
943 .s_frame_interval = tvp514x_s_frame_interval,
944 .s_stream = tvp514x_s_stream,
945};
946
947static const struct v4l2_subdev_pad_ops tvp514x_pad_ops = {
948 .enum_mbus_code = tvp514x_enum_mbus_code,
949 .get_fmt = tvp514x_get_pad_format,
950 .set_fmt = tvp514x_set_pad_format,
951};
952
953static const struct v4l2_subdev_ops tvp514x_ops = {
954 .video = &tvp514x_video_ops,
955 .pad = &tvp514x_pad_ops,
956};
957
958static const struct tvp514x_decoder tvp514x_dev = {
959 .streaming = 0,
960 .fmt_list = tvp514x_fmt_list,
961 .num_fmts = ARRAY_SIZE(tvp514x_fmt_list),
962 .pix = {
963
964 .width = NTSC_NUM_ACTIVE_PIXELS,
965 .height = NTSC_NUM_ACTIVE_LINES,
966 .pixelformat = V4L2_PIX_FMT_UYVY,
967 .field = V4L2_FIELD_INTERLACED,
968 .bytesperline = NTSC_NUM_ACTIVE_PIXELS * 2,
969 .sizeimage = NTSC_NUM_ACTIVE_PIXELS * 2 *
970 NTSC_NUM_ACTIVE_LINES,
971 .colorspace = V4L2_COLORSPACE_SMPTE170M,
972 },
973 .current_std = STD_NTSC_MJ,
974 .std_list = tvp514x_std_list,
975 .num_stds = ARRAY_SIZE(tvp514x_std_list),
976
977};
978
979static struct tvp514x_platform_data *
980tvp514x_get_pdata(struct i2c_client *client)
981{
982 struct tvp514x_platform_data *pdata = NULL;
983 struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
984 struct device_node *endpoint;
985 unsigned int flags;
986
987 if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
988 return client->dev.platform_data;
989
990 endpoint = of_graph_get_next_endpoint(client->dev.of_node, NULL);
991 if (!endpoint)
992 return NULL;
993
994 if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), &bus_cfg))
995 goto done;
996
997 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
998 if (!pdata)
999 goto done;
1000
1001 flags = bus_cfg.bus.parallel.flags;
1002
1003 if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
1004 pdata->hs_polarity = 1;
1005
1006 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
1007 pdata->vs_polarity = 1;
1008
1009 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
1010 pdata->clk_polarity = 1;
1011
1012done:
1013 of_node_put(endpoint);
1014 return pdata;
1015}
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025static int
1026tvp514x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1027{
1028 struct tvp514x_platform_data *pdata = tvp514x_get_pdata(client);
1029 struct tvp514x_decoder *decoder;
1030 struct v4l2_subdev *sd;
1031 int ret;
1032
1033 if (pdata == NULL) {
1034 dev_err(&client->dev, "No platform data\n");
1035 return -EINVAL;
1036 }
1037
1038
1039 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1040 return -EIO;
1041
1042 decoder = devm_kzalloc(&client->dev, sizeof(*decoder), GFP_KERNEL);
1043 if (!decoder)
1044 return -ENOMEM;
1045
1046
1047 *decoder = tvp514x_dev;
1048
1049 memcpy(decoder->tvp514x_regs, tvp514x_reg_list_default,
1050 sizeof(tvp514x_reg_list_default));
1051
1052 decoder->int_seq = (struct tvp514x_reg *)id->driver_data;
1053
1054
1055 decoder->pdata = pdata;
1056
1057
1058
1059
1060
1061
1062 decoder->tvp514x_regs[REG_OUTPUT_FORMATTER2].val |=
1063 (decoder->pdata->clk_polarity << 1);
1064 decoder->tvp514x_regs[REG_SYNC_CONTROL].val |=
1065 ((decoder->pdata->hs_polarity << 2) |
1066 (decoder->pdata->vs_polarity << 3));
1067
1068 decoder->tvp514x_regs[REG_VIDEO_STD].val =
1069 VIDEO_STD_AUTO_SWITCH_BIT;
1070
1071
1072 sd = &decoder->sd;
1073 v4l2_i2c_subdev_init(sd, client, &tvp514x_ops);
1074
1075#if defined(CONFIG_MEDIA_CONTROLLER)
1076 decoder->pad.flags = MEDIA_PAD_FL_SOURCE;
1077 decoder->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1078 decoder->sd.entity.function = MEDIA_ENT_F_ATV_DECODER;
1079
1080 ret = media_entity_pads_init(&decoder->sd.entity, 1, &decoder->pad);
1081 if (ret < 0) {
1082 v4l2_err(sd, "%s decoder driver failed to register !!\n",
1083 sd->name);
1084 return ret;
1085 }
1086#endif
1087 v4l2_ctrl_handler_init(&decoder->hdl, 5);
1088 v4l2_ctrl_new_std(&decoder->hdl, &tvp514x_ctrl_ops,
1089 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1090 v4l2_ctrl_new_std(&decoder->hdl, &tvp514x_ctrl_ops,
1091 V4L2_CID_CONTRAST, 0, 255, 1, 128);
1092 v4l2_ctrl_new_std(&decoder->hdl, &tvp514x_ctrl_ops,
1093 V4L2_CID_SATURATION, 0, 255, 1, 128);
1094 v4l2_ctrl_new_std(&decoder->hdl, &tvp514x_ctrl_ops,
1095 V4L2_CID_HUE, -180, 180, 180, 0);
1096 v4l2_ctrl_new_std(&decoder->hdl, &tvp514x_ctrl_ops,
1097 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1098 sd->ctrl_handler = &decoder->hdl;
1099 if (decoder->hdl.error) {
1100 ret = decoder->hdl.error;
1101 goto done;
1102 }
1103 v4l2_ctrl_handler_setup(&decoder->hdl);
1104
1105 ret = v4l2_async_register_subdev(&decoder->sd);
1106 if (!ret)
1107 v4l2_info(sd, "%s decoder driver registered !!\n", sd->name);
1108
1109done:
1110 if (ret < 0) {
1111 v4l2_ctrl_handler_free(&decoder->hdl);
1112 media_entity_cleanup(&decoder->sd.entity);
1113 }
1114 return ret;
1115}
1116
1117
1118
1119
1120
1121
1122
1123
1124static int tvp514x_remove(struct i2c_client *client)
1125{
1126 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1127 struct tvp514x_decoder *decoder = to_decoder(sd);
1128
1129 v4l2_async_unregister_subdev(&decoder->sd);
1130 media_entity_cleanup(&decoder->sd.entity);
1131 v4l2_ctrl_handler_free(&decoder->hdl);
1132 return 0;
1133}
1134
1135static const struct tvp514x_reg tvp5146_init_reg_seq[] = {
1136 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x02},
1137 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1138 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0x80},
1139 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x01},
1140 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x60},
1141 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1142 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0xB0},
1143 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x01},
1144 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x00},
1145 {TOK_WRITE, REG_OPERATION_MODE, 0x01},
1146 {TOK_WRITE, REG_OPERATION_MODE, 0x00},
1147 {TOK_TERM, 0, 0},
1148};
1149
1150
1151static const struct tvp514x_reg tvp5147_init_reg_seq[] = {
1152 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x02},
1153 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1154 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0x80},
1155 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x01},
1156 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x60},
1157 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1158 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0xB0},
1159 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x01},
1160 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x16},
1161 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1162 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0xA0},
1163 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x16},
1164 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x60},
1165 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1166 {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0xB0},
1167 {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x00},
1168 {TOK_WRITE, REG_OPERATION_MODE, 0x01},
1169 {TOK_WRITE, REG_OPERATION_MODE, 0x00},
1170 {TOK_TERM, 0, 0},
1171};
1172
1173
1174static const struct tvp514x_reg tvp514xm_init_reg_seq[] = {
1175 {TOK_WRITE, REG_OPERATION_MODE, 0x01},
1176 {TOK_WRITE, REG_OPERATION_MODE, 0x00},
1177 {TOK_TERM, 0, 0},
1178};
1179
1180
1181
1182
1183
1184
1185
1186static const struct i2c_device_id tvp514x_id[] = {
1187 {"tvp5146", (unsigned long)tvp5146_init_reg_seq},
1188 {"tvp5146m2", (unsigned long)tvp514xm_init_reg_seq},
1189 {"tvp5147", (unsigned long)tvp5147_init_reg_seq},
1190 {"tvp5147m1", (unsigned long)tvp514xm_init_reg_seq},
1191 {},
1192};
1193
1194MODULE_DEVICE_TABLE(i2c, tvp514x_id);
1195
1196#if IS_ENABLED(CONFIG_OF)
1197static const struct of_device_id tvp514x_of_match[] = {
1198 { .compatible = "ti,tvp5146", },
1199 { .compatible = "ti,tvp5146m2", },
1200 { .compatible = "ti,tvp5147", },
1201 { .compatible = "ti,tvp5147m1", },
1202 { },
1203};
1204MODULE_DEVICE_TABLE(of, tvp514x_of_match);
1205#endif
1206
1207static struct i2c_driver tvp514x_driver = {
1208 .driver = {
1209 .of_match_table = of_match_ptr(tvp514x_of_match),
1210 .name = TVP514X_MODULE_NAME,
1211 },
1212 .probe = tvp514x_probe,
1213 .remove = tvp514x_remove,
1214 .id_table = tvp514x_id,
1215};
1216
1217module_i2c_driver(tvp514x_driver);
1218