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8#include <linux/clk.h>
9#include <linux/clk/tegra.h>
10#include <linux/debugfs.h>
11#include <linux/err.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/iopoll.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/platform_device.h>
19#include <linux/sort.h>
20#include <linux/types.h>
21
22#include <soc/tegra/fuse.h>
23
24#define EMC_INTSTATUS 0x000
25#define EMC_INTMASK 0x004
26#define EMC_DBG 0x008
27#define EMC_TIMING_CONTROL 0x028
28#define EMC_RC 0x02c
29#define EMC_RFC 0x030
30#define EMC_RAS 0x034
31#define EMC_RP 0x038
32#define EMC_R2W 0x03c
33#define EMC_W2R 0x040
34#define EMC_R2P 0x044
35#define EMC_W2P 0x048
36#define EMC_RD_RCD 0x04c
37#define EMC_WR_RCD 0x050
38#define EMC_RRD 0x054
39#define EMC_REXT 0x058
40#define EMC_WDV 0x05c
41#define EMC_QUSE 0x060
42#define EMC_QRST 0x064
43#define EMC_QSAFE 0x068
44#define EMC_RDV 0x06c
45#define EMC_REFRESH 0x070
46#define EMC_BURST_REFRESH_NUM 0x074
47#define EMC_PDEX2WR 0x078
48#define EMC_PDEX2RD 0x07c
49#define EMC_PCHG2PDEN 0x080
50#define EMC_ACT2PDEN 0x084
51#define EMC_AR2PDEN 0x088
52#define EMC_RW2PDEN 0x08c
53#define EMC_TXSR 0x090
54#define EMC_TCKE 0x094
55#define EMC_TFAW 0x098
56#define EMC_TRPAB 0x09c
57#define EMC_TCLKSTABLE 0x0a0
58#define EMC_TCLKSTOP 0x0a4
59#define EMC_TREFBW 0x0a8
60#define EMC_QUSE_EXTRA 0x0ac
61#define EMC_ODT_WRITE 0x0b0
62#define EMC_ODT_READ 0x0b4
63#define EMC_FBIO_CFG5 0x104
64#define EMC_FBIO_CFG6 0x114
65#define EMC_AUTO_CAL_INTERVAL 0x2a8
66#define EMC_CFG_2 0x2b8
67#define EMC_CFG_DIG_DLL 0x2bc
68#define EMC_DLL_XFORM_DQS 0x2c0
69#define EMC_DLL_XFORM_QUSE 0x2c4
70#define EMC_ZCAL_REF_CNT 0x2e0
71#define EMC_ZCAL_WAIT_CNT 0x2e4
72#define EMC_CFG_CLKTRIM_0 0x2d0
73#define EMC_CFG_CLKTRIM_1 0x2d4
74#define EMC_CFG_CLKTRIM_2 0x2d8
75
76#define EMC_CLKCHANGE_REQ_ENABLE BIT(0)
77#define EMC_CLKCHANGE_PD_ENABLE BIT(1)
78#define EMC_CLKCHANGE_SR_ENABLE BIT(2)
79
80#define EMC_TIMING_UPDATE BIT(0)
81
82#define EMC_REFRESH_OVERFLOW_INT BIT(3)
83#define EMC_CLKCHANGE_COMPLETE_INT BIT(4)
84
85#define EMC_DBG_READ_MUX_ASSEMBLY BIT(0)
86#define EMC_DBG_WRITE_MUX_ACTIVE BIT(1)
87#define EMC_DBG_FORCE_UPDATE BIT(2)
88#define EMC_DBG_READ_DQM_CTRL BIT(9)
89#define EMC_DBG_CFG_PRIORITY BIT(24)
90
91static const u16 emc_timing_registers[] = {
92 EMC_RC,
93 EMC_RFC,
94 EMC_RAS,
95 EMC_RP,
96 EMC_R2W,
97 EMC_W2R,
98 EMC_R2P,
99 EMC_W2P,
100 EMC_RD_RCD,
101 EMC_WR_RCD,
102 EMC_RRD,
103 EMC_REXT,
104 EMC_WDV,
105 EMC_QUSE,
106 EMC_QRST,
107 EMC_QSAFE,
108 EMC_RDV,
109 EMC_REFRESH,
110 EMC_BURST_REFRESH_NUM,
111 EMC_PDEX2WR,
112 EMC_PDEX2RD,
113 EMC_PCHG2PDEN,
114 EMC_ACT2PDEN,
115 EMC_AR2PDEN,
116 EMC_RW2PDEN,
117 EMC_TXSR,
118 EMC_TCKE,
119 EMC_TFAW,
120 EMC_TRPAB,
121 EMC_TCLKSTABLE,
122 EMC_TCLKSTOP,
123 EMC_TREFBW,
124 EMC_QUSE_EXTRA,
125 EMC_FBIO_CFG6,
126 EMC_ODT_WRITE,
127 EMC_ODT_READ,
128 EMC_FBIO_CFG5,
129 EMC_CFG_DIG_DLL,
130 EMC_DLL_XFORM_DQS,
131 EMC_DLL_XFORM_QUSE,
132 EMC_ZCAL_REF_CNT,
133 EMC_ZCAL_WAIT_CNT,
134 EMC_AUTO_CAL_INTERVAL,
135 EMC_CFG_CLKTRIM_0,
136 EMC_CFG_CLKTRIM_1,
137 EMC_CFG_CLKTRIM_2,
138};
139
140struct emc_timing {
141 unsigned long rate;
142 u32 data[ARRAY_SIZE(emc_timing_registers)];
143};
144
145struct tegra_emc {
146 struct device *dev;
147 struct notifier_block clk_nb;
148 struct clk *clk;
149 void __iomem *regs;
150
151 struct emc_timing *timings;
152 unsigned int num_timings;
153
154 struct {
155 struct dentry *root;
156 unsigned long min_rate;
157 unsigned long max_rate;
158 } debugfs;
159};
160
161static irqreturn_t tegra_emc_isr(int irq, void *data)
162{
163 struct tegra_emc *emc = data;
164 u32 intmask = EMC_REFRESH_OVERFLOW_INT;
165 u32 status;
166
167 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask;
168 if (!status)
169 return IRQ_NONE;
170
171
172 if (status & EMC_REFRESH_OVERFLOW_INT)
173 dev_err_ratelimited(emc->dev,
174 "refresh request overflow timeout\n");
175
176
177 writel_relaxed(status, emc->regs + EMC_INTSTATUS);
178
179 return IRQ_HANDLED;
180}
181
182static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc,
183 unsigned long rate)
184{
185 struct emc_timing *timing = NULL;
186 unsigned int i;
187
188 for (i = 0; i < emc->num_timings; i++) {
189 if (emc->timings[i].rate >= rate) {
190 timing = &emc->timings[i];
191 break;
192 }
193 }
194
195 if (!timing) {
196 dev_err(emc->dev, "no timing for rate %lu\n", rate);
197 return NULL;
198 }
199
200 return timing;
201}
202
203static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate)
204{
205 struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
206 unsigned int i;
207
208 if (!timing)
209 return -EINVAL;
210
211 dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n",
212 __func__, timing->rate, rate);
213
214
215 for (i = 0; i < ARRAY_SIZE(timing->data); i++)
216 writel_relaxed(timing->data[i],
217 emc->regs + emc_timing_registers[i]);
218
219
220 readl_relaxed(emc->regs + emc_timing_registers[i - 1]);
221
222 return 0;
223}
224
225static int emc_complete_timing_change(struct tegra_emc *emc, bool flush)
226{
227 int err;
228 u32 v;
229
230 dev_dbg(emc->dev, "%s: flush %d\n", __func__, flush);
231
232 if (flush) {
233
234 writel_relaxed(EMC_TIMING_UPDATE,
235 emc->regs + EMC_TIMING_CONTROL);
236 return 0;
237 }
238
239 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v,
240 v & EMC_CLKCHANGE_COMPLETE_INT,
241 1, 100);
242 if (err) {
243 dev_err(emc->dev, "emc-car handshake timeout: %d\n", err);
244 return err;
245 }
246
247 return 0;
248}
249
250static int tegra_emc_clk_change_notify(struct notifier_block *nb,
251 unsigned long msg, void *data)
252{
253 struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb);
254 struct clk_notifier_data *cnd = data;
255 int err;
256
257 switch (msg) {
258 case PRE_RATE_CHANGE:
259 err = emc_prepare_timing_change(emc, cnd->new_rate);
260 break;
261
262 case ABORT_RATE_CHANGE:
263 err = emc_prepare_timing_change(emc, cnd->old_rate);
264 if (err)
265 break;
266
267 err = emc_complete_timing_change(emc, true);
268 break;
269
270 case POST_RATE_CHANGE:
271 err = emc_complete_timing_change(emc, false);
272 break;
273
274 default:
275 return NOTIFY_DONE;
276 }
277
278 return notifier_from_errno(err);
279}
280
281static int load_one_timing_from_dt(struct tegra_emc *emc,
282 struct emc_timing *timing,
283 struct device_node *node)
284{
285 u32 rate;
286 int err;
287
288 if (!of_device_is_compatible(node, "nvidia,tegra20-emc-table")) {
289 dev_err(emc->dev, "incompatible DT node: %pOF\n", node);
290 return -EINVAL;
291 }
292
293 err = of_property_read_u32(node, "clock-frequency", &rate);
294 if (err) {
295 dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n",
296 node, err);
297 return err;
298 }
299
300 err = of_property_read_u32_array(node, "nvidia,emc-registers",
301 timing->data,
302 ARRAY_SIZE(emc_timing_registers));
303 if (err) {
304 dev_err(emc->dev,
305 "timing %pOF: failed to read emc timing data: %d\n",
306 node, err);
307 return err;
308 }
309
310
311
312
313
314 timing->rate = rate * 2 * 1000;
315
316 dev_dbg(emc->dev, "%s: %pOF: EMC rate %lu\n",
317 __func__, node, timing->rate);
318
319 return 0;
320}
321
322static int cmp_timings(const void *_a, const void *_b)
323{
324 const struct emc_timing *a = _a;
325 const struct emc_timing *b = _b;
326
327 if (a->rate < b->rate)
328 return -1;
329
330 if (a->rate > b->rate)
331 return 1;
332
333 return 0;
334}
335
336static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,
337 struct device_node *node)
338{
339 struct device_node *child;
340 struct emc_timing *timing;
341 int child_count;
342 int err;
343
344 child_count = of_get_child_count(node);
345 if (!child_count) {
346 dev_err(emc->dev, "no memory timings in DT node: %pOF\n", node);
347 return -EINVAL;
348 }
349
350 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
351 GFP_KERNEL);
352 if (!emc->timings)
353 return -ENOMEM;
354
355 emc->num_timings = child_count;
356 timing = emc->timings;
357
358 for_each_child_of_node(node, child) {
359 err = load_one_timing_from_dt(emc, timing++, child);
360 if (err) {
361 of_node_put(child);
362 return err;
363 }
364 }
365
366 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
367 NULL);
368
369 dev_info(emc->dev,
370 "got %u timings for RAM code %u (min %luMHz max %luMHz)\n",
371 emc->num_timings,
372 tegra_read_ram_code(),
373 emc->timings[0].rate / 1000000,
374 emc->timings[emc->num_timings - 1].rate / 1000000);
375
376 return 0;
377}
378
379static struct device_node *
380tegra_emc_find_node_by_ram_code(struct device *dev)
381{
382 struct device_node *np;
383 u32 value, ram_code;
384 int err;
385
386 if (!of_property_read_bool(dev->of_node, "nvidia,use-ram-code"))
387 return of_node_get(dev->of_node);
388
389 ram_code = tegra_read_ram_code();
390
391 for (np = of_find_node_by_name(dev->of_node, "emc-tables"); np;
392 np = of_find_node_by_name(np, "emc-tables")) {
393 err = of_property_read_u32(np, "nvidia,ram-code", &value);
394 if (err || value != ram_code) {
395 of_node_put(np);
396 continue;
397 }
398
399 return np;
400 }
401
402 dev_err(dev, "no memory timings for RAM code %u found in device tree\n",
403 ram_code);
404
405 return NULL;
406}
407
408static int emc_setup_hw(struct tegra_emc *emc)
409{
410 u32 intmask = EMC_REFRESH_OVERFLOW_INT;
411 u32 emc_cfg, emc_dbg;
412
413 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2);
414
415
416
417
418
419 if (!(emc_cfg & EMC_CLKCHANGE_PD_ENABLE) &&
420 !(emc_cfg & EMC_CLKCHANGE_SR_ENABLE)) {
421 dev_err(emc->dev,
422 "bootloader didn't specify DRAM auto-suspend mode\n");
423 return -EINVAL;
424 }
425
426
427 emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE;
428 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2);
429
430
431 writel_relaxed(intmask, emc->regs + EMC_INTMASK);
432 writel_relaxed(intmask, emc->regs + EMC_INTSTATUS);
433
434
435 emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
436 emc_dbg |= EMC_DBG_CFG_PRIORITY;
437 emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY;
438 emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE;
439 emc_dbg &= ~EMC_DBG_FORCE_UPDATE;
440 writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
441
442 return 0;
443}
444
445static long emc_round_rate(unsigned long rate,
446 unsigned long min_rate,
447 unsigned long max_rate,
448 void *arg)
449{
450 struct emc_timing *timing = NULL;
451 struct tegra_emc *emc = arg;
452 unsigned int i;
453
454 min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate);
455
456 for (i = 0; i < emc->num_timings; i++) {
457 if (emc->timings[i].rate < rate && i != emc->num_timings - 1)
458 continue;
459
460 if (emc->timings[i].rate > max_rate) {
461 i = max(i, 1u) - 1;
462
463 if (emc->timings[i].rate < min_rate)
464 break;
465 }
466
467 if (emc->timings[i].rate < min_rate)
468 continue;
469
470 timing = &emc->timings[i];
471 break;
472 }
473
474 if (!timing) {
475 dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n",
476 rate, min_rate, max_rate);
477 return -EINVAL;
478 }
479
480 return timing->rate;
481}
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508static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate)
509{
510 unsigned int i;
511
512 for (i = 0; i < emc->num_timings; i++)
513 if (rate == emc->timings[i].rate)
514 return true;
515
516 return false;
517}
518
519static int tegra_emc_debug_available_rates_show(struct seq_file *s, void *data)
520{
521 struct tegra_emc *emc = s->private;
522 const char *prefix = "";
523 unsigned int i;
524
525 for (i = 0; i < emc->num_timings; i++) {
526 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate);
527 prefix = " ";
528 }
529
530 seq_puts(s, "\n");
531
532 return 0;
533}
534
535static int tegra_emc_debug_available_rates_open(struct inode *inode,
536 struct file *file)
537{
538 return single_open(file, tegra_emc_debug_available_rates_show,
539 inode->i_private);
540}
541
542static const struct file_operations tegra_emc_debug_available_rates_fops = {
543 .open = tegra_emc_debug_available_rates_open,
544 .read = seq_read,
545 .llseek = seq_lseek,
546 .release = single_release,
547};
548
549static int tegra_emc_debug_min_rate_get(void *data, u64 *rate)
550{
551 struct tegra_emc *emc = data;
552
553 *rate = emc->debugfs.min_rate;
554
555 return 0;
556}
557
558static int tegra_emc_debug_min_rate_set(void *data, u64 rate)
559{
560 struct tegra_emc *emc = data;
561 int err;
562
563 if (!tegra_emc_validate_rate(emc, rate))
564 return -EINVAL;
565
566 err = clk_set_min_rate(emc->clk, rate);
567 if (err < 0)
568 return err;
569
570 emc->debugfs.min_rate = rate;
571
572 return 0;
573}
574
575DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_min_rate_fops,
576 tegra_emc_debug_min_rate_get,
577 tegra_emc_debug_min_rate_set, "%llu\n");
578
579static int tegra_emc_debug_max_rate_get(void *data, u64 *rate)
580{
581 struct tegra_emc *emc = data;
582
583 *rate = emc->debugfs.max_rate;
584
585 return 0;
586}
587
588static int tegra_emc_debug_max_rate_set(void *data, u64 rate)
589{
590 struct tegra_emc *emc = data;
591 int err;
592
593 if (!tegra_emc_validate_rate(emc, rate))
594 return -EINVAL;
595
596 err = clk_set_max_rate(emc->clk, rate);
597 if (err < 0)
598 return err;
599
600 emc->debugfs.max_rate = rate;
601
602 return 0;
603}
604
605DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_max_rate_fops,
606 tegra_emc_debug_max_rate_get,
607 tegra_emc_debug_max_rate_set, "%llu\n");
608
609static void tegra_emc_debugfs_init(struct tegra_emc *emc)
610{
611 struct device *dev = emc->dev;
612 unsigned int i;
613 int err;
614
615 emc->debugfs.min_rate = ULONG_MAX;
616 emc->debugfs.max_rate = 0;
617
618 for (i = 0; i < emc->num_timings; i++) {
619 if (emc->timings[i].rate < emc->debugfs.min_rate)
620 emc->debugfs.min_rate = emc->timings[i].rate;
621
622 if (emc->timings[i].rate > emc->debugfs.max_rate)
623 emc->debugfs.max_rate = emc->timings[i].rate;
624 }
625
626 if (!emc->num_timings) {
627 emc->debugfs.min_rate = clk_get_rate(emc->clk);
628 emc->debugfs.max_rate = emc->debugfs.min_rate;
629 }
630
631 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
632 emc->debugfs.max_rate);
633 if (err < 0) {
634 dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n",
635 emc->debugfs.min_rate, emc->debugfs.max_rate,
636 emc->clk);
637 }
638
639 emc->debugfs.root = debugfs_create_dir("emc", NULL);
640 if (!emc->debugfs.root) {
641 dev_err(emc->dev, "failed to create debugfs directory\n");
642 return;
643 }
644
645 debugfs_create_file("available_rates", 0444, emc->debugfs.root,
646 emc, &tegra_emc_debug_available_rates_fops);
647 debugfs_create_file("min_rate", 0644, emc->debugfs.root,
648 emc, &tegra_emc_debug_min_rate_fops);
649 debugfs_create_file("max_rate", 0644, emc->debugfs.root,
650 emc, &tegra_emc_debug_max_rate_fops);
651}
652
653static int tegra_emc_probe(struct platform_device *pdev)
654{
655 struct device_node *np;
656 struct tegra_emc *emc;
657 struct resource *res;
658 int irq, err;
659
660
661 if (of_get_child_count(pdev->dev.of_node) == 0) {
662 dev_info(&pdev->dev,
663 "EMC device tree node doesn't have memory timings\n");
664 return 0;
665 }
666
667 irq = platform_get_irq(pdev, 0);
668 if (irq < 0) {
669 dev_err(&pdev->dev, "interrupt not specified\n");
670 dev_err(&pdev->dev, "please update your device tree\n");
671 return irq;
672 }
673
674 np = tegra_emc_find_node_by_ram_code(&pdev->dev);
675 if (!np)
676 return -EINVAL;
677
678 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
679 if (!emc) {
680 of_node_put(np);
681 return -ENOMEM;
682 }
683
684 emc->clk_nb.notifier_call = tegra_emc_clk_change_notify;
685 emc->dev = &pdev->dev;
686
687 err = tegra_emc_load_timings_from_dt(emc, np);
688 of_node_put(np);
689 if (err)
690 return err;
691
692 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
693 emc->regs = devm_ioremap_resource(&pdev->dev, res);
694 if (IS_ERR(emc->regs))
695 return PTR_ERR(emc->regs);
696
697 err = emc_setup_hw(emc);
698 if (err)
699 return err;
700
701 err = devm_request_irq(&pdev->dev, irq, tegra_emc_isr, 0,
702 dev_name(&pdev->dev), emc);
703 if (err) {
704 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", irq, err);
705 return err;
706 }
707
708 tegra20_clk_set_emc_round_callback(emc_round_rate, emc);
709
710 emc->clk = devm_clk_get(&pdev->dev, "emc");
711 if (IS_ERR(emc->clk)) {
712 err = PTR_ERR(emc->clk);
713 dev_err(&pdev->dev, "failed to get emc clock: %d\n", err);
714 goto unset_cb;
715 }
716
717 err = clk_notifier_register(emc->clk, &emc->clk_nb);
718 if (err) {
719 dev_err(&pdev->dev, "failed to register clk notifier: %d\n",
720 err);
721 goto unset_cb;
722 }
723
724 platform_set_drvdata(pdev, emc);
725 tegra_emc_debugfs_init(emc);
726
727 return 0;
728
729unset_cb:
730 tegra20_clk_set_emc_round_callback(NULL, NULL);
731
732 return err;
733}
734
735static const struct of_device_id tegra_emc_of_match[] = {
736 { .compatible = "nvidia,tegra20-emc", },
737 {},
738};
739
740static struct platform_driver tegra_emc_driver = {
741 .probe = tegra_emc_probe,
742 .driver = {
743 .name = "tegra20-emc",
744 .of_match_table = tegra_emc_of_match,
745 .suppress_bind_attrs = true,
746 },
747};
748
749static int __init tegra_emc_init(void)
750{
751 return platform_driver_register(&tegra_emc_driver);
752}
753subsys_initcall(tegra_emc_init);
754
