LXR linux/drivers/misc/xilinx-ai-engine/ai-engine-fpga.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Xilinx AI Engine driver FPGA region implementation
   4 *
   5 * Copyright (C) 2020 Xilinx, Inc.
   6 */
   7
   8#include "ai-engine-internal.h"
   9
  10static int aie_fpga_bridge_enable_set(struct fpga_bridge *bridge, bool enable)
  11{
  12        struct aie_partition *apart = bridge->priv;
  13        int ret;
  14
  15        /*
  16         * TBD:
  17         * "Enable" should enable the SHIM tile configuration.
  18         * "Disable" should disable SHIM DMAs, and wait until SHIM DMA stops,
  19         * and disable SHIM to PL streams within partition.
  20         */
  21        ret = mutex_lock_interruptible(&apart->mlock);
  22        if (ret)
  23                return ret;
  24
  25        if (enable)
  26                apart->status |= XAIE_PART_STATUS_BRIDGE_ENABLED;
  27        else
  28                apart->status &= ~XAIE_PART_STATUS_BRIDGE_ENABLED;
  29        mutex_unlock(&apart->mlock);
  30        return 0;
  31}
  32
  33static int aie_fpga_bridge_enable_show(struct fpga_bridge *bridge)
  34{
  35        struct aie_partition *apart = bridge->priv;
  36        int ret;
  37
  38        ret = mutex_lock_interruptible(&apart->mlock);
  39        if (ret)
  40                return ret;
  41
  42        if (apart->status & XAIE_PART_STATUS_BRIDGE_ENABLED)
  43                ret = 1;
  44        else
  45                ret = 0;
  46        mutex_unlock(&apart->mlock);
  47        return ret;
  48}
  49
  50static const struct fpga_bridge_ops aie_fpga_bridge_ops = {
  51        .enable_set = aie_fpga_bridge_enable_set,
  52        .enable_show = aie_fpga_bridge_enable_show,
  53};
  54
  55/**
  56 * aie_fpga_create_bridge() - Create FPGA bridge for AI engine partition
  57 * @apart: AI engine partition
  58 * @return: 0 for success, negative value for failure
  59 *
  60 * This function will create FPGA bridge for AI engine partition.
  61 * FPGA bridge is the presentation of SHIM row of the AI engine partition.
  62 * FPGA bridge connects AI engine partition with other FPGA regions.
  63 */
  64int aie_fpga_create_bridge(struct aie_partition *apart)
  65{
  66        struct fpga_bridge *br;
  67        int ret;
  68
  69        snprintf(apart->br.name, sizeof(apart->br.name) - 1,
  70                 "xlnx-aie-bridge-%u-%u", apart->range.start.col, 0);
  71        br = devm_fpga_bridge_create(&apart->dev, apart->br.name,
  72                                     &aie_fpga_bridge_ops, apart);
  73        if (!br)
  74                return -ENOMEM;
  75        ret = fpga_bridge_register(br);
  76        if (ret) {
  77                dev_err(&apart->dev, "Failed to register bridge.\n");
  78                return ret;
  79        }
  80        apart->br.br = br;
  81        return 0;
  82}
  83
  84/**
  85 * aie_fpga_free_bridge() - Free AI engine partition FPGA bridge
  86 * @apart: AI engine partition
  87 *
  88 * This function will free the FPGA bridge for AI engine partition.
  89 */
  90void aie_fpga_free_bridge(struct aie_partition *apart)
  91{
  92        if (!WARN_ON(!apart->br.br))
  93                fpga_bridge_unregister(apart->br.br);
  94}
  95