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9#include <linux/err.h>
10#include <linux/init.h>
11#include <linux/slab.h>
12#include <linux/module.h>
13#include <linux/platform_device.h>
14#include <linux/delay.h>
15#include <linux/mtd/mtd.h>
16#include <linux/mtd/rawnand.h>
17#include <linux/mtd/nand_ecc.h>
18#include <linux/mtd/partitions.h>
19#include <linux/io.h>
20#include <linux/platform_data/txx9/ndfmc.h>
21
22
23#define TXX9_NDFDTR 0x00
24#define TXX9_NDFMCR 0x04
25#define TXX9_NDFSR 0x08
26#define TXX9_NDFISR 0x0c
27#define TXX9_NDFIMR 0x10
28#define TXX9_NDFSPR 0x14
29#define TXX9_NDFRSTR 0x18
30
31
32#define TXX9_NDFMCR_WE 0x80
33#define TXX9_NDFMCR_ECC_ALL 0x60
34#define TXX9_NDFMCR_ECC_RESET 0x60
35#define TXX9_NDFMCR_ECC_READ 0x40
36#define TXX9_NDFMCR_ECC_ON 0x20
37#define TXX9_NDFMCR_ECC_OFF 0x00
38#define TXX9_NDFMCR_CE 0x10
39#define TXX9_NDFMCR_BSPRT 0x04
40#define TXX9_NDFMCR_ALE 0x02
41#define TXX9_NDFMCR_CLE 0x01
42
43#define TXX9_NDFMCR_X16 0x0400
44#define TXX9_NDFMCR_DMAREQ_MASK 0x0300
45#define TXX9_NDFMCR_DMAREQ_NODMA 0x0000
46#define TXX9_NDFMCR_DMAREQ_128 0x0100
47#define TXX9_NDFMCR_DMAREQ_256 0x0200
48#define TXX9_NDFMCR_DMAREQ_512 0x0300
49#define TXX9_NDFMCR_CS_MASK 0x0c
50#define TXX9_NDFMCR_CS(ch) ((ch) << 2)
51
52
53#define TXX9_NDFSR_BUSY 0x80
54
55#define TXX9_NDFSR_DMARUN 0x40
56
57
58#define TXX9_NDFRSTR_RST 0x01
59
60struct txx9ndfmc_priv {
61 struct platform_device *dev;
62 struct nand_chip chip;
63 int cs;
64 const char *mtdname;
65};
66
67#define MAX_TXX9NDFMC_DEV 4
68struct txx9ndfmc_drvdata {
69 struct mtd_info *mtds[MAX_TXX9NDFMC_DEV];
70 void __iomem *base;
71 unsigned char hold;
72 unsigned char spw;
73 struct nand_controller controller;
74};
75
76static struct platform_device *mtd_to_platdev(struct mtd_info *mtd)
77{
78 struct nand_chip *chip = mtd_to_nand(mtd);
79 struct txx9ndfmc_priv *txx9_priv = nand_get_controller_data(chip);
80 return txx9_priv->dev;
81}
82
83static void __iomem *ndregaddr(struct platform_device *dev, unsigned int reg)
84{
85 struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
86 struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev);
87
88 return drvdata->base + (reg << plat->shift);
89}
90
91static u32 txx9ndfmc_read(struct platform_device *dev, unsigned int reg)
92{
93 return __raw_readl(ndregaddr(dev, reg));
94}
95
96static void txx9ndfmc_write(struct platform_device *dev,
97 u32 val, unsigned int reg)
98{
99 __raw_writel(val, ndregaddr(dev, reg));
100}
101
102static uint8_t txx9ndfmc_read_byte(struct nand_chip *chip)
103{
104 struct platform_device *dev = mtd_to_platdev(nand_to_mtd(chip));
105
106 return txx9ndfmc_read(dev, TXX9_NDFDTR);
107}
108
109static void txx9ndfmc_write_buf(struct nand_chip *chip, const uint8_t *buf,
110 int len)
111{
112 struct platform_device *dev = mtd_to_platdev(nand_to_mtd(chip));
113 void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
114 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
115
116 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_WE, TXX9_NDFMCR);
117 while (len--)
118 __raw_writel(*buf++, ndfdtr);
119 txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
120}
121
122static void txx9ndfmc_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
123{
124 struct platform_device *dev = mtd_to_platdev(nand_to_mtd(chip));
125 void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
126
127 while (len--)
128 *buf++ = __raw_readl(ndfdtr);
129}
130
131static void txx9ndfmc_cmd_ctrl(struct nand_chip *chip, int cmd,
132 unsigned int ctrl)
133{
134 struct txx9ndfmc_priv *txx9_priv = nand_get_controller_data(chip);
135 struct platform_device *dev = txx9_priv->dev;
136 struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev);
137
138 if (ctrl & NAND_CTRL_CHANGE) {
139 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
140
141 mcr &= ~(TXX9_NDFMCR_CLE | TXX9_NDFMCR_ALE | TXX9_NDFMCR_CE);
142 mcr |= ctrl & NAND_CLE ? TXX9_NDFMCR_CLE : 0;
143 mcr |= ctrl & NAND_ALE ? TXX9_NDFMCR_ALE : 0;
144
145 mcr |= ctrl & NAND_NCE ? TXX9_NDFMCR_CE : 0;
146 if (txx9_priv->cs >= 0 && (ctrl & NAND_NCE)) {
147 mcr &= ~TXX9_NDFMCR_CS_MASK;
148 mcr |= TXX9_NDFMCR_CS(txx9_priv->cs);
149 }
150 txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
151 }
152 if (cmd != NAND_CMD_NONE)
153 txx9ndfmc_write(dev, cmd & 0xff, TXX9_NDFDTR);
154 if (plat->flags & NDFMC_PLAT_FLAG_DUMMYWRITE) {
155
156 if ((ctrl & NAND_CTRL_CHANGE) && cmd == NAND_CMD_NONE)
157 txx9ndfmc_write(dev, 0, TXX9_NDFDTR);
158 }
159}
160
161static int txx9ndfmc_dev_ready(struct nand_chip *chip)
162{
163 struct platform_device *dev = mtd_to_platdev(nand_to_mtd(chip));
164
165 return !(txx9ndfmc_read(dev, TXX9_NDFSR) & TXX9_NDFSR_BUSY);
166}
167
168static int txx9ndfmc_calculate_ecc(struct nand_chip *chip, const uint8_t *dat,
169 uint8_t *ecc_code)
170{
171 struct platform_device *dev = mtd_to_platdev(nand_to_mtd(chip));
172 int eccbytes;
173 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
174
175 mcr &= ~TXX9_NDFMCR_ECC_ALL;
176 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
177 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_READ, TXX9_NDFMCR);
178 for (eccbytes = chip->ecc.bytes; eccbytes > 0; eccbytes -= 3) {
179 ecc_code[1] = txx9ndfmc_read(dev, TXX9_NDFDTR);
180 ecc_code[0] = txx9ndfmc_read(dev, TXX9_NDFDTR);
181 ecc_code[2] = txx9ndfmc_read(dev, TXX9_NDFDTR);
182 ecc_code += 3;
183 }
184 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
185 return 0;
186}
187
188static int txx9ndfmc_correct_data(struct nand_chip *chip, unsigned char *buf,
189 unsigned char *read_ecc,
190 unsigned char *calc_ecc)
191{
192 int eccsize;
193 int corrected = 0;
194 int stat;
195
196 for (eccsize = chip->ecc.size; eccsize > 0; eccsize -= 256) {
197 stat = __nand_correct_data(buf, read_ecc, calc_ecc, 256,
198 false);
199 if (stat < 0)
200 return stat;
201 corrected += stat;
202 buf += 256;
203 read_ecc += 3;
204 calc_ecc += 3;
205 }
206 return corrected;
207}
208
209static void txx9ndfmc_enable_hwecc(struct nand_chip *chip, int mode)
210{
211 struct platform_device *dev = mtd_to_platdev(nand_to_mtd(chip));
212 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
213
214 mcr &= ~TXX9_NDFMCR_ECC_ALL;
215 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_RESET, TXX9_NDFMCR);
216 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
217 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_ON, TXX9_NDFMCR);
218}
219
220static void txx9ndfmc_initialize(struct platform_device *dev)
221{
222 struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev);
223 struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
224 int tmout = 100;
225
226 if (plat->flags & NDFMC_PLAT_FLAG_NO_RSTR)
227 ;
228 else {
229
230 txx9ndfmc_write(dev,
231 txx9ndfmc_read(dev, TXX9_NDFRSTR) |
232 TXX9_NDFRSTR_RST,
233 TXX9_NDFRSTR);
234 while (txx9ndfmc_read(dev, TXX9_NDFRSTR) & TXX9_NDFRSTR_RST) {
235 if (--tmout == 0) {
236 dev_err(&dev->dev, "reset failed.\n");
237 break;
238 }
239 udelay(1);
240 }
241 }
242
243 txx9ndfmc_write(dev, (drvdata->hold << 4) | drvdata->spw, TXX9_NDFSPR);
244 txx9ndfmc_write(dev,
245 (plat->flags & NDFMC_PLAT_FLAG_USE_BSPRT) ?
246 TXX9_NDFMCR_BSPRT : 0, TXX9_NDFMCR);
247}
248
249#define TXX9NDFMC_NS_TO_CYC(gbusclk, ns) \
250 DIV_ROUND_UP((ns) * DIV_ROUND_UP(gbusclk, 1000), 1000000)
251
252static int txx9ndfmc_attach_chip(struct nand_chip *chip)
253{
254 struct mtd_info *mtd = nand_to_mtd(chip);
255
256 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
257 return 0;
258
259 chip->ecc.strength = 1;
260
261 if (mtd->writesize >= 512) {
262 chip->ecc.size = 512;
263 chip->ecc.bytes = 6;
264 } else {
265 chip->ecc.size = 256;
266 chip->ecc.bytes = 3;
267 }
268
269 chip->ecc.calculate = txx9ndfmc_calculate_ecc;
270 chip->ecc.correct = txx9ndfmc_correct_data;
271 chip->ecc.hwctl = txx9ndfmc_enable_hwecc;
272
273 return 0;
274}
275
276static const struct nand_controller_ops txx9ndfmc_controller_ops = {
277 .attach_chip = txx9ndfmc_attach_chip,
278};
279
280static int __init txx9ndfmc_probe(struct platform_device *dev)
281{
282 struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev);
283 int hold, spw;
284 int i;
285 struct txx9ndfmc_drvdata *drvdata;
286 unsigned long gbusclk = plat->gbus_clock;
287 struct resource *res;
288
289 drvdata = devm_kzalloc(&dev->dev, sizeof(*drvdata), GFP_KERNEL);
290 if (!drvdata)
291 return -ENOMEM;
292 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
293 drvdata->base = devm_ioremap_resource(&dev->dev, res);
294 if (IS_ERR(drvdata->base))
295 return PTR_ERR(drvdata->base);
296
297 hold = plat->hold ?: 20;
298 spw = plat->spw ?: 90;
299
300 hold = TXX9NDFMC_NS_TO_CYC(gbusclk, hold);
301 spw = TXX9NDFMC_NS_TO_CYC(gbusclk, spw);
302 if (plat->flags & NDFMC_PLAT_FLAG_HOLDADD)
303 hold -= 2;
304 spw -= 1;
305 hold = clamp(hold, 1, 15);
306 drvdata->hold = hold;
307 spw = clamp(spw, 1, 15);
308 drvdata->spw = spw;
309 dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n",
310 (gbusclk + 500000) / 1000000, hold, spw);
311
312 nand_controller_init(&drvdata->controller);
313 drvdata->controller.ops = &txx9ndfmc_controller_ops;
314
315 platform_set_drvdata(dev, drvdata);
316 txx9ndfmc_initialize(dev);
317
318 for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
319 struct txx9ndfmc_priv *txx9_priv;
320 struct nand_chip *chip;
321 struct mtd_info *mtd;
322
323 if (!(plat->ch_mask & (1 << i)))
324 continue;
325 txx9_priv = kzalloc(sizeof(struct txx9ndfmc_priv),
326 GFP_KERNEL);
327 if (!txx9_priv)
328 continue;
329 chip = &txx9_priv->chip;
330 mtd = nand_to_mtd(chip);
331 mtd->dev.parent = &dev->dev;
332
333 chip->legacy.read_byte = txx9ndfmc_read_byte;
334 chip->legacy.read_buf = txx9ndfmc_read_buf;
335 chip->legacy.write_buf = txx9ndfmc_write_buf;
336 chip->legacy.cmd_ctrl = txx9ndfmc_cmd_ctrl;
337 chip->legacy.dev_ready = txx9ndfmc_dev_ready;
338 chip->legacy.chip_delay = 100;
339 chip->controller = &drvdata->controller;
340
341 nand_set_controller_data(chip, txx9_priv);
342 txx9_priv->dev = dev;
343
344 if (plat->ch_mask != 1) {
345 txx9_priv->cs = i;
346 txx9_priv->mtdname = kasprintf(GFP_KERNEL, "%s.%u",
347 dev_name(&dev->dev), i);
348 } else {
349 txx9_priv->cs = -1;
350 txx9_priv->mtdname = kstrdup(dev_name(&dev->dev),
351 GFP_KERNEL);
352 }
353 if (!txx9_priv->mtdname) {
354 kfree(txx9_priv);
355 dev_err(&dev->dev, "Unable to allocate MTD name.\n");
356 continue;
357 }
358 if (plat->wide_mask & (1 << i))
359 chip->options |= NAND_BUSWIDTH_16;
360
361 if (nand_scan(chip, 1)) {
362 kfree(txx9_priv->mtdname);
363 kfree(txx9_priv);
364 continue;
365 }
366 mtd->name = txx9_priv->mtdname;
367
368 mtd_device_register(mtd, NULL, 0);
369 drvdata->mtds[i] = mtd;
370 }
371
372 return 0;
373}
374
375static int __exit txx9ndfmc_remove(struct platform_device *dev)
376{
377 struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
378 int ret, i;
379
380 if (!drvdata)
381 return 0;
382 for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
383 struct mtd_info *mtd = drvdata->mtds[i];
384 struct nand_chip *chip;
385 struct txx9ndfmc_priv *txx9_priv;
386
387 if (!mtd)
388 continue;
389 chip = mtd_to_nand(mtd);
390 txx9_priv = nand_get_controller_data(chip);
391
392 ret = mtd_device_unregister(nand_to_mtd(chip));
393 WARN_ON(ret);
394 nand_cleanup(chip);
395 kfree(txx9_priv->mtdname);
396 kfree(txx9_priv);
397 }
398 return 0;
399}
400
401#ifdef CONFIG_PM
402static int txx9ndfmc_resume(struct platform_device *dev)
403{
404 if (platform_get_drvdata(dev))
405 txx9ndfmc_initialize(dev);
406 return 0;
407}
408#else
409#define txx9ndfmc_resume NULL
410#endif
411
412static struct platform_driver txx9ndfmc_driver = {
413 .remove = __exit_p(txx9ndfmc_remove),
414 .resume = txx9ndfmc_resume,
415 .driver = {
416 .name = "txx9ndfmc",
417 },
418};
419
420module_platform_driver_probe(txx9ndfmc_driver, txx9ndfmc_probe);
421
422MODULE_LICENSE("GPL");
423MODULE_DESCRIPTION("TXx9 SoC NAND flash controller driver");
424MODULE_ALIAS("platform:txx9ndfmc");
425
