1
2
3
4
5
6#include <linux/module.h>
7#include <linux/platform_device.h>
8#include <linux/of_device.h>
9#include <linux/of.h>
10#include <linux/dma-mapping.h>
11#include "ahb.h"
12#include "debug.h"
13#include "hif.h"
14#include <linux/remoteproc.h>
15
16static const struct of_device_id ath11k_ahb_of_match[] = {
17
18
19
20 { .compatible = "qcom,ipq8074-wifi",
21 .data = (void *)ATH11K_HW_IPQ8074,
22 },
23 { .compatible = "qcom,ipq6018-wifi",
24 .data = (void *)ATH11K_HW_IPQ6018_HW10,
25 },
26 { }
27};
28
29MODULE_DEVICE_TABLE(of, ath11k_ahb_of_match);
30
31static const struct ath11k_bus_params ath11k_ahb_bus_params = {
32 .mhi_support = false,
33 .m3_fw_support = false,
34 .fixed_bdf_addr = true,
35 .fixed_mem_region = true,
36};
37
38#define ATH11K_IRQ_CE0_OFFSET 4
39
40static const char *irq_name[ATH11K_IRQ_NUM_MAX] = {
41 "misc-pulse1",
42 "misc-latch",
43 "sw-exception",
44 "watchdog",
45 "ce0",
46 "ce1",
47 "ce2",
48 "ce3",
49 "ce4",
50 "ce5",
51 "ce6",
52 "ce7",
53 "ce8",
54 "ce9",
55 "ce10",
56 "ce11",
57 "host2wbm-desc-feed",
58 "host2reo-re-injection",
59 "host2reo-command",
60 "host2rxdma-monitor-ring3",
61 "host2rxdma-monitor-ring2",
62 "host2rxdma-monitor-ring1",
63 "reo2ost-exception",
64 "wbm2host-rx-release",
65 "reo2host-status",
66 "reo2host-destination-ring4",
67 "reo2host-destination-ring3",
68 "reo2host-destination-ring2",
69 "reo2host-destination-ring1",
70 "rxdma2host-monitor-destination-mac3",
71 "rxdma2host-monitor-destination-mac2",
72 "rxdma2host-monitor-destination-mac1",
73 "ppdu-end-interrupts-mac3",
74 "ppdu-end-interrupts-mac2",
75 "ppdu-end-interrupts-mac1",
76 "rxdma2host-monitor-status-ring-mac3",
77 "rxdma2host-monitor-status-ring-mac2",
78 "rxdma2host-monitor-status-ring-mac1",
79 "host2rxdma-host-buf-ring-mac3",
80 "host2rxdma-host-buf-ring-mac2",
81 "host2rxdma-host-buf-ring-mac1",
82 "rxdma2host-destination-ring-mac3",
83 "rxdma2host-destination-ring-mac2",
84 "rxdma2host-destination-ring-mac1",
85 "host2tcl-input-ring4",
86 "host2tcl-input-ring3",
87 "host2tcl-input-ring2",
88 "host2tcl-input-ring1",
89 "wbm2host-tx-completions-ring3",
90 "wbm2host-tx-completions-ring2",
91 "wbm2host-tx-completions-ring1",
92 "tcl2host-status-ring",
93};
94
95
96
97
98enum ext_irq_num {
99 host2wbm_desc_feed = 16,
100 host2reo_re_injection,
101 host2reo_command,
102 host2rxdma_monitor_ring3,
103 host2rxdma_monitor_ring2,
104 host2rxdma_monitor_ring1,
105 reo2host_exception,
106 wbm2host_rx_release,
107 reo2host_status,
108 reo2host_destination_ring4,
109 reo2host_destination_ring3,
110 reo2host_destination_ring2,
111 reo2host_destination_ring1,
112 rxdma2host_monitor_destination_mac3,
113 rxdma2host_monitor_destination_mac2,
114 rxdma2host_monitor_destination_mac1,
115 ppdu_end_interrupts_mac3,
116 ppdu_end_interrupts_mac2,
117 ppdu_end_interrupts_mac1,
118 rxdma2host_monitor_status_ring_mac3,
119 rxdma2host_monitor_status_ring_mac2,
120 rxdma2host_monitor_status_ring_mac1,
121 host2rxdma_host_buf_ring_mac3,
122 host2rxdma_host_buf_ring_mac2,
123 host2rxdma_host_buf_ring_mac1,
124 rxdma2host_destination_ring_mac3,
125 rxdma2host_destination_ring_mac2,
126 rxdma2host_destination_ring_mac1,
127 host2tcl_input_ring4,
128 host2tcl_input_ring3,
129 host2tcl_input_ring2,
130 host2tcl_input_ring1,
131 wbm2host_tx_completions_ring3,
132 wbm2host_tx_completions_ring2,
133 wbm2host_tx_completions_ring1,
134 tcl2host_status_ring,
135};
136
137static inline u32 ath11k_ahb_read32(struct ath11k_base *ab, u32 offset)
138{
139 return ioread32(ab->mem + offset);
140}
141
142static inline void ath11k_ahb_write32(struct ath11k_base *ab, u32 offset, u32 value)
143{
144 iowrite32(value, ab->mem + offset);
145}
146
147static void ath11k_ahb_kill_tasklets(struct ath11k_base *ab)
148{
149 int i;
150
151 for (i = 0; i < ab->hw_params.ce_count; i++) {
152 struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i];
153
154 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
155 continue;
156
157 tasklet_kill(&ce_pipe->intr_tq);
158 }
159}
160
161static void ath11k_ahb_ext_grp_disable(struct ath11k_ext_irq_grp *irq_grp)
162{
163 int i;
164
165 for (i = 0; i < irq_grp->num_irq; i++)
166 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
167}
168
169static void __ath11k_ahb_ext_irq_disable(struct ath11k_base *ab)
170{
171 int i;
172
173 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
174 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
175
176 ath11k_ahb_ext_grp_disable(irq_grp);
177
178 napi_synchronize(&irq_grp->napi);
179 napi_disable(&irq_grp->napi);
180 }
181}
182
183static void ath11k_ahb_ext_grp_enable(struct ath11k_ext_irq_grp *irq_grp)
184{
185 int i;
186
187 for (i = 0; i < irq_grp->num_irq; i++)
188 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
189}
190
191static void ath11k_ahb_setbit32(struct ath11k_base *ab, u8 bit, u32 offset)
192{
193 u32 val;
194
195 val = ath11k_ahb_read32(ab, offset);
196 ath11k_ahb_write32(ab, offset, val | BIT(bit));
197}
198
199static void ath11k_ahb_clearbit32(struct ath11k_base *ab, u8 bit, u32 offset)
200{
201 u32 val;
202
203 val = ath11k_ahb_read32(ab, offset);
204 ath11k_ahb_write32(ab, offset, val & ~BIT(bit));
205}
206
207static void ath11k_ahb_ce_irq_enable(struct ath11k_base *ab, u16 ce_id)
208{
209 const struct ce_pipe_config *ce_config;
210
211 ce_config = &ab->hw_params.target_ce_config[ce_id];
212 if (__le32_to_cpu(ce_config->pipedir) & PIPEDIR_OUT)
213 ath11k_ahb_setbit32(ab, ce_id, CE_HOST_IE_ADDRESS);
214
215 if (__le32_to_cpu(ce_config->pipedir) & PIPEDIR_IN) {
216 ath11k_ahb_setbit32(ab, ce_id, CE_HOST_IE_2_ADDRESS);
217 ath11k_ahb_setbit32(ab, ce_id + CE_HOST_IE_3_SHIFT,
218 CE_HOST_IE_3_ADDRESS);
219 }
220}
221
222static void ath11k_ahb_ce_irq_disable(struct ath11k_base *ab, u16 ce_id)
223{
224 const struct ce_pipe_config *ce_config;
225
226 ce_config = &ab->hw_params.target_ce_config[ce_id];
227 if (__le32_to_cpu(ce_config->pipedir) & PIPEDIR_OUT)
228 ath11k_ahb_clearbit32(ab, ce_id, CE_HOST_IE_ADDRESS);
229
230 if (__le32_to_cpu(ce_config->pipedir) & PIPEDIR_IN) {
231 ath11k_ahb_clearbit32(ab, ce_id, CE_HOST_IE_2_ADDRESS);
232 ath11k_ahb_clearbit32(ab, ce_id + CE_HOST_IE_3_SHIFT,
233 CE_HOST_IE_3_ADDRESS);
234 }
235}
236
237static void ath11k_ahb_sync_ce_irqs(struct ath11k_base *ab)
238{
239 int i;
240 int irq_idx;
241
242 for (i = 0; i < ab->hw_params.ce_count; i++) {
243 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
244 continue;
245
246 irq_idx = ATH11K_IRQ_CE0_OFFSET + i;
247 synchronize_irq(ab->irq_num[irq_idx]);
248 }
249}
250
251static void ath11k_ahb_sync_ext_irqs(struct ath11k_base *ab)
252{
253 int i, j;
254 int irq_idx;
255
256 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
257 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
258
259 for (j = 0; j < irq_grp->num_irq; j++) {
260 irq_idx = irq_grp->irqs[j];
261 synchronize_irq(ab->irq_num[irq_idx]);
262 }
263 }
264}
265
266static void ath11k_ahb_ce_irqs_enable(struct ath11k_base *ab)
267{
268 int i;
269
270 for (i = 0; i < ab->hw_params.ce_count; i++) {
271 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
272 continue;
273 ath11k_ahb_ce_irq_enable(ab, i);
274 }
275}
276
277static void ath11k_ahb_ce_irqs_disable(struct ath11k_base *ab)
278{
279 int i;
280
281 for (i = 0; i < ab->hw_params.ce_count; i++) {
282 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
283 continue;
284 ath11k_ahb_ce_irq_disable(ab, i);
285 }
286}
287
288static int ath11k_ahb_start(struct ath11k_base *ab)
289{
290 ath11k_ahb_ce_irqs_enable(ab);
291 ath11k_ce_rx_post_buf(ab);
292
293 return 0;
294}
295
296static void ath11k_ahb_ext_irq_enable(struct ath11k_base *ab)
297{
298 int i;
299
300 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
301 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
302
303 napi_enable(&irq_grp->napi);
304 ath11k_ahb_ext_grp_enable(irq_grp);
305 }
306}
307
308static void ath11k_ahb_ext_irq_disable(struct ath11k_base *ab)
309{
310 __ath11k_ahb_ext_irq_disable(ab);
311 ath11k_ahb_sync_ext_irqs(ab);
312}
313
314static void ath11k_ahb_stop(struct ath11k_base *ab)
315{
316 if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags))
317 ath11k_ahb_ce_irqs_disable(ab);
318 ath11k_ahb_sync_ce_irqs(ab);
319 ath11k_ahb_kill_tasklets(ab);
320 del_timer_sync(&ab->rx_replenish_retry);
321 ath11k_ce_cleanup_pipes(ab);
322}
323
324static int ath11k_ahb_power_up(struct ath11k_base *ab)
325{
326 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
327 int ret;
328
329 ret = rproc_boot(ab_ahb->tgt_rproc);
330 if (ret)
331 ath11k_err(ab, "failed to boot the remote processor Q6\n");
332
333 return ret;
334}
335
336static void ath11k_ahb_power_down(struct ath11k_base *ab)
337{
338 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
339
340 rproc_shutdown(ab_ahb->tgt_rproc);
341}
342
343static void ath11k_ahb_init_qmi_ce_config(struct ath11k_base *ab)
344{
345 struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg;
346
347 cfg->tgt_ce_len = ab->hw_params.target_ce_count;
348 cfg->tgt_ce = ab->hw_params.target_ce_config;
349 cfg->svc_to_ce_map_len = ab->hw_params.svc_to_ce_map_len;
350 cfg->svc_to_ce_map = ab->hw_params.svc_to_ce_map;
351 ab->qmi.service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074;
352}
353
354static void ath11k_ahb_free_ext_irq(struct ath11k_base *ab)
355{
356 int i, j;
357
358 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
359 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
360
361 for (j = 0; j < irq_grp->num_irq; j++)
362 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp);
363 }
364}
365
366static void ath11k_ahb_free_irq(struct ath11k_base *ab)
367{
368 int irq_idx;
369 int i;
370
371 for (i = 0; i < ab->hw_params.ce_count; i++) {
372 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
373 continue;
374 irq_idx = ATH11K_IRQ_CE0_OFFSET + i;
375 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]);
376 }
377
378 ath11k_ahb_free_ext_irq(ab);
379}
380
381static void ath11k_ahb_ce_tasklet(struct tasklet_struct *t)
382{
383 struct ath11k_ce_pipe *ce_pipe = from_tasklet(ce_pipe, t, intr_tq);
384
385 ath11k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num);
386
387 ath11k_ahb_ce_irq_enable(ce_pipe->ab, ce_pipe->pipe_num);
388}
389
390static irqreturn_t ath11k_ahb_ce_interrupt_handler(int irq, void *arg)
391{
392 struct ath11k_ce_pipe *ce_pipe = arg;
393
394
395 ce_pipe->timestamp = jiffies;
396
397 ath11k_ahb_ce_irq_disable(ce_pipe->ab, ce_pipe->pipe_num);
398
399 tasklet_schedule(&ce_pipe->intr_tq);
400
401 return IRQ_HANDLED;
402}
403
404static int ath11k_ahb_ext_grp_napi_poll(struct napi_struct *napi, int budget)
405{
406 struct ath11k_ext_irq_grp *irq_grp = container_of(napi,
407 struct ath11k_ext_irq_grp,
408 napi);
409 struct ath11k_base *ab = irq_grp->ab;
410 int work_done;
411
412 work_done = ath11k_dp_service_srng(ab, irq_grp, budget);
413 if (work_done < budget) {
414 napi_complete_done(napi, work_done);
415 ath11k_ahb_ext_grp_enable(irq_grp);
416 }
417
418 if (work_done > budget)
419 work_done = budget;
420
421 return work_done;
422}
423
424static irqreturn_t ath11k_ahb_ext_interrupt_handler(int irq, void *arg)
425{
426 struct ath11k_ext_irq_grp *irq_grp = arg;
427
428
429 irq_grp->timestamp = jiffies;
430
431 ath11k_ahb_ext_grp_disable(irq_grp);
432
433 napi_schedule(&irq_grp->napi);
434
435 return IRQ_HANDLED;
436}
437
438static int ath11k_ahb_ext_irq_config(struct ath11k_base *ab)
439{
440 struct ath11k_hw_params *hw = &ab->hw_params;
441 int i, j;
442 int irq;
443 int ret;
444
445 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
446 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
447 u32 num_irq = 0;
448
449 irq_grp->ab = ab;
450 irq_grp->grp_id = i;
451 init_dummy_netdev(&irq_grp->napi_ndev);
452 netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi,
453 ath11k_ahb_ext_grp_napi_poll, NAPI_POLL_WEIGHT);
454
455 for (j = 0; j < ATH11K_EXT_IRQ_NUM_MAX; j++) {
456 if (ab->hw_params.ring_mask->tx[i] & BIT(j)) {
457 irq_grp->irqs[num_irq++] =
458 wbm2host_tx_completions_ring1 - j;
459 }
460
461 if (ab->hw_params.ring_mask->rx[i] & BIT(j)) {
462 irq_grp->irqs[num_irq++] =
463 reo2host_destination_ring1 - j;
464 }
465
466 if (ab->hw_params.ring_mask->rx_err[i] & BIT(j))
467 irq_grp->irqs[num_irq++] = reo2host_exception;
468
469 if (ab->hw_params.ring_mask->rx_wbm_rel[i] & BIT(j))
470 irq_grp->irqs[num_irq++] = wbm2host_rx_release;
471
472 if (ab->hw_params.ring_mask->reo_status[i] & BIT(j))
473 irq_grp->irqs[num_irq++] = reo2host_status;
474
475 if (j < ab->hw_params.max_radios) {
476 if (ab->hw_params.ring_mask->rxdma2host[i] & BIT(j)) {
477 irq_grp->irqs[num_irq++] =
478 rxdma2host_destination_ring_mac1 -
479 ath11k_hw_get_mac_from_pdev_id(hw, j);
480 }
481
482 if (ab->hw_params.ring_mask->host2rxdma[i] & BIT(j)) {
483 irq_grp->irqs[num_irq++] =
484 host2rxdma_host_buf_ring_mac1 -
485 ath11k_hw_get_mac_from_pdev_id(hw, j);
486 }
487
488 if (ab->hw_params.ring_mask->rx_mon_status[i] & BIT(j)) {
489 irq_grp->irqs[num_irq++] =
490 ppdu_end_interrupts_mac1 -
491 ath11k_hw_get_mac_from_pdev_id(hw, j);
492 irq_grp->irqs[num_irq++] =
493 rxdma2host_monitor_status_ring_mac1 -
494 ath11k_hw_get_mac_from_pdev_id(hw, j);
495 }
496 }
497 }
498 irq_grp->num_irq = num_irq;
499
500 for (j = 0; j < irq_grp->num_irq; j++) {
501 int irq_idx = irq_grp->irqs[j];
502
503 irq = platform_get_irq_byname(ab->pdev,
504 irq_name[irq_idx]);
505 ab->irq_num[irq_idx] = irq;
506 irq_set_status_flags(irq, IRQ_NOAUTOEN | IRQ_DISABLE_UNLAZY);
507 ret = request_irq(irq, ath11k_ahb_ext_interrupt_handler,
508 IRQF_TRIGGER_RISING,
509 irq_name[irq_idx], irq_grp);
510 if (ret) {
511 ath11k_err(ab, "failed request_irq for %d\n",
512 irq);
513 }
514 }
515 }
516
517 return 0;
518}
519
520static int ath11k_ahb_config_irq(struct ath11k_base *ab)
521{
522 int irq, irq_idx, i;
523 int ret;
524
525
526 for (i = 0; i < ab->hw_params.ce_count; i++) {
527 struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i];
528
529 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
530 continue;
531
532 irq_idx = ATH11K_IRQ_CE0_OFFSET + i;
533
534 tasklet_setup(&ce_pipe->intr_tq, ath11k_ahb_ce_tasklet);
535 irq = platform_get_irq_byname(ab->pdev, irq_name[irq_idx]);
536 ret = request_irq(irq, ath11k_ahb_ce_interrupt_handler,
537 IRQF_TRIGGER_RISING, irq_name[irq_idx],
538 ce_pipe);
539 if (ret)
540 return ret;
541
542 ab->irq_num[irq_idx] = irq;
543 }
544
545
546 ret = ath11k_ahb_ext_irq_config(ab);
547
548 return ret;
549}
550
551static int ath11k_ahb_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
552 u8 *ul_pipe, u8 *dl_pipe)
553{
554 const struct service_to_pipe *entry;
555 bool ul_set = false, dl_set = false;
556 int i;
557
558 for (i = 0; i < ab->hw_params.svc_to_ce_map_len; i++) {
559 entry = &ab->hw_params.svc_to_ce_map[i];
560
561 if (__le32_to_cpu(entry->service_id) != service_id)
562 continue;
563
564 switch (__le32_to_cpu(entry->pipedir)) {
565 case PIPEDIR_NONE:
566 break;
567 case PIPEDIR_IN:
568 WARN_ON(dl_set);
569 *dl_pipe = __le32_to_cpu(entry->pipenum);
570 dl_set = true;
571 break;
572 case PIPEDIR_OUT:
573 WARN_ON(ul_set);
574 *ul_pipe = __le32_to_cpu(entry->pipenum);
575 ul_set = true;
576 break;
577 case PIPEDIR_INOUT:
578 WARN_ON(dl_set);
579 WARN_ON(ul_set);
580 *dl_pipe = __le32_to_cpu(entry->pipenum);
581 *ul_pipe = __le32_to_cpu(entry->pipenum);
582 dl_set = true;
583 ul_set = true;
584 break;
585 }
586 }
587
588 if (WARN_ON(!ul_set || !dl_set))
589 return -ENOENT;
590
591 return 0;
592}
593
594static const struct ath11k_hif_ops ath11k_ahb_hif_ops = {
595 .start = ath11k_ahb_start,
596 .stop = ath11k_ahb_stop,
597 .read32 = ath11k_ahb_read32,
598 .write32 = ath11k_ahb_write32,
599 .irq_enable = ath11k_ahb_ext_irq_enable,
600 .irq_disable = ath11k_ahb_ext_irq_disable,
601 .map_service_to_pipe = ath11k_ahb_map_service_to_pipe,
602 .power_down = ath11k_ahb_power_down,
603 .power_up = ath11k_ahb_power_up,
604};
605
606static int ath11k_core_get_rproc(struct ath11k_base *ab)
607{
608 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
609 struct device *dev = ab->dev;
610 struct rproc *prproc;
611 phandle rproc_phandle;
612
613 if (of_property_read_u32(dev->of_node, "qcom,rproc", &rproc_phandle)) {
614 ath11k_err(ab, "failed to get q6_rproc handle\n");
615 return -ENOENT;
616 }
617
618 prproc = rproc_get_by_phandle(rproc_phandle);
619 if (!prproc) {
620 ath11k_err(ab, "failed to get rproc\n");
621 return -EINVAL;
622 }
623 ab_ahb->tgt_rproc = prproc;
624
625 return 0;
626}
627
628static int ath11k_ahb_probe(struct platform_device *pdev)
629{
630 struct ath11k_base *ab;
631 const struct of_device_id *of_id;
632 struct resource *mem_res;
633 void __iomem *mem;
634 int ret;
635
636 of_id = of_match_device(ath11k_ahb_of_match, &pdev->dev);
637 if (!of_id) {
638 dev_err(&pdev->dev, "failed to find matching device tree id\n");
639 return -EINVAL;
640 }
641
642 mem = devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res);
643 if (IS_ERR(mem)) {
644 dev_err(&pdev->dev, "ioremap error\n");
645 return PTR_ERR(mem);
646 }
647
648 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
649 if (ret) {
650 dev_err(&pdev->dev, "failed to set 32-bit consistent dma\n");
651 return ret;
652 }
653
654 ab = ath11k_core_alloc(&pdev->dev, sizeof(struct ath11k_ahb),
655 ATH11K_BUS_AHB,
656 &ath11k_ahb_bus_params);
657 if (!ab) {
658 dev_err(&pdev->dev, "failed to allocate ath11k base\n");
659 return -ENOMEM;
660 }
661
662 ab->hif.ops = &ath11k_ahb_hif_ops;
663 ab->pdev = pdev;
664 ab->hw_rev = (enum ath11k_hw_rev)of_id->data;
665 ab->mem = mem;
666 ab->mem_len = resource_size(mem_res);
667 platform_set_drvdata(pdev, ab);
668
669 ret = ath11k_core_pre_init(ab);
670 if (ret)
671 goto err_core_free;
672
673 ret = ath11k_hal_srng_init(ab);
674 if (ret)
675 goto err_core_free;
676
677 ret = ath11k_ce_alloc_pipes(ab);
678 if (ret) {
679 ath11k_err(ab, "failed to allocate ce pipes: %d\n", ret);
680 goto err_hal_srng_deinit;
681 }
682
683 ath11k_ahb_init_qmi_ce_config(ab);
684
685 ret = ath11k_core_get_rproc(ab);
686 if (ret) {
687 ath11k_err(ab, "failed to get rproc: %d\n", ret);
688 goto err_ce_free;
689 }
690
691 ret = ath11k_core_init(ab);
692 if (ret) {
693 ath11k_err(ab, "failed to init core: %d\n", ret);
694 goto err_ce_free;
695 }
696
697 ret = ath11k_ahb_config_irq(ab);
698 if (ret) {
699 ath11k_err(ab, "failed to configure irq: %d\n", ret);
700 goto err_ce_free;
701 }
702
703 return 0;
704
705err_ce_free:
706 ath11k_ce_free_pipes(ab);
707
708err_hal_srng_deinit:
709 ath11k_hal_srng_deinit(ab);
710
711err_core_free:
712 ath11k_core_free(ab);
713 platform_set_drvdata(pdev, NULL);
714
715 return ret;
716}
717
718static int ath11k_ahb_remove(struct platform_device *pdev)
719{
720 struct ath11k_base *ab = platform_get_drvdata(pdev);
721 unsigned long left;
722
723 reinit_completion(&ab->driver_recovery);
724
725 if (test_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags)) {
726 left = wait_for_completion_timeout(&ab->driver_recovery,
727 ATH11K_AHB_RECOVERY_TIMEOUT);
728 if (!left)
729 ath11k_warn(ab, "failed to receive recovery response completion\n");
730 }
731
732 set_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags);
733 cancel_work_sync(&ab->restart_work);
734
735 ath11k_core_deinit(ab);
736 ath11k_ahb_free_irq(ab);
737
738 ath11k_hal_srng_deinit(ab);
739 ath11k_ce_free_pipes(ab);
740 ath11k_core_free(ab);
741 platform_set_drvdata(pdev, NULL);
742
743 return 0;
744}
745
746static struct platform_driver ath11k_ahb_driver = {
747 .driver = {
748 .name = "ath11k",
749 .of_match_table = ath11k_ahb_of_match,
750 },
751 .probe = ath11k_ahb_probe,
752 .remove = ath11k_ahb_remove,
753};
754
755static int ath11k_ahb_init(void)
756{
757 return platform_driver_register(&ath11k_ahb_driver);
758}
759module_init(ath11k_ahb_init);
760
761static void ath11k_ahb_exit(void)
762{
763 platform_driver_unregister(&ath11k_ahb_driver);
764}
765module_exit(ath11k_ahb_exit);
766
767MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11ax WLAN AHB devices");
768MODULE_LICENSE("Dual BSD/GPL");
769
