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5#ifndef __RTW8821C_H__
6#define __RTW8821C_H__
7
8#include <asm/byteorder.h>
9
10#define RCR_VHT_ACK BIT(26)
11
12struct rtw8821ce_efuse {
13 u8 mac_addr[ETH_ALEN];
14 u8 vender_id[2];
15 u8 device_id[2];
16 u8 sub_vender_id[2];
17 u8 sub_device_id[2];
18 u8 pmc[2];
19 u8 exp_device_cap[2];
20 u8 msi_cap;
21 u8 ltr_cap;
22 u8 exp_link_control[2];
23 u8 link_cap[4];
24 u8 link_control[2];
25 u8 serial_number[8];
26 u8 res0:2;
27 u8 ltr_en:1;
28 u8 res1:2;
29 u8 obff:2;
30 u8 res2:3;
31 u8 obff_cap:2;
32 u8 res3:4;
33 u8 res4[3];
34 u8 class_code[3];
35 u8 pci_pm_L1_2_supp:1;
36 u8 pci_pm_L1_1_supp:1;
37 u8 aspm_pm_L1_2_supp:1;
38 u8 aspm_pm_L1_1_supp:1;
39 u8 L1_pm_substates_supp:1;
40 u8 res5:3;
41 u8 port_common_mode_restore_time;
42 u8 port_t_power_on_scale:2;
43 u8 res6:1;
44 u8 port_t_power_on_value:5;
45 u8 res7;
46};
47
48struct rtw8821c_efuse {
49 __le16 rtl_id;
50 u8 res0[0x0e];
51
52
53 struct rtw_txpwr_idx txpwr_idx_table[4];
54
55 u8 channel_plan;
56 u8 xtal_k;
57 u8 thermal_meter;
58 u8 iqk_lck;
59 u8 pa_type;
60 u8 lna_type_2g[2];
61 u8 lna_type_5g[2];
62 u8 rf_board_option;
63 u8 rf_feature_option;
64 u8 rf_bt_setting;
65 u8 eeprom_version;
66 u8 eeprom_customer_id;
67 u8 tx_bb_swing_setting_2g;
68 u8 tx_bb_swing_setting_5g;
69 u8 tx_pwr_calibrate_rate;
70 u8 rf_antenna_option;
71 u8 rfe_option;
72 u8 country_code[2];
73 u8 res[3];
74 union {
75 struct rtw8821ce_efuse e;
76 };
77};
78
79static inline void
80_rtw_write32s_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data)
81{
82
83 rtw_write32_mask(rtwdev, addr, mask, data);
84 rtw_write32_mask(rtwdev, addr + 0x200, mask, data);
85}
86
87#define rtw_write32s_mask(rtwdev, addr, mask, data) \
88 do { \
89 BUILD_BUG_ON((addr) < 0xC00 || (addr) >= 0xD00); \
90 \
91 _rtw_write32s_mask(rtwdev, addr, mask, data); \
92 } while (0)
93
94#define BIT_FEN_PCIEA BIT(6)
95#define WLAN_SLOT_TIME 0x09
96#define WLAN_PIFS_TIME 0x19
97#define WLAN_SIFS_CCK_CONT_TX 0xA
98#define WLAN_SIFS_OFDM_CONT_TX 0xE
99#define WLAN_SIFS_CCK_TRX 0x10
100#define WLAN_SIFS_OFDM_TRX 0x10
101#define WLAN_VO_TXOP_LIMIT 0x186
102#define WLAN_VI_TXOP_LIMIT 0x3BC
103#define WLAN_RDG_NAV 0x05
104#define WLAN_TXOP_NAV 0x1B
105#define WLAN_CCK_RX_TSF 0x30
106#define WLAN_OFDM_RX_TSF 0x30
107#define WLAN_TBTT_PROHIBIT 0x04
108#define WLAN_TBTT_HOLD_TIME 0x064
109#define WLAN_DRV_EARLY_INT 0x04
110#define WLAN_BCN_DMA_TIME 0x02
111
112#define WLAN_RX_FILTER0 0x0FFFFFFF
113#define WLAN_RX_FILTER2 0xFFFF
114#define WLAN_RCR_CFG 0xE400220E
115#define WLAN_RXPKT_MAX_SZ 12288
116#define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9)
117
118#define WLAN_AMPDU_MAX_TIME 0x70
119#define WLAN_RTS_LEN_TH 0xFF
120#define WLAN_RTS_TX_TIME_TH 0x08
121#define WLAN_MAX_AGG_PKT_LIMIT 0x20
122#define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20
123#define FAST_EDCA_VO_TH 0x06
124#define FAST_EDCA_VI_TH 0x06
125#define FAST_EDCA_BE_TH 0x06
126#define FAST_EDCA_BK_TH 0x06
127#define WLAN_BAR_RETRY_LIMIT 0x01
128#define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
129
130#define WLAN_TX_FUNC_CFG1 0x30
131#define WLAN_TX_FUNC_CFG2 0x30
132#define WLAN_MAC_OPT_NORM_FUNC1 0x98
133#define WLAN_MAC_OPT_LB_FUNC1 0x80
134#define WLAN_MAC_OPT_FUNC2 0x30810041
135
136#define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \
137 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \
138 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \
139 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX))
140
141#define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\
142 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP))
143
144#define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16))
145#define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8)
146#define WLAN_PRE_TXCNT_TIME_TH 0x1E4
147
148
149#define GET_PHY_STAT_P0_PWDB(phy_stat) \
150 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
151
152
153#define GET_PHY_STAT_P1_PWDB_A(phy_stat) \
154 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
155#define GET_PHY_STAT_P1_PWDB_B(phy_stat) \
156 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
157#define GET_PHY_STAT_P1_RF_MODE(phy_stat) \
158 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
159#define GET_PHY_STAT_P1_L_RXSC(phy_stat) \
160 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
161#define GET_PHY_STAT_P1_HT_RXSC(phy_stat) \
162 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
163#define GET_PHY_STAT_P1_RXEVM_A(phy_stat) \
164 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
165#define GET_PHY_STAT_P1_RXEVM_B(phy_stat) \
166 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8))
167#define GET_PHY_STAT_P1_CFO_TAIL_A(phy_stat) \
168 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
169#define GET_PHY_STAT_P1_CFO_TAIL_B(phy_stat) \
170 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8))
171#define GET_PHY_STAT_P1_RXSNR_A(phy_stat) \
172 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
173#define GET_PHY_STAT_P1_RXSNR_B(phy_stat) \
174 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8))
175
176#define REG_INIRTS_RATE_SEL 0x0480
177#define REG_HTSTFWT 0x800
178#define REG_RXPSEL 0x808
179#define BIT_RX_PSEL_RST (BIT(28) | BIT(29))
180#define REG_TXPSEL 0x80c
181#define REG_RXCCAMSK 0x814
182#define REG_CCASEL 0x82c
183#define REG_PDMFTH 0x830
184#define REG_CCA2ND 0x838
185#define REG_L1WT 0x83c
186#define REG_L1PKWT 0x840
187#define REG_MRC 0x850
188#define REG_CLKTRK 0x860
189#define REG_ADCCLK 0x8ac
190#define REG_ADC160 0x8c4
191#define REG_ADC40 0x8c8
192#define REG_CHFIR 0x8f0
193#define REG_CDDTXP 0x93c
194#define REG_TXPSEL1 0x940
195#define REG_ACBB0 0x948
196#define REG_ACBBRXFIR 0x94c
197#define REG_ACGG2TBL 0x958
198#define REG_FAS 0x9a4
199#define REG_RXSB 0xa00
200#define REG_ADCINI 0xa04
201#define REG_PWRTH 0xa08
202#define REG_TXSF2 0xa24
203#define REG_TXSF6 0xa28
204#define REG_FA_CCK 0xa5c
205#define REG_RXDESC 0xa2c
206#define REG_ENTXCCK 0xa80
207#define REG_PWRTH2 0xaa8
208#define REG_CSRATIO 0xaaa
209#define REG_TXFILTER 0xaac
210#define REG_CNTRST 0xb58
211#define REG_AGCTR_A 0xc08
212#define REG_TXSCALE_A 0xc1c
213#define REG_TXDFIR 0xc20
214#define REG_RXIGI_A 0xc50
215#define REG_TXAGCIDX 0xc94
216#define REG_TRSW 0xca0
217#define REG_RFESEL0 0xcb0
218#define REG_RFESEL8 0xcb4
219#define REG_RFECTL 0xcb8
220#define REG_RFEINV 0xcbc
221#define REG_AGCTR_B 0xe08
222#define REG_RXIGI_B 0xe50
223#define REG_CRC_CCK 0xf04
224#define REG_CRC_OFDM 0xf14
225#define REG_CRC_HT 0xf10
226#define REG_CRC_VHT 0xf0c
227#define REG_CCA_OFDM 0xf08
228#define REG_FA_OFDM 0xf48
229#define REG_CCA_CCK 0xfcc
230#define REG_ANTWT 0x1904
231#define REG_IQKFAILMSK 0x1bf0
232#define BIT_MASK_R_RFE_SEL_15 GENMASK(31, 28)
233#define BIT_SDIO_INT BIT(18)
234#define SAMPLE_RATE_MASK GENMASK(5, 0)
235#define SAMPLE_RATE 0x5
236#define BT_CNT_ENABLE 0x1
237#define BIT_BCN_QUEUE BIT(3)
238#define BCN_PRI_EN 0x1
239#define PTA_CTRL_PIN 0x66
240#define DPDT_CTRL_PIN 0x77
241#define ANTDIC_CTRL_PIN 0x88
242#define REG_CTRL_TYPE 0x67
243#define BIT_CTRL_TYPE1 BIT(5)
244#define BIT_CTRL_TYPE2 BIT(4)
245#define CTRL_TYPE_MASK GENMASK(15, 8)
246
247#define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8))
248#define RF18_BAND_2G (0)
249#define RF18_BAND_5G (BIT(16) | BIT(8))
250#define RF18_CHANNEL_MASK (MASKBYTE0)
251#define RF18_RFSI_MASK (BIT(18) | BIT(17))
252#define RF18_RFSI_GE (BIT(17))
253#define RF18_RFSI_GT (BIT(18))
254#define RF18_BW_MASK (BIT(11) | BIT(10))
255#define RF18_BW_20M (BIT(11) | BIT(10))
256#define RF18_BW_40M (BIT(11))
257#define RF18_BW_80M (BIT(10))
258
259#endif
260
