LXR linux/drivers/pinctrl/tegra/pinctrl-tegra20.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Pinctrl data for the NVIDIA Tegra20 pinmux
   4 *
   5 * Author: Stephen Warren <swarren@nvidia.com>
   6 *
   7 * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
   8 *
   9 * Derived from code:
  10 * Copyright (C) 2010 Google, Inc.
  11 * Copyright (C) 2010 NVIDIA Corporation
  12 */
  13
  14#include <linux/clk-provider.h>
  15#include <linux/init.h>
  16#include <linux/of.h>
  17#include <linux/platform_device.h>
  18#include <linux/pinctrl/pinctrl.h>
  19#include <linux/pinctrl/pinmux.h>
  20
  21#include "pinctrl-tegra.h"
  22
  23/*
  24 * Most pins affected by the pinmux can also be GPIOs. Define these first.
  25 * These must match how the GPIO driver names/numbers its pins.
  26 */
  27#define _GPIO(offset)                   (offset)
  28
  29#define TEGRA_PIN_VI_GP6_PA0            _GPIO(0)
  30#define TEGRA_PIN_UART3_CTS_N_PA1       _GPIO(1)
  31#define TEGRA_PIN_DAP2_FS_PA2           _GPIO(2)
  32#define TEGRA_PIN_DAP2_SCLK_PA3         _GPIO(3)
  33#define TEGRA_PIN_DAP2_DIN_PA4          _GPIO(4)
  34#define TEGRA_PIN_DAP2_DOUT_PA5         _GPIO(5)
  35#define TEGRA_PIN_SDIO3_CLK_PA6         _GPIO(6)
  36#define TEGRA_PIN_SDIO3_CMD_PA7         _GPIO(7)
  37#define TEGRA_PIN_GMI_AD17_PB0          _GPIO(8)
  38#define TEGRA_PIN_GMI_AD18_PB1          _GPIO(9)
  39#define TEGRA_PIN_LCD_PWR0_PB2          _GPIO(10)
  40#define TEGRA_PIN_LCD_PCLK_PB3          _GPIO(11)
  41#define TEGRA_PIN_SDIO3_DAT3_PB4        _GPIO(12)
  42#define TEGRA_PIN_SDIO3_DAT2_PB5        _GPIO(13)
  43#define TEGRA_PIN_SDIO3_DAT1_PB6        _GPIO(14)
  44#define TEGRA_PIN_SDIO3_DAT0_PB7        _GPIO(15)
  45#define TEGRA_PIN_UART3_RTS_N_PC0       _GPIO(16)
  46#define TEGRA_PIN_LCD_PWR1_PC1          _GPIO(17)
  47#define TEGRA_PIN_UART2_TXD_PC2         _GPIO(18)
  48#define TEGRA_PIN_UART2_RXD_PC3         _GPIO(19)
  49#define TEGRA_PIN_GEN1_I2C_SCL_PC4      _GPIO(20)
  50#define TEGRA_PIN_GEN1_I2C_SDA_PC5      _GPIO(21)
  51#define TEGRA_PIN_LCD_PWR2_PC6          _GPIO(22)
  52#define TEGRA_PIN_GMI_WP_N_PC7          _GPIO(23)
  53#define TEGRA_PIN_SDIO3_DAT5_PD0        _GPIO(24)
  54#define TEGRA_PIN_SDIO3_DAT4_PD1        _GPIO(25)
  55#define TEGRA_PIN_VI_GP5_PD2            _GPIO(26)
  56#define TEGRA_PIN_SDIO3_DAT6_PD3        _GPIO(27)
  57#define TEGRA_PIN_SDIO3_DAT7_PD4        _GPIO(28)
  58#define TEGRA_PIN_VI_D1_PD5             _GPIO(29)
  59#define TEGRA_PIN_VI_VSYNC_PD6          _GPIO(30)
  60#define TEGRA_PIN_VI_HSYNC_PD7          _GPIO(31)
  61#define TEGRA_PIN_LCD_D0_PE0            _GPIO(32)
  62#define TEGRA_PIN_LCD_D1_PE1            _GPIO(33)
  63#define TEGRA_PIN_LCD_D2_PE2            _GPIO(34)
  64#define TEGRA_PIN_LCD_D3_PE3            _GPIO(35)
  65#define TEGRA_PIN_LCD_D4_PE4            _GPIO(36)
  66#define TEGRA_PIN_LCD_D5_PE5            _GPIO(37)
  67#define TEGRA_PIN_LCD_D6_PE6            _GPIO(38)
  68#define TEGRA_PIN_LCD_D7_PE7            _GPIO(39)
  69#define TEGRA_PIN_LCD_D8_PF0            _GPIO(40)
  70#define TEGRA_PIN_LCD_D9_PF1            _GPIO(41)
  71#define TEGRA_PIN_LCD_D10_PF2           _GPIO(42)
  72#define TEGRA_PIN_LCD_D11_PF3           _GPIO(43)
  73#define TEGRA_PIN_LCD_D12_PF4           _GPIO(44)
  74#define TEGRA_PIN_LCD_D13_PF5           _GPIO(45)
  75#define TEGRA_PIN_LCD_D14_PF6           _GPIO(46)
  76#define TEGRA_PIN_LCD_D15_PF7           _GPIO(47)
  77#define TEGRA_PIN_GMI_AD0_PG0           _GPIO(48)
  78#define TEGRA_PIN_GMI_AD1_PG1           _GPIO(49)
  79#define TEGRA_PIN_GMI_AD2_PG2           _GPIO(50)
  80#define TEGRA_PIN_GMI_AD3_PG3           _GPIO(51)
  81#define TEGRA_PIN_GMI_AD4_PG4           _GPIO(52)
  82#define TEGRA_PIN_GMI_AD5_PG5           _GPIO(53)
  83#define TEGRA_PIN_GMI_AD6_PG6           _GPIO(54)
  84#define TEGRA_PIN_GMI_AD7_PG7           _GPIO(55)
  85#define TEGRA_PIN_GMI_AD8_PH0           _GPIO(56)
  86#define TEGRA_PIN_GMI_AD9_PH1           _GPIO(57)
  87#define TEGRA_PIN_GMI_AD10_PH2          _GPIO(58)
  88#define TEGRA_PIN_GMI_AD11_PH3          _GPIO(59)
  89#define TEGRA_PIN_GMI_AD12_PH4          _GPIO(60)
  90#define TEGRA_PIN_GMI_AD13_PH5          _GPIO(61)
  91#define TEGRA_PIN_GMI_AD14_PH6          _GPIO(62)
  92#define TEGRA_PIN_GMI_AD15_PH7          _GPIO(63)
  93#define TEGRA_PIN_GMI_HIOW_N_PI0        _GPIO(64)
  94#define TEGRA_PIN_GMI_HIOR_N_PI1        _GPIO(65)
  95#define TEGRA_PIN_GMI_CS5_N_PI2         _GPIO(66)
  96#define TEGRA_PIN_GMI_CS6_N_PI3         _GPIO(67)
  97#define TEGRA_PIN_GMI_RST_N_PI4         _GPIO(68)
  98#define TEGRA_PIN_GMI_IORDY_PI5         _GPIO(69)
  99#define TEGRA_PIN_GMI_CS7_N_PI6         _GPIO(70)
 100#define TEGRA_PIN_GMI_WAIT_PI7          _GPIO(71)
 101#define TEGRA_PIN_GMI_CS0_N_PJ0         _GPIO(72)
 102#define TEGRA_PIN_LCD_DE_PJ1            _GPIO(73)
 103#define TEGRA_PIN_GMI_CS1_N_PJ2         _GPIO(74)
 104#define TEGRA_PIN_LCD_HSYNC_PJ3         _GPIO(75)
 105#define TEGRA_PIN_LCD_VSYNC_PJ4         _GPIO(76)
 106#define TEGRA_PIN_UART2_CTS_N_PJ5       _GPIO(77)
 107#define TEGRA_PIN_UART2_RTS_N_PJ6       _GPIO(78)
 108#define TEGRA_PIN_GMI_AD16_PJ7          _GPIO(79)
 109#define TEGRA_PIN_GMI_ADV_N_PK0         _GPIO(80)
 110#define TEGRA_PIN_GMI_CLK_PK1           _GPIO(81)
 111#define TEGRA_PIN_GMI_CS4_N_PK2         _GPIO(82)
 112#define TEGRA_PIN_GMI_CS2_N_PK3         _GPIO(83)
 113#define TEGRA_PIN_GMI_CS3_N_PK4         _GPIO(84)
 114#define TEGRA_PIN_SPDIF_OUT_PK5         _GPIO(85)
 115#define TEGRA_PIN_SPDIF_IN_PK6          _GPIO(86)
 116#define TEGRA_PIN_GMI_AD19_PK7          _GPIO(87)
 117#define TEGRA_PIN_VI_D2_PL0             _GPIO(88)
 118#define TEGRA_PIN_VI_D3_PL1             _GPIO(89)
 119#define TEGRA_PIN_VI_D4_PL2             _GPIO(90)
 120#define TEGRA_PIN_VI_D5_PL3             _GPIO(91)
 121#define TEGRA_PIN_VI_D6_PL4             _GPIO(92)
 122#define TEGRA_PIN_VI_D7_PL5             _GPIO(93)
 123#define TEGRA_PIN_VI_D8_PL6             _GPIO(94)
 124#define TEGRA_PIN_VI_D9_PL7             _GPIO(95)
 125#define TEGRA_PIN_LCD_D16_PM0           _GPIO(96)
 126#define TEGRA_PIN_LCD_D17_PM1           _GPIO(97)
 127#define TEGRA_PIN_LCD_D18_PM2           _GPIO(98)
 128#define TEGRA_PIN_LCD_D19_PM3           _GPIO(99)
 129#define TEGRA_PIN_LCD_D20_PM4           _GPIO(100)
 130#define TEGRA_PIN_LCD_D21_PM5           _GPIO(101)
 131#define TEGRA_PIN_LCD_D22_PM6           _GPIO(102)
 132#define TEGRA_PIN_LCD_D23_PM7           _GPIO(103)
 133#define TEGRA_PIN_DAP1_FS_PN0           _GPIO(104)
 134#define TEGRA_PIN_DAP1_DIN_PN1          _GPIO(105)
 135#define TEGRA_PIN_DAP1_DOUT_PN2         _GPIO(106)
 136#define TEGRA_PIN_DAP1_SCLK_PN3         _GPIO(107)
 137#define TEGRA_PIN_LCD_CS0_N_PN4         _GPIO(108)
 138#define TEGRA_PIN_LCD_SDOUT_PN5         _GPIO(109)
 139#define TEGRA_PIN_LCD_DC0_PN6           _GPIO(110)
 140#define TEGRA_PIN_HDMI_INT_N_PN7        _GPIO(111)
 141#define TEGRA_PIN_ULPI_DATA7_PO0        _GPIO(112)
 142#define TEGRA_PIN_ULPI_DATA0_PO1        _GPIO(113)
 143#define TEGRA_PIN_ULPI_DATA1_PO2        _GPIO(114)
 144#define TEGRA_PIN_ULPI_DATA2_PO3        _GPIO(115)
 145#define TEGRA_PIN_ULPI_DATA3_PO4        _GPIO(116)
 146#define TEGRA_PIN_ULPI_DATA4_PO5        _GPIO(117)
 147#define TEGRA_PIN_ULPI_DATA5_PO6        _GPIO(118)
 148#define TEGRA_PIN_ULPI_DATA6_PO7        _GPIO(119)
 149#define TEGRA_PIN_DAP3_FS_PP0           _GPIO(120)
 150#define TEGRA_PIN_DAP3_DIN_PP1          _GPIO(121)
 151#define TEGRA_PIN_DAP3_DOUT_PP2         _GPIO(122)
 152#define TEGRA_PIN_DAP3_SCLK_PP3         _GPIO(123)
 153#define TEGRA_PIN_DAP4_FS_PP4           _GPIO(124)
 154#define TEGRA_PIN_DAP4_DIN_PP5          _GPIO(125)
 155#define TEGRA_PIN_DAP4_DOUT_PP6         _GPIO(126)
 156#define TEGRA_PIN_DAP4_SCLK_PP7         _GPIO(127)
 157#define TEGRA_PIN_KB_COL0_PQ0           _GPIO(128)
 158#define TEGRA_PIN_KB_COL1_PQ1           _GPIO(129)
 159#define TEGRA_PIN_KB_COL2_PQ2           _GPIO(130)
 160#define TEGRA_PIN_KB_COL3_PQ3           _GPIO(131)
 161#define TEGRA_PIN_KB_COL4_PQ4           _GPIO(132)
 162#define TEGRA_PIN_KB_COL5_PQ5           _GPIO(133)
 163#define TEGRA_PIN_KB_COL6_PQ6           _GPIO(134)
 164#define TEGRA_PIN_KB_COL7_PQ7           _GPIO(135)
 165#define TEGRA_PIN_KB_ROW0_PR0           _GPIO(136)
 166#define TEGRA_PIN_KB_ROW1_PR1           _GPIO(137)
 167#define TEGRA_PIN_KB_ROW2_PR2           _GPIO(138)
 168#define TEGRA_PIN_KB_ROW3_PR3           _GPIO(139)
 169#define TEGRA_PIN_KB_ROW4_PR4           _GPIO(140)
 170#define TEGRA_PIN_KB_ROW5_PR5           _GPIO(141)
 171#define TEGRA_PIN_KB_ROW6_PR6           _GPIO(142)
 172#define TEGRA_PIN_KB_ROW7_PR7           _GPIO(143)
 173#define TEGRA_PIN_KB_ROW8_PS0           _GPIO(144)
 174#define TEGRA_PIN_KB_ROW9_PS1           _GPIO(145)
 175#define TEGRA_PIN_KB_ROW10_PS2          _GPIO(146)
 176#define TEGRA_PIN_KB_ROW11_PS3          _GPIO(147)
 177#define TEGRA_PIN_KB_ROW12_PS4          _GPIO(148)
 178#define TEGRA_PIN_KB_ROW13_PS5          _GPIO(149)
 179#define TEGRA_PIN_KB_ROW14_PS6          _GPIO(150)
 180#define TEGRA_PIN_KB_ROW15_PS7          _GPIO(151)
 181#define TEGRA_PIN_VI_PCLK_PT0           _GPIO(152)
 182#define TEGRA_PIN_VI_MCLK_PT1           _GPIO(153)
 183#define TEGRA_PIN_VI_D10_PT2            _GPIO(154)
 184#define TEGRA_PIN_VI_D11_PT3            _GPIO(155)
 185#define TEGRA_PIN_VI_D0_PT4             _GPIO(156)
 186#define TEGRA_PIN_GEN2_I2C_SCL_PT5      _GPIO(157)
 187#define TEGRA_PIN_GEN2_I2C_SDA_PT6      _GPIO(158)
 188#define TEGRA_PIN_GMI_DPD_PT7           _GPIO(159)
 189#define TEGRA_PIN_PU0                   _GPIO(160)
 190#define TEGRA_PIN_PU1                   _GPIO(161)
 191#define TEGRA_PIN_PU2                   _GPIO(162)
 192#define TEGRA_PIN_PU3                   _GPIO(163)
 193#define TEGRA_PIN_PU4                   _GPIO(164)
 194#define TEGRA_PIN_PU5                   _GPIO(165)
 195#define TEGRA_PIN_PU6                   _GPIO(166)
 196#define TEGRA_PIN_JTAG_RTCK_PU7         _GPIO(167)
 197#define TEGRA_PIN_PV0                   _GPIO(168)
 198#define TEGRA_PIN_PV1                   _GPIO(169)
 199#define TEGRA_PIN_PV2                   _GPIO(170)
 200#define TEGRA_PIN_PV3                   _GPIO(171)
 201#define TEGRA_PIN_PV4                   _GPIO(172)
 202#define TEGRA_PIN_PV5                   _GPIO(173)
 203#define TEGRA_PIN_PV6                   _GPIO(174)
 204#define TEGRA_PIN_LCD_DC1_PV7           _GPIO(175)
 205#define TEGRA_PIN_LCD_CS1_N_PW0         _GPIO(176)
 206#define TEGRA_PIN_LCD_M1_PW1            _GPIO(177)
 207#define TEGRA_PIN_SPI2_CS1_N_PW2        _GPIO(178)
 208#define TEGRA_PIN_SPI2_CS2_N_PW3        _GPIO(179)
 209#define TEGRA_PIN_DAP_MCLK1_PW4         _GPIO(180)
 210#define TEGRA_PIN_DAP_MCLK2_PW5         _GPIO(181)
 211#define TEGRA_PIN_UART3_TXD_PW6         _GPIO(182)
 212#define TEGRA_PIN_UART3_RXD_PW7         _GPIO(183)
 213#define TEGRA_PIN_SPI2_MOSI_PX0         _GPIO(184)
 214#define TEGRA_PIN_SPI2_MISO_PX1         _GPIO(185)
 215#define TEGRA_PIN_SPI2_SCK_PX2          _GPIO(186)
 216#define TEGRA_PIN_SPI2_CS0_N_PX3        _GPIO(187)
 217#define TEGRA_PIN_SPI1_MOSI_PX4         _GPIO(188)
 218#define TEGRA_PIN_SPI1_SCK_PX5          _GPIO(189)
 219#define TEGRA_PIN_SPI1_CS0_N_PX6        _GPIO(190)
 220#define TEGRA_PIN_SPI1_MISO_PX7         _GPIO(191)
 221#define TEGRA_PIN_ULPI_CLK_PY0          _GPIO(192)
 222#define TEGRA_PIN_ULPI_DIR_PY1          _GPIO(193)
 223#define TEGRA_PIN_ULPI_NXT_PY2          _GPIO(194)
 224#define TEGRA_PIN_ULPI_STP_PY3          _GPIO(195)
 225#define TEGRA_PIN_SDIO1_DAT3_PY4        _GPIO(196)
 226#define TEGRA_PIN_SDIO1_DAT2_PY5        _GPIO(197)
 227#define TEGRA_PIN_SDIO1_DAT1_PY6        _GPIO(198)
 228#define TEGRA_PIN_SDIO1_DAT0_PY7        _GPIO(199)
 229#define TEGRA_PIN_SDIO1_CLK_PZ0         _GPIO(200)
 230#define TEGRA_PIN_SDIO1_CMD_PZ1         _GPIO(201)
 231#define TEGRA_PIN_LCD_SDIN_PZ2          _GPIO(202)
 232#define TEGRA_PIN_LCD_WR_N_PZ3          _GPIO(203)
 233#define TEGRA_PIN_LCD_SCK_PZ4           _GPIO(204)
 234#define TEGRA_PIN_SYS_CLK_REQ_PZ5       _GPIO(205)
 235#define TEGRA_PIN_PWR_I2C_SCL_PZ6       _GPIO(206)
 236#define TEGRA_PIN_PWR_I2C_SDA_PZ7       _GPIO(207)
 237#define TEGRA_PIN_GMI_AD20_PAA0         _GPIO(208)
 238#define TEGRA_PIN_GMI_AD21_PAA1         _GPIO(209)
 239#define TEGRA_PIN_GMI_AD22_PAA2         _GPIO(210)
 240#define TEGRA_PIN_GMI_AD23_PAA3         _GPIO(211)
 241#define TEGRA_PIN_GMI_AD24_PAA4         _GPIO(212)
 242#define TEGRA_PIN_GMI_AD25_PAA5         _GPIO(213)
 243#define TEGRA_PIN_GMI_AD26_PAA6         _GPIO(214)
 244#define TEGRA_PIN_GMI_AD27_PAA7         _GPIO(215)
 245#define TEGRA_PIN_LED_BLINK_PBB0        _GPIO(216)
 246#define TEGRA_PIN_VI_GP0_PBB1           _GPIO(217)
 247#define TEGRA_PIN_CAM_I2C_SCL_PBB2      _GPIO(218)
 248#define TEGRA_PIN_CAM_I2C_SDA_PBB3      _GPIO(219)
 249#define TEGRA_PIN_VI_GP3_PBB4           _GPIO(220)
 250#define TEGRA_PIN_VI_GP4_PBB5           _GPIO(221)
 251#define TEGRA_PIN_PBB6                  _GPIO(222)
 252#define TEGRA_PIN_PBB7                  _GPIO(223)
 253
 254/* All non-GPIO pins follow */
 255#define NUM_GPIOS                       (TEGRA_PIN_PBB7 + 1)
 256#define _PIN(offset)                    (NUM_GPIOS + (offset))
 257
 258#define TEGRA_PIN_CRT_HSYNC             _PIN(30)
 259#define TEGRA_PIN_CRT_VSYNC             _PIN(31)
 260#define TEGRA_PIN_DDC_SCL               _PIN(32)
 261#define TEGRA_PIN_DDC_SDA               _PIN(33)
 262#define TEGRA_PIN_OWC                   _PIN(34)
 263#define TEGRA_PIN_CORE_PWR_REQ          _PIN(35)
 264#define TEGRA_PIN_CPU_PWR_REQ           _PIN(36)
 265#define TEGRA_PIN_PWR_INT_N             _PIN(37)
 266#define TEGRA_PIN_CLK_32_K_IN           _PIN(38)
 267#define TEGRA_PIN_DDR_COMP_PD           _PIN(39)
 268#define TEGRA_PIN_DDR_COMP_PU           _PIN(40)
 269#define TEGRA_PIN_DDR_A0                _PIN(41)
 270#define TEGRA_PIN_DDR_A1                _PIN(42)
 271#define TEGRA_PIN_DDR_A2                _PIN(43)
 272#define TEGRA_PIN_DDR_A3                _PIN(44)
 273#define TEGRA_PIN_DDR_A4                _PIN(45)
 274#define TEGRA_PIN_DDR_A5                _PIN(46)
 275#define TEGRA_PIN_DDR_A6                _PIN(47)
 276#define TEGRA_PIN_DDR_A7                _PIN(48)
 277#define TEGRA_PIN_DDR_A8                _PIN(49)
 278#define TEGRA_PIN_DDR_A9                _PIN(50)
 279#define TEGRA_PIN_DDR_A10               _PIN(51)
 280#define TEGRA_PIN_DDR_A11               _PIN(52)
 281#define TEGRA_PIN_DDR_A12               _PIN(53)
 282#define TEGRA_PIN_DDR_A13               _PIN(54)
 283#define TEGRA_PIN_DDR_A14               _PIN(55)
 284#define TEGRA_PIN_DDR_CAS_N             _PIN(56)
 285#define TEGRA_PIN_DDR_BA0               _PIN(57)
 286#define TEGRA_PIN_DDR_BA1               _PIN(58)
 287#define TEGRA_PIN_DDR_BA2               _PIN(59)
 288#define TEGRA_PIN_DDR_DQS0P             _PIN(60)
 289#define TEGRA_PIN_DDR_DQS0N             _PIN(61)
 290#define TEGRA_PIN_DDR_DQS1P             _PIN(62)
 291#define TEGRA_PIN_DDR_DQS1N             _PIN(63)
 292#define TEGRA_PIN_DDR_DQS2P             _PIN(64)
 293#define TEGRA_PIN_DDR_DQS2N             _PIN(65)
 294#define TEGRA_PIN_DDR_DQS3P             _PIN(66)
 295#define TEGRA_PIN_DDR_DQS3N             _PIN(67)
 296#define TEGRA_PIN_DDR_CKE0              _PIN(68)
 297#define TEGRA_PIN_DDR_CKE1              _PIN(69)
 298#define TEGRA_PIN_DDR_CLK               _PIN(70)
 299#define TEGRA_PIN_DDR_CLK_N             _PIN(71)
 300#define TEGRA_PIN_DDR_DM0               _PIN(72)
 301#define TEGRA_PIN_DDR_DM1               _PIN(73)
 302#define TEGRA_PIN_DDR_DM2               _PIN(74)
 303#define TEGRA_PIN_DDR_DM3               _PIN(75)
 304#define TEGRA_PIN_DDR_ODT               _PIN(76)
 305#define TEGRA_PIN_DDR_QUSE0             _PIN(77)
 306#define TEGRA_PIN_DDR_QUSE1             _PIN(78)
 307#define TEGRA_PIN_DDR_QUSE2             _PIN(79)
 308#define TEGRA_PIN_DDR_QUSE3             _PIN(80)
 309#define TEGRA_PIN_DDR_RAS_N             _PIN(81)
 310#define TEGRA_PIN_DDR_WE_N              _PIN(82)
 311#define TEGRA_PIN_DDR_DQ0               _PIN(83)
 312#define TEGRA_PIN_DDR_DQ1               _PIN(84)
 313#define TEGRA_PIN_DDR_DQ2               _PIN(85)
 314#define TEGRA_PIN_DDR_DQ3               _PIN(86)
 315#define TEGRA_PIN_DDR_DQ4               _PIN(87)
 316#define TEGRA_PIN_DDR_DQ5               _PIN(88)
 317#define TEGRA_PIN_DDR_DQ6               _PIN(89)
 318#define TEGRA_PIN_DDR_DQ7               _PIN(90)
 319#define TEGRA_PIN_DDR_DQ8               _PIN(91)
 320#define TEGRA_PIN_DDR_DQ9               _PIN(92)
 321#define TEGRA_PIN_DDR_DQ10              _PIN(93)
 322#define TEGRA_PIN_DDR_DQ11              _PIN(94)
 323#define TEGRA_PIN_DDR_DQ12              _PIN(95)
 324#define TEGRA_PIN_DDR_DQ13              _PIN(96)
 325#define TEGRA_PIN_DDR_DQ14              _PIN(97)
 326#define TEGRA_PIN_DDR_DQ15              _PIN(98)
 327#define TEGRA_PIN_DDR_DQ16              _PIN(99)
 328#define TEGRA_PIN_DDR_DQ17              _PIN(100)
 329#define TEGRA_PIN_DDR_DQ18              _PIN(101)
 330#define TEGRA_PIN_DDR_DQ19              _PIN(102)
 331#define TEGRA_PIN_DDR_DQ20              _PIN(103)
 332#define TEGRA_PIN_DDR_DQ21              _PIN(104)
 333#define TEGRA_PIN_DDR_DQ22              _PIN(105)
 334#define TEGRA_PIN_DDR_DQ23              _PIN(106)
 335#define TEGRA_PIN_DDR_DQ24              _PIN(107)
 336#define TEGRA_PIN_DDR_DQ25              _PIN(108)
 337#define TEGRA_PIN_DDR_DQ26              _PIN(109)
 338#define TEGRA_PIN_DDR_DQ27              _PIN(110)
 339#define TEGRA_PIN_DDR_DQ28              _PIN(111)
 340#define TEGRA_PIN_DDR_DQ29              _PIN(112)
 341#define TEGRA_PIN_DDR_DQ30              _PIN(113)
 342#define TEGRA_PIN_DDR_DQ31              _PIN(114)
 343#define TEGRA_PIN_DDR_CS0_N             _PIN(115)
 344#define TEGRA_PIN_DDR_CS1_N             _PIN(116)
 345#define TEGRA_PIN_SYS_RESET             _PIN(117)
 346#define TEGRA_PIN_JTAG_TRST_N           _PIN(118)
 347#define TEGRA_PIN_JTAG_TDO              _PIN(119)
 348#define TEGRA_PIN_JTAG_TMS              _PIN(120)
 349#define TEGRA_PIN_JTAG_TCK              _PIN(121)
 350#define TEGRA_PIN_JTAG_TDI              _PIN(122)
 351#define TEGRA_PIN_TEST_MODE_EN          _PIN(123)
 352
 353static const struct pinctrl_pin_desc tegra20_pins[] = {
 354        PINCTRL_PIN(TEGRA_PIN_VI_GP6_PA0, "VI_GP6 PA0"),
 355        PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
 356        PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
 357        PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
 358        PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
 359        PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
 360        PINCTRL_PIN(TEGRA_PIN_SDIO3_CLK_PA6, "SDIO3_CLK PA6"),
 361        PINCTRL_PIN(TEGRA_PIN_SDIO3_CMD_PA7, "SDIO3_CMD PA7"),
 362        PINCTRL_PIN(TEGRA_PIN_GMI_AD17_PB0, "GMI_AD17 PB0"),
 363        PINCTRL_PIN(TEGRA_PIN_GMI_AD18_PB1, "GMI_AD18 PB1"),
 364        PINCTRL_PIN(TEGRA_PIN_LCD_PWR0_PB2, "LCD_PWR0 PB2"),
 365        PINCTRL_PIN(TEGRA_PIN_LCD_PCLK_PB3, "LCD_PCLK PB3"),
 366        PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT3_PB4, "SDIO3_DAT3 PB4"),
 367        PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT2_PB5, "SDIO3_DAT2 PB5"),
 368        PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT1_PB6, "SDIO3_DAT1 PB6"),
 369        PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT0_PB7, "SDIO3_DAT0 PB7"),
 370        PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
 371        PINCTRL_PIN(TEGRA_PIN_LCD_PWR1_PC1, "LCD_PWR1 PC1"),
 372        PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
 373        PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
 374        PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
 375        PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
 376        PINCTRL_PIN(TEGRA_PIN_LCD_PWR2_PC6, "LCD_PWR2 PC6"),
 377        PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
 378        PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT5_PD0, "SDIO3_DAT5 PD0"),
 379        PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT4_PD1, "SDIO3_DAT4 PD1"),
 380        PINCTRL_PIN(TEGRA_PIN_VI_GP5_PD2, "VI_GP5 PD2"),
 381        PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT6_PD3, "SDIO3_DAT6 PD3"),
 382        PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT7_PD4, "SDIO3_DAT7 PD4"),
 383        PINCTRL_PIN(TEGRA_PIN_VI_D1_PD5, "VI_D1 PD5"),
 384        PINCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "VI_VSYNC PD6"),
 385        PINCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, "VI_HSYNC PD7"),
 386        PINCTRL_PIN(TEGRA_PIN_LCD_D0_PE0, "LCD_D0 PE0"),
 387        PINCTRL_PIN(TEGRA_PIN_LCD_D1_PE1, "LCD_D1 PE1"),
 388        PINCTRL_PIN(TEGRA_PIN_LCD_D2_PE2, "LCD_D2 PE2"),
 389        PINCTRL_PIN(TEGRA_PIN_LCD_D3_PE3, "LCD_D3 PE3"),
 390        PINCTRL_PIN(TEGRA_PIN_LCD_D4_PE4, "LCD_D4 PE4"),
 391        PINCTRL_PIN(TEGRA_PIN_LCD_D5_PE5, "LCD_D5 PE5"),
 392        PINCTRL_PIN(TEGRA_PIN_LCD_D6_PE6, "LCD_D6 PE6"),
 393        PINCTRL_PIN(TEGRA_PIN_LCD_D7_PE7, "LCD_D7 PE7"),
 394        PINCTRL_PIN(TEGRA_PIN_LCD_D8_PF0, "LCD_D8 PF0"),
 395        PINCTRL_PIN(TEGRA_PIN_LCD_D9_PF1, "LCD_D9 PF1"),
 396        PINCTRL_PIN(TEGRA_PIN_LCD_D10_PF2, "LCD_D10 PF2"),
 397        PINCTRL_PIN(TEGRA_PIN_LCD_D11_PF3, "LCD_D11 PF3"),
 398        PINCTRL_PIN(TEGRA_PIN_LCD_D12_PF4, "LCD_D12 PF4"),
 399        PINCTRL_PIN(TEGRA_PIN_LCD_D13_PF5, "LCD_D13 PF5"),
 400        PINCTRL_PIN(TEGRA_PIN_LCD_D14_PF6, "LCD_D14 PF6"),
 401        PINCTRL_PIN(TEGRA_PIN_LCD_D15_PF7, "LCD_D15 PF7"),
 402        PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
 403        PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
 404        PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
 405        PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
 406        PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
 407        PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
 408        PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
 409        PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
 410        PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
 411        PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
 412        PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
 413        PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
 414        PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
 415        PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
 416        PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
 417        PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
 418        PINCTRL_PIN(TEGRA_PIN_GMI_HIOW_N_PI0, "GMI_HIOW_N PI0"),
 419        PINCTRL_PIN(TEGRA_PIN_GMI_HIOR_N_PI1, "GMI_HIOR_N PI1"),
 420        PINCTRL_PIN(TEGRA_PIN_GMI_CS5_N_PI2, "GMI_CS5_N PI2"),
 421        PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
 422        PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
 423        PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
 424        PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
 425        PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
 426        PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
 427        PINCTRL_PIN(TEGRA_PIN_LCD_DE_PJ1, "LCD_DE PJ1"),
 428        PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
 429        PINCTRL_PIN(TEGRA_PIN_LCD_HSYNC_PJ3, "LCD_HSYNC PJ3"),
 430        PINCTRL_PIN(TEGRA_PIN_LCD_VSYNC_PJ4, "LCD_VSYNC PJ4"),
 431        PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
 432        PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
 433        PINCTRL_PIN(TEGRA_PIN_GMI_AD16_PJ7, "GMI_AD16 PJ7"),
 434        PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
 435        PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
 436        PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
 437        PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
 438        PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
 439        PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
 440        PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
 441        PINCTRL_PIN(TEGRA_PIN_GMI_AD19_PK7, "GMI_AD19 PK7"),
 442        PINCTRL_PIN(TEGRA_PIN_VI_D2_PL0, "VI_D2 PL0"),
 443        PINCTRL_PIN(TEGRA_PIN_VI_D3_PL1, "VI_D3 PL1"),
 444        PINCTRL_PIN(TEGRA_PIN_VI_D4_PL2, "VI_D4 PL2"),
 445        PINCTRL_PIN(TEGRA_PIN_VI_D5_PL3, "VI_D5 PL3"),
 446        PINCTRL_PIN(TEGRA_PIN_VI_D6_PL4, "VI_D6 PL4"),
 447        PINCTRL_PIN(TEGRA_PIN_VI_D7_PL5, "VI_D7 PL5"),
 448        PINCTRL_PIN(TEGRA_PIN_VI_D8_PL6, "VI_D8 PL6"),
 449        PINCTRL_PIN(TEGRA_PIN_VI_D9_PL7, "VI_D9 PL7"),
 450        PINCTRL_PIN(TEGRA_PIN_LCD_D16_PM0, "LCD_D16 PM0"),
 451        PINCTRL_PIN(TEGRA_PIN_LCD_D17_PM1, "LCD_D17 PM1"),
 452        PINCTRL_PIN(TEGRA_PIN_LCD_D18_PM2, "LCD_D18 PM2"),
 453        PINCTRL_PIN(TEGRA_PIN_LCD_D19_PM3, "LCD_D19 PM3"),
 454        PINCTRL_PIN(TEGRA_PIN_LCD_D20_PM4, "LCD_D20 PM4"),
 455        PINCTRL_PIN(TEGRA_PIN_LCD_D21_PM5, "LCD_D21 PM5"),
 456        PINCTRL_PIN(TEGRA_PIN_LCD_D22_PM6, "LCD_D22 PM6"),
 457        PINCTRL_PIN(TEGRA_PIN_LCD_D23_PM7, "LCD_D23 PM7"),
 458        PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
 459        PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
 460        PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
 461        PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
 462        PINCTRL_PIN(TEGRA_PIN_LCD_CS0_N_PN4, "LCD_CS0_N PN4"),
 463        PINCTRL_PIN(TEGRA_PIN_LCD_SDOUT_PN5, "LCD_SDOUT PN5"),
 464        PINCTRL_PIN(TEGRA_PIN_LCD_DC0_PN6, "LCD_DC0 PN6"),
 465        PINCTRL_PIN(TEGRA_PIN_HDMI_INT_N_PN7, "HDMI_INT_N PN7"),
 466        PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
 467        PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
 468        PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
 469        PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
 470        PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
 471        PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
 472        PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
 473        PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
 474        PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
 475        PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
 476        PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
 477        PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
 478        PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
 479        PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
 480        PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
 481        PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
 482        PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
 483        PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
 484        PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
 485        PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
 486        PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
 487        PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
 488        PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
 489        PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
 490        PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
 491        PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
 492        PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
 493        PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
 494        PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
 495        PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
 496        PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
 497        PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
 498        PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
 499        PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
 500        PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
 501        PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"),
 502        PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"),
 503        PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"),
 504        PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"),
 505        PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"),
 506        PINCTRL_PIN(TEGRA_PIN_VI_PCLK_PT0, "VI_PCLK PT0"),
 507        PINCTRL_PIN(TEGRA_PIN_VI_MCLK_PT1, "VI_MCLK PT1"),
 508        PINCTRL_PIN(TEGRA_PIN_VI_D10_PT2, "VD_D10 PT2"),
 509        PINCTRL_PIN(TEGRA_PIN_VI_D11_PT3, "VI_D11 PT3"),
 510        PINCTRL_PIN(TEGRA_PIN_VI_D0_PT4, "VI_D0 PT4"),
 511        PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
 512        PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
 513        PINCTRL_PIN(TEGRA_PIN_GMI_DPD_PT7, "GMI_DPD PT7"),
 514        /* PU0..6: GPIO only */
 515        PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
 516        PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
 517        PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
 518        PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
 519        PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
 520        PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
 521        PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
 522        PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK_PU7, "JTAG_RTCK PU7"),
 523        /* PV0..1: GPIO only */
 524        PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
 525        PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
 526        /* PV2..3: Balls are named after GPIO not function */
 527        PINCTRL_PIN(TEGRA_PIN_PV2, "PV2"),
 528        PINCTRL_PIN(TEGRA_PIN_PV3, "PV3"),
 529        /* PV4..6: GPIO only */
 530        PINCTRL_PIN(TEGRA_PIN_PV4, "PV4"),
 531        PINCTRL_PIN(TEGRA_PIN_PV5, "PV5"),
 532        PINCTRL_PIN(TEGRA_PIN_PV6, "PV6"),
 533        PINCTRL_PIN(TEGRA_PIN_LCD_DC1_PV7, "LCD_DC1 PV7"),
 534        PINCTRL_PIN(TEGRA_PIN_LCD_CS1_N_PW0, "LCD_CS1_N PW0"),
 535        PINCTRL_PIN(TEGRA_PIN_LCD_M1_PW1, "LCD_M1 PW1"),
 536        PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_N_PW2, "SPI2_CS1_N PW2"),
 537        PINCTRL_PIN(TEGRA_PIN_SPI2_CS2_N_PW3, "SPI2_CS2_N PW3"),
 538        PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_PW4, "DAP_MCLK1 PW4"),
 539        PINCTRL_PIN(TEGRA_PIN_DAP_MCLK2_PW5, "DAP_MCLK2 PW5"),
 540        PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
 541        PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
 542        PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PX0, "SPI2_MOSI PX0"),
 543        PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PX1, "SPI2_MISO PX1"),
 544        PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PX2, "SPI2_SCK PX2"),
 545        PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_N_PX3, "SPI2_CS0_N PX3"),
 546        PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PX4, "SPI1_MOSI PX4"),
 547        PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PX5, "SPI1_SCK PX5"),
 548        PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_N_PX6, "SPI1_CS0_N PX6"),
 549        PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PX7, "SPI1_MISO PX7"),
 550        PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
 551        PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
 552        PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
 553        PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
 554        PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT3_PY4, "SDIO1_DAT3 PY4"),
 555        PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT2_PY5, "SDIO1_DAT2 PY5"),
 556        PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT1_PY6, "SDIO1_DAT1 PY6"),
 557        PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT0_PY7, "SDIO1_DAT0 PY7"),
 558        PINCTRL_PIN(TEGRA_PIN_SDIO1_CLK_PZ0, "SDIO1_CLK PZ0"),
 559        PINCTRL_PIN(TEGRA_PIN_SDIO1_CMD_PZ1, "SDIO1_CMD PZ1"),
 560        PINCTRL_PIN(TEGRA_PIN_LCD_SDIN_PZ2, "LCD_SDIN PZ2"),
 561        PINCTRL_PIN(TEGRA_PIN_LCD_WR_N_PZ3, "LCD_WR_N PZ3"),
 562        PINCTRL_PIN(TEGRA_PIN_LCD_SCK_PZ4, "LCD_SCK PZ4"),
 563        PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
 564        PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
 565        PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
 566        PINCTRL_PIN(TEGRA_PIN_GMI_AD20_PAA0, "GMI_AD20 PAA0"),
 567        PINCTRL_PIN(TEGRA_PIN_GMI_AD21_PAA1, "GMI_AD21 PAA1"),
 568        PINCTRL_PIN(TEGRA_PIN_GMI_AD22_PAA2, "GMI_AD22 PAA2"),
 569        PINCTRL_PIN(TEGRA_PIN_GMI_AD23_PAA3, "GMI_AD23 PAA3"),
 570        PINCTRL_PIN(TEGRA_PIN_GMI_AD24_PAA4, "GMI_AD24 PAA4"),
 571        PINCTRL_PIN(TEGRA_PIN_GMI_AD25_PAA5, "GMI_AD25 PAA5"),
 572        PINCTRL_PIN(TEGRA_PIN_GMI_AD26_PAA6, "GMI_AD26 PAA6"),
 573        PINCTRL_PIN(TEGRA_PIN_GMI_AD27_PAA7, "GMI_AD27 PAA7"),
 574        PINCTRL_PIN(TEGRA_PIN_LED_BLINK_PBB0, "LED_BLINK PBB0"),
 575        PINCTRL_PIN(TEGRA_PIN_VI_GP0_PBB1, "VI_GP0 PBB1"),
 576        PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB2, "CAM_I2C_SCL PBB2"),
 577        PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB3, "CAM_I2C_SDA PBB3"),
 578        PINCTRL_PIN(TEGRA_PIN_VI_GP3_PBB4, "VI_GP3 PBB4"),
 579        PINCTRL_PIN(TEGRA_PIN_VI_GP4_PBB5, "VI_GP4 PBB5"),
 580        PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
 581        PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
 582        PINCTRL_PIN(TEGRA_PIN_CRT_HSYNC, "CRT_HSYNC"),
 583        PINCTRL_PIN(TEGRA_PIN_CRT_VSYNC, "CRT_VSYNC"),
 584        PINCTRL_PIN(TEGRA_PIN_DDC_SCL, "DDC_SCL"),
 585        PINCTRL_PIN(TEGRA_PIN_DDC_SDA, "DDC_SDA"),
 586        PINCTRL_PIN(TEGRA_PIN_OWC, "OWC"),
 587        PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
 588        PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
 589        PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
 590        PINCTRL_PIN(TEGRA_PIN_CLK_32_K_IN, "CLK_32_K_IN"),
 591        PINCTRL_PIN(TEGRA_PIN_DDR_COMP_PD, "DDR_COMP_PD"),
 592        PINCTRL_PIN(TEGRA_PIN_DDR_COMP_PU, "DDR_COMP_PU"),
 593        PINCTRL_PIN(TEGRA_PIN_DDR_A0, "DDR_A0"),
 594        PINCTRL_PIN(TEGRA_PIN_DDR_A1, "DDR_A1"),
 595        PINCTRL_PIN(TEGRA_PIN_DDR_A2, "DDR_A2"),
 596        PINCTRL_PIN(TEGRA_PIN_DDR_A3, "DDR_A3"),
 597        PINCTRL_PIN(TEGRA_PIN_DDR_A4, "DDR_A4"),
 598        PINCTRL_PIN(TEGRA_PIN_DDR_A5, "DDR_A5"),
 599        PINCTRL_PIN(TEGRA_PIN_DDR_A6, "DDR_A6"),
 600        PINCTRL_PIN(TEGRA_PIN_DDR_A7, "DDR_A7"),
 601        PINCTRL_PIN(TEGRA_PIN_DDR_A8, "DDR_A8"),
 602        PINCTRL_PIN(TEGRA_PIN_DDR_A9, "DDR_A9"),
 603        PINCTRL_PIN(TEGRA_PIN_DDR_A10, "DDR_A10"),
 604        PINCTRL_PIN(TEGRA_PIN_DDR_A11, "DDR_A11"),
 605        PINCTRL_PIN(TEGRA_PIN_DDR_A12, "DDR_A12"),
 606        PINCTRL_PIN(TEGRA_PIN_DDR_A13, "DDR_A13"),
 607        PINCTRL_PIN(TEGRA_PIN_DDR_A14, "DDR_A14"),
 608        PINCTRL_PIN(TEGRA_PIN_DDR_CAS_N, "DDR_CAS_N"),
 609        PINCTRL_PIN(TEGRA_PIN_DDR_BA0, "DDR_BA0"),
 610        PINCTRL_PIN(TEGRA_PIN_DDR_BA1, "DDR_BA1"),
 611        PINCTRL_PIN(TEGRA_PIN_DDR_BA2, "DDR_BA2"),
 612        PINCTRL_PIN(TEGRA_PIN_DDR_DQS0P, "DDR_DQS0P"),
 613        PINCTRL_PIN(TEGRA_PIN_DDR_DQS0N, "DDR_DQS0N"),
 614        PINCTRL_PIN(TEGRA_PIN_DDR_DQS1P, "DDR_DQS1P"),
 615        PINCTRL_PIN(TEGRA_PIN_DDR_DQS1N, "DDR_DQS1N"),
 616        PINCTRL_PIN(TEGRA_PIN_DDR_DQS2P, "DDR_DQS2P"),
 617        PINCTRL_PIN(TEGRA_PIN_DDR_DQS2N, "DDR_DQS2N"),
 618        PINCTRL_PIN(TEGRA_PIN_DDR_DQS3P, "DDR_DQS3P"),
 619        PINCTRL_PIN(TEGRA_PIN_DDR_DQS3N, "DDR_DQS3N"),
 620        PINCTRL_PIN(TEGRA_PIN_DDR_CKE0, "DDR_CKE0"),
 621        PINCTRL_PIN(TEGRA_PIN_DDR_CKE1, "DDR_CKE1"),
 622        PINCTRL_PIN(TEGRA_PIN_DDR_CLK, "DDR_CLK"),
 623        PINCTRL_PIN(TEGRA_PIN_DDR_CLK_N, "DDR_CLK_N"),
 624        PINCTRL_PIN(TEGRA_PIN_DDR_DM0, "DDR_DM0"),
 625        PINCTRL_PIN(TEGRA_PIN_DDR_DM1, "DDR_DM1"),
 626        PINCTRL_PIN(TEGRA_PIN_DDR_DM2, "DDR_DM2"),
 627        PINCTRL_PIN(TEGRA_PIN_DDR_DM3, "DDR_DM3"),
 628        PINCTRL_PIN(TEGRA_PIN_DDR_ODT, "DDR_ODT"),
 629        PINCTRL_PIN(TEGRA_PIN_DDR_QUSE0, "DDR_QUSE0"),
 630        PINCTRL_PIN(TEGRA_PIN_DDR_QUSE1, "DDR_QUSE1"),
 631        PINCTRL_PIN(TEGRA_PIN_DDR_QUSE2, "DDR_QUSE2"),
 632        PINCTRL_PIN(TEGRA_PIN_DDR_QUSE3, "DDR_QUSE3"),
 633        PINCTRL_PIN(TEGRA_PIN_DDR_RAS_N, "DDR_RAS_N"),
 634        PINCTRL_PIN(TEGRA_PIN_DDR_WE_N, "DDR_WE_N"),
 635        PINCTRL_PIN(TEGRA_PIN_DDR_DQ0, "DDR_DQ0"),
 636        PINCTRL_PIN(TEGRA_PIN_DDR_DQ1, "DDR_DQ1"),
 637        PINCTRL_PIN(TEGRA_PIN_DDR_DQ2, "DDR_DQ2"),
 638        PINCTRL_PIN(TEGRA_PIN_DDR_DQ3, "DDR_DQ3"),
 639        PINCTRL_PIN(TEGRA_PIN_DDR_DQ4, "DDR_DQ4"),
 640        PINCTRL_PIN(TEGRA_PIN_DDR_DQ5, "DDR_DQ5"),
 641        PINCTRL_PIN(TEGRA_PIN_DDR_DQ6, "DDR_DQ6"),
 642        PINCTRL_PIN(TEGRA_PIN_DDR_DQ7, "DDR_DQ7"),
 643        PINCTRL_PIN(TEGRA_PIN_DDR_DQ8, "DDR_DQ8"),
 644        PINCTRL_PIN(TEGRA_PIN_DDR_DQ9, "DDR_DQ9"),
 645        PINCTRL_PIN(TEGRA_PIN_DDR_DQ10, "DDR_DQ10"),
 646        PINCTRL_PIN(TEGRA_PIN_DDR_DQ11, "DDR_DQ11"),
 647        PINCTRL_PIN(TEGRA_PIN_DDR_DQ12, "DDR_DQ12"),
 648        PINCTRL_PIN(TEGRA_PIN_DDR_DQ13, "DDR_DQ13"),
 649        PINCTRL_PIN(TEGRA_PIN_DDR_DQ14, "DDR_DQ14"),
 650        PINCTRL_PIN(TEGRA_PIN_DDR_DQ15, "DDR_DQ15"),
 651        PINCTRL_PIN(TEGRA_PIN_DDR_DQ16, "DDR_DQ16"),
 652        PINCTRL_PIN(TEGRA_PIN_DDR_DQ17, "DDR_DQ17"),
 653        PINCTRL_PIN(TEGRA_PIN_DDR_DQ18, "DDR_DQ18"),
 654        PINCTRL_PIN(TEGRA_PIN_DDR_DQ19, "DDR_DQ19"),
 655        PINCTRL_PIN(TEGRA_PIN_DDR_DQ20, "DDR_DQ20"),
 656        PINCTRL_PIN(TEGRA_PIN_DDR_DQ21, "DDR_DQ21"),
 657        PINCTRL_PIN(TEGRA_PIN_DDR_DQ22, "DDR_DQ22"),
 658        PINCTRL_PIN(TEGRA_PIN_DDR_DQ23, "DDR_DQ23"),
 659        PINCTRL_PIN(TEGRA_PIN_DDR_DQ24, "DDR_DQ24"),
 660        PINCTRL_PIN(TEGRA_PIN_DDR_DQ25, "DDR_DQ25"),
 661        PINCTRL_PIN(TEGRA_PIN_DDR_DQ26, "DDR_DQ26"),
 662        PINCTRL_PIN(TEGRA_PIN_DDR_DQ27, "DDR_DQ27"),
 663        PINCTRL_PIN(TEGRA_PIN_DDR_DQ28, "DDR_DQ28"),
 664        PINCTRL_PIN(TEGRA_PIN_DDR_DQ29, "DDR_DQ29"),
 665        PINCTRL_PIN(TEGRA_PIN_DDR_DQ30, "DDR_DQ30"),
 666        PINCTRL_PIN(TEGRA_PIN_DDR_DQ31, "DDR_DQ31"),
 667        PINCTRL_PIN(TEGRA_PIN_DDR_CS0_N, "DDR_CS0_N"),
 668        PINCTRL_PIN(TEGRA_PIN_DDR_CS1_N, "DDR_CS1_N"),
 669        PINCTRL_PIN(TEGRA_PIN_SYS_RESET, "SYS_RESET"),
 670        PINCTRL_PIN(TEGRA_PIN_JTAG_TRST_N, "JTAG_TRST_N"),
 671        PINCTRL_PIN(TEGRA_PIN_JTAG_TDO, "JTAG_TDO"),
 672        PINCTRL_PIN(TEGRA_PIN_JTAG_TMS, "JTAG_TMS"),
 673        PINCTRL_PIN(TEGRA_PIN_JTAG_TCK, "JTAG_TCK"),
 674        PINCTRL_PIN(TEGRA_PIN_JTAG_TDI, "JTAG_TDI"),
 675        PINCTRL_PIN(TEGRA_PIN_TEST_MODE_EN, "TEST_MODE_EN"),
 676};
 677
 678static const unsigned ata_pins[] = {
 679        TEGRA_PIN_GMI_CS6_N_PI3,
 680        TEGRA_PIN_GMI_CS7_N_PI6,
 681        TEGRA_PIN_GMI_RST_N_PI4,
 682};
 683
 684static const unsigned atb_pins[] = {
 685        TEGRA_PIN_GMI_CS5_N_PI2,
 686        TEGRA_PIN_GMI_DPD_PT7,
 687};
 688
 689static const unsigned atc_pins[] = {
 690        TEGRA_PIN_GMI_IORDY_PI5,
 691        TEGRA_PIN_GMI_WAIT_PI7,
 692        TEGRA_PIN_GMI_ADV_N_PK0,
 693        TEGRA_PIN_GMI_CLK_PK1,
 694        TEGRA_PIN_GMI_CS2_N_PK3,
 695        TEGRA_PIN_GMI_CS3_N_PK4,
 696        TEGRA_PIN_GMI_CS4_N_PK2,
 697        TEGRA_PIN_GMI_AD0_PG0,
 698        TEGRA_PIN_GMI_AD1_PG1,
 699        TEGRA_PIN_GMI_AD2_PG2,
 700        TEGRA_PIN_GMI_AD3_PG3,
 701        TEGRA_PIN_GMI_AD4_PG4,
 702        TEGRA_PIN_GMI_AD5_PG5,
 703        TEGRA_PIN_GMI_AD6_PG6,
 704        TEGRA_PIN_GMI_AD7_PG7,
 705        TEGRA_PIN_GMI_HIOW_N_PI0,
 706        TEGRA_PIN_GMI_HIOR_N_PI1,
 707};
 708
 709static const unsigned atd_pins[] = {
 710        TEGRA_PIN_GMI_AD8_PH0,
 711        TEGRA_PIN_GMI_AD9_PH1,
 712        TEGRA_PIN_GMI_AD10_PH2,
 713        TEGRA_PIN_GMI_AD11_PH3,
 714};
 715
 716static const unsigned ate_pins[] = {
 717        TEGRA_PIN_GMI_AD12_PH4,
 718        TEGRA_PIN_GMI_AD13_PH5,
 719        TEGRA_PIN_GMI_AD14_PH6,
 720        TEGRA_PIN_GMI_AD15_PH7,
 721};
 722
 723static const unsigned cdev1_pins[] = {
 724        TEGRA_PIN_DAP_MCLK1_PW4,
 725};
 726
 727static const unsigned cdev2_pins[] = {
 728        TEGRA_PIN_DAP_MCLK2_PW5,
 729};
 730
 731static const unsigned crtp_pins[] = {
 732        TEGRA_PIN_CRT_HSYNC,
 733        TEGRA_PIN_CRT_VSYNC,
 734};
 735
 736static const unsigned csus_pins[] = {
 737        TEGRA_PIN_VI_MCLK_PT1,
 738};
 739
 740static const unsigned dap1_pins[] = {
 741        TEGRA_PIN_DAP1_FS_PN0,
 742        TEGRA_PIN_DAP1_DIN_PN1,
 743        TEGRA_PIN_DAP1_DOUT_PN2,
 744        TEGRA_PIN_DAP1_SCLK_PN3,
 745};
 746
 747static const unsigned dap2_pins[] = {
 748        TEGRA_PIN_DAP2_FS_PA2,
 749        TEGRA_PIN_DAP2_SCLK_PA3,
 750        TEGRA_PIN_DAP2_DIN_PA4,
 751        TEGRA_PIN_DAP2_DOUT_PA5,
 752};
 753
 754static const unsigned dap3_pins[] = {
 755        TEGRA_PIN_DAP3_FS_PP0,
 756        TEGRA_PIN_DAP3_DIN_PP1,
 757        TEGRA_PIN_DAP3_DOUT_PP2,
 758        TEGRA_PIN_DAP3_SCLK_PP3,
 759};
 760
 761static const unsigned dap4_pins[] = {
 762        TEGRA_PIN_DAP4_FS_PP4,
 763        TEGRA_PIN_DAP4_DIN_PP5,
 764        TEGRA_PIN_DAP4_DOUT_PP6,
 765        TEGRA_PIN_DAP4_SCLK_PP7,
 766};
 767
 768static const unsigned ddc_pins[] = {
 769        TEGRA_PIN_DDC_SCL,
 770        TEGRA_PIN_DDC_SDA,
 771};
 772
 773static const unsigned dta_pins[] = {
 774        TEGRA_PIN_VI_D0_PT4,
 775        TEGRA_PIN_VI_D1_PD5,
 776};
 777
 778static const unsigned dtb_pins[] = {
 779        TEGRA_PIN_VI_D10_PT2,
 780        TEGRA_PIN_VI_D11_PT3,
 781};
 782
 783static const unsigned dtc_pins[] = {
 784        TEGRA_PIN_VI_HSYNC_PD7,
 785        TEGRA_PIN_VI_VSYNC_PD6,
 786};
 787
 788static const unsigned dtd_pins[] = {
 789        TEGRA_PIN_VI_PCLK_PT0,
 790        TEGRA_PIN_VI_D2_PL0,
 791        TEGRA_PIN_VI_D3_PL1,
 792        TEGRA_PIN_VI_D4_PL2,
 793        TEGRA_PIN_VI_D5_PL3,
 794        TEGRA_PIN_VI_D6_PL4,
 795        TEGRA_PIN_VI_D7_PL5,
 796        TEGRA_PIN_VI_D8_PL6,
 797        TEGRA_PIN_VI_D9_PL7,
 798};
 799
 800static const unsigned dte_pins[] = {
 801        TEGRA_PIN_VI_GP0_PBB1,
 802        TEGRA_PIN_VI_GP3_PBB4,
 803        TEGRA_PIN_VI_GP4_PBB5,
 804        TEGRA_PIN_VI_GP5_PD2,
 805        TEGRA_PIN_VI_GP6_PA0,
 806};
 807
 808static const unsigned dtf_pins[] = {
 809        TEGRA_PIN_CAM_I2C_SCL_PBB2,
 810        TEGRA_PIN_CAM_I2C_SDA_PBB3,
 811};
 812
 813static const unsigned gma_pins[] = {
 814        TEGRA_PIN_GMI_AD20_PAA0,
 815        TEGRA_PIN_GMI_AD21_PAA1,
 816        TEGRA_PIN_GMI_AD22_PAA2,
 817        TEGRA_PIN_GMI_AD23_PAA3,
 818};
 819
 820static const unsigned gmb_pins[] = {
 821        TEGRA_PIN_GMI_WP_N_PC7,
 822};
 823
 824static const unsigned gmc_pins[] = {
 825        TEGRA_PIN_GMI_AD16_PJ7,
 826        TEGRA_PIN_GMI_AD17_PB0,
 827        TEGRA_PIN_GMI_AD18_PB1,
 828        TEGRA_PIN_GMI_AD19_PK7,
 829};
 830
 831static const unsigned gmd_pins[] = {
 832        TEGRA_PIN_GMI_CS0_N_PJ0,
 833        TEGRA_PIN_GMI_CS1_N_PJ2,
 834};
 835
 836static const unsigned gme_pins[] = {
 837        TEGRA_PIN_GMI_AD24_PAA4,
 838        TEGRA_PIN_GMI_AD25_PAA5,
 839        TEGRA_PIN_GMI_AD26_PAA6,
 840        TEGRA_PIN_GMI_AD27_PAA7,
 841};
 842
 843static const unsigned gpu_pins[] = {
 844        TEGRA_PIN_PU0,
 845        TEGRA_PIN_PU1,
 846        TEGRA_PIN_PU2,
 847        TEGRA_PIN_PU3,
 848        TEGRA_PIN_PU4,
 849        TEGRA_PIN_PU5,
 850        TEGRA_PIN_PU6,
 851};
 852
 853static const unsigned gpu7_pins[] = {
 854        TEGRA_PIN_JTAG_RTCK_PU7,
 855};
 856
 857static const unsigned gpv_pins[] = {
 858        TEGRA_PIN_PV4,
 859        TEGRA_PIN_PV5,
 860        TEGRA_PIN_PV6,
 861};
 862
 863static const unsigned hdint_pins[] = {
 864        TEGRA_PIN_HDMI_INT_N_PN7,
 865};
 866
 867static const unsigned i2cp_pins[] = {
 868        TEGRA_PIN_PWR_I2C_SCL_PZ6,
 869        TEGRA_PIN_PWR_I2C_SDA_PZ7,
 870};
 871
 872static const unsigned irrx_pins[] = {
 873        TEGRA_PIN_UART2_RTS_N_PJ6,
 874};
 875
 876static const unsigned irtx_pins[] = {
 877        TEGRA_PIN_UART2_CTS_N_PJ5,
 878};
 879
 880static const unsigned kbca_pins[] = {
 881        TEGRA_PIN_KB_ROW0_PR0,
 882        TEGRA_PIN_KB_ROW1_PR1,
 883        TEGRA_PIN_KB_ROW2_PR2,
 884};
 885
 886static const unsigned kbcb_pins[] = {
 887        TEGRA_PIN_KB_ROW7_PR7,
 888        TEGRA_PIN_KB_ROW8_PS0,
 889        TEGRA_PIN_KB_ROW9_PS1,
 890        TEGRA_PIN_KB_ROW10_PS2,
 891        TEGRA_PIN_KB_ROW11_PS3,
 892        TEGRA_PIN_KB_ROW12_PS4,
 893        TEGRA_PIN_KB_ROW13_PS5,
 894        TEGRA_PIN_KB_ROW14_PS6,
 895        TEGRA_PIN_KB_ROW15_PS7,
 896};
 897
 898static const unsigned kbcc_pins[] = {
 899        TEGRA_PIN_KB_COL0_PQ0,
 900        TEGRA_PIN_KB_COL1_PQ1,
 901};
 902
 903static const unsigned kbcd_pins[] = {
 904        TEGRA_PIN_KB_ROW3_PR3,
 905        TEGRA_PIN_KB_ROW4_PR4,
 906        TEGRA_PIN_KB_ROW5_PR5,
 907        TEGRA_PIN_KB_ROW6_PR6,
 908};
 909
 910static const unsigned kbce_pins[] = {
 911        TEGRA_PIN_KB_COL7_PQ7,
 912};
 913
 914static const unsigned kbcf_pins[] = {
 915        TEGRA_PIN_KB_COL2_PQ2,
 916        TEGRA_PIN_KB_COL3_PQ3,
 917        TEGRA_PIN_KB_COL4_PQ4,
 918        TEGRA_PIN_KB_COL5_PQ5,
 919        TEGRA_PIN_KB_COL6_PQ6,
 920};
 921
 922static const unsigned lcsn_pins[] = {
 923        TEGRA_PIN_LCD_CS0_N_PN4,
 924};
 925
 926static const unsigned ld0_pins[] = {
 927        TEGRA_PIN_LCD_D0_PE0,
 928};
 929
 930static const unsigned ld1_pins[] = {
 931        TEGRA_PIN_LCD_D1_PE1,
 932};
 933
 934static const unsigned ld2_pins[] = {
 935        TEGRA_PIN_LCD_D2_PE2,
 936};
 937
 938static const unsigned ld3_pins[] = {
 939        TEGRA_PIN_LCD_D3_PE3,
 940};
 941
 942static const unsigned ld4_pins[] = {
 943        TEGRA_PIN_LCD_D4_PE4,
 944};
 945
 946static const unsigned ld5_pins[] = {
 947        TEGRA_PIN_LCD_D5_PE5,
 948};
 949
 950static const unsigned ld6_pins[] = {
 951        TEGRA_PIN_LCD_D6_PE6,
 952};
 953
 954static const unsigned ld7_pins[] = {
 955        TEGRA_PIN_LCD_D7_PE7,
 956};
 957
 958static const unsigned ld8_pins[] = {
 959        TEGRA_PIN_LCD_D8_PF0,
 960};
 961
 962static const unsigned ld9_pins[] = {
 963        TEGRA_PIN_LCD_D9_PF1,
 964};
 965
 966static const unsigned ld10_pins[] = {
 967        TEGRA_PIN_LCD_D10_PF2,
 968};
 969
 970static const unsigned ld11_pins[] = {
 971        TEGRA_PIN_LCD_D11_PF3,
 972};
 973
 974static const unsigned ld12_pins[] = {
 975        TEGRA_PIN_LCD_D12_PF4,
 976};
 977
 978static const unsigned ld13_pins[] = {
 979        TEGRA_PIN_LCD_D13_PF5,
 980};
 981
 982static const unsigned ld14_pins[] = {
 983        TEGRA_PIN_LCD_D14_PF6,
 984};
 985
 986static const unsigned ld15_pins[] = {
 987        TEGRA_PIN_LCD_D15_PF7,
 988};
 989
 990static const unsigned ld16_pins[] = {
 991        TEGRA_PIN_LCD_D16_PM0,
 992};
 993
 994static const unsigned ld17_pins[] = {
 995        TEGRA_PIN_LCD_D17_PM1,
 996};
 997
 998static const unsigned ldc_pins[] = {
 999        TEGRA_PIN_LCD_DC0_PN6,
1000};

1001
1002static const unsigned ldi_pins[] = {
1003        TEGRA_PIN_LCD_D22_PM6,
1004};
1005
1006static const unsigned lhp0_pins[] = {
1007        TEGRA_PIN_LCD_D21_PM5,
1008};
1009
1010static const unsigned lhp1_pins[] = {
1011        TEGRA_PIN_LCD_D18_PM2,
1012};
1013
1014static const unsigned lhp2_pins[] = {
1015        TEGRA_PIN_LCD_D19_PM3,
1016};
1017
1018static const unsigned lhs_pins[] = {
1019        TEGRA_PIN_LCD_HSYNC_PJ3,
1020};
1021
1022static const unsigned lm0_pins[] = {
1023        TEGRA_PIN_LCD_CS1_N_PW0,
1024};
1025
1026static const unsigned lm1_pins[] = {
1027        TEGRA_PIN_LCD_M1_PW1,
1028};
1029
1030static const unsigned lpp_pins[] = {
1031        TEGRA_PIN_LCD_D23_PM7,
1032};
1033
1034static const unsigned lpw0_pins[] = {
1035        TEGRA_PIN_LCD_PWR0_PB2,
1036};
1037
1038static const unsigned lpw1_pins[] = {
1039        TEGRA_PIN_LCD_PWR1_PC1,
1040};
1041
1042static const unsigned lpw2_pins[] = {
1043        TEGRA_PIN_LCD_PWR2_PC6,
1044};
1045
1046static const unsigned lsc0_pins[] = {
1047        TEGRA_PIN_LCD_PCLK_PB3,
1048};
1049
1050static const unsigned lsc1_pins[] = {
1051        TEGRA_PIN_LCD_WR_N_PZ3,
1052};
1053
1054static const unsigned lsck_pins[] = {
1055        TEGRA_PIN_LCD_SCK_PZ4,
1056};
1057
1058static const unsigned lsda_pins[] = {
1059        TEGRA_PIN_LCD_SDOUT_PN5,
1060};
1061
1062static const unsigned lsdi_pins[] = {
1063        TEGRA_PIN_LCD_SDIN_PZ2,
1064};
1065
1066static const unsigned lspi_pins[] = {
1067        TEGRA_PIN_LCD_DE_PJ1,
1068};
1069
1070static const unsigned lvp0_pins[] = {
1071        TEGRA_PIN_LCD_DC1_PV7,
1072};
1073
1074static const unsigned lvp1_pins[] = {
1075        TEGRA_PIN_LCD_D20_PM4,
1076};
1077
1078static const unsigned lvs_pins[] = {
1079        TEGRA_PIN_LCD_VSYNC_PJ4,
1080};
1081
1082static const unsigned ls_pins[] = {
1083        TEGRA_PIN_LCD_PWR0_PB2,
1084        TEGRA_PIN_LCD_PWR1_PC1,
1085        TEGRA_PIN_LCD_PWR2_PC6,
1086        TEGRA_PIN_LCD_SDIN_PZ2,
1087        TEGRA_PIN_LCD_SDOUT_PN5,
1088        TEGRA_PIN_LCD_WR_N_PZ3,
1089        TEGRA_PIN_LCD_CS0_N_PN4,
1090        TEGRA_PIN_LCD_DC0_PN6,
1091        TEGRA_PIN_LCD_SCK_PZ4,
1092};
1093
1094static const unsigned lc_pins[] = {
1095        TEGRA_PIN_LCD_PCLK_PB3,
1096        TEGRA_PIN_LCD_DE_PJ1,
1097        TEGRA_PIN_LCD_HSYNC_PJ3,
1098        TEGRA_PIN_LCD_VSYNC_PJ4,
1099        TEGRA_PIN_LCD_CS1_N_PW0,
1100        TEGRA_PIN_LCD_M1_PW1,
1101        TEGRA_PIN_LCD_DC1_PV7,
1102        TEGRA_PIN_HDMI_INT_N_PN7,
1103};
1104
1105static const unsigned ld17_0_pins[] = {
1106        TEGRA_PIN_LCD_D0_PE0,
1107        TEGRA_PIN_LCD_D1_PE1,
1108        TEGRA_PIN_LCD_D2_PE2,
1109        TEGRA_PIN_LCD_D3_PE3,
1110        TEGRA_PIN_LCD_D4_PE4,
1111        TEGRA_PIN_LCD_D5_PE5,
1112        TEGRA_PIN_LCD_D6_PE6,
1113        TEGRA_PIN_LCD_D7_PE7,
1114        TEGRA_PIN_LCD_D8_PF0,
1115        TEGRA_PIN_LCD_D9_PF1,
1116        TEGRA_PIN_LCD_D10_PF2,
1117        TEGRA_PIN_LCD_D11_PF3,
1118        TEGRA_PIN_LCD_D12_PF4,
1119        TEGRA_PIN_LCD_D13_PF5,
1120        TEGRA_PIN_LCD_D14_PF6,
1121        TEGRA_PIN_LCD_D15_PF7,
1122        TEGRA_PIN_LCD_D16_PM0,
1123        TEGRA_PIN_LCD_D17_PM1,
1124};
1125
1126static const unsigned ld19_18_pins[] = {
1127        TEGRA_PIN_LCD_D18_PM2,
1128        TEGRA_PIN_LCD_D19_PM3,
1129};
1130
1131static const unsigned ld21_20_pins[] = {
1132        TEGRA_PIN_LCD_D20_PM4,
1133        TEGRA_PIN_LCD_D21_PM5,
1134};
1135
1136static const unsigned ld23_22_pins[] = {
1137        TEGRA_PIN_LCD_D22_PM6,
1138        TEGRA_PIN_LCD_D23_PM7,
1139};
1140
1141static const unsigned owc_pins[] = {
1142        TEGRA_PIN_OWC,
1143};
1144
1145static const unsigned pmc_pins[] = {
1146        TEGRA_PIN_LED_BLINK_PBB0,
1147        TEGRA_PIN_SYS_CLK_REQ_PZ5,
1148        TEGRA_PIN_CORE_PWR_REQ,
1149        TEGRA_PIN_CPU_PWR_REQ,
1150        TEGRA_PIN_PWR_INT_N,
1151};
1152
1153static const unsigned pta_pins[] = {
1154        TEGRA_PIN_GEN2_I2C_SCL_PT5,
1155        TEGRA_PIN_GEN2_I2C_SDA_PT6,
1156};
1157
1158static const unsigned rm_pins[] = {
1159        TEGRA_PIN_GEN1_I2C_SCL_PC4,
1160        TEGRA_PIN_GEN1_I2C_SDA_PC5,
1161};
1162
1163static const unsigned sdb_pins[] = {
1164        TEGRA_PIN_SDIO3_CMD_PA7,
1165};
1166
1167static const unsigned sdc_pins[] = {
1168        TEGRA_PIN_SDIO3_DAT0_PB7,
1169        TEGRA_PIN_SDIO3_DAT1_PB6,
1170        TEGRA_PIN_SDIO3_DAT2_PB5,
1171        TEGRA_PIN_SDIO3_DAT3_PB4,
1172};
1173
1174static const unsigned sdd_pins[] = {
1175        TEGRA_PIN_SDIO3_CLK_PA6,
1176};
1177
1178static const unsigned sdio1_pins[] = {
1179        TEGRA_PIN_SDIO1_CLK_PZ0,
1180        TEGRA_PIN_SDIO1_CMD_PZ1,
1181        TEGRA_PIN_SDIO1_DAT0_PY7,
1182        TEGRA_PIN_SDIO1_DAT1_PY6,
1183        TEGRA_PIN_SDIO1_DAT2_PY5,
1184        TEGRA_PIN_SDIO1_DAT3_PY4,
1185};
1186
1187static const unsigned slxa_pins[] = {
1188        TEGRA_PIN_SDIO3_DAT4_PD1,
1189};
1190
1191static const unsigned slxc_pins[] = {
1192        TEGRA_PIN_SDIO3_DAT6_PD3,
1193};
1194
1195static const unsigned slxd_pins[] = {
1196        TEGRA_PIN_SDIO3_DAT7_PD4,
1197};
1198
1199static const unsigned slxk_pins[] = {
1200        TEGRA_PIN_SDIO3_DAT5_PD0,
1201};
1202
1203static const unsigned spdi_pins[] = {
1204        TEGRA_PIN_SPDIF_IN_PK6,
1205};
1206
1207static const unsigned spdo_pins[] = {
1208        TEGRA_PIN_SPDIF_OUT_PK5,
1209};
1210
1211static const unsigned spia_pins[] = {
1212        TEGRA_PIN_SPI2_MOSI_PX0,
1213};
1214
1215static const unsigned spib_pins[] = {
1216        TEGRA_PIN_SPI2_MISO_PX1,
1217};
1218
1219static const unsigned spic_pins[] = {
1220        TEGRA_PIN_SPI2_CS0_N_PX3,
1221        TEGRA_PIN_SPI2_SCK_PX2,
1222};
1223
1224static const unsigned spid_pins[] = {
1225        TEGRA_PIN_SPI1_MOSI_PX4,
1226};
1227
1228static const unsigned spie_pins[] = {
1229        TEGRA_PIN_SPI1_CS0_N_PX6,
1230        TEGRA_PIN_SPI1_SCK_PX5,
1231};
1232
1233static const unsigned spif_pins[] = {
1234        TEGRA_PIN_SPI1_MISO_PX7,
1235};
1236
1237static const unsigned spig_pins[] = {
1238        TEGRA_PIN_SPI2_CS1_N_PW2,
1239};
1240
1241static const unsigned spih_pins[] = {
1242        TEGRA_PIN_SPI2_CS2_N_PW3,
1243};
1244
1245static const unsigned uaa_pins[] = {
1246        TEGRA_PIN_ULPI_DATA0_PO1,
1247        TEGRA_PIN_ULPI_DATA1_PO2,
1248        TEGRA_PIN_ULPI_DATA2_PO3,
1249        TEGRA_PIN_ULPI_DATA3_PO4,
1250};
1251
1252static const unsigned uab_pins[] = {
1253        TEGRA_PIN_ULPI_DATA4_PO5,
1254        TEGRA_PIN_ULPI_DATA5_PO6,
1255        TEGRA_PIN_ULPI_DATA6_PO7,
1256        TEGRA_PIN_ULPI_DATA7_PO0,
1257};
1258
1259static const unsigned uac_pins[] = {
1260        TEGRA_PIN_PV0,
1261        TEGRA_PIN_PV1,
1262        TEGRA_PIN_PV2,
1263        TEGRA_PIN_PV3,
1264};
1265
1266static const unsigned ck32_pins[] = {
1267        TEGRA_PIN_CLK_32_K_IN,
1268};
1269
1270static const unsigned uad_pins[] = {
1271        TEGRA_PIN_UART2_RXD_PC3,
1272        TEGRA_PIN_UART2_TXD_PC2,
1273};
1274
1275static const unsigned uca_pins[] = {
1276        TEGRA_PIN_UART3_RXD_PW7,
1277        TEGRA_PIN_UART3_TXD_PW6,
1278};
1279
1280static const unsigned ucb_pins[] = {
1281        TEGRA_PIN_UART3_CTS_N_PA1,
1282        TEGRA_PIN_UART3_RTS_N_PC0,
1283};
1284
1285static const unsigned uda_pins[] = {
1286        TEGRA_PIN_ULPI_CLK_PY0,
1287        TEGRA_PIN_ULPI_DIR_PY1,
1288        TEGRA_PIN_ULPI_NXT_PY2,
1289        TEGRA_PIN_ULPI_STP_PY3,
1290};
1291
1292static const unsigned ddrc_pins[] = {
1293        TEGRA_PIN_DDR_COMP_PD,
1294        TEGRA_PIN_DDR_COMP_PU,
1295};
1296
1297static const unsigned pmca_pins[] = {
1298        TEGRA_PIN_LED_BLINK_PBB0,
1299};
1300
1301static const unsigned pmcb_pins[] = {
1302        TEGRA_PIN_SYS_CLK_REQ_PZ5,
1303};
1304
1305static const unsigned pmcc_pins[] = {
1306        TEGRA_PIN_CORE_PWR_REQ,
1307};
1308
1309static const unsigned pmcd_pins[] = {
1310        TEGRA_PIN_CPU_PWR_REQ,
1311};
1312
1313static const unsigned pmce_pins[] = {
1314        TEGRA_PIN_PWR_INT_N,
1315};
1316
1317static const unsigned xm2c_pins[] = {
1318        TEGRA_PIN_DDR_A0,
1319        TEGRA_PIN_DDR_A1,
1320        TEGRA_PIN_DDR_A2,
1321        TEGRA_PIN_DDR_A3,
1322        TEGRA_PIN_DDR_A4,
1323        TEGRA_PIN_DDR_A5,
1324        TEGRA_PIN_DDR_A6,
1325        TEGRA_PIN_DDR_A7,
1326        TEGRA_PIN_DDR_A8,
1327        TEGRA_PIN_DDR_A9,
1328        TEGRA_PIN_DDR_A10,
1329        TEGRA_PIN_DDR_A11,
1330        TEGRA_PIN_DDR_A12,
1331        TEGRA_PIN_DDR_A13,
1332        TEGRA_PIN_DDR_A14,
1333        TEGRA_PIN_DDR_CAS_N,
1334        TEGRA_PIN_DDR_BA0,
1335        TEGRA_PIN_DDR_BA1,
1336        TEGRA_PIN_DDR_BA2,
1337        TEGRA_PIN_DDR_DQS0P,
1338        TEGRA_PIN_DDR_DQS0N,
1339        TEGRA_PIN_DDR_DQS1P,
1340        TEGRA_PIN_DDR_DQS1N,
1341        TEGRA_PIN_DDR_DQS2P,
1342        TEGRA_PIN_DDR_DQS2N,
1343        TEGRA_PIN_DDR_DQS3P,
1344        TEGRA_PIN_DDR_DQS3N,
1345        TEGRA_PIN_DDR_CS0_N,
1346        TEGRA_PIN_DDR_CS1_N,
1347        TEGRA_PIN_DDR_CKE0,
1348        TEGRA_PIN_DDR_CKE1,
1349        TEGRA_PIN_DDR_CLK,
1350        TEGRA_PIN_DDR_CLK_N,
1351        TEGRA_PIN_DDR_DM0,
1352        TEGRA_PIN_DDR_DM1,
1353        TEGRA_PIN_DDR_DM2,
1354        TEGRA_PIN_DDR_DM3,
1355        TEGRA_PIN_DDR_ODT,
1356        TEGRA_PIN_DDR_RAS_N,
1357        TEGRA_PIN_DDR_WE_N,
1358        TEGRA_PIN_DDR_QUSE0,
1359        TEGRA_PIN_DDR_QUSE1,
1360        TEGRA_PIN_DDR_QUSE2,
1361        TEGRA_PIN_DDR_QUSE3,
1362};
1363
1364static const unsigned xm2d_pins[] = {
1365        TEGRA_PIN_DDR_DQ0,
1366        TEGRA_PIN_DDR_DQ1,
1367        TEGRA_PIN_DDR_DQ2,
1368        TEGRA_PIN_DDR_DQ3,
1369        TEGRA_PIN_DDR_DQ4,
1370        TEGRA_PIN_DDR_DQ5,
1371        TEGRA_PIN_DDR_DQ6,
1372        TEGRA_PIN_DDR_DQ7,
1373        TEGRA_PIN_DDR_DQ8,
1374        TEGRA_PIN_DDR_DQ9,
1375        TEGRA_PIN_DDR_DQ10,
1376        TEGRA_PIN_DDR_DQ11,
1377        TEGRA_PIN_DDR_DQ12,
1378        TEGRA_PIN_DDR_DQ13,
1379        TEGRA_PIN_DDR_DQ14,
1380        TEGRA_PIN_DDR_DQ15,
1381        TEGRA_PIN_DDR_DQ16,
1382        TEGRA_PIN_DDR_DQ17,
1383        TEGRA_PIN_DDR_DQ18,
1384        TEGRA_PIN_DDR_DQ19,
1385        TEGRA_PIN_DDR_DQ20,
1386        TEGRA_PIN_DDR_DQ21,
1387        TEGRA_PIN_DDR_DQ22,
1388        TEGRA_PIN_DDR_DQ23,
1389        TEGRA_PIN_DDR_DQ24,
1390        TEGRA_PIN_DDR_DQ25,
1391        TEGRA_PIN_DDR_DQ26,
1392        TEGRA_PIN_DDR_DQ27,
1393        TEGRA_PIN_DDR_DQ28,
1394        TEGRA_PIN_DDR_DQ29,
1395        TEGRA_PIN_DDR_DQ30,
1396        TEGRA_PIN_DDR_DQ31,
1397};
1398
1399static const unsigned drive_ao1_pins[] = {
1400        TEGRA_PIN_SYS_RESET,
1401        TEGRA_PIN_PWR_I2C_SCL_PZ6,
1402        TEGRA_PIN_PWR_I2C_SDA_PZ7,
1403        TEGRA_PIN_KB_ROW0_PR0,
1404        TEGRA_PIN_KB_ROW1_PR1,
1405        TEGRA_PIN_KB_ROW2_PR2,
1406        TEGRA_PIN_KB_ROW3_PR3,
1407        TEGRA_PIN_KB_ROW4_PR4,
1408        TEGRA_PIN_KB_ROW5_PR5,
1409        TEGRA_PIN_KB_ROW6_PR6,
1410        TEGRA_PIN_KB_ROW7_PR7,
1411};
1412
1413static const unsigned drive_ao2_pins[] = {
1414        TEGRA_PIN_KB_ROW8_PS0,
1415        TEGRA_PIN_KB_ROW9_PS1,
1416        TEGRA_PIN_KB_ROW10_PS2,
1417        TEGRA_PIN_KB_ROW11_PS3,
1418        TEGRA_PIN_KB_ROW12_PS4,
1419        TEGRA_PIN_KB_ROW13_PS5,
1420        TEGRA_PIN_KB_ROW14_PS6,
1421        TEGRA_PIN_KB_ROW15_PS7,
1422        TEGRA_PIN_KB_COL0_PQ0,
1423        TEGRA_PIN_KB_COL1_PQ1,
1424        TEGRA_PIN_KB_COL2_PQ2,
1425        TEGRA_PIN_KB_COL3_PQ3,
1426        TEGRA_PIN_KB_COL4_PQ4,
1427        TEGRA_PIN_KB_COL5_PQ5,
1428        TEGRA_PIN_KB_COL6_PQ6,
1429        TEGRA_PIN_KB_COL7_PQ7,
1430        TEGRA_PIN_LED_BLINK_PBB0,
1431        TEGRA_PIN_SYS_CLK_REQ_PZ5,
1432        TEGRA_PIN_CORE_PWR_REQ,
1433        TEGRA_PIN_CPU_PWR_REQ,
1434        TEGRA_PIN_PWR_INT_N,
1435        TEGRA_PIN_CLK_32_K_IN,
1436};
1437
1438static const unsigned drive_at1_pins[] = {
1439        TEGRA_PIN_GMI_IORDY_PI5,
1440        TEGRA_PIN_GMI_AD8_PH0,
1441        TEGRA_PIN_GMI_AD9_PH1,
1442        TEGRA_PIN_GMI_AD10_PH2,
1443        TEGRA_PIN_GMI_AD11_PH3,
1444        TEGRA_PIN_GMI_AD12_PH4,
1445        TEGRA_PIN_GMI_AD13_PH5,
1446        TEGRA_PIN_GMI_AD14_PH6,
1447        TEGRA_PIN_GMI_AD15_PH7,
1448        TEGRA_PIN_GMI_CS7_N_PI6,
1449        TEGRA_PIN_GMI_DPD_PT7,
1450        TEGRA_PIN_GEN2_I2C_SCL_PT5,
1451        TEGRA_PIN_GEN2_I2C_SDA_PT6,
1452};
1453
1454static const unsigned drive_at2_pins[] = {
1455        TEGRA_PIN_GMI_WAIT_PI7,
1456        TEGRA_PIN_GMI_ADV_N_PK0,
1457        TEGRA_PIN_GMI_CLK_PK1,
1458        TEGRA_PIN_GMI_CS6_N_PI3,
1459        TEGRA_PIN_GMI_CS5_N_PI2,
1460        TEGRA_PIN_GMI_CS4_N_PK2,
1461        TEGRA_PIN_GMI_CS3_N_PK4,
1462        TEGRA_PIN_GMI_CS2_N_PK3,
1463        TEGRA_PIN_GMI_AD0_PG0,
1464        TEGRA_PIN_GMI_AD1_PG1,
1465        TEGRA_PIN_GMI_AD2_PG2,
1466        TEGRA_PIN_GMI_AD3_PG3,
1467        TEGRA_PIN_GMI_AD4_PG4,
1468        TEGRA_PIN_GMI_AD5_PG5,
1469        TEGRA_PIN_GMI_AD6_PG6,
1470        TEGRA_PIN_GMI_AD7_PG7,
1471        TEGRA_PIN_GMI_HIOW_N_PI0,
1472        TEGRA_PIN_GMI_HIOR_N_PI1,
1473        TEGRA_PIN_GMI_RST_N_PI4,
1474};
1475
1476static const unsigned drive_cdev1_pins[] = {
1477        TEGRA_PIN_DAP_MCLK1_PW4,
1478};
1479
1480static const unsigned drive_cdev2_pins[] = {
1481        TEGRA_PIN_DAP_MCLK2_PW5,
1482};
1483
1484static const unsigned drive_csus_pins[] = {
1485        TEGRA_PIN_VI_MCLK_PT1,
1486};
1487
1488static const unsigned drive_dap1_pins[] = {
1489        TEGRA_PIN_DAP1_FS_PN0,
1490        TEGRA_PIN_DAP1_DIN_PN1,
1491        TEGRA_PIN_DAP1_DOUT_PN2,
1492        TEGRA_PIN_DAP1_SCLK_PN3,
1493        TEGRA_PIN_SPDIF_OUT_PK5,
1494        TEGRA_PIN_SPDIF_IN_PK6,
1495};
1496
1497static const unsigned drive_dap2_pins[] = {
1498        TEGRA_PIN_DAP2_FS_PA2,
1499        TEGRA_PIN_DAP2_SCLK_PA3,
1500        TEGRA_PIN_DAP2_DIN_PA4,
1501        TEGRA_PIN_DAP2_DOUT_PA5,
1502};
1503
1504static const unsigned drive_dap3_pins[] = {
1505        TEGRA_PIN_DAP3_FS_PP0,
1506        TEGRA_PIN_DAP3_DIN_PP1,
1507        TEGRA_PIN_DAP3_DOUT_PP2,
1508        TEGRA_PIN_DAP3_SCLK_PP3,
1509};
1510
1511static const unsigned drive_dap4_pins[] = {
1512        TEGRA_PIN_DAP4_FS_PP4,
1513        TEGRA_PIN_DAP4_DIN_PP5,
1514        TEGRA_PIN_DAP4_DOUT_PP6,
1515        TEGRA_PIN_DAP4_SCLK_PP7,
1516};
1517
1518static const unsigned drive_dbg_pins[] = {
1519        TEGRA_PIN_PU0,
1520        TEGRA_PIN_PU1,
1521        TEGRA_PIN_PU2,
1522        TEGRA_PIN_PU3,
1523        TEGRA_PIN_PU4,
1524        TEGRA_PIN_PU5,
1525        TEGRA_PIN_PU6,
1526        TEGRA_PIN_JTAG_RTCK_PU7,
1527        TEGRA_PIN_GEN1_I2C_SDA_PC5,
1528        TEGRA_PIN_GEN1_I2C_SCL_PC4,
1529        TEGRA_PIN_JTAG_TRST_N,
1530        TEGRA_PIN_JTAG_TDO,
1531        TEGRA_PIN_JTAG_TMS,
1532        TEGRA_PIN_JTAG_TCK,
1533        TEGRA_PIN_JTAG_TDI,
1534        TEGRA_PIN_TEST_MODE_EN,
1535};
1536
1537static const unsigned drive_lcd1_pins[] = {
1538        TEGRA_PIN_LCD_PWR1_PC1,
1539        TEGRA_PIN_LCD_PWR2_PC6,
1540        TEGRA_PIN_LCD_SDIN_PZ2,
1541        TEGRA_PIN_LCD_SDOUT_PN5,
1542        TEGRA_PIN_LCD_WR_N_PZ3,
1543        TEGRA_PIN_LCD_CS0_N_PN4,
1544        TEGRA_PIN_LCD_DC0_PN6,
1545        TEGRA_PIN_LCD_SCK_PZ4,
1546};
1547
1548static const unsigned drive_lcd2_pins[] = {
1549        TEGRA_PIN_LCD_PWR0_PB2,
1550        TEGRA_PIN_LCD_PCLK_PB3,
1551        TEGRA_PIN_LCD_DE_PJ1,
1552        TEGRA_PIN_LCD_HSYNC_PJ3,
1553        TEGRA_PIN_LCD_VSYNC_PJ4,
1554        TEGRA_PIN_LCD_D0_PE0,
1555        TEGRA_PIN_LCD_D1_PE1,
1556        TEGRA_PIN_LCD_D2_PE2,
1557        TEGRA_PIN_LCD_D3_PE3,
1558        TEGRA_PIN_LCD_D4_PE4,
1559        TEGRA_PIN_LCD_D5_PE5,
1560        TEGRA_PIN_LCD_D6_PE6,
1561        TEGRA_PIN_LCD_D7_PE7,
1562        TEGRA_PIN_LCD_D8_PF0,
1563        TEGRA_PIN_LCD_D9_PF1,
1564        TEGRA_PIN_LCD_D10_PF2,
1565        TEGRA_PIN_LCD_D11_PF3,
1566        TEGRA_PIN_LCD_D12_PF4,
1567        TEGRA_PIN_LCD_D13_PF5,
1568        TEGRA_PIN_LCD_D14_PF6,
1569        TEGRA_PIN_LCD_D15_PF7,
1570        TEGRA_PIN_LCD_D16_PM0,
1571        TEGRA_PIN_LCD_D17_PM1,
1572        TEGRA_PIN_LCD_D18_PM2,
1573        TEGRA_PIN_LCD_D19_PM3,
1574        TEGRA_PIN_LCD_D20_PM4,
1575        TEGRA_PIN_LCD_D21_PM5,
1576        TEGRA_PIN_LCD_D22_PM6,
1577        TEGRA_PIN_LCD_D23_PM7,
1578        TEGRA_PIN_LCD_CS1_N_PW0,
1579        TEGRA_PIN_LCD_M1_PW1,
1580        TEGRA_PIN_LCD_DC1_PV7,
1581        TEGRA_PIN_HDMI_INT_N_PN7,
1582};
1583
1584static const unsigned drive_sdmmc2_pins[] = {
1585        TEGRA_PIN_SDIO3_DAT4_PD1,
1586        TEGRA_PIN_SDIO3_DAT5_PD0,
1587        TEGRA_PIN_SDIO3_DAT6_PD3,
1588        TEGRA_PIN_SDIO3_DAT7_PD4,
1589};
1590
1591static const unsigned drive_sdmmc3_pins[] = {
1592        TEGRA_PIN_SDIO3_CLK_PA6,
1593        TEGRA_PIN_SDIO3_CMD_PA7,
1594        TEGRA_PIN_SDIO3_DAT0_PB7,
1595        TEGRA_PIN_SDIO3_DAT1_PB6,
1596        TEGRA_PIN_SDIO3_DAT2_PB5,
1597        TEGRA_PIN_SDIO3_DAT3_PB4,
1598        TEGRA_PIN_PV4,
1599        TEGRA_PIN_PV5,
1600        TEGRA_PIN_PV6,
1601};
1602
1603static const unsigned drive_spi_pins[] = {
1604        TEGRA_PIN_SPI2_MOSI_PX0,
1605        TEGRA_PIN_SPI2_MISO_PX1,
1606        TEGRA_PIN_SPI2_SCK_PX2,
1607        TEGRA_PIN_SPI2_CS0_N_PX3,
1608        TEGRA_PIN_SPI1_MOSI_PX4,
1609        TEGRA_PIN_SPI1_SCK_PX5,
1610        TEGRA_PIN_SPI1_CS0_N_PX6,
1611        TEGRA_PIN_SPI1_MISO_PX7,
1612        TEGRA_PIN_SPI2_CS1_N_PW2,
1613        TEGRA_PIN_SPI2_CS2_N_PW3,
1614};
1615
1616static const unsigned drive_uaa_pins[] = {
1617        TEGRA_PIN_ULPI_DATA0_PO1,
1618        TEGRA_PIN_ULPI_DATA1_PO2,
1619        TEGRA_PIN_ULPI_DATA2_PO3,
1620        TEGRA_PIN_ULPI_DATA3_PO4,
1621};
1622
1623static const unsigned drive_uab_pins[] = {
1624        TEGRA_PIN_ULPI_DATA4_PO5,
1625        TEGRA_PIN_ULPI_DATA5_PO6,
1626        TEGRA_PIN_ULPI_DATA6_PO7,
1627        TEGRA_PIN_ULPI_DATA7_PO0,
1628        TEGRA_PIN_PV0,
1629        TEGRA_PIN_PV1,
1630        TEGRA_PIN_PV2,
1631        TEGRA_PIN_PV3,
1632};
1633
1634static const unsigned drive_uart2_pins[] = {
1635        TEGRA_PIN_UART2_TXD_PC2,
1636        TEGRA_PIN_UART2_RXD_PC3,
1637        TEGRA_PIN_UART2_RTS_N_PJ6,
1638        TEGRA_PIN_UART2_CTS_N_PJ5,
1639};
1640
1641static const unsigned drive_uart3_pins[] = {
1642        TEGRA_PIN_UART3_TXD_PW6,
1643        TEGRA_PIN_UART3_RXD_PW7,
1644        TEGRA_PIN_UART3_RTS_N_PC0,
1645        TEGRA_PIN_UART3_CTS_N_PA1,
1646};
1647
1648static const unsigned drive_vi1_pins[] = {
1649        TEGRA_PIN_VI_D0_PT4,
1650        TEGRA_PIN_VI_D1_PD5,
1651        TEGRA_PIN_VI_D2_PL0,
1652        TEGRA_PIN_VI_D3_PL1,
1653        TEGRA_PIN_VI_D4_PL2,
1654        TEGRA_PIN_VI_D5_PL3,
1655        TEGRA_PIN_VI_D6_PL4,
1656        TEGRA_PIN_VI_D7_PL5,
1657        TEGRA_PIN_VI_D8_PL6,
1658        TEGRA_PIN_VI_D9_PL7,
1659        TEGRA_PIN_VI_D10_PT2,
1660        TEGRA_PIN_VI_D11_PT3,
1661        TEGRA_PIN_VI_PCLK_PT0,
1662        TEGRA_PIN_VI_VSYNC_PD6,
1663        TEGRA_PIN_VI_HSYNC_PD7,
1664};
1665
1666static const unsigned drive_vi2_pins[] = {
1667        TEGRA_PIN_VI_GP0_PBB1,
1668        TEGRA_PIN_CAM_I2C_SCL_PBB2,
1669        TEGRA_PIN_CAM_I2C_SDA_PBB3,
1670        TEGRA_PIN_VI_GP3_PBB4,
1671        TEGRA_PIN_VI_GP4_PBB5,
1672        TEGRA_PIN_VI_GP5_PD2,
1673        TEGRA_PIN_VI_GP6_PA0,
1674};
1675
1676static const unsigned drive_xm2a_pins[] = {
1677        TEGRA_PIN_DDR_A0,
1678        TEGRA_PIN_DDR_A1,
1679        TEGRA_PIN_DDR_A2,
1680        TEGRA_PIN_DDR_A3,
1681        TEGRA_PIN_DDR_A4,
1682        TEGRA_PIN_DDR_A5,
1683        TEGRA_PIN_DDR_A6,
1684        TEGRA_PIN_DDR_A7,
1685        TEGRA_PIN_DDR_A8,
1686        TEGRA_PIN_DDR_A9,
1687        TEGRA_PIN_DDR_A10,
1688        TEGRA_PIN_DDR_A11,
1689        TEGRA_PIN_DDR_A12,
1690        TEGRA_PIN_DDR_A13,
1691        TEGRA_PIN_DDR_A14,
1692        TEGRA_PIN_DDR_BA0,
1693        TEGRA_PIN_DDR_BA1,
1694        TEGRA_PIN_DDR_BA2,
1695        TEGRA_PIN_DDR_CS0_N,
1696        TEGRA_PIN_DDR_CS1_N,
1697        TEGRA_PIN_DDR_ODT,
1698        TEGRA_PIN_DDR_RAS_N,
1699        TEGRA_PIN_DDR_CAS_N,
1700        TEGRA_PIN_DDR_WE_N,
1701        TEGRA_PIN_DDR_CKE0,
1702        TEGRA_PIN_DDR_CKE1,
1703};
1704
1705static const unsigned drive_xm2c_pins[] = {
1706        TEGRA_PIN_DDR_DQS0P,
1707        TEGRA_PIN_DDR_DQS0N,
1708        TEGRA_PIN_DDR_DQS1P,
1709        TEGRA_PIN_DDR_DQS1N,
1710        TEGRA_PIN_DDR_DQS2P,
1711        TEGRA_PIN_DDR_DQS2N,
1712        TEGRA_PIN_DDR_DQS3P,
1713        TEGRA_PIN_DDR_DQS3N,
1714        TEGRA_PIN_DDR_QUSE0,
1715        TEGRA_PIN_DDR_QUSE1,
1716        TEGRA_PIN_DDR_QUSE2,
1717        TEGRA_PIN_DDR_QUSE3,
1718};
1719
1720static const unsigned drive_xm2d_pins[] = {
1721        TEGRA_PIN_DDR_DQ0,
1722        TEGRA_PIN_DDR_DQ1,
1723        TEGRA_PIN_DDR_DQ2,
1724        TEGRA_PIN_DDR_DQ3,
1725        TEGRA_PIN_DDR_DQ4,
1726        TEGRA_PIN_DDR_DQ5,
1727        TEGRA_PIN_DDR_DQ6,
1728        TEGRA_PIN_DDR_DQ7,
1729        TEGRA_PIN_DDR_DQ8,
1730        TEGRA_PIN_DDR_DQ9,
1731        TEGRA_PIN_DDR_DQ10,
1732        TEGRA_PIN_DDR_DQ11,
1733        TEGRA_PIN_DDR_DQ12,
1734        TEGRA_PIN_DDR_DQ13,
1735        TEGRA_PIN_DDR_DQ14,
1736        TEGRA_PIN_DDR_DQ15,
1737        TEGRA_PIN_DDR_DQ16,
1738        TEGRA_PIN_DDR_DQ17,
1739        TEGRA_PIN_DDR_DQ18,
1740        TEGRA_PIN_DDR_DQ19,
1741        TEGRA_PIN_DDR_DQ20,
1742        TEGRA_PIN_DDR_DQ21,
1743        TEGRA_PIN_DDR_DQ22,
1744        TEGRA_PIN_DDR_DQ23,
1745        TEGRA_PIN_DDR_DQ24,
1746        TEGRA_PIN_DDR_DQ25,
1747        TEGRA_PIN_DDR_DQ26,
1748        TEGRA_PIN_DDR_DQ27,
1749        TEGRA_PIN_DDR_DQ28,
1750        TEGRA_PIN_DDR_DQ29,
1751        TEGRA_PIN_DDR_DQ30,
1752        TEGRA_PIN_DDR_DQ31,
1753        TEGRA_PIN_DDR_DM0,
1754        TEGRA_PIN_DDR_DM1,
1755        TEGRA_PIN_DDR_DM2,
1756        TEGRA_PIN_DDR_DM3,
1757};
1758
1759static const unsigned drive_xm2clk_pins[] = {
1760        TEGRA_PIN_DDR_CLK,
1761        TEGRA_PIN_DDR_CLK_N,
1762};
1763
1764static const unsigned drive_sdio1_pins[] = {
1765        TEGRA_PIN_SDIO1_CLK_PZ0,
1766        TEGRA_PIN_SDIO1_CMD_PZ1,
1767        TEGRA_PIN_SDIO1_DAT0_PY7,
1768        TEGRA_PIN_SDIO1_DAT1_PY6,
1769        TEGRA_PIN_SDIO1_DAT2_PY5,
1770        TEGRA_PIN_SDIO1_DAT3_PY4,
1771};
1772
1773static const unsigned drive_crt_pins[] = {
1774        TEGRA_PIN_CRT_HSYNC,
1775        TEGRA_PIN_CRT_VSYNC,
1776};
1777
1778static const unsigned drive_ddc_pins[] = {
1779        TEGRA_PIN_DDC_SCL,
1780        TEGRA_PIN_DDC_SDA,
1781};
1782
1783static const unsigned drive_gma_pins[] = {
1784        TEGRA_PIN_GMI_AD20_PAA0,
1785        TEGRA_PIN_GMI_AD21_PAA1,
1786        TEGRA_PIN_GMI_AD22_PAA2,
1787        TEGRA_PIN_GMI_AD23_PAA3,
1788};
1789
1790static const unsigned drive_gmb_pins[] = {
1791        TEGRA_PIN_GMI_WP_N_PC7,
1792};
1793
1794static const unsigned drive_gmc_pins[] = {
1795        TEGRA_PIN_GMI_AD16_PJ7,
1796        TEGRA_PIN_GMI_AD17_PB0,
1797        TEGRA_PIN_GMI_AD18_PB1,
1798        TEGRA_PIN_GMI_AD19_PK7,
1799};
1800
1801static const unsigned drive_gmd_pins[] = {
1802        TEGRA_PIN_GMI_CS0_N_PJ0,
1803        TEGRA_PIN_GMI_CS1_N_PJ2,
1804};
1805
1806static const unsigned drive_gme_pins[] = {
1807        TEGRA_PIN_GMI_AD24_PAA4,
1808        TEGRA_PIN_GMI_AD25_PAA5,
1809        TEGRA_PIN_GMI_AD26_PAA6,
1810        TEGRA_PIN_GMI_AD27_PAA7,
1811};
1812
1813static const unsigned drive_owr_pins[] = {
1814        TEGRA_PIN_OWC,
1815};
1816
1817static const unsigned drive_uda_pins[] = {
1818        TEGRA_PIN_ULPI_CLK_PY0,
1819        TEGRA_PIN_ULPI_DIR_PY1,
1820        TEGRA_PIN_ULPI_NXT_PY2,
1821        TEGRA_PIN_ULPI_STP_PY3,
1822};
1823
1824enum tegra_mux {
1825        TEGRA_MUX_AHB_CLK,
1826        TEGRA_MUX_APB_CLK,
1827        TEGRA_MUX_AUDIO_SYNC,
1828        TEGRA_MUX_CRT,
1829        TEGRA_MUX_DAP1,
1830        TEGRA_MUX_DAP2,
1831        TEGRA_MUX_DAP3,
1832        TEGRA_MUX_DAP4,
1833        TEGRA_MUX_DAP5,
1834        TEGRA_MUX_DISPLAYA,
1835        TEGRA_MUX_DISPLAYB,
1836        TEGRA_MUX_EMC_TEST0_DLL,
1837        TEGRA_MUX_EMC_TEST1_DLL,
1838        TEGRA_MUX_GMI,
1839        TEGRA_MUX_GMI_INT,
1840        TEGRA_MUX_HDMI,
1841        TEGRA_MUX_I2CP,
1842        TEGRA_MUX_I2C1,
1843        TEGRA_MUX_I2C2,
1844        TEGRA_MUX_I2C3,
1845        TEGRA_MUX_IDE,
1846        TEGRA_MUX_IRDA,
1847        TEGRA_MUX_KBC,
1848        TEGRA_MUX_MIO,
1849        TEGRA_MUX_MIPI_HS,
1850        TEGRA_MUX_NAND,
1851        TEGRA_MUX_OSC,
1852        TEGRA_MUX_OWR,
1853        TEGRA_MUX_PCIE,
1854        TEGRA_MUX_PLLA_OUT,
1855        TEGRA_MUX_PLLC_OUT1,
1856        TEGRA_MUX_PLLM_OUT1,
1857        TEGRA_MUX_PLLP_OUT2,
1858        TEGRA_MUX_PLLP_OUT3,
1859        TEGRA_MUX_PLLP_OUT4,
1860        TEGRA_MUX_PWM,
1861        TEGRA_MUX_PWR_INTR,
1862        TEGRA_MUX_PWR_ON,
1863        TEGRA_MUX_RSVD1,
1864        TEGRA_MUX_RSVD2,
1865        TEGRA_MUX_RSVD3,
1866        TEGRA_MUX_RSVD4,
1867        TEGRA_MUX_RTCK,
1868        TEGRA_MUX_SDIO1,
1869        TEGRA_MUX_SDIO2,
1870        TEGRA_MUX_SDIO3,
1871        TEGRA_MUX_SDIO4,
1872        TEGRA_MUX_SFLASH,
1873        TEGRA_MUX_SPDIF,
1874        TEGRA_MUX_SPI1,
1875        TEGRA_MUX_SPI2,
1876        TEGRA_MUX_SPI2_ALT,
1877        TEGRA_MUX_SPI3,
1878        TEGRA_MUX_SPI4,
1879        TEGRA_MUX_TRACE,
1880        TEGRA_MUX_TWC,
1881        TEGRA_MUX_UARTA,
1882        TEGRA_MUX_UARTB,
1883        TEGRA_MUX_UARTC,
1884        TEGRA_MUX_UARTD,
1885        TEGRA_MUX_UARTE,
1886        TEGRA_MUX_ULPI,
1887        TEGRA_MUX_VI,
1888        TEGRA_MUX_VI_SENSOR_CLK,
1889        TEGRA_MUX_XIO,
1890};
1891
1892#define FUNCTION(fname)                                 \
1893        {                                               \
1894                .name = #fname,                         \
1895        }
1896
1897static struct tegra_function tegra20_functions[] = {
1898        FUNCTION(ahb_clk),
1899        FUNCTION(apb_clk),
1900        FUNCTION(audio_sync),
1901        FUNCTION(crt),
1902        FUNCTION(dap1),
1903        FUNCTION(dap2),
1904        FUNCTION(dap3),
1905        FUNCTION(dap4),
1906        FUNCTION(dap5),
1907        FUNCTION(displaya),
1908        FUNCTION(displayb),
1909        FUNCTION(emc_test0_dll),
1910        FUNCTION(emc_test1_dll),
1911        FUNCTION(gmi),
1912        FUNCTION(gmi_int),
1913        FUNCTION(hdmi),
1914        FUNCTION(i2cp),
1915        FUNCTION(i2c1),
1916        FUNCTION(i2c2),
1917        FUNCTION(i2c3),
1918        FUNCTION(ide),
1919        FUNCTION(irda),
1920        FUNCTION(kbc),
1921        FUNCTION(mio),
1922        FUNCTION(mipi_hs),
1923        FUNCTION(nand),
1924        FUNCTION(osc),
1925        FUNCTION(owr),
1926        FUNCTION(pcie),
1927        FUNCTION(plla_out),
1928        FUNCTION(pllc_out1),
1929        FUNCTION(pllm_out1),
1930        FUNCTION(pllp_out2),
1931        FUNCTION(pllp_out3),
1932        FUNCTION(pllp_out4),
1933        FUNCTION(pwm),
1934        FUNCTION(pwr_intr),
1935        FUNCTION(pwr_on),
1936        FUNCTION(rsvd1),
1937        FUNCTION(rsvd2),
1938        FUNCTION(rsvd3),
1939        FUNCTION(rsvd4),
1940        FUNCTION(rtck),
1941        FUNCTION(sdio1),
1942        FUNCTION(sdio2),
1943        FUNCTION(sdio3),
1944        FUNCTION(sdio4),
1945        FUNCTION(sflash),
1946        FUNCTION(spdif),
1947        FUNCTION(spi1),
1948        FUNCTION(spi2),
1949        FUNCTION(spi2_alt),
1950        FUNCTION(spi3),
1951        FUNCTION(spi4),
1952        FUNCTION(trace),
1953        FUNCTION(twc),
1954        FUNCTION(uarta),
1955        FUNCTION(uartb),
1956        FUNCTION(uartc),
1957        FUNCTION(uartd),
1958        FUNCTION(uarte),
1959        FUNCTION(ulpi),
1960        FUNCTION(vi),
1961        FUNCTION(vi_sensor_clk),
1962        FUNCTION(xio),
1963};
1964
1965#define TRISTATE_REG_A          0x14
1966#define PIN_MUX_CTL_REG_A       0x80
1967#define PULLUPDOWN_REG_A        0xa0
1968#define PINGROUP_REG_A          0x868
1969
1970/* Pin group with mux control, and typically tri-state and pull-up/down too */
1971#define MUX_PG(pg_name, f0, f1, f2, f3,                         \
1972               tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b)      \
1973        {                                                       \
1974                .name = #pg_name,                               \
1975                .pins = pg_name##_pins,                         \
1976                .npins = ARRAY_SIZE(pg_name##_pins),            \
1977                .funcs = {                                      \
1978                        TEGRA_MUX_ ## f0,                       \
1979                        TEGRA_MUX_ ## f1,                       \
1980                        TEGRA_MUX_ ## f2,                       \
1981                        TEGRA_MUX_ ## f3,                       \
1982                },                                              \
1983                .mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A),       \
1984                .mux_bank = 1,                                  \
1985                .mux_bit = mux_b,                               \
1986                .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A),      \
1987                .pupd_bank = 2,                                 \
1988                .pupd_bit = pupd_b,                             \
1989                .tri_reg = ((tri_r) - TRISTATE_REG_A),          \
1990                .tri_bank = 0,                                  \
1991                .tri_bit = tri_b,                               \
1992                .einput_bit = -1,                               \
1993                .odrain_bit = -1,                               \
1994                .lock_bit = -1,                                 \
1995                .ioreset_bit = -1,                              \
1996                .rcv_sel_bit = -1,                              \
1997                .drv_reg = -1,                                  \
1998                .parked_bitmask = 0,                            \
1999        }
2000

2001/* Pin groups with only pull up and pull down control */
2002#define PULL_PG(pg_name, pupd_r, pupd_b)                        \
2003        {                                                       \
2004                .name = #pg_name,                               \
2005                .pins = pg_name##_pins,                         \
2006                .npins = ARRAY_SIZE(pg_name##_pins),            \
2007                .mux_reg = -1,                                  \
2008                .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A),      \
2009                .pupd_bank = 2,                                 \
2010                .pupd_bit = pupd_b,                             \
2011                .drv_reg = -1,                                  \
2012                .parked_bitmask = 0,                            \
2013        }
2014
2015/* Pin groups for drive strength registers (configurable version) */
2016#define DRV_PG_EXT(pg_name, r, hsm_b, schmitt_b, lpmd_b,        \
2017                   drvdn_b, drvup_b,                            \
2018                   slwr_b, slwr_w, slwf_b, slwf_w)              \
2019        {                                                       \
2020                .name = "drive_" #pg_name,                      \
2021                .pins = drive_##pg_name##_pins,                 \
2022                .npins = ARRAY_SIZE(drive_##pg_name##_pins),    \
2023                .mux_reg = -1,                                  \
2024                .pupd_reg = -1,                                 \
2025                .tri_reg = -1,                                  \
2026                .drv_reg = ((r) - PINGROUP_REG_A),              \
2027                .drv_bank = 3,                                  \
2028                .parked_bitmask = 0,                            \
2029                .hsm_bit = hsm_b,                               \
2030                .schmitt_bit = schmitt_b,                       \
2031                .lpmd_bit = lpmd_b,                             \
2032                .drvdn_bit = drvdn_b,                           \
2033                .drvdn_width = 5,                               \
2034                .drvup_bit = drvup_b,                           \
2035                .drvup_width = 5,                               \
2036                .slwr_bit = slwr_b,                             \
2037                .slwr_width = slwr_w,                           \
2038                .slwf_bit = slwf_b,                             \
2039                .slwf_width = slwf_w,                           \
2040                .drvtype_bit = -1,                              \
2041        }
2042
2043/* Pin groups for drive strength registers (simple version) */
2044#define DRV_PG(pg_name, r) \
2045        DRV_PG_EXT(pg_name, r, 2,  3,  4, 12, 20, 28, 2, 30, 2)
2046
2047static const struct tegra_pingroup tegra20_groups[] = {
2048        /*     name,   f0,        f1,        f2,        f3,            tri r/b,  mux r/b,  pupd r/b */
2049        MUX_PG(ata,    IDE,       NAND,      GMI,       RSVD4,         0x14, 0,  0x80, 24, 0xa0, 0),
2050        MUX_PG(atb,    IDE,       NAND,      GMI,       SDIO4,         0x14, 1,  0x80, 16, 0xa0, 2),
2051        MUX_PG(atc,    IDE,       NAND,      GMI,       SDIO4,         0x14, 2,  0x80, 22, 0xa0, 4),
2052        MUX_PG(atd,    IDE,       NAND,      GMI,       SDIO4,         0x14, 3,  0x80, 20, 0xa0, 6),
2053        MUX_PG(ate,    IDE,       NAND,      GMI,       RSVD4,         0x18, 25, 0x80, 12, 0xa0, 8),
2054        MUX_PG(cdev1,  OSC,       PLLA_OUT,  PLLM_OUT1, AUDIO_SYNC,    0x14, 4,  0x88, 2,  0xa8, 0),
2055        MUX_PG(cdev2,  OSC,       AHB_CLK,   APB_CLK,   PLLP_OUT4,     0x14, 5,  0x88, 4,  0xa8, 2),
2056        MUX_PG(crtp,   CRT,       RSVD2,     RSVD3,     RSVD4,         0x20, 14, 0x98, 20, 0xa4, 24),
2057        MUX_PG(csus,   PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, 0x14, 6,  0x88, 6,  0xac, 24),
2058        MUX_PG(dap1,   DAP1,      RSVD2,     GMI,       SDIO2,         0x14, 7,  0x88, 20, 0xa0, 10),
2059        MUX_PG(dap2,   DAP2,      TWC,       RSVD3,     GMI,           0x14, 8,  0x88, 22, 0xa0, 12),
2060        MUX_PG(dap3,   DAP3,      RSVD2,     RSVD3,     RSVD4,         0x14, 9,  0x88, 24, 0xa0, 14),
2061        MUX_PG(dap4,   DAP4,      RSVD2,     GMI,       RSVD4,         0x14, 10, 0x88, 26, 0xa0, 16),
2062        MUX_PG(ddc,    I2C2,      RSVD2,     RSVD3,     RSVD4,         0x18, 31, 0x88, 0,  0xb0, 28),
2063        MUX_PG(dta,    RSVD1,     SDIO2,     VI,        RSVD4,         0x14, 11, 0x84, 20, 0xa0, 18),
2064        MUX_PG(dtb,    RSVD1,     RSVD2,     VI,        SPI1,          0x14, 12, 0x84, 22, 0xa0, 20),
2065        MUX_PG(dtc,    RSVD1,     RSVD2,     VI,        RSVD4,         0x14, 13, 0x84, 26, 0xa0, 22),
2066        MUX_PG(dtd,    RSVD1,     SDIO2,     VI,        RSVD4,         0x14, 14, 0x84, 28, 0xa0, 24),
2067        MUX_PG(dte,    RSVD1,     RSVD2,     VI,        SPI1,          0x14, 15, 0x84, 30, 0xa0, 26),
2068        MUX_PG(dtf,    I2C3,      RSVD2,     VI,        RSVD4,         0x20, 12, 0x98, 30, 0xa0, 28),
2069        MUX_PG(gma,    UARTE,     SPI3,      GMI,       SDIO4,         0x14, 28, 0x84, 0,  0xb0, 20),
2070        MUX_PG(gmb,    IDE,       NAND,      GMI,       GMI_INT,       0x18, 29, 0x88, 28, 0xb0, 22),
2071        MUX_PG(gmc,    UARTD,     SPI4,      GMI,       SFLASH,        0x14, 29, 0x84, 2,  0xb0, 24),
2072        MUX_PG(gmd,    RSVD1,     NAND,      GMI,       SFLASH,        0x18, 30, 0x88, 30, 0xb0, 26),
2073        MUX_PG(gme,    RSVD1,     DAP5,      GMI,       SDIO4,         0x18, 0,  0x8c, 0,  0xa8, 24),
2074        MUX_PG(gpu,    PWM,       UARTA,     GMI,       RSVD4,         0x14, 16, 0x8c, 4,  0xa4, 20),
2075        MUX_PG(gpu7,   RTCK,      RSVD2,     RSVD3,     RSVD4,         0x20, 11, 0x98, 28, 0xa4, 6),
2076        MUX_PG(gpv,    PCIE,      RSVD2,     RSVD3,     RSVD4,         0x14, 17, 0x8c, 2,  0xa0, 30),
2077        MUX_PG(hdint,  HDMI,      RSVD2,     RSVD3,     RSVD4,         0x1c, 23, 0x84, 4,  -1,   -1),
2078        MUX_PG(i2cp,   I2CP,      RSVD2,     RSVD3,     RSVD4,         0x14, 18, 0x88, 8,  0xa4, 2),
2079        MUX_PG(irrx,   UARTA,     UARTB,     GMI,       SPI4,          0x14, 20, 0x88, 18, 0xa8, 22),
2080        MUX_PG(irtx,   UARTA,     UARTB,     GMI,       SPI4,          0x14, 19, 0x88, 16, 0xa8, 20),
2081        MUX_PG(kbca,   KBC,       NAND,      SDIO2,     EMC_TEST0_DLL, 0x14, 22, 0x88, 10, 0xa4, 8),
2082        MUX_PG(kbcb,   KBC,       NAND,      SDIO2,     MIO,           0x14, 21, 0x88, 12, 0xa4, 10),
2083        MUX_PG(kbcc,   KBC,       NAND,      TRACE,     EMC_TEST1_DLL, 0x18, 26, 0x88, 14, 0xa4, 12),
2084        MUX_PG(kbcd,   KBC,       NAND,      SDIO2,     MIO,           0x20, 10, 0x98, 26, 0xa4, 14),
2085        MUX_PG(kbce,   KBC,       NAND,      OWR,       RSVD4,         0x14, 26, 0x80, 28, 0xb0, 2),
2086        MUX_PG(kbcf,   KBC,       NAND,      TRACE,     MIO,           0x14, 27, 0x80, 26, 0xb0, 0),
2087        MUX_PG(lcsn,   DISPLAYA,  DISPLAYB,  SPI3,      RSVD4,         0x1c, 31, 0x90, 12, -1,   -1),
2088        MUX_PG(ld0,    DISPLAYA,  DISPLAYB,  XIO,       RSVD4,         0x1c, 0,  0x94, 0,  -1,   -1),
2089        MUX_PG(ld1,    DISPLAYA,  DISPLAYB,  XIO,       RSVD4,         0x1c, 1,  0x94, 2,  -1,   -1),
2090        MUX_PG(ld2,    DISPLAYA,  DISPLAYB,  XIO,       RSVD4,         0x1c, 2,  0x94, 4,  -1,   -1),
2091        MUX_PG(ld3,    DISPLAYA,  DISPLAYB,  XIO,       RSVD4,         0x1c, 3,  0x94, 6,  -1,   -1),
2092        MUX_PG(ld4,    DISPLAYA,  DISPLAYB,  XIO,       RSVD4,         0x1c, 4,  0x94, 8,  -1,   -1),
2093        MUX_PG(ld5,    DISPLAYA,  DISPLAYB,  XIO,       RSVD4,         0x1c, 5,  0x94, 10, -1,   -1),
2094        MUX_PG(ld6,    DISPLAYA,  DISPLAYB,  XIO,       RSVD4,         0x1c, 6,  0x94, 12, -1,   -1),
2095        MUX_PG(ld7,    DISPLAYA,  DISPLAYB,  XIO,       RSVD4,         0x1c, 7,  0x94, 14, -1,   -1),
2096        MUX_PG(ld8,    DISPLAYA,  DISPLAYB,  XIO,       RSVD4,         0x1c, 8,  0x94, 16, -1,   -1),
2097        MUX_PG(ld9,    DISPLAYA,  DISPLAYB,  XIO,       RSVD4,         0x1c, 9,  0x94, 18, -1,   -1),
2098        MUX_PG(ld10,   DISPLAYA,  DISPLAYB,  XIO,       RSVD4,         0x1c, 10, 0x94, 20, -1,   -1),
2099        MUX_PG(ld11,   DISPLAYA,  DISPLAYB,  XIO,       RSVD4,         0x1c, 11, 0x94, 22, -1,   -1),
2100        MUX_PG(ld12,   DISPLAYA,  DISPLAYB,  XIO,       RSVD4,         0x1c, 12, 0x94, 24, -1,   -1),
2101        MUX_PG(ld13,   DISPLAYA,  DISPLAYB,  XIO,       RSVD4,         0x1c, 13, 0x94, 26, -1,   -1),
2102        MUX_PG(ld14,   DISPLAYA,  DISPLAYB,  XIO,       RSVD4,         0x1c, 14, 0x94, 28, -1,   -1),
2103        MUX_PG(ld15,   DISPLAYA,  DISPLAYB,  XIO,       RSVD4,         0x1c, 15, 0x94, 30, -1,   -1),
2104        MUX_PG(ld16,   DISPLAYA,  DISPLAYB,  XIO,       RSVD4,         0x1c, 16, 0x98, 0,  -1,   -1),
2105        MUX_PG(ld17,   DISPLAYA,  DISPLAYB,  RSVD3,     RSVD4,         0x1c, 17, 0x98, 2,  -1,   -1),
2106        MUX_PG(ldc,    DISPLAYA,  DISPLAYB,  RSVD3,     RSVD4,         0x1c, 30, 0x90, 14, -1,   -1),
2107        MUX_PG(ldi,    DISPLAYA,  DISPLAYB,  RSVD3,     RSVD4,         0x20, 6,  0x98, 16, -1,   -1),
2108        MUX_PG(lhp0,   DISPLAYA,  DISPLAYB,  RSVD3,     RSVD4,         0x1c, 18, 0x98, 10, -1,   -1),
2109        MUX_PG(lhp1,   DISPLAYA,  DISPLAYB,  RSVD3,     RSVD4,         0x1c, 19, 0x98, 4,  -1,   -1),
2110        MUX_PG(lhp2,   DISPLAYA,  DISPLAYB,  RSVD3,     RSVD4,         0x1c, 20, 0x98, 6,  -1,   -1),
2111        MUX_PG(lhs,    DISPLAYA,  DISPLAYB,  XIO,       RSVD4,         0x20, 7,  0x90, 22, -1,   -1),
2112        MUX_PG(lm0,    DISPLAYA,  DISPLAYB,  SPI3,      RSVD4,         0x1c, 24, 0x90, 26, -1,   -1),
2113        MUX_PG(lm1,    DISPLAYA,  DISPLAYB,  RSVD3,     CRT,           0x1c, 25, 0x90, 28, -1,   -1),
2114        MUX_PG(lpp,    DISPLAYA,  DISPLAYB,  RSVD3,     RSVD4,         0x20, 8,  0x98, 14, -1,   -1),
2115        MUX_PG(lpw0,   DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          0x20, 3,  0x90, 0,  -1,   -1),
2116        MUX_PG(lpw1,   DISPLAYA,  DISPLAYB,  RSVD3,     RSVD4,         0x20, 4,  0x90, 2,  -1,   -1),
2117        MUX_PG(lpw2,   DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          0x20, 5,  0x90, 4,  -1,   -1),
2118        MUX_PG(lsc0,   DISPLAYA,  DISPLAYB,  XIO,       RSVD4,         0x1c, 27, 0x90, 18, -1,   -1),
2119        MUX_PG(lsc1,   DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          0x1c, 28, 0x90, 20, -1,   -1),
2120        MUX_PG(lsck,   DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          0x1c, 29, 0x90, 16, -1,   -1),
2121        MUX_PG(lsda,   DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          0x20, 1,  0x90, 8,  -1,   -1),
2122        MUX_PG(lsdi,   DISPLAYA,  DISPLAYB,  SPI3,      RSVD4,         0x20, 2,  0x90, 6,  -1,   -1),
2123        MUX_PG(lspi,   DISPLAYA,  DISPLAYB,  XIO,       HDMI,          0x20, 0,  0x90, 10, -1,   -1),
2124        MUX_PG(lvp0,   DISPLAYA,  DISPLAYB,  RSVD3,     RSVD4,         0x1c, 21, 0x90, 30, -1,   -1),
2125        MUX_PG(lvp1,   DISPLAYA,  DISPLAYB,  RSVD3,     RSVD4,         0x1c, 22, 0x98, 8,  -1,   -1),
2126        MUX_PG(lvs,    DISPLAYA,  DISPLAYB,  XIO,       RSVD4,         0x1c, 26, 0x90, 24, -1,   -1),
2127        MUX_PG(owc,    OWR,       RSVD2,     RSVD3,     RSVD4,         0x14, 31, 0x84, 8,  0xb0, 30),
2128        MUX_PG(pmc,    PWR_ON,    PWR_INTR,  RSVD3,     RSVD4,         0x14, 23, 0x98, 18, -1,   -1),
2129        MUX_PG(pta,    I2C2,      HDMI,      GMI,       RSVD4,         0x14, 24, 0x98, 22, 0xa4, 4),
2130        MUX_PG(rm,     I2C1,      RSVD2,     RSVD3,     RSVD4,         0x14, 25, 0x80, 14, 0xa4, 0),
2131        MUX_PG(sdb,    UARTA,     PWM,       SDIO3,     SPI2,          0x20, 15, 0x8c, 10, -1,   -1),
2132        MUX_PG(sdc,    PWM,       TWC,       SDIO3,     SPI3,          0x18, 1,  0x8c, 12, 0xac, 28),
2133        MUX_PG(sdd,    UARTA,     PWM,       SDIO3,     SPI3,          0x18, 2,  0x8c, 14, 0xac, 30),
2134        MUX_PG(sdio1,  SDIO1,     RSVD2,     UARTE,     UARTA,         0x14, 30, 0x80, 30, 0xb0, 18),
2135        MUX_PG(slxa,   PCIE,      SPI4,      SDIO3,     SPI2,          0x18, 3,  0x84, 6,  0xa4, 22),
2136        MUX_PG(slxc,   SPDIF,     SPI4,      SDIO3,     SPI2,          0x18, 5,  0x84, 10, 0xa4, 26),
2137        MUX_PG(slxd,   SPDIF,     SPI4,      SDIO3,     SPI2,          0x18, 6,  0x84, 12, 0xa4, 28),
2138        MUX_PG(slxk,   PCIE,      SPI4,      SDIO3,     SPI2,          0x18, 7,  0x84, 14, 0xa4, 30),
2139        MUX_PG(spdi,   SPDIF,     RSVD2,     I2C1,      SDIO2,         0x18, 8,  0x8c, 8,  0xa4, 16),
2140        MUX_PG(spdo,   SPDIF,     RSVD2,     I2C1,      SDIO2,         0x18, 9,  0x8c, 6,  0xa4, 18),
2141        MUX_PG(spia,   SPI1,      SPI2,      SPI3,      GMI,           0x18, 10, 0x8c, 30, 0xa8, 4),
2142        MUX_PG(spib,   SPI1,      SPI2,      SPI3,      GMI,           0x18, 11, 0x8c, 28, 0xa8, 6),
2143        MUX_PG(spic,   SPI1,      SPI2,      SPI3,      GMI,           0x18, 12, 0x8c, 26, 0xa8, 8),
2144        MUX_PG(spid,   SPI2,      SPI1,      SPI2_ALT,  GMI,           0x18, 13, 0x8c, 24, 0xa8, 10),
2145        MUX_PG(spie,   SPI2,      SPI1,      SPI2_ALT,  GMI,           0x18, 14, 0x8c, 22, 0xa8, 12),
2146        MUX_PG(spif,   SPI3,      SPI1,      SPI2,      RSVD4,         0x18, 15, 0x8c, 20, 0xa8, 14),
2147        MUX_PG(spig,   SPI3,      SPI2,      SPI2_ALT,  I2C1,          0x18, 16, 0x8c, 18, 0xa8, 16),
2148        MUX_PG(spih,   SPI3,      SPI2,      SPI2_ALT,  I2C1,          0x18, 17, 0x8c, 16, 0xa8, 18),
2149        MUX_PG(uaa,    SPI3,      MIPI_HS,   UARTA,     ULPI,          0x18, 18, 0x80, 0,  0xac, 0),
2150        MUX_PG(uab,    SPI2,      MIPI_HS,   UARTA,     ULPI,          0x18, 19, 0x80, 2,  0xac, 2),
2151        MUX_PG(uac,    OWR,       RSVD2,     RSVD3,     RSVD4,         0x18, 20, 0x80, 4,  0xac, 4),
2152        MUX_PG(uad,    IRDA,      SPDIF,     UARTA,     SPI4,          0x18, 21, 0x80, 6,  0xac, 6),
2153        MUX_PG(uca,    UARTC,     RSVD2,     GMI,       RSVD4,         0x18, 22, 0x84, 16, 0xac, 8),
2154        MUX_PG(ucb,    UARTC,     PWM,       GMI,       RSVD4,         0x18, 23, 0x84, 18, 0xac, 10),
2155        MUX_PG(uda,    SPI1,      RSVD2,     UARTD,     ULPI,          0x20, 13, 0x80, 8,  0xb0, 16),
2156        /*      pg_name, pupd_r/b */
2157        PULL_PG(ck32,    0xb0, 14),
2158        PULL_PG(ddrc,    0xac, 26),
2159        PULL_PG(pmca,    0xb0, 4),
2160        PULL_PG(pmcb,    0xb0, 6),
2161        PULL_PG(pmcc,    0xb0, 8),
2162        PULL_PG(pmcd,    0xb0, 10),
2163        PULL_PG(pmce,    0xb0, 12),
2164        PULL_PG(xm2c,    0xa8, 30),
2165        PULL_PG(xm2d,    0xa8, 28),
2166        PULL_PG(ls,      0xac, 20),
2167        PULL_PG(lc,      0xac, 22),
2168        PULL_PG(ld17_0,  0xac, 12),
2169        PULL_PG(ld19_18, 0xac, 14),
2170        PULL_PG(ld21_20, 0xac, 16),
2171        PULL_PG(ld23_22, 0xac, 18),
2172        /*     pg_name,    r */
2173        DRV_PG(ao1,        0x868),
2174        DRV_PG(ao2,        0x86c),
2175        DRV_PG(at1,        0x870),
2176        DRV_PG(at2,        0x874),
2177        DRV_PG(cdev1,      0x878),
2178        DRV_PG(cdev2,      0x87c),
2179        DRV_PG(csus,       0x880),
2180        DRV_PG(dap1,       0x884),
2181        DRV_PG(dap2,       0x888),
2182        DRV_PG(dap3,       0x88c),
2183        DRV_PG(dap4,       0x890),
2184        DRV_PG(dbg,        0x894),
2185        DRV_PG(lcd1,       0x898),
2186        DRV_PG(lcd2,       0x89c),
2187        DRV_PG(sdmmc2,     0x8a0),
2188        DRV_PG(sdmmc3,     0x8a4),
2189        DRV_PG(spi,        0x8a8),
2190        DRV_PG(uaa,        0x8ac),
2191        DRV_PG(uab,        0x8b0),
2192        DRV_PG(uart2,      0x8b4),
2193        DRV_PG(uart3,      0x8b8),
2194        DRV_PG(vi1,        0x8bc),
2195        DRV_PG(vi2,        0x8c0),
2196        /*         pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvup_b, slwr_b, slwr_w, slwf_b, slwf_w */
2197        DRV_PG_EXT(xm2a,   0x8c4, -1, -1,  4, 14, 19, 24, 4, 28, 4),
2198        DRV_PG_EXT(xm2c,   0x8c8, -1,  3, -1, 14, 19, 24, 4, 28, 4),
2199        DRV_PG_EXT(xm2d,   0x8cc, -1,  3, -1, 14, 19, 24, 4, 28, 4),
2200        DRV_PG_EXT(xm2clk, 0x8d0, -1, -1, -1, 14, 19, 24, 4, 28, 4),
2201        /*     pg_name,    r */
2202        DRV_PG(sdio1,      0x8e0),
2203        DRV_PG(crt,        0x8ec),
2204        DRV_PG(ddc,        0x8f0),
2205        DRV_PG(gma,        0x8f4),
2206        DRV_PG(gmb,        0x8f8),
2207        DRV_PG(gmc,        0x8fc),
2208        DRV_PG(gmd,        0x900),
2209        DRV_PG(gme,        0x904),
2210        DRV_PG(owr,        0x908),
2211        DRV_PG(uda,        0x90c),
2212};
2213
2214static const struct tegra_pinctrl_soc_data tegra20_pinctrl = {
2215        .ngpios = NUM_GPIOS,
2216        .gpio_compatible = "nvidia,tegra20-gpio",
2217        .pins = tegra20_pins,
2218        .npins = ARRAY_SIZE(tegra20_pins),
2219        .functions = tegra20_functions,
2220        .nfunctions = ARRAY_SIZE(tegra20_functions),
2221        .groups = tegra20_groups,
2222        .ngroups = ARRAY_SIZE(tegra20_groups),
2223        .hsm_in_mux = false,
2224        .schmitt_in_mux = false,
2225        .drvtype_in_mux = false,
2226};
2227
2228static const char *cdev1_parents[] = {
2229        "dev1_osc_div", "pll_a_out0", "pll_m_out1", "audio",
2230};
2231
2232static const char *cdev2_parents[] = {
2233        "dev2_osc_div", "hclk", "pclk", "pll_p_out4",
2234};
2235
2236static void tegra20_pinctrl_register_clock_muxes(struct platform_device *pdev)
2237{
2238        struct tegra_pmx *pmx = platform_get_drvdata(pdev);
2239
2240        clk_register_mux(NULL, "cdev1_mux", cdev1_parents, 4, 0,
2241                         pmx->regs[1] + 0x8, 2, 2, CLK_MUX_READ_ONLY, NULL);
2242
2243        clk_register_mux(NULL, "cdev2_mux", cdev2_parents, 4, 0,
2244                         pmx->regs[1] + 0x8, 4, 2, CLK_MUX_READ_ONLY, NULL);
2245}
2246
2247static int tegra20_pinctrl_probe(struct platform_device *pdev)
2248{
2249        int err;
2250
2251        err = tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
2252        if (err)
2253                return err;
2254
2255        tegra20_pinctrl_register_clock_muxes(pdev);
2256
2257        return 0;
2258}
2259
2260static const struct of_device_id tegra20_pinctrl_of_match[] = {
2261        { .compatible = "nvidia,tegra20-pinmux", },
2262        { },
2263};
2264
2265static struct platform_driver tegra20_pinctrl_driver = {
2266        .driver = {
2267                .name = "tegra20-pinctrl",
2268                .of_match_table = tegra20_pinctrl_of_match,
2269        },
2270        .probe = tegra20_pinctrl_probe,
2271};
2272
2273static int __init tegra20_pinctrl_init(void)
2274{
2275        return platform_driver_register(&tegra20_pinctrl_driver);
2276}
2277arch_initcall(tegra20_pinctrl_init);
2278