1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * EMXX FCD (Function Controller Driver) for USB. 4 * 5 * Copyright (C) 2010 Renesas Electronics Corporation 6 */ 7 8#ifndef _LINUX_EMXX_H 9#define _LINUX_EMXX_H 10 11/*---------------------------------------------------------------------------*/ 12 13/*----------------- Default define */ 14#define USE_DMA 1 15#define USE_SUSPEND_WAIT 1 16 17/*------------ Board dependence(Resource) */ 18#define VBUS_VALUE GPIO_VBUS 19 20/* below hacked up for staging integration */ 21#define GPIO_VBUS 0 /* GPIO_P153 on KZM9D */ 22#define INT_VBUS 0 /* IRQ for GPIO_P153 */ 23struct gpio_desc *vbus_gpio; 24int vbus_irq; 25 26/*------------ Board dependence(Wait) */ 27 28/* CHATTERING wait time ms */ 29#define VBUS_CHATTERING_MDELAY 1 30/* DMA Abort wait time ms */ 31#define DMA_DISABLE_TIME 10 32 33/*------------ Controller dependence */ 34#define NUM_ENDPOINTS 14 /* Endpoint */ 35#define REG_EP_NUM 15 /* Endpoint Register */ 36#define DMA_MAX_COUNT 256 /* DMA Block */ 37 38#define EPC_RST_DISABLE_TIME 1 /* 1 usec */ 39#define EPC_DIRPD_DISABLE_TIME 1 /* 1 msec */ 40#define EPC_PLL_LOCK_COUNT 1000 /* 1000 */ 41#define IN_DATA_EMPTY_COUNT 1000 /* 1000 */ 42 43#define CHATGER_TIME 700 /* 700msec */ 44#define USB_SUSPEND_TIME 2000 /* 2 sec */ 45 46/* U2F FLAG */ 47#define U2F_ENABLE 1 48#define U2F_DISABLE 0 49 50#define TEST_FORCE_ENABLE (BIT(18) | BIT(16)) 51 52#define INT_SEL BIT(10) 53#define CONSTFS BIT(9) 54#define SOF_RCV BIT(8) 55#define RSUM_IN BIT(7) 56#define SUSPEND BIT(6) 57#define CONF BIT(5) 58#define DEFAULT BIT(4) 59#define CONNECTB BIT(3) 60#define PUE2 BIT(2) 61 62#define MAX_TEST_MODE_NUM 0x05 63#define TEST_MODE_SHIFT 16 64 65/*------- (0x0004) USB Status Register */ 66#define SPEED_MODE BIT(6) 67#define HIGH_SPEED BIT(6) 68 69#define CONF BIT(5) 70#define DEFAULT BIT(4) 71#define USB_RST BIT(3) 72#define SPND_OUT BIT(2) 73#define RSUM_OUT BIT(1) 74 75/*------- (0x0008) USB Address Register */ 76#define USB_ADDR 0x007F0000 77#define SOF_STATUS BIT(15) 78#define UFRAME (BIT(14) | BIT(13) | BIT(12)) 79#define FRAME 0x000007FF 80 81#define USB_ADRS_SHIFT 16 82 83/*------- (0x000C) UTMI Characteristic 1 Register */ 84#define SQUSET (BIT(7) | BIT(6) | BIT(5) | BIT(4)) 85 86#define USB_SQUSET (BIT(6) | BIT(5) | BIT(4)) 87 88/*------- (0x0010) TEST Control Register */ 89#define FORCEHS BIT(2) 90#define CS_TESTMODEEN BIT(1) 91#define LOOPBACK BIT(0) 92 93/*------- (0x0018) Setup Data 0 Register */ 94/*------- (0x001C) Setup Data 1 Register */ 95 96/*------- (0x0020) USB Interrupt Status Register */ 97#define EPN_INT 0x00FFFF00 98#define EP15_INT BIT(23) 99#define EP14_INT BIT(22) 100#define EP13_INT BIT(21) 101#define EP12_INT BIT(20) 102#define EP11_INT BIT(19) 103#define EP10_INT BIT(18) 104#define EP9_INT BIT(17) 105#define EP8_INT BIT(16) 106#define EP7_INT BIT(15) 107#define EP6_INT BIT(14) 108#define EP5_INT BIT(13) 109#define EP4_INT BIT(12) 110#define EP3_INT BIT(11) 111#define EP2_INT BIT(10) 112#define EP1_INT BIT(9) 113#define EP0_INT BIT(8) 114#define SPEED_MODE_INT BIT(6) 115#define SOF_ERROR_INT BIT(5) 116#define SOF_INT BIT(4) 117#define USB_RST_INT BIT(3) 118#define SPND_INT BIT(2) 119#define RSUM_INT BIT(1) 120 121#define USB_INT_STA_RW 0x7E 122 123/*------- (0x0024) USB Interrupt Enable Register */ 124#define EP15_0_EN 0x00FFFF00 125#define EP15_EN BIT(23) 126#define EP14_EN BIT(22) 127#define EP13_EN BIT(21) 128#define EP12_EN BIT(20) 129#define EP11_EN BIT(19) 130#define EP10_EN BIT(18) 131#define EP9_EN BIT(17) 132#define EP8_EN BIT(16) 133#define EP7_EN BIT(15) 134#define EP6_EN BIT(14) 135#define EP5_EN BIT(13) 136#define EP4_EN BIT(12) 137#define EP3_EN BIT(11) 138#define EP2_EN BIT(10) 139#define EP1_EN BIT(9) 140#define EP0_EN BIT(8) 141#define SPEED_MODE_EN BIT(6) 142#define SOF_ERROR_EN BIT(5) 143#define SOF_EN BIT(4) 144#define USB_RST_EN BIT(3) 145#define SPND_EN BIT(2) 146#define RSUM_EN BIT(1) 147 148#define USB_INT_EN_BIT \ 149 (EP0_EN | SPEED_MODE_EN | USB_RST_EN | SPND_EN | RSUM_EN) 150 151/*------- (0x0028) EP0 Control Register */ 152#define EP0_STGSEL BIT(18) 153#define EP0_OVERSEL BIT(17) 154#define EP0_AUTO BIT(16) 155#define EP0_PIDCLR BIT(9) 156#define EP0_BCLR BIT(8) 157#define EP0_DEND BIT(7) 158#define EP0_DW (BIT(6) | BIT(5)) 159#define EP0_DW4 0 160#define EP0_DW3 (BIT(6) | BIT(5)) 161#define EP0_DW2 BIT(6) 162#define EP0_DW1 BIT(5) 163 164#define EP0_INAK_EN BIT(4) 165#define EP0_PERR_NAK_CLR BIT(3) 166#define EP0_STL BIT(2) 167#define EP0_INAK BIT(1) 168#define EP0_ONAK BIT(0) 169 170/*------- (0x002C) EP0 Status Register */ 171#define EP0_PID BIT(18) 172#define EP0_PERR_NAK BIT(17) 173#define EP0_PERR_NAK_INT BIT(16) 174#define EP0_OUT_NAK_INT BIT(15) 175#define EP0_OUT_NULL BIT(14) 176#define EP0_OUT_FULL BIT(13) 177#define EP0_OUT_EMPTY BIT(12) 178#define EP0_IN_NAK_INT BIT(11) 179#define EP0_IN_DATA BIT(10) 180#define EP0_IN_FULL BIT(9) 181#define EP0_IN_EMPTY BIT(8) 182#define EP0_OUT_NULL_INT BIT(7) 183#define EP0_OUT_OR_INT BIT(6) 184#define EP0_OUT_INT BIT(5) 185#define EP0_IN_INT BIT(4) 186#define EP0_STALL_INT BIT(3) 187#define STG_END_INT BIT(2) 188#define STG_START_INT BIT(1) 189#define SETUP_INT BIT(0) 190 191#define EP0_STATUS_RW_BIT (BIT(16) | BIT(15) | BIT(11) | 0xFF) 192 193/*------- (0x0030) EP0 Interrupt Enable Register */ 194#define EP0_PERR_NAK_EN BIT(16) 195#define EP0_OUT_NAK_EN BIT(15) 196 197#define EP0_IN_NAK_EN BIT(11) 198 199#define EP0_OUT_NULL_EN BIT(7) 200#define EP0_OUT_OR_EN BIT(6) 201#define EP0_OUT_EN BIT(5) 202#define EP0_IN_EN BIT(4) 203#define EP0_STALL_EN BIT(3) 204#define STG_END_EN BIT(2) 205#define STG_START_EN BIT(1) 206#define SETUP_EN BIT(0) 207 208#define EP0_INT_EN_BIT \ 209 (EP0_OUT_OR_EN | EP0_OUT_EN | EP0_IN_EN | STG_END_EN | SETUP_EN) 210 211/*------- (0x0034) EP0 Length Register */ 212#define EP0_LDATA 0x0000007F 213 214/*------- (0x0038) EP0 Read Register */ 215/*------- (0x003C) EP0 Write Register */ 216 217/*------- (0x0040:) EPN Control Register */ 218#define EPN_EN BIT(31) 219#define EPN_BUF_TYPE BIT(30) 220#define EPN_BUF_SINGLE BIT(30) 221 222#define EPN_DIR0 BIT(26) 223#define EPN_MODE (BIT(25) | BIT(24)) 224#define EPN_BULK 0 225#define EPN_INTERRUPT BIT(24) 226#define EPN_ISO BIT(25) 227 228#define EPN_OVERSEL BIT(17) 229#define EPN_AUTO BIT(16) 230 231#define EPN_IPIDCLR BIT(11) 232#define EPN_OPIDCLR BIT(10) 233#define EPN_BCLR BIT(9) 234#define EPN_CBCLR BIT(8) 235#define EPN_DEND BIT(7) 236#define EPN_DW (BIT(6) | BIT(5)) 237#define EPN_DW4 0 238#define EPN_DW3 (BIT(6) | BIT(5)) 239#define EPN_DW2 BIT(6) 240#define EPN_DW1 BIT(5) 241 242#define EPN_OSTL_EN BIT(4) 243#define EPN_ISTL BIT(3) 244#define EPN_OSTL BIT(2) 245 246#define EPN_ONAK BIT(0) 247 248/*------- (0x0044:) EPN Status Register */ 249#define EPN_ISO_PIDERR BIT(29) /* R */ 250#define EPN_OPID BIT(28) /* R */ 251#define EPN_OUT_NOTKN BIT(27) /* R */ 252#define EPN_ISO_OR BIT(26) /* R */ 253 254#define EPN_ISO_CRC BIT(24) /* R */ 255#define EPN_OUT_END_INT BIT(23) /* RW */ 256#define EPN_OUT_OR_INT BIT(22) /* RW */ 257#define EPN_OUT_NAK_ERR_INT BIT(21) /* RW */ 258#define EPN_OUT_STALL_INT BIT(20) /* RW */ 259#define EPN_OUT_INT BIT(19) /* RW */ 260#define EPN_OUT_NULL_INT BIT(18) /* RW */ 261#define EPN_OUT_FULL BIT(17) /* R */ 262#define EPN_OUT_EMPTY BIT(16) /* R */ 263 264#define EPN_IPID BIT(10) /* R */ 265#define EPN_IN_NOTKN BIT(9) /* R */ 266#define EPN_ISO_UR BIT(8) /* R */ 267#define EPN_IN_END_INT BIT(7) /* RW */ 268 269#define EPN_IN_NAK_ERR_INT BIT(5) /* RW */ 270#define EPN_IN_STALL_INT BIT(4) /* RW */ 271#define EPN_IN_INT BIT(3) /* RW */ 272#define EPN_IN_DATA BIT(2) /* R */ 273#define EPN_IN_FULL BIT(1) /* R */ 274#define EPN_IN_EMPTY BIT(0) /* R */ 275 276#define EPN_INT_EN \ 277 (EPN_OUT_END_INT | EPN_OUT_INT | EPN_IN_END_INT | EPN_IN_INT) 278 279/*------- (0x0048:) EPN Interrupt Enable Register */ 280#define EPN_OUT_END_EN BIT(23) /* RW */ 281#define EPN_OUT_OR_EN BIT(22) /* RW */ 282#define EPN_OUT_NAK_ERR_EN BIT(21) /* RW */ 283#define EPN_OUT_STALL_EN BIT(20) /* RW */ 284#define EPN_OUT_EN BIT(19) /* RW */ 285#define EPN_OUT_NULL_EN BIT(18) /* RW */ 286 287#define EPN_IN_END_EN BIT(7) /* RW */ 288 289#define EPN_IN_NAK_ERR_EN BIT(5) /* RW */ 290#define EPN_IN_STALL_EN BIT(4) /* RW */ 291#define EPN_IN_EN BIT(3) /* RW */ 292 293/*------- (0x004C:) EPN Interrupt Enable Register */ 294#define EPN_STOP_MODE BIT(11) 295#define EPN_DEND_SET BIT(10) 296#define EPN_BURST_SET BIT(9) 297#define EPN_STOP_SET BIT(8) 298 299#define EPN_DMA_EN BIT(4) 300 301#define EPN_DMAMODE0 BIT(0) 302 303/*------- (0x0050:) EPN MaxPacket & BaseAddress Register */ 304#define EPN_BASEAD 0x1FFF0000 305#define EPN_MPKT 0x000007FF 306 307/*------- (0x0054:) EPN Length & DMA Count Register */ 308#define EPN_DMACNT 0x01FF0000 309#define EPN_LDATA 0x000007FF 310 311/*------- (0x0058:) EPN Read Register */ 312/*------- (0x005C:) EPN Write Register */ 313 314/*------- (0x1000) AHBSCTR Register */ 315#define WAIT_MODE BIT(0) 316 317/*------- (0x1004) AHBMCTR Register */ 318#define ARBITER_CTR BIT(31) /* RW */ 319#define MCYCLE_RST BIT(12) /* RW */ 320 321#define ENDIAN_CTR (BIT(9) | BIT(8)) /* RW */ 322#define ENDIAN_BYTE_SWAP BIT(9) 323#define ENDIAN_HALF_WORD_SWAP ENDIAN_CTR 324 325#define HBUSREQ_MODE BIT(5) /* RW */ 326#define HTRANS_MODE BIT(4) /* RW */ 327 328#define WBURST_TYPE BIT(2) /* RW */ 329#define BURST_TYPE (BIT(1) | BIT(0)) /* RW */ 330#define BURST_MAX_16 0 331#define BURST_MAX_8 BIT(0) 332#define BURST_MAX_4 BIT(1) 333#define BURST_SINGLE BURST_TYPE 334 335/*------- (0x1008) AHBBINT Register */ 336#define DMA_ENDINT 0xFFFE0000 /* RW */ 337 338#define AHB_VBUS_INT BIT(13) /* RW */ 339 340#define MBUS_ERRINT BIT(6) /* RW */ 341 342#define SBUS_ERRINT0 BIT(4) /* RW */ 343#define ERR_MASTER 0x0000000F /* R */ 344 345/*------- (0x100C) AHBBINTEN Register */ 346#define DMA_ENDINTEN 0xFFFE0000 /* RW */ 347 348#define VBUS_INTEN BIT(13) /* RW */ 349 350#define MBUS_ERRINTEN BIT(6) /* RW */ 351 352#define SBUS_ERRINT0EN BIT(4) /* RW */ 353 354/*------- (0x1010) EPCTR Register */ 355#define DIRPD BIT(12) /* RW */ 356 357#define VBUS_LEVEL BIT(8) /* R */ 358 359#define PLL_RESUME BIT(5) /* RW */ 360#define PLL_LOCK BIT(4) /* R */ 361 362#define EPC_RST BIT(0) /* RW */ 363 364/*------- (0x1014) USBF_EPTEST Register */ 365#define LINESTATE (BIT(9) | BIT(8)) /* R */ 366#define DM_LEVEL BIT(9) /* R */ 367#define DP_LEVEL BIT(8) /* R */ 368 369#define PHY_TST BIT(1) /* RW */ 370#define PHY_TSTCLK BIT(0) /* RW */ 371 372/*------- (0x1020) USBSSVER Register */ 373#define AHBB_VER 0x00FF0000 /* R */ 374#define EPC_VER 0x0000FF00 /* R */ 375#define SS_VER 0x000000FF /* R */ 376 377/*------- (0x1024) USBSSCONF Register */ 378#define EP_AVAILABLE 0xFFFF0000 /* R */ 379#define DMA_AVAILABLE 0x0000FFFF /* R */ 380 381/*------- (0x1110:) EPNDCR1 Register */ 382#define DCR1_EPN_DMACNT 0x00FF0000 /* RW */ 383 384#define DCR1_EPN_DIR0 BIT(1) /* RW */ 385#define DCR1_EPN_REQEN BIT(0) /* RW */ 386 387/*------- (0x1114:) EPNDCR2 Register */ 388#define DCR2_EPN_LMPKT 0x07FF0000 /* RW */ 389 390#define DCR2_EPN_MPKT 0x000007FF /* RW */ 391 392/*------- (0x1118:) EPNTADR Register */ 393#define EPN_TADR 0xFFFFFFFF /* RW */ 394 395/*===========================================================================*/ 396/* Struct */ 397/*------- ep_regs */ 398struct ep_regs { 399 u32 EP_CONTROL; /* EP Control */ 400 u32 EP_STATUS; /* EP Status */ 401 u32 EP_INT_ENA; /* EP Interrupt Enable */ 402 u32 EP_DMA_CTRL; /* EP DMA Control */ 403 u32 EP_PCKT_ADRS; /* EP Maxpacket & BaseAddress */ 404 u32 EP_LEN_DCNT; /* EP Length & DMA count */ 405 u32 EP_READ; /* EP Read */ 406 u32 EP_WRITE; /* EP Write */ 407}; 408 409/*------- ep_dcr */ 410struct ep_dcr { 411 u32 EP_DCR1; /* EP_DCR1 */ 412 u32 EP_DCR2; /* EP_DCR2 */ 413 u32 EP_TADR; /* EP_TADR */ 414 u32 Reserved; /* Reserved */ 415}; 416 417/*------- Function Registers */ 418struct fc_regs { 419 u32 USB_CONTROL; /* (0x0000) USB Control */ 420 u32 USB_STATUS; /* (0x0004) USB Status */ 421 u32 USB_ADDRESS; /* (0x0008) USB Address */ 422 u32 UTMI_CHARACTER_1; /* (0x000C) UTMI Setting */ 423 u32 TEST_CONTROL; /* (0x0010) TEST Control */ 424 u32 reserved_14; /* (0x0014) Reserved */ 425 u32 SETUP_DATA0; /* (0x0018) Setup Data0 */ 426 u32 SETUP_DATA1; /* (0x001C) Setup Data1 */ 427 u32 USB_INT_STA; /* (0x0020) USB Interrupt Status */ 428 u32 USB_INT_ENA; /* (0x0024) USB Interrupt Enable */ 429 u32 EP0_CONTROL; /* (0x0028) EP0 Control */ 430 u32 EP0_STATUS; /* (0x002C) EP0 Status */ 431 u32 EP0_INT_ENA; /* (0x0030) EP0 Interrupt Enable */ 432 u32 EP0_LENGTH; /* (0x0034) EP0 Length */ 433 u32 EP0_READ; /* (0x0038) EP0 Read */ 434 u32 EP0_WRITE; /* (0x003C) EP0 Write */ 435 436 struct ep_regs EP_REGS[REG_EP_NUM]; /* Endpoint Register */ 437 438 u8 reserved_220[0x1000 - 0x220]; /* (0x0220:0x0FFF) Reserved */ 439 440 u32 AHBSCTR; /* (0x1000) AHBSCTR */ 441 u32 AHBMCTR; /* (0x1004) AHBMCTR */ 442 u32 AHBBINT; /* (0x1008) AHBBINT */ 443 u32 AHBBINTEN; /* (0x100C) AHBBINTEN */ 444 u32 EPCTR; /* (0x1010) EPCTR */ 445 u32 USBF_EPTEST; /* (0x1014) USBF_EPTEST */ 446 447 u8 reserved_1018[0x20 - 0x18]; /* (0x1018:0x101F) Reserved */ 448 449 u32 USBSSVER; /* (0x1020) USBSSVER */ 450 u32 USBSSCONF; /* (0x1024) USBSSCONF */ 451 452 u8 reserved_1028[0x110 - 0x28]; /* (0x1028:0x110F) Reserved */ 453 454 struct ep_dcr EP_DCR[REG_EP_NUM]; /* */ 455 456 u8 reserved_1200[0x1000 - 0x200]; /* Reserved */ 457} __aligned(32); 458 459#define EP0_PACKETSIZE 64 460#define EP_PACKETSIZE 1024 461 462/* EPN RAM SIZE */ 463#define D_RAM_SIZE_CTRL 64 464 465/* EPN Bulk Endpoint Max Packet Size */ 466#define D_FS_RAM_SIZE_BULK 64 467#define D_HS_RAM_SIZE_BULK 512 468 469struct nbu2ss_udc; 470 471enum ep0_state { 472 EP0_IDLE, 473 EP0_IN_DATA_PHASE, 474 EP0_OUT_DATA_PHASE, 475 EP0_IN_STATUS_PHASE, 476 EP0_OUT_STATUS_PAHSE, 477 EP0_END_XFER, 478 EP0_SUSPEND, 479 EP0_STALL, 480}; 481 482struct nbu2ss_req { 483 struct usb_request req; 484 struct list_head queue; 485 486 u32 div_len; 487 bool dma_flag; 488 bool zero; 489 490 bool unaligned; 491 492 unsigned mapped:1; 493}; 494 495struct nbu2ss_ep { 496 struct usb_ep ep; 497 struct list_head queue; 498 499 struct nbu2ss_udc *udc; 500 501 const struct usb_endpoint_descriptor *desc; 502 503 u8 epnum; 504 u8 direct; 505 u8 ep_type; 506 507 unsigned wedged:1; 508 unsigned halted:1; 509 unsigned stalled:1; 510 511 u8 *virt_buf; 512 dma_addr_t phys_buf; 513}; 514 515struct nbu2ss_udc { 516 struct usb_gadget gadget; 517 struct usb_gadget_driver *driver; 518 struct platform_device *pdev; 519 struct device *dev; 520 spinlock_t lock; /* Protects nbu2ss_udc structure fields */ 521 struct completion *pdone; 522 523 enum ep0_state ep0state; 524 enum usb_device_state devstate; 525 struct usb_ctrlrequest ctrl; 526 struct nbu2ss_req ep0_req; 527 u8 ep0_buf[EP0_PACKETSIZE]; 528 529 struct nbu2ss_ep ep[NUM_ENDPOINTS]; 530 531 unsigned softconnect:1; 532 unsigned vbus_active:1; 533 unsigned linux_suspended:1; 534 unsigned linux_resume:1; 535 unsigned usb_suspended:1; 536 unsigned remote_wakeup:1; 537 unsigned udc_enabled:1; 538 539 unsigned int mA; 540 541 u32 curr_config; /* Current Configuration Number */ 542 543 struct fc_regs __iomem *p_regs; 544}; 545 546/* USB register access structure */ 547union usb_reg_access { 548 struct { 549 unsigned char DATA[4]; 550 } byte; 551 unsigned int dw; 552}; 553 554/*-------------------------------------------------------------------------*/ 555 556#endif /* _LINUX_EMXX_H */ 557