linux/include/linux/mmc/sdio.h
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   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 *  include/linux/mmc/sdio.h
   4 *
   5 *  Copyright 2006-2007 Pierre Ossman
   6 */
   7
   8#ifndef LINUX_MMC_SDIO_H
   9#define LINUX_MMC_SDIO_H
  10
  11/* SDIO commands                         type  argument     response */
  12#define SD_IO_SEND_OP_COND          5 /* bcr  [23:0] OCR         R4  */
  13#define SD_IO_RW_DIRECT            52 /* ac   [31:0] See below   R5  */
  14#define SD_IO_RW_EXTENDED          53 /* adtc [31:0] See below   R5  */
  15
  16/*
  17 * SD_IO_RW_DIRECT argument format:
  18 *
  19 *      [31] R/W flag
  20 *      [30:28] Function number
  21 *      [27] RAW flag
  22 *      [25:9] Register address
  23 *      [7:0] Data
  24 */
  25
  26/*
  27 * SD_IO_RW_EXTENDED argument format:
  28 *
  29 *      [31] R/W flag
  30 *      [30:28] Function number
  31 *      [27] Block mode
  32 *      [26] Increment address
  33 *      [25:9] Register address
  34 *      [8:0] Byte/block count
  35 */
  36
  37#define R4_18V_PRESENT (1<<24)
  38#define R4_MEMORY_PRESENT (1 << 27)
  39
  40/*
  41  SDIO status in R5
  42  Type
  43        e : error bit
  44        s : status bit
  45        r : detected and set for the actual command response
  46        x : detected and set during command execution. the host must poll
  47            the card by sending status command in order to read these bits.
  48  Clear condition
  49        a : according to the card state
  50        b : always related to the previous command. Reception of
  51            a valid command will clear it (with a delay of one command)
  52        c : clear by read
  53 */
  54
  55#define R5_COM_CRC_ERROR        (1 << 15)       /* er, b */
  56#define R5_ILLEGAL_COMMAND      (1 << 14)       /* er, b */
  57#define R5_ERROR                (1 << 11)       /* erx, c */
  58#define R5_FUNCTION_NUMBER      (1 << 9)        /* er, c */
  59#define R5_OUT_OF_RANGE         (1 << 8)        /* er, c */
  60#define R5_STATUS(x)            (x & 0xCB00)
  61#define R5_IO_CURRENT_STATE(x)  ((x & 0x3000) >> 12) /* s, b */
  62
  63/*
  64 * Card Common Control Registers (CCCR)
  65 */
  66
  67#define SDIO_CCCR_CCCR          0x00
  68
  69#define  SDIO_CCCR_REV_1_00     0       /* CCCR/FBR Version 1.00 */
  70#define  SDIO_CCCR_REV_1_10     1       /* CCCR/FBR Version 1.10 */
  71#define  SDIO_CCCR_REV_1_20     2       /* CCCR/FBR Version 1.20 */
  72#define  SDIO_CCCR_REV_3_00     3       /* CCCR/FBR Version 3.00 */
  73
  74#define  SDIO_SDIO_REV_1_00     0       /* SDIO Spec Version 1.00 */
  75#define  SDIO_SDIO_REV_1_10     1       /* SDIO Spec Version 1.10 */
  76#define  SDIO_SDIO_REV_1_20     2       /* SDIO Spec Version 1.20 */
  77#define  SDIO_SDIO_REV_2_00     3       /* SDIO Spec Version 2.00 */
  78#define  SDIO_SDIO_REV_3_00     4       /* SDIO Spec Version 3.00 */
  79
  80#define SDIO_CCCR_SD            0x01
  81
  82#define  SDIO_SD_REV_1_01       0       /* SD Physical Spec Version 1.01 */
  83#define  SDIO_SD_REV_1_10       1       /* SD Physical Spec Version 1.10 */
  84#define  SDIO_SD_REV_2_00       2       /* SD Physical Spec Version 2.00 */
  85#define  SDIO_SD_REV_3_00       3       /* SD Physical Spev Version 3.00 */
  86
  87#define SDIO_CCCR_IOEx          0x02
  88#define SDIO_CCCR_IORx          0x03
  89
  90#define SDIO_CCCR_IENx          0x04    /* Function/Master Interrupt Enable */
  91#define SDIO_CCCR_INTx          0x05    /* Function Interrupt Pending */
  92
  93#define SDIO_CCCR_ABORT         0x06    /* function abort/card reset */
  94
  95#define SDIO_CCCR_IF            0x07    /* bus interface controls */
  96
  97#define  SDIO_BUS_WIDTH_MASK    0x03    /* data bus width setting */
  98#define  SDIO_BUS_WIDTH_1BIT    0x00
  99#define  SDIO_BUS_WIDTH_RESERVED 0x01
 100#define  SDIO_BUS_WIDTH_4BIT    0x02
 101#define  SDIO_BUS_ECSI          0x20    /* Enable continuous SPI interrupt */
 102#define  SDIO_BUS_SCSI          0x40    /* Support continuous SPI interrupt */
 103
 104#define  SDIO_BUS_ASYNC_INT     0x20
 105
 106#define  SDIO_BUS_CD_DISABLE     0x80   /* disable pull-up on DAT3 (pin 1) */
 107
 108#define SDIO_CCCR_CAPS          0x08
 109
 110#define  SDIO_CCCR_CAP_SDC      0x01    /* can do CMD52 while data transfer */
 111#define  SDIO_CCCR_CAP_SMB      0x02    /* can do multi-block xfers (CMD53) */
 112#define  SDIO_CCCR_CAP_SRW      0x04    /* supports read-wait protocol */
 113#define  SDIO_CCCR_CAP_SBS      0x08    /* supports suspend/resume */
 114#define  SDIO_CCCR_CAP_S4MI     0x10    /* interrupt during 4-bit CMD53 */
 115#define  SDIO_CCCR_CAP_E4MI     0x20    /* enable ints during 4-bit CMD53 */
 116#define  SDIO_CCCR_CAP_LSC      0x40    /* low speed card */
 117#define  SDIO_CCCR_CAP_4BLS     0x80    /* 4 bit low speed card */
 118
 119#define SDIO_CCCR_CIS           0x09    /* common CIS pointer (3 bytes) */
 120
 121/* Following 4 regs are valid only if SBS is set */
 122#define SDIO_CCCR_SUSPEND       0x0c
 123#define SDIO_CCCR_SELx          0x0d
 124#define SDIO_CCCR_EXECx         0x0e
 125#define SDIO_CCCR_READYx        0x0f
 126
 127#define SDIO_CCCR_BLKSIZE       0x10
 128
 129#define SDIO_CCCR_POWER         0x12
 130
 131#define  SDIO_POWER_SMPC        0x01    /* Supports Master Power Control */
 132#define  SDIO_POWER_EMPC        0x02    /* Enable Master Power Control */
 133
 134#define SDIO_CCCR_SPEED         0x13
 135
 136#define  SDIO_SPEED_SHS         0x01    /* Supports High-Speed mode */
 137#define  SDIO_SPEED_BSS_SHIFT   1
 138#define  SDIO_SPEED_BSS_MASK    (7<<SDIO_SPEED_BSS_SHIFT)
 139#define  SDIO_SPEED_SDR12       (0<<SDIO_SPEED_BSS_SHIFT)
 140#define  SDIO_SPEED_SDR25       (1<<SDIO_SPEED_BSS_SHIFT)
 141#define  SDIO_SPEED_SDR50       (2<<SDIO_SPEED_BSS_SHIFT)
 142#define  SDIO_SPEED_SDR104      (3<<SDIO_SPEED_BSS_SHIFT)
 143#define  SDIO_SPEED_DDR50       (4<<SDIO_SPEED_BSS_SHIFT)
 144#define  SDIO_SPEED_EHS         SDIO_SPEED_SDR25        /* Enable High-Speed */
 145
 146#define SDIO_CCCR_UHS           0x14
 147#define  SDIO_UHS_SDR50         0x01
 148#define  SDIO_UHS_SDR104        0x02
 149#define  SDIO_UHS_DDR50         0x04
 150
 151#define SDIO_CCCR_DRIVE_STRENGTH 0x15
 152#define  SDIO_SDTx_MASK         0x07
 153#define  SDIO_DRIVE_SDTA        (1<<0)
 154#define  SDIO_DRIVE_SDTC        (1<<1)
 155#define  SDIO_DRIVE_SDTD        (1<<2)
 156#define  SDIO_DRIVE_DTSx_MASK   0x03
 157#define  SDIO_DRIVE_DTSx_SHIFT  4
 158#define  SDIO_DTSx_SET_TYPE_B   (0 << SDIO_DRIVE_DTSx_SHIFT)
 159#define  SDIO_DTSx_SET_TYPE_A   (1 << SDIO_DRIVE_DTSx_SHIFT)
 160#define  SDIO_DTSx_SET_TYPE_C   (2 << SDIO_DRIVE_DTSx_SHIFT)
 161#define  SDIO_DTSx_SET_TYPE_D   (3 << SDIO_DRIVE_DTSx_SHIFT)
 162/*
 163 * Function Basic Registers (FBR)
 164 */
 165
 166#define SDIO_FBR_BASE(f)        ((f) * 0x100) /* base of function f's FBRs */
 167
 168#define SDIO_FBR_STD_IF         0x00
 169
 170#define  SDIO_FBR_SUPPORTS_CSA  0x40    /* supports Code Storage Area */
 171#define  SDIO_FBR_ENABLE_CSA    0x80    /* enable Code Storage Area */
 172
 173#define SDIO_FBR_STD_IF_EXT     0x01
 174
 175#define SDIO_FBR_POWER          0x02
 176
 177#define  SDIO_FBR_POWER_SPS     0x01    /* Supports Power Selection */
 178#define  SDIO_FBR_POWER_EPS     0x02    /* Enable (low) Power Selection */
 179
 180#define SDIO_FBR_CIS            0x09    /* CIS pointer (3 bytes) */
 181
 182
 183#define SDIO_FBR_CSA            0x0C    /* CSA pointer (3 bytes) */
 184
 185#define SDIO_FBR_CSA_DATA       0x0F
 186
 187#define SDIO_FBR_BLKSIZE        0x10    /* block size (2 bytes) */
 188
 189#endif /* LINUX_MMC_SDIO_H */
 190