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32#ifndef __AMDGPU_DRM_H__
33#define __AMDGPU_DRM_H__
34
35#include "drm.h"
36
37#if defined(__cplusplus)
38extern "C" {
39#endif
40
41#define DRM_AMDGPU_GEM_CREATE 0x00
42#define DRM_AMDGPU_GEM_MMAP 0x01
43#define DRM_AMDGPU_CTX 0x02
44#define DRM_AMDGPU_BO_LIST 0x03
45#define DRM_AMDGPU_CS 0x04
46#define DRM_AMDGPU_INFO 0x05
47#define DRM_AMDGPU_GEM_METADATA 0x06
48#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07
49#define DRM_AMDGPU_GEM_VA 0x08
50#define DRM_AMDGPU_WAIT_CS 0x09
51#define DRM_AMDGPU_GEM_OP 0x10
52#define DRM_AMDGPU_GEM_USERPTR 0x11
53#define DRM_AMDGPU_WAIT_FENCES 0x12
54#define DRM_AMDGPU_VM 0x13
55#define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
56#define DRM_AMDGPU_SCHED 0x15
57
58#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
59#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
60#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
61#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
62#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
63#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
64#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
65#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
66#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
67#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
68#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
69#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
70#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
71#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
72#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
73#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
74
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97
98#define AMDGPU_GEM_DOMAIN_CPU 0x1
99#define AMDGPU_GEM_DOMAIN_GTT 0x2
100#define AMDGPU_GEM_DOMAIN_VRAM 0x4
101#define AMDGPU_GEM_DOMAIN_GDS 0x8
102#define AMDGPU_GEM_DOMAIN_GWS 0x10
103#define AMDGPU_GEM_DOMAIN_OA 0x20
104#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
105 AMDGPU_GEM_DOMAIN_GTT | \
106 AMDGPU_GEM_DOMAIN_VRAM | \
107 AMDGPU_GEM_DOMAIN_GDS | \
108 AMDGPU_GEM_DOMAIN_GWS | \
109 AMDGPU_GEM_DOMAIN_OA)
110
111
112#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
113
114#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
115
116#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
117
118#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
119
120#define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
121
122#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
123
124#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
125
126#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)
127
128
129
130
131#define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8)
132
133
134
135#define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9)
136
137
138
139
140#define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10)
141
142struct drm_amdgpu_gem_create_in {
143
144 __u64 bo_size;
145
146 __u64 alignment;
147
148 __u64 domains;
149
150 __u64 domain_flags;
151};
152
153struct drm_amdgpu_gem_create_out {
154
155 __u32 handle;
156 __u32 _pad;
157};
158
159union drm_amdgpu_gem_create {
160 struct drm_amdgpu_gem_create_in in;
161 struct drm_amdgpu_gem_create_out out;
162};
163
164
165#define AMDGPU_BO_LIST_OP_CREATE 0
166
167#define AMDGPU_BO_LIST_OP_DESTROY 1
168
169#define AMDGPU_BO_LIST_OP_UPDATE 2
170
171struct drm_amdgpu_bo_list_in {
172
173 __u32 operation;
174
175 __u32 list_handle;
176
177 __u32 bo_number;
178
179 __u32 bo_info_size;
180
181 __u64 bo_info_ptr;
182};
183
184struct drm_amdgpu_bo_list_entry {
185
186 __u32 bo_handle;
187
188 __u32 bo_priority;
189};
190
191struct drm_amdgpu_bo_list_out {
192
193 __u32 list_handle;
194 __u32 _pad;
195};
196
197union drm_amdgpu_bo_list {
198 struct drm_amdgpu_bo_list_in in;
199 struct drm_amdgpu_bo_list_out out;
200};
201
202
203#define AMDGPU_CTX_OP_ALLOC_CTX 1
204#define AMDGPU_CTX_OP_FREE_CTX 2
205#define AMDGPU_CTX_OP_QUERY_STATE 3
206#define AMDGPU_CTX_OP_QUERY_STATE2 4
207
208
209#define AMDGPU_CTX_NO_RESET 0
210
211#define AMDGPU_CTX_GUILTY_RESET 1
212
213#define AMDGPU_CTX_INNOCENT_RESET 2
214
215#define AMDGPU_CTX_UNKNOWN_RESET 3
216
217
218#define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0)
219
220#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
221
222#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)
223
224#define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3)
225#define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4)
226
227
228#define AMDGPU_CTX_PRIORITY_UNSET -2048
229#define AMDGPU_CTX_PRIORITY_VERY_LOW -1023
230#define AMDGPU_CTX_PRIORITY_LOW -512
231#define AMDGPU_CTX_PRIORITY_NORMAL 0
232
233
234
235
236#define AMDGPU_CTX_PRIORITY_HIGH 512
237#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
238
239struct drm_amdgpu_ctx_in {
240
241 __u32 op;
242
243 __u32 flags;
244 __u32 ctx_id;
245
246 __s32 priority;
247};
248
249union drm_amdgpu_ctx_out {
250 struct {
251 __u32 ctx_id;
252 __u32 _pad;
253 } alloc;
254
255 struct {
256
257 __u64 flags;
258
259 __u32 hangs;
260
261 __u32 reset_status;
262 } state;
263};
264
265union drm_amdgpu_ctx {
266 struct drm_amdgpu_ctx_in in;
267 union drm_amdgpu_ctx_out out;
268};
269
270
271#define AMDGPU_VM_OP_RESERVE_VMID 1
272#define AMDGPU_VM_OP_UNRESERVE_VMID 2
273
274struct drm_amdgpu_vm_in {
275
276 __u32 op;
277 __u32 flags;
278};
279
280struct drm_amdgpu_vm_out {
281
282 __u64 flags;
283};
284
285union drm_amdgpu_vm {
286 struct drm_amdgpu_vm_in in;
287 struct drm_amdgpu_vm_out out;
288};
289
290
291#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1
292#define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2
293
294struct drm_amdgpu_sched_in {
295
296 __u32 op;
297 __u32 fd;
298
299 __s32 priority;
300 __u32 ctx_id;
301};
302
303union drm_amdgpu_sched {
304 struct drm_amdgpu_sched_in in;
305};
306
307
308
309
310
311
312#define AMDGPU_GEM_USERPTR_READONLY (1 << 0)
313#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
314#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
315#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
316
317struct drm_amdgpu_gem_userptr {
318 __u64 addr;
319 __u64 size;
320
321 __u32 flags;
322
323 __u32 handle;
324};
325
326
327
328#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
329#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
330#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4
331#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f
332#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9
333#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7
334#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12
335#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7
336#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15
337#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3
338#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17
339#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3
340#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19
341#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3
342#define AMDGPU_TILING_NUM_BANKS_SHIFT 21
343#define AMDGPU_TILING_NUM_BANKS_MASK 0x3
344
345
346#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
347#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
348#define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5
349#define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF
350#define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29
351#define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF
352#define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43
353#define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1
354#define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44
355#define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1
356#define AMDGPU_TILING_SCANOUT_SHIFT 63
357#define AMDGPU_TILING_SCANOUT_MASK 0x1
358
359
360#define AMDGPU_TILING_SET(field, value) \
361 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
362#define AMDGPU_TILING_GET(value, field) \
363 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
364
365#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
366#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
367
368
369struct drm_amdgpu_gem_metadata {
370
371 __u32 handle;
372
373 __u32 op;
374 struct {
375
376 __u64 flags;
377
378 __u64 tiling_info;
379 __u32 data_size_bytes;
380 __u32 data[64];
381 } data;
382};
383
384struct drm_amdgpu_gem_mmap_in {
385
386 __u32 handle;
387 __u32 _pad;
388};
389
390struct drm_amdgpu_gem_mmap_out {
391
392 __u64 addr_ptr;
393};
394
395union drm_amdgpu_gem_mmap {
396 struct drm_amdgpu_gem_mmap_in in;
397 struct drm_amdgpu_gem_mmap_out out;
398};
399
400struct drm_amdgpu_gem_wait_idle_in {
401
402 __u32 handle;
403
404 __u32 flags;
405
406 __u64 timeout;
407};
408
409struct drm_amdgpu_gem_wait_idle_out {
410
411 __u32 status;
412
413 __u32 domain;
414};
415
416union drm_amdgpu_gem_wait_idle {
417 struct drm_amdgpu_gem_wait_idle_in in;
418 struct drm_amdgpu_gem_wait_idle_out out;
419};
420
421struct drm_amdgpu_wait_cs_in {
422
423
424
425
426 __u64 handle;
427
428 __u64 timeout;
429 __u32 ip_type;
430 __u32 ip_instance;
431 __u32 ring;
432 __u32 ctx_id;
433};
434
435struct drm_amdgpu_wait_cs_out {
436
437 __u64 status;
438};
439
440union drm_amdgpu_wait_cs {
441 struct drm_amdgpu_wait_cs_in in;
442 struct drm_amdgpu_wait_cs_out out;
443};
444
445struct drm_amdgpu_fence {
446 __u32 ctx_id;
447 __u32 ip_type;
448 __u32 ip_instance;
449 __u32 ring;
450 __u64 seq_no;
451};
452
453struct drm_amdgpu_wait_fences_in {
454
455 __u64 fences;
456 __u32 fence_count;
457 __u32 wait_all;
458 __u64 timeout_ns;
459};
460
461struct drm_amdgpu_wait_fences_out {
462 __u32 status;
463 __u32 first_signaled;
464};
465
466union drm_amdgpu_wait_fences {
467 struct drm_amdgpu_wait_fences_in in;
468 struct drm_amdgpu_wait_fences_out out;
469};
470
471#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
472#define AMDGPU_GEM_OP_SET_PLACEMENT 1
473
474
475struct drm_amdgpu_gem_op {
476
477 __u32 handle;
478
479 __u32 op;
480
481 __u64 value;
482};
483
484#define AMDGPU_VA_OP_MAP 1
485#define AMDGPU_VA_OP_UNMAP 2
486#define AMDGPU_VA_OP_CLEAR 3
487#define AMDGPU_VA_OP_REPLACE 4
488
489
490#define AMDGPU_VM_DELAY_UPDATE (1 << 0)
491
492
493
494#define AMDGPU_VM_PAGE_READABLE (1 << 1)
495
496#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
497
498#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
499
500#define AMDGPU_VM_PAGE_PRT (1 << 4)
501
502#define AMDGPU_VM_MTYPE_MASK (0xf << 5)
503
504#define AMDGPU_VM_MTYPE_DEFAULT (0 << 5)
505
506#define AMDGPU_VM_MTYPE_NC (1 << 5)
507
508#define AMDGPU_VM_MTYPE_WC (2 << 5)
509
510#define AMDGPU_VM_MTYPE_CC (3 << 5)
511
512#define AMDGPU_VM_MTYPE_UC (4 << 5)
513
514#define AMDGPU_VM_MTYPE_RW (5 << 5)
515
516struct drm_amdgpu_gem_va {
517
518 __u32 handle;
519 __u32 _pad;
520
521 __u32 operation;
522
523 __u32 flags;
524
525 __u64 va_address;
526
527 __u64 offset_in_bo;
528
529 __u64 map_size;
530};
531
532#define AMDGPU_HW_IP_GFX 0
533#define AMDGPU_HW_IP_COMPUTE 1
534#define AMDGPU_HW_IP_DMA 2
535#define AMDGPU_HW_IP_UVD 3
536#define AMDGPU_HW_IP_VCE 4
537#define AMDGPU_HW_IP_UVD_ENC 5
538#define AMDGPU_HW_IP_VCN_DEC 6
539#define AMDGPU_HW_IP_VCN_ENC 7
540#define AMDGPU_HW_IP_VCN_JPEG 8
541#define AMDGPU_HW_IP_NUM 9
542
543#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
544
545#define AMDGPU_CHUNK_ID_IB 0x01
546#define AMDGPU_CHUNK_ID_FENCE 0x02
547#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
548#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
549#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
550#define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
551#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
552#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08
553#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09
554
555struct drm_amdgpu_cs_chunk {
556 __u32 chunk_id;
557 __u32 length_dw;
558 __u64 chunk_data;
559};
560
561struct drm_amdgpu_cs_in {
562
563 __u32 ctx_id;
564
565 __u32 bo_list_handle;
566 __u32 num_chunks;
567 __u32 flags;
568
569 __u64 chunks;
570};
571
572struct drm_amdgpu_cs_out {
573 __u64 handle;
574};
575
576union drm_amdgpu_cs {
577 struct drm_amdgpu_cs_in in;
578 struct drm_amdgpu_cs_out out;
579};
580
581
582
583
584#define AMDGPU_IB_FLAG_CE (1<<0)
585
586
587#define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
588
589
590#define AMDGPU_IB_FLAG_PREEMPT (1<<2)
591
592
593
594#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
595
596
597
598
599#define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)
600
601
602
603#define AMDGPU_IB_FLAGS_SECURE (1 << 5)
604
605
606
607#define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6)
608
609struct drm_amdgpu_cs_chunk_ib {
610 __u32 _pad;
611
612 __u32 flags;
613
614 __u64 va_start;
615
616 __u32 ib_bytes;
617
618 __u32 ip_type;
619
620 __u32 ip_instance;
621
622 __u32 ring;
623};
624
625struct drm_amdgpu_cs_chunk_dep {
626 __u32 ip_type;
627 __u32 ip_instance;
628 __u32 ring;
629 __u32 ctx_id;
630 __u64 handle;
631};
632
633struct drm_amdgpu_cs_chunk_fence {
634 __u32 handle;
635 __u32 offset;
636};
637
638struct drm_amdgpu_cs_chunk_sem {
639 __u32 handle;
640};
641
642struct drm_amdgpu_cs_chunk_syncobj {
643 __u32 handle;
644 __u32 flags;
645 __u64 point;
646};
647
648#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0
649#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1
650#define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
651
652union drm_amdgpu_fence_to_handle {
653 struct {
654 struct drm_amdgpu_fence fence;
655 __u32 what;
656 __u32 pad;
657 } in;
658 struct {
659 __u32 handle;
660 } out;
661};
662
663struct drm_amdgpu_cs_chunk_data {
664 union {
665 struct drm_amdgpu_cs_chunk_ib ib_data;
666 struct drm_amdgpu_cs_chunk_fence fence_data;
667 };
668};
669
670
671
672
673
674#define AMDGPU_IDS_FLAGS_FUSION 0x1
675#define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
676#define AMDGPU_IDS_FLAGS_TMZ 0x4
677
678
679#define AMDGPU_INFO_ACCEL_WORKING 0x00
680
681#define AMDGPU_INFO_CRTC_FROM_ID 0x01
682
683#define AMDGPU_INFO_HW_IP_INFO 0x02
684
685#define AMDGPU_INFO_HW_IP_COUNT 0x03
686
687#define AMDGPU_INFO_TIMESTAMP 0x05
688
689#define AMDGPU_INFO_FW_VERSION 0x0e
690
691 #define AMDGPU_INFO_FW_VCE 0x1
692
693 #define AMDGPU_INFO_FW_UVD 0x2
694
695 #define AMDGPU_INFO_FW_GMC 0x03
696
697 #define AMDGPU_INFO_FW_GFX_ME 0x04
698
699 #define AMDGPU_INFO_FW_GFX_PFP 0x05
700
701 #define AMDGPU_INFO_FW_GFX_CE 0x06
702
703 #define AMDGPU_INFO_FW_GFX_RLC 0x07
704
705 #define AMDGPU_INFO_FW_GFX_MEC 0x08
706
707 #define AMDGPU_INFO_FW_SMC 0x0a
708
709 #define AMDGPU_INFO_FW_SDMA 0x0b
710
711 #define AMDGPU_INFO_FW_SOS 0x0c
712
713 #define AMDGPU_INFO_FW_ASD 0x0d
714
715 #define AMDGPU_INFO_FW_VCN 0x0e
716
717 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f
718
719 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
720
721 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
722
723 #define AMDGPU_INFO_FW_DMCU 0x12
724 #define AMDGPU_INFO_FW_TA 0x13
725
726 #define AMDGPU_INFO_FW_DMCUB 0x14
727
728
729#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
730
731#define AMDGPU_INFO_VRAM_USAGE 0x10
732
733#define AMDGPU_INFO_GTT_USAGE 0x11
734
735#define AMDGPU_INFO_GDS_CONFIG 0x13
736
737#define AMDGPU_INFO_VRAM_GTT 0x14
738
739#define AMDGPU_INFO_READ_MMR_REG 0x15
740
741#define AMDGPU_INFO_DEV_INFO 0x16
742
743#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
744
745#define AMDGPU_INFO_NUM_EVICTIONS 0x18
746
747#define AMDGPU_INFO_MEMORY 0x19
748
749#define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A
750
751#define AMDGPU_INFO_VBIOS 0x1B
752
753 #define AMDGPU_INFO_VBIOS_SIZE 0x1
754
755 #define AMDGPU_INFO_VBIOS_IMAGE 0x2
756
757#define AMDGPU_INFO_NUM_HANDLES 0x1C
758
759#define AMDGPU_INFO_SENSOR 0x1D
760
761 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1
762
763 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2
764
765 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3
766
767 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4
768
769 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5
770
771 #define AMDGPU_INFO_SENSOR_VDDNB 0x6
772
773 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7
774
775 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8
776
777 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9
778
779#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
780#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
781
782#define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20
783
784
785#define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0)
786
787#define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1)
788
789#define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2)
790
791#define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3)
792
793#define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4)
794
795#define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5)
796
797#define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6)
798
799#define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7)
800
801#define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8)
802
803#define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9)
804
805#define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10)
806
807#define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11)
808
809#define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12)
810
811#define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13)
812
813#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
814#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
815#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
816#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff
817
818struct drm_amdgpu_query_fw {
819
820 __u32 fw_type;
821
822
823
824
825 __u32 ip_instance;
826
827
828
829
830 __u32 index;
831 __u32 _pad;
832};
833
834
835struct drm_amdgpu_info {
836
837 __u64 return_pointer;
838
839
840 __u32 return_size;
841
842 __u32 query;
843
844 union {
845 struct {
846 __u32 id;
847 __u32 _pad;
848 } mode_crtc;
849
850 struct {
851
852 __u32 type;
853
854
855
856
857 __u32 ip_instance;
858 } query_hw_ip;
859
860 struct {
861 __u32 dword_offset;
862
863 __u32 count;
864 __u32 instance;
865
866 __u32 flags;
867 } read_mmr_reg;
868
869 struct drm_amdgpu_query_fw query_fw;
870
871 struct {
872 __u32 type;
873 __u32 offset;
874 } vbios_info;
875
876 struct {
877 __u32 type;
878 } sensor_info;
879 };
880};
881
882struct drm_amdgpu_info_gds {
883
884 __u32 gds_gfx_partition_size;
885
886 __u32 compute_partition_size;
887
888 __u32 gds_total_size;
889
890 __u32 gws_per_gfx_partition;
891
892 __u32 gws_per_compute_partition;
893
894 __u32 oa_per_gfx_partition;
895
896 __u32 oa_per_compute_partition;
897 __u32 _pad;
898};
899
900struct drm_amdgpu_info_vram_gtt {
901 __u64 vram_size;
902 __u64 vram_cpu_accessible_size;
903 __u64 gtt_size;
904};
905
906struct drm_amdgpu_heap_info {
907
908 __u64 total_heap_size;
909
910
911 __u64 usable_heap_size;
912
913
914
915
916
917
918
919 __u64 heap_usage;
920
921
922
923
924
925 __u64 max_allocation;
926};
927
928struct drm_amdgpu_memory_info {
929 struct drm_amdgpu_heap_info vram;
930 struct drm_amdgpu_heap_info cpu_accessible_vram;
931 struct drm_amdgpu_heap_info gtt;
932};
933
934struct drm_amdgpu_info_firmware {
935 __u32 ver;
936 __u32 feature;
937};
938
939#define AMDGPU_VRAM_TYPE_UNKNOWN 0
940#define AMDGPU_VRAM_TYPE_GDDR1 1
941#define AMDGPU_VRAM_TYPE_DDR2 2
942#define AMDGPU_VRAM_TYPE_GDDR3 3
943#define AMDGPU_VRAM_TYPE_GDDR4 4
944#define AMDGPU_VRAM_TYPE_GDDR5 5
945#define AMDGPU_VRAM_TYPE_HBM 6
946#define AMDGPU_VRAM_TYPE_DDR3 7
947#define AMDGPU_VRAM_TYPE_DDR4 8
948#define AMDGPU_VRAM_TYPE_GDDR6 9
949
950struct drm_amdgpu_info_device {
951
952 __u32 device_id;
953
954 __u32 chip_rev;
955 __u32 external_rev;
956
957 __u32 pci_rev;
958 __u32 family;
959 __u32 num_shader_engines;
960 __u32 num_shader_arrays_per_engine;
961
962 __u32 gpu_counter_freq;
963 __u64 max_engine_clock;
964 __u64 max_memory_clock;
965
966 __u32 cu_active_number;
967
968 __u32 cu_ao_mask;
969 __u32 cu_bitmap[4][4];
970
971 __u32 enabled_rb_pipes_mask;
972 __u32 num_rb_pipes;
973 __u32 num_hw_gfx_contexts;
974 __u32 _pad;
975 __u64 ids_flags;
976
977 __u64 virtual_address_offset;
978
979 __u64 virtual_address_max;
980
981 __u32 virtual_address_alignment;
982
983 __u32 pte_fragment_size;
984 __u32 gart_page_size;
985
986 __u32 ce_ram_size;
987
988 __u32 vram_type;
989
990 __u32 vram_bit_width;
991
992 __u32 vce_harvest_config;
993
994 __u32 gc_double_offchip_lds_buf;
995
996 __u64 prim_buf_gpu_addr;
997
998 __u64 pos_buf_gpu_addr;
999
1000 __u64 cntl_sb_buf_gpu_addr;
1001
1002 __u64 param_buf_gpu_addr;
1003 __u32 prim_buf_size;
1004 __u32 pos_buf_size;
1005 __u32 cntl_sb_buf_size;
1006 __u32 param_buf_size;
1007
1008 __u32 wave_front_size;
1009
1010 __u32 num_shader_visible_vgprs;
1011
1012 __u32 num_cu_per_sh;
1013
1014 __u32 num_tcc_blocks;
1015
1016 __u32 gs_vgt_table_depth;
1017
1018 __u32 gs_prim_buffer_depth;
1019
1020 __u32 max_gs_waves_per_vgt;
1021 __u32 _pad1;
1022
1023 __u32 cu_ao_bitmap[4][4];
1024
1025 __u64 high_va_offset;
1026
1027 __u64 high_va_max;
1028
1029 __u32 pa_sc_tile_steering_override;
1030
1031 __u64 tcc_disabled_mask;
1032};
1033
1034struct drm_amdgpu_info_hw_ip {
1035
1036 __u32 hw_ip_version_major;
1037 __u32 hw_ip_version_minor;
1038
1039 __u64 capabilities_flags;
1040
1041 __u32 ib_start_alignment;
1042
1043 __u32 ib_size_alignment;
1044
1045 __u32 available_rings;
1046 __u32 _pad;
1047};
1048
1049struct drm_amdgpu_info_num_handles {
1050
1051 __u32 uvd_max_handles;
1052
1053 __u32 uvd_used_handles;
1054};
1055
1056#define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6
1057
1058struct drm_amdgpu_info_vce_clock_table_entry {
1059
1060 __u32 sclk;
1061
1062 __u32 mclk;
1063
1064 __u32 eclk;
1065 __u32 pad;
1066};
1067
1068struct drm_amdgpu_info_vce_clock_table {
1069 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
1070 __u32 num_valid_entries;
1071 __u32 pad;
1072};
1073
1074
1075
1076
1077#define AMDGPU_FAMILY_UNKNOWN 0
1078#define AMDGPU_FAMILY_SI 110
1079#define AMDGPU_FAMILY_CI 120
1080#define AMDGPU_FAMILY_KV 125
1081#define AMDGPU_FAMILY_VI 130
1082#define AMDGPU_FAMILY_CZ 135
1083#define AMDGPU_FAMILY_AI 141
1084#define AMDGPU_FAMILY_RV 142
1085#define AMDGPU_FAMILY_NV 143
1086
1087#if defined(__cplusplus)
1088}
1089#endif
1090
1091#endif
1092