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47#ifndef __VMW_PVRDMA_ABI_H__
48#define __VMW_PVRDMA_ABI_H__
49
50#include <linux/types.h>
51
52#define PVRDMA_UVERBS_ABI_VERSION 3
53#define PVRDMA_UAR_HANDLE_MASK 0x00FFFFFF
54#define PVRDMA_UAR_QP_OFFSET 0
55#define PVRDMA_UAR_QP_SEND (1 << 30)
56#define PVRDMA_UAR_QP_RECV (1 << 31)
57#define PVRDMA_UAR_CQ_OFFSET 4
58#define PVRDMA_UAR_CQ_ARM_SOL (1 << 29)
59#define PVRDMA_UAR_CQ_ARM (1 << 30)
60#define PVRDMA_UAR_CQ_POLL (1 << 31)
61#define PVRDMA_UAR_SRQ_OFFSET 8
62#define PVRDMA_UAR_SRQ_RECV (1 << 30)
63
64enum pvrdma_wr_opcode {
65 PVRDMA_WR_RDMA_WRITE,
66 PVRDMA_WR_RDMA_WRITE_WITH_IMM,
67 PVRDMA_WR_SEND,
68 PVRDMA_WR_SEND_WITH_IMM,
69 PVRDMA_WR_RDMA_READ,
70 PVRDMA_WR_ATOMIC_CMP_AND_SWP,
71 PVRDMA_WR_ATOMIC_FETCH_AND_ADD,
72 PVRDMA_WR_LSO,
73 PVRDMA_WR_SEND_WITH_INV,
74 PVRDMA_WR_RDMA_READ_WITH_INV,
75 PVRDMA_WR_LOCAL_INV,
76 PVRDMA_WR_FAST_REG_MR,
77 PVRDMA_WR_MASKED_ATOMIC_CMP_AND_SWP,
78 PVRDMA_WR_MASKED_ATOMIC_FETCH_AND_ADD,
79 PVRDMA_WR_BIND_MW,
80 PVRDMA_WR_REG_SIG_MR,
81 PVRDMA_WR_ERROR,
82};
83
84enum pvrdma_wc_status {
85 PVRDMA_WC_SUCCESS,
86 PVRDMA_WC_LOC_LEN_ERR,
87 PVRDMA_WC_LOC_QP_OP_ERR,
88 PVRDMA_WC_LOC_EEC_OP_ERR,
89 PVRDMA_WC_LOC_PROT_ERR,
90 PVRDMA_WC_WR_FLUSH_ERR,
91 PVRDMA_WC_MW_BIND_ERR,
92 PVRDMA_WC_BAD_RESP_ERR,
93 PVRDMA_WC_LOC_ACCESS_ERR,
94 PVRDMA_WC_REM_INV_REQ_ERR,
95 PVRDMA_WC_REM_ACCESS_ERR,
96 PVRDMA_WC_REM_OP_ERR,
97 PVRDMA_WC_RETRY_EXC_ERR,
98 PVRDMA_WC_RNR_RETRY_EXC_ERR,
99 PVRDMA_WC_LOC_RDD_VIOL_ERR,
100 PVRDMA_WC_REM_INV_RD_REQ_ERR,
101 PVRDMA_WC_REM_ABORT_ERR,
102 PVRDMA_WC_INV_EECN_ERR,
103 PVRDMA_WC_INV_EEC_STATE_ERR,
104 PVRDMA_WC_FATAL_ERR,
105 PVRDMA_WC_RESP_TIMEOUT_ERR,
106 PVRDMA_WC_GENERAL_ERR,
107};
108
109enum pvrdma_wc_opcode {
110 PVRDMA_WC_SEND,
111 PVRDMA_WC_RDMA_WRITE,
112 PVRDMA_WC_RDMA_READ,
113 PVRDMA_WC_COMP_SWAP,
114 PVRDMA_WC_FETCH_ADD,
115 PVRDMA_WC_BIND_MW,
116 PVRDMA_WC_LSO,
117 PVRDMA_WC_LOCAL_INV,
118 PVRDMA_WC_FAST_REG_MR,
119 PVRDMA_WC_MASKED_COMP_SWAP,
120 PVRDMA_WC_MASKED_FETCH_ADD,
121 PVRDMA_WC_RECV = 1 << 7,
122 PVRDMA_WC_RECV_RDMA_WITH_IMM,
123};
124
125enum pvrdma_wc_flags {
126 PVRDMA_WC_GRH = 1 << 0,
127 PVRDMA_WC_WITH_IMM = 1 << 1,
128 PVRDMA_WC_WITH_INVALIDATE = 1 << 2,
129 PVRDMA_WC_IP_CSUM_OK = 1 << 3,
130 PVRDMA_WC_WITH_SMAC = 1 << 4,
131 PVRDMA_WC_WITH_VLAN = 1 << 5,
132 PVRDMA_WC_WITH_NETWORK_HDR_TYPE = 1 << 6,
133 PVRDMA_WC_FLAGS_MAX = PVRDMA_WC_WITH_NETWORK_HDR_TYPE,
134};
135
136struct pvrdma_alloc_ucontext_resp {
137 __u32 qp_tab_size;
138 __u32 reserved;
139};
140
141struct pvrdma_alloc_pd_resp {
142 __u32 pdn;
143 __u32 reserved;
144};
145
146struct pvrdma_create_cq {
147 __aligned_u64 buf_addr;
148 __u32 buf_size;
149 __u32 reserved;
150};
151
152struct pvrdma_create_cq_resp {
153 __u32 cqn;
154 __u32 reserved;
155};
156
157struct pvrdma_resize_cq {
158 __aligned_u64 buf_addr;
159 __u32 buf_size;
160 __u32 reserved;
161};
162
163struct pvrdma_create_srq {
164 __aligned_u64 buf_addr;
165 __u32 buf_size;
166 __u32 reserved;
167};
168
169struct pvrdma_create_srq_resp {
170 __u32 srqn;
171 __u32 reserved;
172};
173
174struct pvrdma_create_qp {
175 __aligned_u64 rbuf_addr;
176 __aligned_u64 sbuf_addr;
177 __u32 rbuf_size;
178 __u32 sbuf_size;
179 __aligned_u64 qp_addr;
180};
181
182struct pvrdma_create_qp_resp {
183 __u32 qpn;
184 __u32 qp_handle;
185};
186
187
188struct pvrdma_ex_cmp_swap {
189 __aligned_u64 swap_val;
190 __aligned_u64 compare_val;
191 __aligned_u64 swap_mask;
192 __aligned_u64 compare_mask;
193};
194
195
196struct pvrdma_ex_fetch_add {
197 __aligned_u64 add_val;
198 __aligned_u64 field_boundary;
199};
200
201
202struct pvrdma_av {
203 __u32 port_pd;
204 __u32 sl_tclass_flowlabel;
205 __u8 dgid[16];
206 __u8 src_path_bits;
207 __u8 gid_index;
208 __u8 stat_rate;
209 __u8 hop_limit;
210 __u8 dmac[6];
211 __u8 reserved[6];
212};
213
214
215struct pvrdma_sge {
216 __aligned_u64 addr;
217 __u32 length;
218 __u32 lkey;
219};
220
221
222struct pvrdma_rq_wqe_hdr {
223 __aligned_u64 wr_id;
224 __u32 num_sge;
225 __u32 total_len;
226};
227
228
229
230struct pvrdma_sq_wqe_hdr {
231 __aligned_u64 wr_id;
232 __u32 num_sge;
233 __u32 total_len;
234 __u32 opcode;
235 __u32 send_flags;
236 union {
237 __be32 imm_data;
238 __u32 invalidate_rkey;
239 } ex;
240 __u32 reserved;
241 union {
242 struct {
243 __aligned_u64 remote_addr;
244 __u32 rkey;
245 __u8 reserved[4];
246 } rdma;
247 struct {
248 __aligned_u64 remote_addr;
249 __aligned_u64 compare_add;
250 __aligned_u64 swap;
251 __u32 rkey;
252 __u32 reserved;
253 } atomic;
254 struct {
255 __aligned_u64 remote_addr;
256 __u32 log_arg_sz;
257 __u32 rkey;
258 union {
259 struct pvrdma_ex_cmp_swap cmp_swap;
260 struct pvrdma_ex_fetch_add fetch_add;
261 } wr_data;
262 } masked_atomics;
263 struct {
264 __aligned_u64 iova_start;
265 __aligned_u64 pl_pdir_dma;
266 __u32 page_shift;
267 __u32 page_list_len;
268 __u32 length;
269 __u32 access_flags;
270 __u32 rkey;
271 __u32 reserved;
272 } fast_reg;
273 struct {
274 __u32 remote_qpn;
275 __u32 remote_qkey;
276 struct pvrdma_av av;
277 } ud;
278 } wr;
279};
280
281
282
283struct pvrdma_cqe {
284 __aligned_u64 wr_id;
285 __aligned_u64 qp;
286 __u32 opcode;
287 __u32 status;
288 __u32 byte_len;
289 __be32 imm_data;
290 __u32 src_qp;
291 __u32 wc_flags;
292 __u32 vendor_err;
293 __u16 pkey_index;
294 __u16 slid;
295 __u8 sl;
296 __u8 dlid_path_bits;
297 __u8 port_num;
298 __u8 smac[6];
299 __u8 network_hdr_type;
300 __u8 reserved2[6];
301};
302
303#endif
304