// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * HD audio interface patch for Creative CA0132 chip
 *
 * Copyright (c) 2011, Creative Technology Ltd.
 *
 * Based on patch_ca0110.c
 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
 */

#include <linux/init.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/mutex.h>
#include <linux/module.h>
#include <linux/firmware.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/io.h>
#include <linux/pci.h>
#include <asm/io.h>
#include <sound/core.h>
#include <sound/hda_codec.h>
#include "hda_local.h"
#include "hda_auto_parser.h"
#include "hda_jack.h"

#include "ca0132_regs.h"

/* Enable this to see controls for tuning purpose. */
/*#define ENABLE_TUNING_CONTROLS*/

#ifdef ENABLE_TUNING_CONTROLS
#include <sound/tlv.h>
#endif

#define FLOAT_ZERO      0x00000000
#define FLOAT_ONE       0x3f800000
#define FLOAT_TWO       0x40000000
#define FLOAT_THREE     0x40400000
#define FLOAT_FIVE      0x40a00000
#define FLOAT_SIX       0x40c00000
#define FLOAT_EIGHT     0x41000000
#define FLOAT_MINUS_5   0xc0a00000

#define UNSOL_TAG_DSP   0x16

#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)

#define DMA_TRANSFER_FRAME_SIZE_NWORDS          8
#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS      32
#define DMA_OVERLAY_FRAME_SIZE_NWORDS           2

#define MASTERCONTROL                           0x80
#define MASTERCONTROL_ALLOC_DMA_CHAN            10
#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS  60

#define WIDGET_CHIP_CTRL      0x15
#define WIDGET_DSP_CTRL       0x16

#define MEM_CONNID_MICIN1     3
#define MEM_CONNID_MICIN2     5
#define MEM_CONNID_MICOUT1    12
#define MEM_CONNID_MICOUT2    14
#define MEM_CONNID_WUH        10
#define MEM_CONNID_DSP        16
#define MEM_CONNID_DMIC       100

#define SCP_SET    0
#define SCP_GET    1

#define EFX_FILE   "ctefx.bin"
#define DESKTOP_EFX_FILE   "ctefx-desktop.bin"
#define R3DI_EFX_FILE  "ctefx-r3di.bin"

#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
MODULE_FIRMWARE(EFX_FILE);
MODULE_FIRMWARE(DESKTOP_EFX_FILE);
MODULE_FIRMWARE(R3DI_EFX_FILE);
#endif

static const char *const dirstr[2] = { "Playback", "Capture" };

#define NUM_OF_OUTPUTS 2
static const char *const out_type_str[2] = { "Speakers", "Headphone" };
enum {
        SPEAKER_OUT,
        HEADPHONE_OUT,
};

enum {
        DIGITAL_MIC,
        LINE_MIC_IN
};

/* Strings for Input Source Enum Control */
static const char *const in_src_str[3] = {"Rear Mic", "Line", "Front Mic" };
#define IN_SRC_NUM_OF_INPUTS 3
enum {
        REAR_MIC,
        REAR_LINE_IN,
        FRONT_MIC,
};

enum {
#define VNODE_START_NID    0x80
        VNID_SPK = VNODE_START_NID,                     /* Speaker vnid */
        VNID_MIC,
        VNID_HP_SEL,
        VNID_AMIC1_SEL,
        VNID_HP_ASEL,
        VNID_AMIC1_ASEL,
        VNODE_END_NID,
#define VNODES_COUNT  (VNODE_END_NID - VNODE_START_NID)

#define EFFECT_START_NID    0x90
#define OUT_EFFECT_START_NID    EFFECT_START_NID
        SURROUND = OUT_EFFECT_START_NID,
        CRYSTALIZER,
        DIALOG_PLUS,
        SMART_VOLUME,
        X_BASS,
        EQUALIZER,
        OUT_EFFECT_END_NID,
#define OUT_EFFECTS_COUNT  (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)

#define IN_EFFECT_START_NID  OUT_EFFECT_END_NID
        ECHO_CANCELLATION = IN_EFFECT_START_NID,
        VOICE_FOCUS,
        MIC_SVM,
        NOISE_REDUCTION,
        IN_EFFECT_END_NID,
#define IN_EFFECTS_COUNT  (IN_EFFECT_END_NID - IN_EFFECT_START_NID)

        VOICEFX = IN_EFFECT_END_NID,
        PLAY_ENHANCEMENT,
        CRYSTAL_VOICE,
        EFFECT_END_NID,
        OUTPUT_SOURCE_ENUM,
        INPUT_SOURCE_ENUM,
        XBASS_XOVER,
        EQ_PRESET_ENUM,
        SMART_VOLUME_ENUM,
        MIC_BOOST_ENUM,
        AE5_HEADPHONE_GAIN_ENUM,
        AE5_SOUND_FILTER_ENUM,
        ZXR_HEADPHONE_GAIN,
        SPEAKER_CHANNEL_CFG_ENUM,
        SPEAKER_FULL_RANGE_FRONT,
        SPEAKER_FULL_RANGE_REAR,
        BASS_REDIRECTION,
        BASS_REDIRECTION_XOVER,
#define EFFECTS_COUNT  (EFFECT_END_NID - EFFECT_START_NID)
};

/* Effects values size*/
#define EFFECT_VALS_MAX_COUNT 12

/*
 * Default values for the effect slider controls, they are in order of their
 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
 * X-bass.
 */
static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
/* Amount of effect level sliders for ca0132_alt controls. */
#define EFFECT_LEVEL_SLIDERS 5

/* Latency introduced by DSP blocks in milliseconds. */
#define DSP_CAPTURE_INIT_LATENCY        0
#define DSP_CRYSTAL_VOICE_LATENCY       124
#define DSP_PLAYBACK_INIT_LATENCY       13
#define DSP_PLAY_ENHANCEMENT_LATENCY    30
#define DSP_SPEAKER_OUT_LATENCY         7

struct ct_effect {
        char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
        hda_nid_t nid;
        int mid; /*effect module ID*/
        int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
        int direct; /* 0:output; 1:input*/
        int params; /* number of default non-on/off params */
        /*effect default values, 1st is on/off. */
        unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
};

#define EFX_DIR_OUT 0
#define EFX_DIR_IN  1

static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
        { .name = "Surround",
          .nid = SURROUND,
          .mid = 0x96,
          .reqs = {0, 1},
          .direct = EFX_DIR_OUT,
          .params = 1,
          .def_vals = {0x3F800000, 0x3F2B851F}
        },
        { .name = "Crystalizer",
          .nid = CRYSTALIZER,
          .mid = 0x96,
          .reqs = {7, 8},
          .direct = EFX_DIR_OUT,
          .params = 1,
          .def_vals = {0x3F800000, 0x3F266666}
        },
        { .name = "Dialog Plus",
          .nid = DIALOG_PLUS,
          .mid = 0x96,
          .reqs = {2, 3},
          .direct = EFX_DIR_OUT,
          .params = 1,
          .def_vals = {0x00000000, 0x3F000000}
        },
        { .name = "Smart Volume",
          .nid = SMART_VOLUME,
          .mid = 0x96,
          .reqs = {4, 5, 6},
          .direct = EFX_DIR_OUT,
          .params = 2,
          .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
        },
        { .name = "X-Bass",
          .nid = X_BASS,
          .mid = 0x96,
          .reqs = {24, 23, 25},
          .direct = EFX_DIR_OUT,
          .params = 2,
          .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
        },
        { .name = "Equalizer",
          .nid = EQUALIZER,
          .mid = 0x96,
          .reqs = {9, 10, 11, 12, 13, 14,
                        15, 16, 17, 18, 19, 20},
          .direct = EFX_DIR_OUT,
          .params = 11,
          .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
                       0x00000000, 0x00000000, 0x00000000, 0x00000000,
                       0x00000000, 0x00000000, 0x00000000, 0x00000000}
        },
        { .name = "Echo Cancellation",
          .nid = ECHO_CANCELLATION,
          .mid = 0x95,
          .reqs = {0, 1, 2, 3},
          .direct = EFX_DIR_IN,
          .params = 3,
          .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
        },
        { .name = "Voice Focus",
          .nid = VOICE_FOCUS,
          .mid = 0x95,
          .reqs = {6, 7, 8, 9},
          .direct = EFX_DIR_IN,
          .params = 3,
          .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
        },
        { .name = "Mic SVM",
          .nid = MIC_SVM,
          .mid = 0x95,
          .reqs = {44, 45},
          .direct = EFX_DIR_IN,
          .params = 1,
          .def_vals = {0x00000000, 0x3F3D70A4}
        },
        { .name = "Noise Reduction",
          .nid = NOISE_REDUCTION,
          .mid = 0x95,
          .reqs = {4, 5},
          .direct = EFX_DIR_IN,
          .params = 1,
          .def_vals = {0x3F800000, 0x3F000000}
        },
        { .name = "VoiceFX",
          .nid = VOICEFX,
          .mid = 0x95,
          .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
          .direct = EFX_DIR_IN,
          .params = 8,
          .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
                       0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
                       0x00000000}
        }
};

/* Tuning controls */
#ifdef ENABLE_TUNING_CONTROLS

enum {
#define TUNING_CTL_START_NID  0xC0
        WEDGE_ANGLE = TUNING_CTL_START_NID,
        SVM_LEVEL,
        EQUALIZER_BAND_0,
        EQUALIZER_BAND_1,
        EQUALIZER_BAND_2,
        EQUALIZER_BAND_3,
        EQUALIZER_BAND_4,
        EQUALIZER_BAND_5,
        EQUALIZER_BAND_6,
        EQUALIZER_BAND_7,
        EQUALIZER_BAND_8,
        EQUALIZER_BAND_9,
        TUNING_CTL_END_NID
#define TUNING_CTLS_COUNT  (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
};

struct ct_tuning_ctl {
        char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
        hda_nid_t parent_nid;
        hda_nid_t nid;
        int mid; /*effect module ID*/
        int req; /*effect module request*/
        int direct; /* 0:output; 1:input*/
        unsigned int def_val;/*effect default values*/
};

static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
        { .name = "Wedge Angle",
          .parent_nid = VOICE_FOCUS,
          .nid = WEDGE_ANGLE,
          .mid = 0x95,
          .req = 8,
          .direct = EFX_DIR_IN,
          .def_val = 0x41F00000
        },
        { .name = "SVM Level",
          .parent_nid = MIC_SVM,
          .nid = SVM_LEVEL,
          .mid = 0x95,
          .req = 45,
          .direct = EFX_DIR_IN,
          .def_val = 0x3F3D70A4
        },
        { .name = "EQ Band0",
          .parent_nid = EQUALIZER,
          .nid = EQUALIZER_BAND_0,
          .mid = 0x96,
          .req = 11,
          .direct = EFX_DIR_OUT,
          .def_val = 0x00000000
        },
        { .name = "EQ Band1",
          .parent_nid = EQUALIZER,
          .nid = EQUALIZER_BAND_1,
          .mid = 0x96,
          .req = 12,
          .direct = EFX_DIR_OUT,
          .def_val = 0x00000000
        },
        { .name = "EQ Band2",
          .parent_nid = EQUALIZER,
          .nid = EQUALIZER_BAND_2,
          .mid = 0x96,
          .req = 13,
          .direct = EFX_DIR_OUT,
          .def_val = 0x00000000
        },
        { .name = "EQ Band3",
          .parent_nid = EQUALIZER,
          .nid = EQUALIZER_BAND_3,
          .mid = 0x96,
          .req = 14,
          .direct = EFX_DIR_OUT,
          .def_val = 0x00000000
        },
        { .name = "EQ Band4",
          .parent_nid = EQUALIZER,
          .nid = EQUALIZER_BAND_4,
          .mid = 0x96,
          .req = 15,
          .direct = EFX_DIR_OUT,
          .def_val = 0x00000000
        },
        { .name = "EQ Band5",
          .parent_nid = EQUALIZER,
          .nid = EQUALIZER_BAND_5,
          .mid = 0x96,
          .req = 16,
          .direct = EFX_DIR_OUT,
          .def_val = 0x00000000
        },
        { .name = "EQ Band6",
          .parent_nid = EQUALIZER,
          .nid = EQUALIZER_BAND_6,
          .mid = 0x96,
          .req = 17,
          .direct = EFX_DIR_OUT,
          .def_val = 0x00000000
        },
        { .name = "EQ Band7",
          .parent_nid = EQUALIZER,
          .nid = EQUALIZER_BAND_7,
          .mid = 0x96,
          .req = 18,
          .direct = EFX_DIR_OUT,
          .def_val = 0x00000000
        },
        { .name = "EQ Band8",
          .parent_nid = EQUALIZER,
          .nid = EQUALIZER_BAND_8,
          .mid = 0x96,
          .req = 19,
          .direct = EFX_DIR_OUT,
          .def_val = 0x00000000
        },
        { .name = "EQ Band9",
          .parent_nid = EQUALIZER,
          .nid = EQUALIZER_BAND_9,
          .mid = 0x96,
          .req = 20,
          .direct = EFX_DIR_OUT,
          .def_val = 0x00000000
        }
};
#endif

/* Voice FX Presets */
#define VOICEFX_MAX_PARAM_COUNT 9

struct ct_voicefx {
        char *name;
        hda_nid_t nid;
        int mid;
        int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
};

struct ct_voicefx_preset {
        char *name; /*preset name*/
        unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
};

static const struct ct_voicefx ca0132_voicefx = {
        .name = "VoiceFX Capture Switch",
        .nid = VOICEFX,
        .mid = 0x95,
        .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
};

static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
        { .name = "Neutral",
          .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
                    0x44FA0000, 0x3F800000, 0x3F800000,
                    0x3F800000, 0x00000000, 0x00000000 }
        },
        { .name = "Female2Male",
          .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
                    0x44FA0000, 0x3F19999A, 0x3F866666,
                    0x3F800000, 0x00000000, 0x00000000 }
        },
        { .name = "Male2Female",
          .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
                    0x450AC000, 0x4017AE14, 0x3F6B851F,
                    0x3F800000, 0x00000000, 0x00000000 }
        },
        { .name = "ScrappyKid",
          .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
                    0x44FA0000, 0x40400000, 0x3F28F5C3,
                    0x3F800000, 0x00000000, 0x00000000 }
        },
        { .name = "Elderly",
          .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
                    0x44E10000, 0x3FB33333, 0x3FB9999A,
                    0x3F800000, 0x3E3A2E43, 0x00000000 }
        },
        { .name = "Orc",
          .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
                    0x45098000, 0x3F266666, 0x3FC00000,
                    0x3F800000, 0x00000000, 0x00000000 }
        },
        { .name = "Elf",
          .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
                    0x45193000, 0x3F8E147B, 0x3F75C28F,
                    0x3F800000, 0x00000000, 0x00000000 }
        },
        { .name = "Dwarf",
          .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
                    0x45007000, 0x3F451EB8, 0x3F7851EC,
                    0x3F800000, 0x00000000, 0x00000000 }
        },
        { .name = "AlienBrute",
          .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
                    0x451F6000, 0x3F266666, 0x3FA7D945,
                    0x3F800000, 0x3CF5C28F, 0x00000000 }
        },
        { .name = "Robot",
          .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
                    0x44FA0000, 0x3FB2718B, 0x3F800000,
                    0xBC07010E, 0x00000000, 0x00000000 }
        },
        { .name = "Marine",
          .vals = { 0x3F800000, 0x43C20000, 0x44906000,
                    0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
                    0x3F0A3D71, 0x00000000, 0x00000000 }
        },
        { .name = "Emo",
          .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
                    0x44FA0000, 0x3F800000, 0x3F800000,
                    0x3E4CCCCD, 0x00000000, 0x00000000 }
        },
        { .name = "DeepVoice",
          .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
                    0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
                    0x3F800000, 0x00000000, 0x00000000 }
        },
        { .name = "Munchkin",
          .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
                    0x44FA0000, 0x3F800000, 0x3F1A043C,
                    0x3F800000, 0x00000000, 0x00000000 }
        }
};

/* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */

#define EQ_PRESET_MAX_PARAM_COUNT 11

struct ct_eq {
        char *name;
        hda_nid_t nid;
        int mid;
        int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
};

struct ct_eq_preset {
        char *name; /*preset name*/
        unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
};

static const struct ct_eq ca0132_alt_eq_enum = {
        .name = "FX: Equalizer Preset Switch",
        .nid = EQ_PRESET_ENUM,
        .mid = 0x96,
        .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
};


static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
        { .name = "Flat",
         .vals = { 0x00000000, 0x00000000, 0x00000000,
                   0x00000000, 0x00000000, 0x00000000,
                   0x00000000, 0x00000000, 0x00000000,
                   0x00000000, 0x00000000            }
        },
        { .name = "Acoustic",
         .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
                   0x40000000, 0x00000000, 0x00000000,
                   0x00000000, 0x00000000, 0x40000000,
                   0x40000000, 0x40000000            }
        },
        { .name = "Classical",
         .vals = { 0x00000000, 0x00000000, 0x40C00000,
                   0x40C00000, 0x40466666, 0x00000000,
                   0x00000000, 0x00000000, 0x00000000,
                   0x40466666, 0x40466666            }
        },
        { .name = "Country",
         .vals = { 0x00000000, 0xBF99999A, 0x00000000,
                   0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
                   0x00000000, 0x00000000, 0x40000000,
                   0x40466666, 0x40800000            }
        },
        { .name = "Dance",
         .vals = { 0x00000000, 0xBF99999A, 0x40000000,
                   0x40466666, 0x40866666, 0xBF99999A,
                   0xBF99999A, 0x00000000, 0x00000000,
                   0x40800000, 0x40800000            }
        },
        { .name = "Jazz",
         .vals = { 0x00000000, 0x00000000, 0x00000000,
                   0x3F8CCCCD, 0x40800000, 0x40800000,
                   0x40800000, 0x00000000, 0x3F8CCCCD,
                   0x40466666, 0x40466666            }
        },
        { .name = "New Age",
         .vals = { 0x00000000, 0x00000000, 0x40000000,
                   0x40000000, 0x00000000, 0x00000000,
                   0x00000000, 0x3F8CCCCD, 0x40000000,
                   0x40000000, 0x40000000            }
        },
        { .name = "Pop",
         .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
                   0x40000000, 0x40000000, 0x00000000,
                   0xBF99999A, 0xBF99999A, 0x00000000,
                   0x40466666, 0x40C00000            }
        },
        { .name = "Rock",
         .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
                   0x3F8CCCCD, 0x40000000, 0xBF99999A,
                   0xBF99999A, 0x00000000, 0x00000000,
                   0x40800000, 0x40800000            }
        },
        { .name = "Vocal",
         .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
                   0xBF99999A, 0x00000000, 0x40466666,
                   0x40800000, 0x40466666, 0x00000000,
                   0x00000000, 0x3F8CCCCD            }
        }
};

/*
 * DSP reqs for handling full-range speakers/bass redirection. If a speaker is
 * set as not being full range, and bass redirection is enabled, all
 * frequencies below the crossover frequency are redirected to the LFE
 * channel. If the surround configuration has no LFE channel, this can't be
 * enabled. X-Bass must be disabled when using these.
 */
enum speaker_range_reqs {
        SPEAKER_BASS_REDIRECT            = 0x15,
        SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16,
        /* Between 0x16-0x1a are the X-Bass reqs. */
        SPEAKER_FULL_RANGE_FRONT_L_R     = 0x1a,
        SPEAKER_FULL_RANGE_CENTER_LFE    = 0x1b,
        SPEAKER_FULL_RANGE_REAR_L_R      = 0x1c,
        SPEAKER_FULL_RANGE_SURROUND_L_R  = 0x1d,
        SPEAKER_BASS_REDIRECT_SUB_GAIN   = 0x1e,
};

/*
 * Definitions for the DSP req's to handle speaker tuning. These all belong to
 * module ID 0x96, the output effects module.
 */
enum speaker_tuning_reqs {
        /*
         * Currently, this value is always set to 0.0f. However, on Windows,
         * when selecting certain headphone profiles on the new Sound Blaster
         * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is
         * sent. This gets the speaker EQ address area, which is then used to
         * send over (presumably) an equalizer profile for the specific
         * headphone setup. It is sent using the same method the DSP
         * firmware is uploaded with, which I believe is why the 'ctspeq.bin'
         * file exists in linux firmware tree but goes unused. It would also
         * explain why the QUERY_SPEAKER_EQ_ADDRESS req is defined but unused.
         * Once this profile is sent over, SPEAKER_TUNING_USE_SPEAKER_EQ is
         * set to 1.0f.
         */
        SPEAKER_TUNING_USE_SPEAKER_EQ           = 0x1f,
        SPEAKER_TUNING_ENABLE_CENTER_EQ         = 0x20,
        SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL     = 0x21,
        SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL    = 0x22,
        SPEAKER_TUNING_CENTER_VOL_LEVEL         = 0x23,
        SPEAKER_TUNING_LFE_VOL_LEVEL            = 0x24,
        SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL      = 0x25,
        SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL     = 0x26,
        SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL  = 0x27,
        SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28,
        /*
         * Inversion is used when setting headphone virtualization to line
         * out. Not sure why this is, but it's the only place it's ever used.
         */
        SPEAKER_TUNING_FRONT_LEFT_INVERT        = 0x29,
        SPEAKER_TUNING_FRONT_RIGHT_INVERT       = 0x2a,
        SPEAKER_TUNING_CENTER_INVERT            = 0x2b,
        SPEAKER_TUNING_LFE_INVERT               = 0x2c,
        SPEAKER_TUNING_REAR_LEFT_INVERT         = 0x2d,
        SPEAKER_TUNING_REAR_RIGHT_INVERT        = 0x2e,
        SPEAKER_TUNING_SURROUND_LEFT_INVERT     = 0x2f,
        SPEAKER_TUNING_SURROUND_RIGHT_INVERT    = 0x30,
        /* Delay is used when setting surround speaker distance in Windows. */
        SPEAKER_TUNING_FRONT_LEFT_DELAY         = 0x31,
        SPEAKER_TUNING_FRONT_RIGHT_DELAY        = 0x32,
        SPEAKER_TUNING_CENTER_DELAY             = 0x33,
        SPEAKER_TUNING_LFE_DELAY                = 0x34,
        SPEAKER_TUNING_REAR_LEFT_DELAY          = 0x35,
        SPEAKER_TUNING_REAR_RIGHT_DELAY         = 0x36,
        SPEAKER_TUNING_SURROUND_LEFT_DELAY      = 0x37,
        SPEAKER_TUNING_SURROUND_RIGHT_DELAY     = 0x38,
        /* Of these two, only mute seems to ever be used. */
        SPEAKER_TUNING_MAIN_VOLUME              = 0x39,
        SPEAKER_TUNING_MUTE                     = 0x3a,
};

/* Surround output channel count configuration structures. */
#define SPEAKER_CHANNEL_CFG_COUNT 5
enum {
        SPEAKER_CHANNELS_2_0,
        SPEAKER_CHANNELS_2_1,
        SPEAKER_CHANNELS_4_0,
        SPEAKER_CHANNELS_4_1,
        SPEAKER_CHANNELS_5_1,
};

struct ca0132_alt_speaker_channel_cfg {
        char *name;
        unsigned int val;
};

static const struct ca0132_alt_speaker_channel_cfg speaker_channel_cfgs[] = {
        { .name = "2.0",
          .val = FLOAT_ONE
        },
        { .name = "2.1",
          .val = FLOAT_TWO
        },
        { .name = "4.0",
          .val = FLOAT_FIVE
        },
        { .name = "4.1",
          .val = FLOAT_SIX
        },
        { .name = "5.1",
          .val = FLOAT_EIGHT
        }
};

/*
 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
 * and I don't know what the third req is, but it's always zero. I assume it's
 * some sort of update or set command to tell the DSP there's new volume info.
 */
#define DSP_VOL_OUT 0
#define DSP_VOL_IN  1

struct ct_dsp_volume_ctl {
        hda_nid_t vnid;
        int mid; /* module ID*/
        unsigned int reqs[3]; /* scp req ID */
};

static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
        { .vnid = VNID_SPK,
          .mid = 0x32,
          .reqs = {3, 4, 2}
        },
        { .vnid = VNID_MIC,
          .mid = 0x37,
          .reqs = {2, 3, 1}
        }
};

/* Values for ca0113_mmio_command_set for selecting output. */
#define AE_CA0113_OUT_SET_COMMANDS 6
struct ae_ca0113_output_set {
        unsigned int group[AE_CA0113_OUT_SET_COMMANDS];
        unsigned int target[AE_CA0113_OUT_SET_COMMANDS];
        unsigned int vals[NUM_OF_OUTPUTS][AE_CA0113_OUT_SET_COMMANDS];
};

static const struct ae_ca0113_output_set ae5_ca0113_output_presets = {
        .group =  { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
        .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
                    /* Speakers. */
        .vals =   { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
                    /* Headphones. */
                    { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } },
};

static const struct ae_ca0113_output_set ae7_ca0113_output_presets = {
        .group  = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
        .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
                    /* Speakers. */
        .vals   = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
                    /* Headphones. */
                    { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } },
};

/* ae5 ca0113 command sequences to set headphone gain levels. */
#define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4
struct ae5_headphone_gain_set {
        char *name;
        unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS];
};

static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = {
        { .name = "Low (16-31",
          .vals = { 0xff, 0x2c, 0xf5, 0x32 }
        },
        { .name = "Medium (32-149",
          .vals = { 0x38, 0xa8, 0x3e, 0x4c }
        },
        { .name = "High (150-600",
          .vals = { 0xff, 0xff, 0xff, 0x7f }
        }
};

struct ae5_filter_set {
        char *name;
        unsigned int val;
};

static const struct ae5_filter_set ae5_filter_presets[] = {
        { .name = "Slow Roll Off",
          .val = 0xa0
        },
        { .name = "Minimum Phase",
          .val = 0xc0
        },
        { .name = "Fast Roll Off",
          .val = 0x80
        }
};

enum hda_cmd_vendor_io {
        /* for DspIO node */
        VENDOR_DSPIO_SCP_WRITE_DATA_LOW      = 0x000,
        VENDOR_DSPIO_SCP_WRITE_DATA_HIGH     = 0x100,

        VENDOR_DSPIO_STATUS                  = 0xF01,
        VENDOR_DSPIO_SCP_POST_READ_DATA      = 0x702,
        VENDOR_DSPIO_SCP_READ_DATA           = 0xF02,
        VENDOR_DSPIO_DSP_INIT                = 0x703,
        VENDOR_DSPIO_SCP_POST_COUNT_QUERY    = 0x704,
        VENDOR_DSPIO_SCP_READ_COUNT          = 0xF04,

        /* for ChipIO node */
        VENDOR_CHIPIO_ADDRESS_LOW            = 0x000,
        VENDOR_CHIPIO_ADDRESS_HIGH           = 0x100,
        VENDOR_CHIPIO_STREAM_FORMAT          = 0x200,
        VENDOR_CHIPIO_DATA_LOW               = 0x300,
        VENDOR_CHIPIO_DATA_HIGH              = 0x400,

        VENDOR_CHIPIO_8051_WRITE_DIRECT      = 0x500,
        VENDOR_CHIPIO_8051_READ_DIRECT       = 0xD00,

        VENDOR_CHIPIO_GET_PARAMETER          = 0xF00,
        VENDOR_CHIPIO_STATUS                 = 0xF01,
        VENDOR_CHIPIO_HIC_POST_READ          = 0x702,
        VENDOR_CHIPIO_HIC_READ_DATA          = 0xF03,

        VENDOR_CHIPIO_8051_DATA_WRITE        = 0x707,
        VENDOR_CHIPIO_8051_DATA_READ         = 0xF07,
        VENDOR_CHIPIO_8051_PMEM_READ         = 0xF08,
        VENDOR_CHIPIO_8051_IRAM_WRITE        = 0x709,
        VENDOR_CHIPIO_8051_IRAM_READ         = 0xF09,

        VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE   = 0x70A,
        VENDOR_CHIPIO_CT_EXTENSIONS_GET      = 0xF0A,

        VENDOR_CHIPIO_PLL_PMU_WRITE          = 0x70C,
        VENDOR_CHIPIO_PLL_PMU_READ           = 0xF0C,
        VENDOR_CHIPIO_8051_ADDRESS_LOW       = 0x70D,
        VENDOR_CHIPIO_8051_ADDRESS_HIGH      = 0x70E,
        VENDOR_CHIPIO_FLAG_SET               = 0x70F,
        VENDOR_CHIPIO_FLAGS_GET              = 0xF0F,
        VENDOR_CHIPIO_PARAM_SET              = 0x710,
        VENDOR_CHIPIO_PARAM_GET              = 0xF10,

        VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET  = 0x711,
        VENDOR_CHIPIO_PORT_ALLOC_SET         = 0x712,
        VENDOR_CHIPIO_PORT_ALLOC_GET         = 0xF12,
        VENDOR_CHIPIO_PORT_FREE_SET          = 0x713,

        VENDOR_CHIPIO_PARAM_EX_ID_GET        = 0xF17,
        VENDOR_CHIPIO_PARAM_EX_ID_SET        = 0x717,
        VENDOR_CHIPIO_PARAM_EX_VALUE_GET     = 0xF18,
        VENDOR_CHIPIO_PARAM_EX_VALUE_SET     = 0x718,

        VENDOR_CHIPIO_DMIC_CTL_SET           = 0x788,
        VENDOR_CHIPIO_DMIC_CTL_GET           = 0xF88,
        VENDOR_CHIPIO_DMIC_PIN_SET           = 0x789,
        VENDOR_CHIPIO_DMIC_PIN_GET           = 0xF89,
        VENDOR_CHIPIO_DMIC_MCLK_SET          = 0x78A,
        VENDOR_CHIPIO_DMIC_MCLK_GET          = 0xF8A,

        VENDOR_CHIPIO_EAPD_SEL_SET           = 0x78D
};

/*
 *  Control flag IDs
 */
enum control_flag_id {
        /* Connection manager stream setup is bypassed/enabled */
        CONTROL_FLAG_C_MGR                  = 0,
        /* DSP DMA is bypassed/enabled */
        CONTROL_FLAG_DMA                    = 1,
        /* 8051 'idle' mode is disabled/enabled */
        CONTROL_FLAG_IDLE_ENABLE            = 2,
        /* Tracker for the SPDIF-in path is bypassed/enabled */
        CONTROL_FLAG_TRACKER                = 3,
        /* DigitalOut to Spdif2Out connection is disabled/enabled */
        CONTROL_FLAG_SPDIF2OUT              = 4,
        /* Digital Microphone is disabled/enabled */
        CONTROL_FLAG_DMIC                   = 5,
        /* ADC_B rate is 48 kHz/96 kHz */
        CONTROL_FLAG_ADC_B_96KHZ            = 6,
        /* ADC_C rate is 48 kHz/96 kHz */
        CONTROL_FLAG_ADC_C_96KHZ            = 7,
        /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
        CONTROL_FLAG_DAC_96KHZ              = 8,
        /* DSP rate is 48 kHz/96 kHz */
        CONTROL_FLAG_DSP_96KHZ              = 9,
        /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
        CONTROL_FLAG_SRC_CLOCK_196MHZ       = 10,
        /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
        CONTROL_FLAG_SRC_RATE_96KHZ         = 11,
        /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
        CONTROL_FLAG_DECODE_LOOP            = 12,
        /* De-emphasis filter on DAC-1 disabled/enabled */
        CONTROL_FLAG_DAC1_DEEMPHASIS        = 13,
        /* De-emphasis filter on DAC-2 disabled/enabled */
        CONTROL_FLAG_DAC2_DEEMPHASIS        = 14,
        /* De-emphasis filter on DAC-3 disabled/enabled */
        CONTROL_FLAG_DAC3_DEEMPHASIS        = 15,
        /* High-pass filter on ADC_B disabled/enabled */
        CONTROL_FLAG_ADC_B_HIGH_PASS        = 16,
        /* High-pass filter on ADC_C disabled/enabled */
        CONTROL_FLAG_ADC_C_HIGH_PASS        = 17,
        /* Common mode on Port_A disabled/enabled */
        CONTROL_FLAG_PORT_A_COMMON_MODE     = 18,
        /* Common mode on Port_D disabled/enabled */
        CONTROL_FLAG_PORT_D_COMMON_MODE     = 19,
        /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
        CONTROL_FLAG_PORT_A_10KOHM_LOAD     = 20,
        /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
        CONTROL_FLAG_PORT_D_10KOHM_LOAD     = 21,
        /* ASI rate is 48kHz/96kHz */
        CONTROL_FLAG_ASI_96KHZ              = 22,
        /* DAC power settings able to control attached ports no/yes */
        CONTROL_FLAG_DACS_CONTROL_PORTS     = 23,
        /* Clock Stop OK reporting is disabled/enabled */
        CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
        /* Number of control flags */
        CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
};

/*
 * Control parameter IDs
 */
enum control_param_id {
        /* 0: None, 1: Mic1In*/
        CONTROL_PARAM_VIP_SOURCE               = 1,
        /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
        CONTROL_PARAM_SPDIF1_SOURCE            = 2,
        /* Port A output stage gain setting to use when 16 Ohm output
         * impedance is selected*/
        CONTROL_PARAM_PORTA_160OHM_GAIN        = 8,
        /* Port D output stage gain setting to use when 16 Ohm output
         * impedance is selected*/
        CONTROL_PARAM_PORTD_160OHM_GAIN        = 10,

        /*
         * This control param name was found in the 8051 memory, and makes
         * sense given the fact the AE-5 uses it and has the ASI flag set.
         */
        CONTROL_PARAM_ASI                      = 23,

        /* Stream Control */

        /* Select stream with the given ID */
        CONTROL_PARAM_STREAM_ID                = 24,
        /* Source connection point for the selected stream */
        CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
        /* Destination connection point for the selected stream */
        CONTROL_PARAM_STREAM_DEST_CONN_POINT   = 26,
        /* Number of audio channels in the selected stream */
        CONTROL_PARAM_STREAMS_CHANNELS         = 27,
        /*Enable control for the selected stream */
        CONTROL_PARAM_STREAM_CONTROL           = 28,

        /* Connection Point Control */

        /* Select connection point with the given ID */
        CONTROL_PARAM_CONN_POINT_ID            = 29,
        /* Connection point sample rate */
        CONTROL_PARAM_CONN_POINT_SAMPLE_RATE   = 30,

        /* Node Control */

        /* Select HDA node with the given ID */
        CONTROL_PARAM_NODE_ID                  = 31
};

/*
 *  Dsp Io Status codes
 */
enum hda_vendor_status_dspio {
        /* Success */
        VENDOR_STATUS_DSPIO_OK                       = 0x00,
        /* Busy, unable to accept new command, the host must retry */
        VENDOR_STATUS_DSPIO_BUSY                     = 0x01,
        /* SCP command queue is full */
        VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL   = 0x02,
        /* SCP response queue is empty */
        VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
};

/*
 *  Chip Io Status codes
 */
enum hda_vendor_status_chipio {
        /* Success */
        VENDOR_STATUS_CHIPIO_OK   = 0x00,
        /* Busy, unable to accept new command, the host must retry */
        VENDOR_STATUS_CHIPIO_BUSY = 0x01
};

/*
 *  CA0132 sample rate
 */
enum ca0132_sample_rate {
        SR_6_000        = 0x00,
        SR_8_000        = 0x01,
        SR_9_600        = 0x02,
        SR_11_025       = 0x03,
        SR_16_000       = 0x04,
        SR_22_050       = 0x05,
        SR_24_000       = 0x06,
        SR_32_000       = 0x07,
        SR_44_100       = 0x08,
        SR_48_000       = 0x09,
        SR_88_200       = 0x0A,
        SR_96_000       = 0x0B,

        SR_144_000      = 0x0C,
        SR_176_400      = 0x0D,
        SR_192_000      = 0x0E,
        SR_384_000      = 0x0F,

        SR_COUNT        = 0x10,

        SR_RATE_UNKNOWN = 0x1F
};

enum dsp_download_state {
        DSP_DOWNLOAD_FAILED = -1,
        DSP_DOWNLOAD_INIT   = 0,
        DSP_DOWNLOADING     = 1,
        DSP_DOWNLOADED      = 2
};

/* retrieve parameters from hda format */
#define get_hdafmt_chs(fmt)     (fmt & 0xf)
#define get_hdafmt_bits(fmt)    ((fmt >> 4) & 0x7)
#define get_hdafmt_rate(fmt)    ((fmt >> 8) & 0x7f)
#define get_hdafmt_type(fmt)    ((fmt >> 15) & 0x1)

/*
 * CA0132 specific
 */

struct ca0132_spec {
        const struct snd_kcontrol_new *mixers[5];
        unsigned int num_mixers;
        const struct hda_verb *base_init_verbs;
        const struct hda_verb *base_exit_verbs;
        const struct hda_verb *chip_init_verbs;
        const struct hda_verb *desktop_init_verbs;
        struct hda_verb *spec_init_verbs;
        struct auto_pin_cfg autocfg;

        /* Nodes configurations */
        struct hda_multi_out multiout;
        hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
        hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
        unsigned int num_outputs;
        hda_nid_t input_pins[AUTO_PIN_LAST];
        hda_nid_t adcs[AUTO_PIN_LAST];
        hda_nid_t dig_out;
        hda_nid_t dig_in;
        unsigned int num_inputs;
        hda_nid_t shared_mic_nid;
        hda_nid_t shared_out_nid;
        hda_nid_t unsol_tag_hp;
        hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
        hda_nid_t unsol_tag_amic1;

        /* chip access */
        struct mutex chipio_mutex; /* chip access mutex */
        u32 curr_chip_addx;

        /* DSP download related */
        enum dsp_download_state dsp_state;
        unsigned int dsp_stream_id;
        unsigned int wait_scp;
        unsigned int wait_scp_header;
        unsigned int wait_num_data;
        unsigned int scp_resp_header;
        unsigned int scp_resp_data[4];
        unsigned int scp_resp_count;
        bool startup_check_entered;
        bool dsp_reload;

        /* mixer and effects related */
        unsigned char dmic_ctl;
        int cur_out_type;
        int cur_mic_type;
        long vnode_lvol[VNODES_COUNT];
        long vnode_rvol[VNODES_COUNT];
        long vnode_lswitch[VNODES_COUNT];
        long vnode_rswitch[VNODES_COUNT];
        long effects_switch[EFFECTS_COUNT];
        long voicefx_val;
        long cur_mic_boost;
        /* ca0132_alt control related values */
        unsigned char in_enum_val;
        unsigned char out_enum_val;
        unsigned char channel_cfg_val;
        unsigned char speaker_range_val[2];
        unsigned char mic_boost_enum_val;
        unsigned char smart_volume_setting;
        unsigned char bass_redirection_val;
        long bass_redirect_xover_freq;
        long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
        long xbass_xover_freq;
        long eq_preset_val;
        unsigned int tlv[4];
        struct hda_vmaster_mute_hook vmaster_mute;
        /* AE-5 Control values */
        unsigned char ae5_headphone_gain_val;
        unsigned char ae5_filter_val;
        /* ZxR Control Values */
        unsigned char zxr_gain_set;

        struct hda_codec *codec;
        struct delayed_work unsol_hp_work;
        int quirk;

#ifdef ENABLE_TUNING_CONTROLS
        long cur_ctl_vals[TUNING_CTLS_COUNT];
#endif
        /*
         * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
         * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
         * things.
         */
        bool use_pci_mmio;
        void __iomem *mem_base;

        /*
         * Whether or not to use the alt functions like alt_select_out,
         * alt_select_in, etc. Only used on desktop codecs for now, because of
         * surround sound support.
         */
        bool use_alt_functions;

        /*
         * Whether or not to use alt controls:  volume effect sliders, EQ
         * presets, smart volume presets, and new control names with FX prefix.
         * Renames PlayEnhancement and CrystalVoice too.
         */
        bool use_alt_controls;
};

/*
 * CA0132 quirks table
 */
enum {
        QUIRK_NONE,
        QUIRK_ALIENWARE,
        QUIRK_ALIENWARE_M17XR4,
        QUIRK_SBZ,
        QUIRK_ZXR,
        QUIRK_ZXR_DBPRO,
        QUIRK_R3DI,
        QUIRK_R3D,
        QUIRK_AE5,
        QUIRK_AE7,
};

#ifdef CONFIG_PCI
#define ca0132_quirk(spec)              ((spec)->quirk)
#define ca0132_use_pci_mmio(spec)       ((spec)->use_pci_mmio)
#define ca0132_use_alt_functions(spec)  ((spec)->use_alt_functions)
#define ca0132_use_alt_controls(spec)   ((spec)->use_alt_controls)
#else
#define ca0132_quirk(spec)              ({ (void)(spec); QUIRK_NONE; })
#define ca0132_use_alt_functions(spec)  ({ (void)(spec); false; })
#define ca0132_use_pci_mmio(spec)       ({ (void)(spec); false; })
#define ca0132_use_alt_controls(spec)   ({ (void)(spec); false; })
#endif

static const struct hda_pintbl alienware_pincfgs[] = {
        { 0x0b, 0x90170110 }, /* Builtin Speaker */
        { 0x0c, 0x411111f0 }, /* N/A */
        { 0x0d, 0x411111f0 }, /* N/A */
        { 0x0e, 0x411111f0 }, /* N/A */
        { 0x0f, 0x0321101f }, /* HP */
        { 0x10, 0x411111f0 }, /* Headset?  disabled for now */
        { 0x11, 0x03a11021 }, /* Mic */
        { 0x12, 0xd5a30140 }, /* Builtin Mic */
        { 0x13, 0x411111f0 }, /* N/A */
        { 0x18, 0x411111f0 }, /* N/A */
        {}
};

/* Sound Blaster Z pin configs taken from Windows Driver */
static const struct hda_pintbl sbz_pincfgs[] = {
        { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
        { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
        { 0x0d, 0x014510f0 }, /* Digital Out */
        { 0x0e, 0x01c510f0 }, /* SPDIF In */
        { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
        { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
        { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
        { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
        { 0x13, 0x908700f0 }, /* What U Hear In*/
        { 0x18, 0x50d000f0 }, /* N/A */
        {}
};

/* Sound Blaster ZxR pin configs taken from Windows Driver */
static const struct hda_pintbl zxr_pincfgs[] = {
        { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */
        { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/
        { 0x0d, 0x014510f0 }, /* Digital Out */
        { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/
        { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */
        { 0x10, 0x01017111 }, /* Port D -- Center/LFE */
        { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */
        { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */
        { 0x13, 0x908700f0 }, /* What U Hear In*/
        { 0x18, 0x50d000f0 }, /* N/A */
        {}
};

/* Recon3D pin configs taken from Windows Driver */
static const struct hda_pintbl r3d_pincfgs[] = {
        { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
        { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
        { 0x0d, 0x014510f0 }, /* Digital Out */
        { 0x0e, 0x01c520f0 }, /* SPDIF In */
        { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
        { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
        { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
        { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
        { 0x13, 0x908700f0 }, /* What U Hear In*/
        { 0x18, 0x50d000f0 }, /* N/A */
        {}
};

/* Sound Blaster AE-5 pin configs taken from Windows Driver */
static const struct hda_pintbl ae5_pincfgs[] = {
        { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
        { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
        { 0x0d, 0x014510f0 }, /* Digital Out */
        { 0x0e, 0x01c510f0 }, /* SPDIF In */
        { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
        { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
        { 0x11, 0x01a170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
        { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
        { 0x13, 0x908700f0 }, /* What U Hear In*/
        { 0x18, 0x50d000f0 }, /* N/A */
        {}
};

/* Recon3D integrated pin configs taken from Windows Driver */
static const struct hda_pintbl r3di_pincfgs[] = {
        { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
        { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
        { 0x0d, 0x014510f0 }, /* Digital Out */
        { 0x0e, 0x41c520f0 }, /* SPDIF In */
        { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
        { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
        { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
        { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
        { 0x13, 0x908700f0 }, /* What U Hear In*/
        { 0x18, 0x500000f0 }, /* N/A */
        {}
};

static const struct hda_pintbl ae7_pincfgs[] = {
        { 0x0b, 0x01017010 },
        { 0x0c, 0x014510f0 },
        { 0x0d, 0x414510f0 },
        { 0x0e, 0x01c520f0 },
        { 0x0f, 0x01017114 },
        { 0x10, 0x01017011 },
        { 0x11, 0x018170ff },
        { 0x12, 0x01a170f0 },
        { 0x13, 0x908700f0 },
        { 0x18, 0x500000f0 },
        {}
};

static const struct snd_pci_quirk ca0132_quirks[] = {
        SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
        SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
        SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
        SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
        SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
        SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
        SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ),
        SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ),
        SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
        SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
        SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
        SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI),
        SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
        SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D),
        SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
        SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7),
        {}
};

/* Output selection quirk info structures. */
#define MAX_QUIRK_MMIO_GPIO_SET_VALS 3
#define MAX_QUIRK_SCP_SET_VALS 2
struct ca0132_alt_out_set_info {
        unsigned int dac2port; /* ParamID 0x0d value. */

        bool has_hda_gpio;
        char hda_gpio_pin;
        char hda_gpio_set;

        unsigned int mmio_gpio_count;
        char mmio_gpio_pin[MAX_QUIRK_MMIO_GPIO_SET_VALS];
        char mmio_gpio_set[MAX_QUIRK_MMIO_GPIO_SET_VALS];

        unsigned int scp_cmds_count;
        unsigned int scp_cmd_mid[MAX_QUIRK_SCP_SET_VALS];
        unsigned int scp_cmd_req[MAX_QUIRK_SCP_SET_VALS];
        unsigned int scp_cmd_val[MAX_QUIRK_SCP_SET_VALS];

        bool has_chipio_write;
        unsigned int chipio_write_addr;
        unsigned int chipio_write_data;
};

struct ca0132_alt_out_set_quirk_data {
        int quirk_id;

        bool has_headphone_gain;
        bool is_ae_series;

        struct ca0132_alt_out_set_info out_set_info[NUM_OF_OUTPUTS];
};

static const struct ca0132_alt_out_set_quirk_data quirk_out_set_data[] = {
        { .quirk_id = QUIRK_R3DI,
          .has_headphone_gain = false,
          .is_ae_series       = false,
          .out_set_info = {
                /* Speakers. */
                { .dac2port         = 0x24,
                  .has_hda_gpio     = true,
                  .hda_gpio_pin     = 2,
                  .hda_gpio_set     = 1,
                  .mmio_gpio_count  = 0,
                  .scp_cmds_count   = 0,
                  .has_chipio_write = false,
                },
                /* Headphones. */
                { .dac2port         = 0x21,
                  .has_hda_gpio     = true,
                  .hda_gpio_pin     = 2,
                  .hda_gpio_set     = 0,
                  .mmio_gpio_count  = 0,
                  .scp_cmds_count   = 0,
                  .has_chipio_write = false,
                } },
        },
        { .quirk_id = QUIRK_R3D,
          .has_headphone_gain = false,
          .is_ae_series       = false,
          .out_set_info = {
                /* Speakers. */
                { .dac2port         = 0x24,
                  .has_hda_gpio     = false,
                  .mmio_gpio_count  = 1,
                  .mmio_gpio_pin    = { 1 },
                  .mmio_gpio_set    = { 1 },
                  .scp_cmds_count   = 0,
                  .has_chipio_write = false,
                },
                /* Headphones. */
                { .dac2port         = 0x21,
                  .has_hda_gpio     = false,
                  .mmio_gpio_count  = 1,
                  .mmio_gpio_pin    = { 1 },
                  .mmio_gpio_set    = { 0 },
                  .scp_cmds_count   = 0,
                  .has_chipio_write = false,
                } },
        },
        { .quirk_id = QUIRK_SBZ,
          .has_headphone_gain = false,
          .is_ae_series       = false,
          .out_set_info = {
                /* Speakers. */
                { .dac2port         = 0x18,
                  .has_hda_gpio     = false,
                  .mmio_gpio_count  = 3,
                  .mmio_gpio_pin    = { 7, 4, 1 },
                  .mmio_gpio_set    = { 0, 1, 1 },
                  .scp_cmds_count   = 0,
                  .has_chipio_write = false, },
                /* Headphones. */
                { .dac2port         = 0x12,
                  .has_hda_gpio     = false,
                  .mmio_gpio_count  = 3,
                  .mmio_gpio_pin    = { 7, 4, 1 },
                  .mmio_gpio_set    = { 1, 1, 0 },
                  .scp_cmds_count   = 0,
                  .has_chipio_write = false,
                } },
        },
        { .quirk_id = QUIRK_ZXR,
          .has_headphone_gain = true,
          .is_ae_series       = false,
          .out_set_info = {
                /* Speakers. */
                { .dac2port         = 0x24,
                  .has_hda_gpio     = false,
                  .mmio_gpio_count  = 3,
                  .mmio_gpio_pin    = { 2, 3, 5 },
                  .mmio_gpio_set    = { 1, 1, 0 },
                  .scp_cmds_count   = 0,
                  .has_chipio_write = false,
                },
                /* Headphones. */
                { .dac2port         = 0x21,
                  .has_hda_gpio     = false,
                  .mmio_gpio_count  = 3,
                  .mmio_gpio_pin    = { 2, 3, 5 },
                  .mmio_gpio_set    = { 0, 1, 1 },
                  .scp_cmds_count   = 0,
                  .has_chipio_write = false,
                } },
        },
        { .quirk_id = QUIRK_AE5,
          .has_headphone_gain = true,
          .is_ae_series       = true,
          .out_set_info = {
                /* Speakers. */
                { .dac2port          = 0xa4,
                  .has_hda_gpio      = false,
                  .mmio_gpio_count   = 0,
                  .scp_cmds_count    = 2,
                  .scp_cmd_mid       = { 0x96, 0x96 },
                  .scp_cmd_req       = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
                                         SPEAKER_TUNING_FRONT_RIGHT_INVERT },
                  .scp_cmd_val       = { FLOAT_ZERO, FLOAT_ZERO },
                  .has_chipio_write  = true,
                  .chipio_write_addr = 0x0018b03c,
                  .chipio_write_data = 0x00000012
                },
                /* Headphones. */
                { .dac2port          = 0xa1,
                  .has_hda_gpio      = false,
                  .mmio_gpio_count   = 0,
                  .scp_cmds_count    = 2,
                  .scp_cmd_mid       = { 0x96, 0x96 },
                  .scp_cmd_req       = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
                                         SPEAKER_TUNING_FRONT_RIGHT_INVERT },
                  .scp_cmd_val       = { FLOAT_ONE, FLOAT_ONE },
                  .has_chipio_write  = true,
                  .chipio_write_addr = 0x0018b03c,
                  .chipio_write_data = 0x00000012
                } },
        },
        { .quirk_id = QUIRK_AE7,
          .has_headphone_gain = true,
          .is_ae_series       = true,
          .out_set_info = {
                /* Speakers. */
                { .dac2port          = 0x58,
                  .has_hda_gpio      = false,
                  .mmio_gpio_count   = 1,
                  .mmio_gpio_pin     = { 0 },
                  .mmio_gpio_set     = { 1 },
                  .scp_cmds_count    = 2,
                  .scp_cmd_mid       = { 0x96, 0x96 },
                  .scp_cmd_req       = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
                                         SPEAKER_TUNING_FRONT_RIGHT_INVERT },
                  .scp_cmd_val       = { FLOAT_ZERO, FLOAT_ZERO },
                  .has_chipio_write  = true,
                  .chipio_write_addr = 0x0018b03c,
                  .chipio_write_data = 0x00000000
                },
                /* Headphones. */
                { .dac2port          = 0x58,
                  .has_hda_gpio      = false,
                  .mmio_gpio_count   = 1,
                  .mmio_gpio_pin     = { 0 },
                  .mmio_gpio_set     = { 1 },
                  .scp_cmds_count    = 2,
                  .scp_cmd_mid       = { 0x96, 0x96 },
                  .scp_cmd_req       = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
                                         SPEAKER_TUNING_FRONT_RIGHT_INVERT },
                  .scp_cmd_val       = { FLOAT_ONE, FLOAT_ONE },
                  .has_chipio_write  = true,
                  .chipio_write_addr = 0x0018b03c,
                  .chipio_write_data = 0x00000010
                } },
        }
};

/*
 * CA0132 codec access
 */
static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
                unsigned int verb, unsigned int parm, unsigned int *res)
{
        unsigned int response;
        response = snd_hda_codec_read(codec, nid, 0, verb, parm);
        *res = response;

        return ((response == -1) ? -1 : 0);
}

static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
                unsigned short converter_format, unsigned int *res)
{
        return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
                                converter_format & 0xffff, res);
}

static int codec_set_converter_stream_channel(struct hda_codec *codec,
                                hda_nid_t nid, unsigned char stream,
                                unsigned char channel, unsigned int *res)
{
        unsigned char converter_stream_channel = 0;

        converter_stream_channel = (stream << 4) | (channel & 0x0f);
        return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
                                converter_stream_channel, res);
}

/* Chip access helper function */
static int chipio_send(struct hda_codec *codec,
                       unsigned int reg,
                       unsigned int data)
{
        unsigned int res;
        unsigned long timeout = jiffies + msecs_to_jiffies(1000);

        /* send bits of data specified by reg */
        do {
                res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
                                         reg, data);
                if (res == VENDOR_STATUS_CHIPIO_OK)
                        return 0;
                msleep(20);
        } while (time_before(jiffies, timeout));

        return -EIO;
}

/*
 * Write chip address through the vendor widget -- NOT protected by the Mutex!
 */
static int chipio_write_address(struct hda_codec *codec,
                                unsigned int chip_addx)
{
        struct ca0132_spec *spec = codec->spec;
        int res;

        if (spec->curr_chip_addx == chip_addx)
                        return 0;

        /* send low 16 bits of the address */
        res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
                          chip_addx & 0xffff);

        if (res != -EIO) {
                /* send high 16 bits of the address */
                res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
                                  chip_addx >> 16);
        }

        spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;

        return res;
}

/*
 * Write data through the vendor widget -- NOT protected by the Mutex!
 */
static int chipio_write_data(struct hda_codec *codec, unsigned int data)
{
        struct ca0132_spec *spec = codec->spec;
        int res;

        /* send low 16 bits of the data */
        res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);

        if (res != -EIO) {
                /* send high 16 bits of the data */
                res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
                                  data >> 16);
        }

        /*If no error encountered, automatically increment the address
        as per chip behaviour*/
        spec->curr_chip_addx = (res != -EIO) ?
                                        (spec->curr_chip_addx + 4) : ~0U;
        return res;
}

/*
 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
 */
static int chipio_write_data_multiple(struct hda_codec *codec,
                                      const u32 *data,
                                      unsigned int count)
{
        int status = 0;

        if (data == NULL) {
                codec_dbg(codec, "chipio_write_data null ptr\n");
                return -EINVAL;
        }

        while ((count-- != 0) && (status == 0))
                status = chipio_write_data(codec, *data++);

        return status;
}


/*
 * Read data through the vendor widget -- NOT protected by the Mutex!
 */
static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
{
        struct ca0132_spec *spec = codec->spec;
        int res;

        /* post read */
        res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);

        if (res != -EIO) {
                /* read status */
                res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
        }

        if (res != -EIO) {
                /* read data */
                *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
                                           VENDOR_CHIPIO_HIC_READ_DATA,
                                           0);
        }

        /*If no error encountered, automatically increment the address
        as per chip behaviour*/
        spec->curr_chip_addx = (res != -EIO) ?
                                        (spec->curr_chip_addx + 4) : ~0U;
        return res;
}

/*
 * Write given value to the given address through the chip I/O widget.
 * protected by the Mutex
 */
static int chipio_write(struct hda_codec *codec,
                unsigned int chip_addx, const unsigned int data)
{
        struct ca0132_spec *spec = codec->spec;
        int err;

        mutex_lock(&spec->chipio_mutex);

        /* write the address, and if successful proceed to write data */
        err = chipio_write_address(codec, chip_addx);
        if (err < 0)
                goto exit;

        err = chipio_write_data(codec, data);
        if (err < 0)
                goto exit;

exit:
        mutex_unlock(&spec->chipio_mutex);
        return err;
}

/*
 * Write given value to the given address through the chip I/O widget.
 * not protected by the Mutex
 */
static int chipio_write_no_mutex(struct hda_codec *codec,
                unsigned int chip_addx, const unsigned int data)
{
        int err;


        /* write the address, and if successful proceed to write data */
        err = chipio_write_address(codec, chip_addx);
        if (err < 0)
                goto exit;

        err = chipio_write_data(codec, data);
        if (err < 0)
                goto exit;

exit:
        return err;
}

/*
 * Write multiple values to the given address through the chip I/O widget.
 * protected by the Mutex
 */
static int chipio_write_multiple(struct hda_codec *codec,
                                 u32 chip_addx,
                                 const u32 *data,
                                 unsigned int count)
{
        struct ca0132_spec *spec = codec->spec;
        int status;

        mutex_lock(&spec->chipio_mutex);
        status = chipio_write_address(codec, chip_addx);
        if (status < 0)
                goto error;

        status = chipio_write_data_multiple(codec, data, count);
error:
        mutex_unlock(&spec->chipio_mutex);

        return status;
}

/*
 * Read the given address through the chip I/O widget
 * protected by the Mutex
 */
static int chipio_read(struct hda_codec *codec,
                unsigned int chip_addx, unsigned int *data)
{
        struct ca0132_spec *spec = codec->spec;
        int err;

        mutex_lock(&spec->chipio_mutex);

        /* write the address, and if successful proceed to write data */
        err = chipio_write_address(codec, chip_addx);
        if (err < 0)
                goto exit;

        err = chipio_read_data(codec, data);
        if (err < 0)
                goto exit;

exit:
        mutex_unlock(&spec->chipio_mutex);
        return err;
}

/*
 * Set chip control flags through the chip I/O widget.
 */
static void chipio_set_control_flag(struct hda_codec *codec,
                                    enum control_flag_id flag_id,
                                    bool flag_state)
{
        unsigned int val;
        unsigned int flag_bit;

        flag_bit = (flag_state ? 1 : 0);
        val = (flag_bit << 7) | (flag_id);
        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
                            VENDOR_CHIPIO_FLAG_SET, val);
}

/*
 * Set chip parameters through the chip I/O widget.
 */
static void chipio_set_control_param(struct hda_codec *codec,
                enum control_param_id param_id, int param_val)
{
        struct ca0132_spec *spec = codec->spec;
        int val;

        if ((param_id < 32) && (param_val < 8)) {
                val = (param_val << 5) | (param_id);
                snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
                                    VENDOR_CHIPIO_PARAM_SET, val);
        } else {
                mutex_lock(&spec->chipio_mutex);
                if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
                        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
                                            VENDOR_CHIPIO_PARAM_EX_ID_SET,
                                            param_id);
                        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
                                            VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
                                            param_val);
                }
                mutex_unlock(&spec->chipio_mutex);
        }
}

/*
 * Set chip parameters through the chip I/O widget. NO MUTEX.
 */
static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
                enum control_param_id param_id, int param_val)
{
        int val;

        if ((param_id < 32) && (param_val < 8)) {
                val = (param_val << 5) | (param_id);
                snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
                                    VENDOR_CHIPIO_PARAM_SET, val);
        } else {
                if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
                        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
                                            VENDOR_CHIPIO_PARAM_EX_ID_SET,
                                            param_id);
                        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
                                            VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
                                            param_val);
                }
        }
}
/*
 * Connect stream to a source point, and then connect
 * that source point to a destination point.
 */
static void chipio_set_stream_source_dest(struct hda_codec *codec,
                                int streamid, int source_point, int dest_point)
{
        chipio_set_control_param_no_mutex(codec,
                        CONTROL_PARAM_STREAM_ID, streamid);
        chipio_set_control_param_no_mutex(codec,
                        CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
        chipio_set_control_param_no_mutex(codec,
                        CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
}

/*
 * Set number of channels in the selected stream.
 */
static void chipio_set_stream_channels(struct hda_codec *codec,
                                int streamid, unsigned int channels)
{
        chipio_set_control_param_no_mutex(codec,
                        CONTROL_PARAM_STREAM_ID, streamid);
        chipio_set_control_param_no_mutex(codec,
                        CONTROL_PARAM_STREAMS_CHANNELS, channels);
}

/*
 * Enable/Disable audio stream.
 */
static void chipio_set_stream_control(struct hda_codec *codec,
                                int streamid, int enable)
{
        chipio_set_control_param_no_mutex(codec,
                        CONTROL_PARAM_STREAM_ID, streamid);
        chipio_set_control_param_no_mutex(codec,
                        CONTROL_PARAM_STREAM_CONTROL, enable);
}


/*
 * Set sampling rate of the connection point. NO MUTEX.
 */
static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
                                int connid, enum ca0132_sample_rate rate)
{
        chipio_set_control_param_no_mutex(codec,
                        CONTROL_PARAM_CONN_POINT_ID, connid);
        chipio_set_control_param_no_mutex(codec,
                        CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
}

/*
 * Set sampling rate of the connection point.
 */
static void chipio_set_conn_rate(struct hda_codec *codec,
                                int connid, enum ca0132_sample_rate rate)
{
        chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
        chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
                                 rate);
}

/*
 * Writes to the 8051's internal address space directly instead of indirectly,
 * giving access to the special function registers located at addresses
 * 0x80-0xFF.
 */
static void chipio_8051_write_direct(struct hda_codec *codec,
                unsigned int addr, unsigned int data)
{
        unsigned int verb;

        verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data;
        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
}

/*
 * Enable clocks.
 */
static void chipio_enable_clocks(struct hda_codec *codec)
{
        struct ca0132_spec *spec = codec->spec;

        mutex_lock(&spec->chipio_mutex);
        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
                            VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
                            VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
                            VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
                            VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
                            VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
                            VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
        mutex_unlock(&spec->chipio_mutex);
}

/*
 * CA0132 DSP IO stuffs
 */
static int dspio_send(struct hda_codec *codec, unsigned int reg,
                      unsigned int data)
{
        int res;
        unsigned long timeout = jiffies + msecs_to_jiffies(1000);

        /* send bits of data specified by reg to dsp */
        do {
                res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
                if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
                        return res;
                msleep(20);
        } while (time_before(jiffies, timeout));

        return -EIO;
}

/*
 * Wait for DSP to be ready for commands
 */
static void dspio_write_wait(struct hda_codec *codec)
{
        int status;
        unsigned long timeout = jiffies + msecs_to_jiffies(1000);

        do {
                status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
                                                VENDOR_DSPIO_STATUS, 0);
                if ((status == VENDOR_STATUS_DSPIO_OK) ||
                    (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
                        break;
                msleep(1);
        } while (time_before(jiffies, timeout));
}

/*
 * Write SCP data to DSP
 */
static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
{
        struct ca0132_spec *spec = codec->spec;
        int status;

        dspio_write_wait(codec);

        mutex_lock(&spec->chipio_mutex);
        status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
                            scp_data & 0xffff);
        if (status < 0)
                goto error;

        status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
                                    scp_data >> 16);
        if (status < 0)
                goto error;

        /* OK, now check if the write itself has executed*/
        status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
                                    VENDOR_DSPIO_STATUS, 0);
error:
        mutex_unlock(&spec->chipio_mutex);

        return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
                        -EIO : 0;
}

/*
 * Write multiple SCP data to DSP
 */
static int dspio_write_multiple(struct hda_codec *codec,
                                unsigned int *buffer, unsigned int size)
{
        int status = 0;
        unsigned int count;

        if (buffer == NULL)
                return -EINVAL;

        count = 0;
        while (count < size) {
                status = dspio_write(codec, *buffer++);
                if (status != 0)
                        break;
                count++;
        }

        return status;
}

static int dspio_read(struct hda_codec *codec, unsigned int *data)
{
        int status;

        status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
        if (status == -EIO)
                return status;

        status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
        if (status == -EIO ||
            status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
                return -EIO;

        *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
                                   VENDOR_DSPIO_SCP_READ_DATA, 0);

        return 0;
}

static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
                               unsigned int *buf_size, unsigned int size_count)
{
        int status = 0;
        unsigned int size = *buf_size;
        unsigned int count;
        unsigned int skip_count;
        unsigned int dummy;

        if (buffer == NULL)
                return -1;

        count = 0;
        while (count < size && count < size_count) {
                status = dspio_read(codec, buffer++);
                if (status != 0)
                        break;
                count++;
        }

        skip_count = count;
        if (status == 0) {
                while (skip_count < size) {
                        status = dspio_read(codec, &dummy);
                        if (status != 0)
                                break;
                        skip_count++;
                }
        }
        *buf_size = count;

        return status;
}

/*
 * Construct the SCP header using corresponding fields
 */
static inline unsigned int
make_scp_header(unsigned int target_id, unsigned int source_id,
                unsigned int get_flag, unsigned int req,
                unsigned int device_flag, unsigned int resp_flag,
                unsigned int error_flag, unsigned int data_size)
{
        unsigned int header = 0;

        header = (data_size & 0x1f) << 27;
        header |= (error_flag & 0x01) << 26;
        header |= (resp_flag & 0x01) << 25;
        header |= (device_flag & 0x01) << 24;
        header |= (req & 0x7f) << 17;
        header |= (get_flag & 0x01) << 16;
        header |= (source_id & 0xff) << 8;
        header |= target_id & 0xff;

        return header;
}

/*
 * Extract corresponding fields from SCP header
 */
static inline void
extract_scp_header(unsigned int header,
                   unsigned int *target_id, unsigned int *source_id,
                   unsigned int *get_flag, unsigned int *req,
                   unsigned int *device_flag, unsigned int *resp_flag,
                   unsigned int *error_flag, unsigned int *data_size)
{
        if (data_size)
                *data_size = (header >> 27) & 0x1f;
        if (error_flag)
                *error_flag = (header >> 26) & 0x01;
        if (resp_flag)
                *resp_flag = (header >> 25) & 0x01;
        if (device_flag)
                *device_flag = (header >> 24) & 0x01;
        if (req)
                *req = (header >> 17) & 0x7f;
        if (get_flag)
                *get_flag = (header >> 16) & 0x01;
        if (source_id)
                *source_id = (header >> 8) & 0xff;
        if (target_id)
                *target_id = header & 0xff;
}

#define SCP_MAX_DATA_WORDS  (16)

/* Structure to contain any SCP message */
struct scp_msg {
        unsigned int hdr;
        unsigned int data[SCP_MAX_DATA_WORDS];
};

static void dspio_clear_response_queue(struct hda_codec *codec)
{
        unsigned long timeout = jiffies + msecs_to_jiffies(1000);
        unsigned int dummy = 0;
        int status;

        /* clear all from the response queue */
        do {
                status = dspio_read(codec, &dummy);
        } while (status == 0 && time_before(jiffies, timeout));
}

static int dspio_get_response_data(struct hda_codec *codec)
{
        struct ca0132_spec *spec = codec->spec;
        unsigned int data = 0;
        unsigned int count;

        if (dspio_read(codec, &data) < 0)
                return -EIO;

        if ((data & 0x00ffffff) == spec->wait_scp_header) {
                spec->scp_resp_header = data;
                spec->scp_resp_count = data >> 27;
                count = spec->wait_num_data;
                dspio_read_multiple(codec, spec->scp_resp_data,
                                    &spec->scp_resp_count, count);
                return 0;
        }

        return -EIO;
}

/*
 * Send SCP message to DSP
 */
static int dspio_send_scp_message(struct hda_codec *codec,
                                  unsigned char *send_buf,
                                  unsigned int send_buf_size,
                                  unsigned char *return_buf,
                                  unsigned int return_buf_size,
                                  unsigned int *bytes_returned)
{
        struct ca0132_spec *spec = codec->spec;
        int status = -1;
        unsigned int scp_send_size = 0;
        unsigned int total_size;
        bool waiting_for_resp = false;
        unsigned int header;
        struct scp_msg *ret_msg;
        unsigned int resp_src_id, resp_target_id;
        unsigned int data_size, src_id, target_id, get_flag, device_flag;

        if (bytes_returned)
                *bytes_returned = 0;

        /* get scp header from buffer */
        header = *((unsigned int *)send_buf);
        extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
                           &device_flag, NULL, NULL, &data_size);
        scp_send_size = data_size + 1;
        total_size = (scp_send_size * 4);

        if (send_buf_size < total_size)
                return -EINVAL;

        if (get_flag || device_flag) {
                if (!return_buf || return_buf_size < 4 || !bytes_returned)
                        return -EINVAL;

                spec->wait_scp_header = *((unsigned int *)send_buf);

                /* swap source id with target id */
                resp_target_id = src_id;
                resp_src_id = target_id;
                spec->wait_scp_header &= 0xffff0000;
                spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
                spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
                spec->wait_scp = 1;
                waiting_for_resp = true;
        }

        status = dspio_write_multiple(codec, (unsigned int *)send_buf,
                                      scp_send_size);
        if (status < 0) {
                spec->wait_scp = 0;
                return status;
        }

        if (waiting_for_resp) {
                unsigned long timeout = jiffies + msecs_to_jiffies(1000);
                memset(return_buf, 0, return_buf_size);
                do {
                        msleep(20);
                } while (spec->wait_scp && time_before(jiffies, timeout));
                waiting_for_resp = false;
                if (!spec->wait_scp) {
                        ret_msg = (struct scp_msg *)return_buf;
                        memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
                        memcpy(&ret_msg->data, spec->scp_resp_data,
                               spec->wait_num_data);
                        *bytes_returned = (spec->scp_resp_count + 1) * 4;
                        status = 0;
                } else {
                        status = -EIO;
                }
                spec->wait_scp = 0;
        }

        return status;
}

/**
 * Prepare and send the SCP message to DSP
 * @codec: the HDA codec
 * @mod_id: ID of the DSP module to send the command
 * @src_id: ID of the source
 * @req: ID of request to send to the DSP module
 * @dir: SET or GET
 * @data: pointer to the data to send with the request, request specific
 * @len: length of the data, in bytes
 * @reply: point to the buffer to hold data returned for a reply
 * @reply_len: length of the reply buffer returned from GET
 *
 * Returns zero or a negative error code.
 */
static int dspio_scp(struct hda_codec *codec,
                int mod_id, int src_id, int req, int dir, const void *data,
                unsigned int len, void *reply, unsigned int *reply_len)
{
        int status = 0;
        struct scp_msg scp_send, scp_reply;
        unsigned int ret_bytes, send_size, ret_size;
        unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
        unsigned int reply_data_size;

        memset(&scp_send, 0, sizeof(scp_send));
        memset(&scp_reply, 0, sizeof(scp_reply));

        if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
                return -EINVAL;

        if (dir == SCP_GET && reply == NULL) {
                codec_dbg(codec, "dspio_scp get but has no buffer\n");
                return -EINVAL;
        }

        if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
                codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
                return -EINVAL;
        }

        scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
                                       0, 0, 0, len/sizeof(unsigned int));
        if (data != NULL && len > 0) {
                len = min((unsigned int)(sizeof(scp_send.data)), len);
                memcpy(scp_send.data, data, len);
        }

        ret_bytes = 0;
        send_size = sizeof(unsigned int) + len;
        status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
                                        send_size, (unsigned char *)&scp_reply,
                                        sizeof(scp_reply), &ret_bytes);

        if (status < 0) {
                codec_dbg(codec, "dspio_scp: send scp msg failed\n");
                return status;
        }

        /* extract send and reply headers members */
        extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
                           NULL, NULL, NULL, NULL, NULL);
        extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
                           &reply_resp_flag, &reply_error_flag,
                           &reply_data_size);

        if (!send_get_flag)
                return 0;

        if (reply_resp_flag && !reply_error_flag) {
                ret_size = (ret_bytes - sizeof(scp_reply.hdr))
                                        / sizeof(unsigned int);

                if (*reply_len < ret_size*sizeof(unsigned int)) {
                        codec_dbg(codec, "reply too long for buf\n");
                        return -EINVAL;
                } else if (ret_size != reply_data_size) {
                        codec_dbg(codec, "RetLen and HdrLen .NE.\n");
                        return -EINVAL;
                } else if (!reply) {
                        codec_dbg(codec, "NULL reply\n");
                        return -EINVAL;
                } else {
                        *reply_len = ret_size*sizeof(unsigned int);
                        memcpy(reply, scp_reply.data, *reply_len);
                }
        } else {
                codec_dbg(codec, "reply ill-formed or errflag set\n");
                return -EIO;
        }

        return status;
}

/*
 * Set DSP parameters
 */
static int dspio_set_param(struct hda_codec *codec, int mod_id,
                        int src_id, int req, const void *data, unsigned int len)
{
        return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
                        NULL);
}

static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
                        int req, const unsigned int data)
{
        return dspio_set_param(codec, mod_id, 0x20, req, &data,
                        sizeof(unsigned int));
}

static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
                        int req, const unsigned int data)
{
        return dspio_set_param(codec, mod_id, 0x00, req, &data,
                        sizeof(unsigned int));
}

/*
 * Allocate a DSP DMA channel via an SCP message
 */
static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
{
        int status = 0;
        unsigned int size = sizeof(dma_chan);

        codec_dbg(codec, "     dspio_alloc_dma_chan() -- begin\n");
        status = dspio_scp(codec, MASTERCONTROL, 0x20,
                        MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
                        dma_chan, &size);

        if (status < 0) {
                codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
                return status;
        }

        if ((*dma_chan + 1) == 0) {
                codec_dbg(codec, "no free dma channels to allocate\n");
                return -EBUSY;
        }

        codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
        codec_dbg(codec, "     dspio_alloc_dma_chan() -- complete\n");

        return status;
}

/*
 * Free a DSP DMA via an SCP message
 */
static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
{
        int status = 0;
        unsigned int dummy = 0;

        codec_dbg(codec, "     dspio_free_dma_chan() -- begin\n");
        codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);

        status = dspio_scp(codec, MASTERCONTROL, 0x20,
                        MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
                        sizeof(dma_chan), NULL, &dummy);

        if (status < 0) {
                codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
                return status;
        }

        codec_dbg(codec, "     dspio_free_dma_chan() -- complete\n");

        return status;
}

/*
 * (Re)start the DSP
 */
static int dsp_set_run_state(struct hda_codec *codec)
{
        unsigned int dbg_ctrl_reg;
        unsigned int halt_state;
        int err;

        err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
        if (err < 0)
                return err;

        halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
                      DSP_DBGCNTL_STATE_LOBIT;

        if (halt_state != 0) {
                dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
                                  DSP_DBGCNTL_SS_MASK);
                err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
                                   dbg_ctrl_reg);
                if (err < 0)
                        return err;

                dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
                                DSP_DBGCNTL_EXEC_MASK;
                err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
                                   dbg_ctrl_reg);
                if (err < 0)
                        return err;
        }

        return 0;
}

/*
 * Reset the DSP
 */
static int dsp_reset(struct hda_codec *codec)
{
        unsigned int res;
        int retry = 20;

        codec_dbg(codec, "dsp_reset\n");
        do {
                res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
                retry--;
        } while (res == -EIO && retry);

        if (!retry) {
                codec_dbg(codec, "dsp_reset timeout\n");
                return -EIO;
        }

        return 0;
}

/*
 * Convert chip address to DSP address
 */
static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
                                        bool *code, bool *yram)
{
        *code = *yram = false;

        if (UC_RANGE(chip_addx, 1)) {
                *code = true;
                return UC_OFF(chip_addx);
        } else if (X_RANGE_ALL(chip_addx, 1)) {
                return X_OFF(chip_addx);
        } else if (Y_RANGE_ALL(chip_addx, 1)) {
                *yram = true;
                return Y_OFF(chip_addx);
        }

        return INVALID_CHIP_ADDRESS;
}

/*
 * Check if the DSP DMA is active
 */
static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
{
        unsigned int dma_chnlstart_reg;

        chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);

        return ((dma_chnlstart_reg & (1 <<
                        (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
}

static int dsp_dma_setup_common(struct hda_codec *codec,
                                unsigned int chip_addx,
                                unsigned int dma_chan,
                                unsigned int port_map_mask,
                                bool ovly)
{
        int status = 0;
        unsigned int chnl_prop;
        unsigned int dsp_addx;
        unsigned int active;
        bool code, yram;

        codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");

        if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
                codec_dbg(codec, "dma chan num invalid\n");
                return -EINVAL;
        }

        if (dsp_is_dma_active(codec, dma_chan)) {
                codec_dbg(codec, "dma already active\n");
                return -EBUSY;
        }

        dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);

        if (dsp_addx == INVALID_CHIP_ADDRESS) {
                codec_dbg(codec, "invalid chip addr\n");
                return -ENXIO;
        }

        chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
        active = 0;

        codec_dbg(codec, "   dsp_dma_setup_common()    start reg pgm\n");

        if (ovly) {
                status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
                                     &chnl_prop);

                if (status < 0) {
                        codec_dbg(codec, "read CHNLPROP Reg fail\n");
                        return status;
                }
                codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
        }

        if (!code)
                chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
        else
                chnl_prop |=  (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));

        chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));

        status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
        if (status < 0) {
                codec_dbg(codec, "write CHNLPROP Reg fail\n");
                return status;
        }
        codec_dbg(codec, "   dsp_dma_setup_common()    Write CHNLPROP\n");

        if (ovly) {
                status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
                                     &active);

                if (status < 0) {
                        codec_dbg(codec, "read ACTIVE Reg fail\n");
                        return status;
                }
                codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
        }

        active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
                DSPDMAC_ACTIVE_AAR_MASK;

        status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
        if (status < 0) {
                codec_dbg(codec, "write ACTIVE Reg fail\n");
                return status;
        }

        codec_dbg(codec, "   dsp_dma_setup_common()    Write ACTIVE\n");

        status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
                              port_map_mask);
        if (status < 0) {
                codec_dbg(codec, "write AUDCHSEL Reg fail\n");
                return status;
        }
        codec_dbg(codec, "   dsp_dma_setup_common()    Write AUDCHSEL\n");

        status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
                        DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
        if (status < 0) {
                codec_dbg(codec, "write IRQCNT Reg fail\n");
                return status;
        }
        codec_dbg(codec, "   dsp_dma_setup_common()    Write IRQCNT\n");

        codec_dbg(codec,
                   "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
                   "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
                   chip_addx, dsp_addx, dma_chan,
                   port_map_mask, chnl_prop, active);

        codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");

        return 0;
}

/*
 * Setup the DSP DMA per-transfer-specific registers
 */
static int dsp_dma_setup(struct hda_codec *codec,
                        unsigned int chip_addx,
                        unsigned int count,
                        unsigned int dma_chan)
{
        int status = 0;
        bool code, yram;
        unsigned int dsp_addx;
        unsigned int addr_field;
        unsigned int incr_field;
        unsigned int base_cnt;
        unsigned int cur_cnt;
        unsigned int dma_cfg = 0;
        unsigned int adr_ofs = 0;
        unsigned int xfr_cnt = 0;
        const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
                                                DSPDMAC_XFRCNT_BCNT_LOBIT + 1);

        codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");

        if (count > max_dma_count) {
                codec_dbg(codec, "count too big\n");
                return -EINVAL;
        }

        dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
        if (dsp_addx == INVALID_CHIP_ADDRESS) {
                codec_dbg(codec, "invalid chip addr\n");
                return -ENXIO;
        }

        codec_dbg(codec, "   dsp_dma_setup()    start reg pgm\n");

        addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
        incr_field   = 0;

        if (!code) {
                addr_field <<= 1;
                if (yram)
                        addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);

                incr_field  = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
        }

        dma_cfg = addr_field + incr_field;
        status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
                                dma_cfg);
        if (status < 0) {
                codec_dbg(codec, "write DMACFG Reg fail\n");
                return status;
        }
        codec_dbg(codec, "   dsp_dma_setup()    Write DMACFG\n");

        adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
                                                        (code ? 0 : 1));

        status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
                                adr_ofs);
        if (status < 0) {
                codec_dbg(codec, "write DSPADROFS Reg fail\n");
                return status;
        }
        codec_dbg(codec, "   dsp_dma_setup()    Write DSPADROFS\n");

        base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;

        cur_cnt  = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;

        xfr_cnt = base_cnt | cur_cnt;

        status = chipio_write(codec,
                                DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
        if (status < 0) {
                codec_dbg(codec, "write XFRCNT Reg fail\n");
                return status;
        }
        codec_dbg(codec, "   dsp_dma_setup()    Write XFRCNT\n");

        codec_dbg(codec,
                   "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
                   "ADROFS=0x%x, XFRCNT=0x%x\n",
                   chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);

        codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");

        return 0;
}

/*
 * Start the DSP DMA
 */
static int dsp_dma_start(struct hda_codec *codec,
                         unsigned int dma_chan, bool ovly)
{
        unsigned int reg = 0;
        int status = 0;

        codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");

        if (ovly) {
                status = chipio_read(codec,
                                     DSPDMAC_CHNLSTART_INST_OFFSET, &reg);

                if (status < 0) {
                        codec_dbg(codec, "read CHNLSTART reg fail\n");
                        return status;
                }
                codec_dbg(codec, "-- dsp_dma_start()    Read CHNLSTART\n");

                reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
                                DSPDMAC_CHNLSTART_DIS_MASK);
        }

        status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
                        reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
        if (status < 0) {
                codec_dbg(codec, "write CHNLSTART reg fail\n");
                return status;
        }
        codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");

        return status;
}

/*
 * Stop the DSP DMA
 */
static int dsp_dma_stop(struct hda_codec *codec,
                        unsigned int dma_chan, bool ovly)
{
        unsigned int reg = 0;
        int status = 0;

        codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");

        if (ovly) {
                status = chipio_read(codec,
                                     DSPDMAC_CHNLSTART_INST_OFFSET, &reg);

                if (status < 0) {
                        codec_dbg(codec, "read CHNLSTART reg fail\n");
                        return status;
                }
                codec_dbg(codec, "-- dsp_dma_stop()    Read CHNLSTART\n");
                reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
                                DSPDMAC_CHNLSTART_DIS_MASK);
        }

        status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
                        reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
        if (status < 0) {
                codec_dbg(codec, "write CHNLSTART reg fail\n");
                return status;
        }
        codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");

        return status;
}

/**
 * Allocate router ports
 *
 * @codec: the HDA codec
 * @num_chans: number of channels in the stream
 * @ports_per_channel: number of ports per channel
 * @start_device: start device
 * @port_map: pointer to the port list to hold the allocated ports
 *
 * Returns zero or a negative error code.
 */
static int dsp_allocate_router_ports(struct hda_codec *codec,
                                     unsigned int num_chans,
                                     unsigned int ports_per_channel,
                                     unsigned int start_device,
                                     unsigned int *port_map)
{
        int status = 0;
        int res;
        u8 val;

        status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
        if (status < 0)
                return status;

        val = start_device << 6;
        val |= (ports_per_channel - 1) << 4;
        val |= num_chans - 1;

        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
                            VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
                            val);

        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
                            VENDOR_CHIPIO_PORT_ALLOC_SET,
                            MEM_CONNID_DSP);

        status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
        if (status < 0)
                return status;

        res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
                                VENDOR_CHIPIO_PORT_ALLOC_GET, 0);

        *port_map = res;

        return (res < 0) ? res : 0;
}

/*
 * Free router ports
 */
static int dsp_free_router_ports(struct hda_codec *codec)
{
        int status = 0;

        status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
        if (status < 0)
                return status;

        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
                            VENDOR_CHIPIO_PORT_FREE_SET,
                            MEM_CONNID_DSP);

        status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);

        return status;
}

/*
 * Allocate DSP ports for the download stream
 */
static int dsp_allocate_ports(struct hda_codec *codec,
                        unsigned int num_chans,
                        unsigned int rate_multi, unsigned int *port_map)
{
        int status;

        codec_dbg(codec, "     dsp_allocate_ports() -- begin\n");

        if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
                codec_dbg(codec, "bad rate multiple\n");
                return -EINVAL;
        }

        status = dsp_allocate_router_ports(codec, num_chans,
                                           rate_multi, 0, port_map);

        codec_dbg(codec, "     dsp_allocate_ports() -- complete\n");

        return status;
}

static int dsp_allocate_ports_format(struct hda_codec *codec,
                        const unsigned short fmt,
                        unsigned int *port_map)
{
        int status;
        unsigned int num_chans;

        unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
        unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
        unsigned int rate_multi = sample_rate_mul / sample_rate_div;

        if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
                codec_dbg(codec, "bad rate multiple\n");
                return -EINVAL;
        }

        num_chans = get_hdafmt_chs(fmt) + 1;

        status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);

        return status;
}

/*
 * free DSP ports
 */
static int dsp_free_ports(struct hda_codec *codec)
{
        int status;

        codec_dbg(codec, "     dsp_free_ports() -- begin\n");

        status = dsp_free_router_ports(codec);
        if (status < 0) {
                codec_dbg(codec, "free router ports fail\n");
                return status;
        }
        codec_dbg(codec, "     dsp_free_ports() -- complete\n");

        return status;
}

/*
 *  HDA DMA engine stuffs for DSP code download
 */
struct dma_engine {
        struct hda_codec *codec;
        unsigned short m_converter_format;
        struct snd_dma_buffer *dmab;
        unsigned int buf_size;
};


enum dma_state {
        DMA_STATE_STOP  = 0,
        DMA_STATE_RUN   = 1
};

static int dma_convert_to_hda_format(struct hda_codec *codec,
                unsigned int sample_rate,
                unsigned short channels,
                unsigned short *hda_format)
{
        unsigned int format_val;

        format_val = snd_hdac_calc_stream_format(sample_rate,
                                channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);

        if (hda_format)
                *hda_format = (unsigned short)format_val;

        return 0;
}

/*
 *  Reset DMA for DSP download
 */
static int dma_reset(struct dma_engine *dma)
{
        struct hda_codec *codec = dma->codec;
        struct ca0132_spec *spec = codec->spec;
        int status;

        if (dma->dmab->area)
                snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);

        status = snd_hda_codec_load_dsp_prepare(codec,
                        dma->m_converter_format,
                        dma->buf_size,
                        dma->dmab);
        if (status < 0)
                return status;
        spec->dsp_stream_id = status;
        return 0;
}

static int dma_set_state(struct dma_engine *dma, enum dma_state state)
{
        bool cmd;

        switch (state) {
        case DMA_STATE_STOP:
                cmd = false;
                break;
        case DMA_STATE_RUN:
                cmd = true;
                break;
        default:
                return 0;
        }

        snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
        return 0;
}

static unsigned int dma_get_buffer_size(struct dma_engine *dma)
{
        return dma->dmab->bytes;
}

static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
{
        return dma->dmab->area;
}

static int dma_xfer(struct dma_engine *dma,
                const unsigned int *data,
                unsigned int count)
{
        memcpy(dma->dmab->area, data, count);
        return 0;
}

static void dma_get_converter_format(
                struct dma_engine *dma,
                unsigned short *format)
{
        if (format)
                *format = dma->m_converter_format;
}

static unsigned int dma_get_stream_id(struct dma_engine *dma)
{
        struct ca0132_spec *spec = dma->codec->spec;

        return spec->dsp_stream_id;
}

struct dsp_image_seg {
        u32 magic;
        u32 chip_addr;
        u32 count;
        u32 data[];
};

static const u32 g_magic_value = 0x4c46584d;
static const u32 g_chip_addr_magic_value = 0xFFFFFF01;

static bool is_valid(const struct dsp_image_seg *p)
{
        return p->magic == g_magic_value;
}

static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
{

        return g_chip_addr_magic_value == p->chip_addr;
}

static bool is_last(const struct dsp_image_seg *p)
{
        return p->count == 0;
}

static size_t dsp_sizeof(const struct dsp_image_seg *p)
{
        return struct_size(p, data, p->count);
}

static const struct dsp_image_seg *get_next_seg_ptr(
                                const struct dsp_image_seg *p)
{
        return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
}

/*
 * CA0132 chip DSP transfer stuffs.  For DSP download.
 */
#define INVALID_DMA_CHANNEL (~0U)

/*
 * Program a list of address/data pairs via the ChipIO widget.
 * The segment data is in the format of successive pairs of words.
 * These are repeated as indicated by the segment's count field.
 */
static int dspxfr_hci_write(struct hda_codec *codec,
                        const struct dsp_image_seg *fls)
{
        int status;
        const u32 *data;
        unsigned int count;

        if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
                codec_dbg(codec, "hci_write invalid params\n");
                return -EINVAL;
        }

        count = fls->count;
        data = (u32 *)(fls->data);
        while (count >= 2) {
                status = chipio_write(codec, data[0], data[1]);
                if (status < 0) {
                        codec_dbg(codec, "hci_write chipio failed\n");
                        return status;
                }
                count -= 2;
                data  += 2;
        }
        return 0;
}

/**
 * Write a block of data into DSP code or data RAM using pre-allocated
 * DMA engine.
 *
 * @codec: the HDA codec
 * @fls: pointer to a fast load image
 * @reloc: Relocation address for loading single-segment overlays, or 0 for
 *         no relocation
 * @dma_engine: pointer to DMA engine to be used for DSP download
 * @dma_chan: The number of DMA channels used for DSP download
 * @port_map_mask: port mapping
 * @ovly: TRUE if overlay format is required
 *
 * Returns zero or a negative error code.
 */
static int dspxfr_one_seg(struct hda_codec *codec,
                        const struct dsp_image_seg *fls,
                        unsigned int reloc,
                        struct dma_engine *dma_engine,
                        unsigned int dma_chan,
                        unsigned int port_map_mask,
                        bool ovly)
{
        int status = 0;
        bool comm_dma_setup_done = false;
        const unsigned int *data;
        unsigned int chip_addx;
        unsigned int words_to_write;
        unsigned int buffer_size_words;
        unsigned char *buffer_addx;
        unsigned short hda_format;
        unsigned int sample_rate_div;
        unsigned int sample_rate_mul;
        unsigned int num_chans;
        unsigned int hda_frame_size_words;
        unsigned int remainder_words;
        const u32 *data_remainder;
        u32 chip_addx_remainder;
        unsigned int run_size_words;
        const struct dsp_image_seg *hci_write = NULL;
        unsigned long timeout;
        bool dma_active;

        if (fls == NULL)
                return -EINVAL;
        if (is_hci_prog_list_seg(fls)) {
                hci_write = fls;
                fls = get_next_seg_ptr(fls);
        }

        if (hci_write && (!fls || is_last(fls))) {
                codec_dbg(codec, "hci_write\n");
                return dspxfr_hci_write(codec, hci_write);
        }

        if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
                codec_dbg(codec, "Invalid Params\n");
                return -EINVAL;
        }

        data = fls->data;
        chip_addx = fls->chip_addr;
        words_to_write = fls->count;

        if (!words_to_write)
                return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
        if (reloc)
                chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);

        if (!UC_RANGE(chip_addx, words_to_write) &&
            !X_RANGE_ALL(chip_addx, words_to_write) &&
            !Y_RANGE_ALL(chip_addx, words_to_write)) {
                codec_dbg(codec, "Invalid chip_addx Params\n");
                return -EINVAL;
        }

        buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
                                        sizeof(u32);

        buffer_addx = dma_get_buffer_addr(dma_engine);

        if (buffer_addx == NULL) {
                codec_dbg(codec, "dma_engine buffer NULL\n");
                return -EINVAL;
        }

        dma_get_converter_format(dma_engine, &hda_format);
        sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
        sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
        num_chans = get_hdafmt_chs(hda_format) + 1;

        hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
                        (num_chans * sample_rate_mul / sample_rate_div));

        if (hda_frame_size_words == 0) {
                codec_dbg(codec, "frmsz zero\n");
                return -EINVAL;
        }

        buffer_size_words = min(buffer_size_words,
                                (unsigned int)(UC_RANGE(chip_addx, 1) ?
                                65536 : 32768));
        buffer_size_words -= buffer_size_words % hda_frame_size_words;
        codec_dbg(codec,
                   "chpadr=0x%08x frmsz=%u nchan=%u "
                   "rate_mul=%u div=%u bufsz=%u\n",
                   chip_addx, hda_frame_size_words, num_chans,
                   sample_rate_mul, sample_rate_div, buffer_size_words);

        if (buffer_size_words < hda_frame_size_words) {
                codec_dbg(codec, "dspxfr_one_seg:failed\n");
                return -EINVAL;
        }

        remainder_words = words_to_write % hda_frame_size_words;
        data_remainder = data;
        chip_addx_remainder = chip_addx;

        data += remainder_words;
        chip_addx += remainder_words*sizeof(u32);
        words_to_write -= remainder_words;

        while (words_to_write != 0) {
                run_size_words = min(buffer_size_words, words_to_write);
                codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
                            words_to_write, run_size_words, remainder_words);
                dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
                if (!comm_dma_setup_done) {
                        status = dsp_dma_stop(codec, dma_chan, ovly);
                        if (status < 0)
                                return status;
                        status = dsp_dma_setup_common(codec, chip_addx,
                                                dma_chan, port_map_mask, ovly);
                        if (status < 0)
                                return status;
                        comm_dma_setup_done = true;
                }

                status = dsp_dma_setup(codec, chip_addx,
                                                run_size_words, dma_chan);
                if (status < 0)
                        return status;
                status = dsp_dma_start(codec, dma_chan, ovly);
                if (status < 0)
                        return status;
                if (!dsp_is_dma_active(codec, dma_chan)) {
                        codec_dbg(codec, "dspxfr:DMA did not start\n");
                        return -EIO;
                }
                status = dma_set_state(dma_engine, DMA_STATE_RUN);
                if (status < 0)
                        return status;
                if (remainder_words != 0) {
                        status = chipio_write_multiple(codec,
                                                chip_addx_remainder,
                                                data_remainder,
                                                remainder_words);
                        if (status < 0)
                                return status;
                        remainder_words = 0;
                }
                if (hci_write) {
                        status = dspxfr_hci_write(codec, hci_write);
                        if (status < 0)
                                return status;
                        hci_write = NULL;
                }

                timeout = jiffies + msecs_to_jiffies(2000);
                do {
                        dma_active = dsp_is_dma_active(codec, dma_chan);
                        if (!dma_active)
                                break;
                        msleep(20);
                } while (time_before(jiffies, timeout));
                if (dma_active)
                        break;

                codec_dbg(codec, "+++++ DMA complete\n");
                dma_set_state(dma_engine, DMA_STATE_STOP);
                status = dma_reset(dma_engine);

                if (status < 0)
                        return status;

                data += run_size_words;
                chip_addx += run_size_words*sizeof(u32);
                words_to_write -= run_size_words;
        }

        if (remainder_words != 0) {
                status = chipio_write_multiple(codec, chip_addx_remainder,
                                        data_remainder, remainder_words);
        }

        return status;
}

/**
 * Write the entire DSP image of a DSP code/data overlay to DSP memories
 *
 * @codec: the HDA codec
 * @fls_data: pointer to a fast load image
 * @reloc: Relocation address for loading single-segment overlays, or 0 for
 *         no relocation
 * @sample_rate: sampling rate of the stream used for DSP download
 * @channels: channels of the stream used for DSP download
 * @ovly: TRUE if overlay format is required
 *
 * Returns zero or a negative error code.
 */
static int dspxfr_image(struct hda_codec *codec,
                        const struct dsp_image_seg *fls_data,
                        unsigned int reloc,
                        unsigned int sample_rate,
                        unsigned short channels,
                        bool ovly)
{
        struct ca0132_spec *spec = codec->spec;
        int status;
        unsigned short hda_format = 0;
        unsigned int response;
        unsigned char stream_id = 0;
        struct dma_engine *dma_engine;
        unsigned int dma_chan;
        unsigned int port_map_mask;

        if (fls_data == NULL)
                return -EINVAL;

        dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
        if (!dma_engine)
                return -ENOMEM;

        dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
        if (!dma_engine->dmab) {
                kfree(dma_engine);
                return -ENOMEM;
        }

        dma_engine->codec = codec;
        dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
        dma_engine->m_converter_format = hda_format;
        dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
                        DSP_DMA_WRITE_BUFLEN_INIT) * 2;

        dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;

        status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
                                        hda_format, &response);

        if (status < 0) {
                codec_dbg(codec, "set converter format fail\n");
                goto exit;
        }

        status = snd_hda_codec_load_dsp_prepare(codec,
                                dma_engine->m_converter_format,
                                dma_engine->buf_size,
                                dma_engine->dmab);
        if (status < 0)
                goto exit;
        spec->dsp_stream_id = status;

        if (ovly) {
                status = dspio_alloc_dma_chan(codec, &dma_chan);
                if (status < 0) {
                        codec_dbg(codec, "alloc dmachan fail\n");
                        dma_chan = INVALID_DMA_CHANNEL;
                        goto exit;
                }
        }

        port_map_mask = 0;
        status = dsp_allocate_ports_format(codec, hda_format,
                                        &port_map_mask);
        if (status < 0) {
                codec_dbg(codec, "alloc ports fail\n");
                goto exit;
        }

        stream_id = dma_get_stream_id(dma_engine);
        status = codec_set_converter_stream_channel(codec,
                        WIDGET_CHIP_CTRL, stream_id, 0, &response);
        if (status < 0) {
                codec_dbg(codec, "set stream chan fail\n");
                goto exit;
        }

        while ((fls_data != NULL) && !is_last(fls_data)) {
                if (!is_valid(fls_data)) {
                        codec_dbg(codec, "FLS check fail\n");
                        status = -EINVAL;
                        goto exit;
                }
                status = dspxfr_one_seg(codec, fls_data, reloc,
                                        dma_engine, dma_chan,
                                        port_map_mask, ovly);
                if (status < 0)
                        break;

                if (is_hci_prog_list_seg(fls_data))
                        fls_data = get_next_seg_ptr(fls_data);

                if ((fls_data != NULL) && !is_last(fls_data))
                        fls_data = get_next_seg_ptr(fls_data);
        }

        if (port_map_mask != 0)
                status = dsp_free_ports(codec);

        if (status < 0)
                goto exit;

        status = codec_set_converter_stream_channel(codec,
                                WIDGET_CHIP_CTRL, 0, 0, &response);

exit:
        if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
                dspio_free_dma_chan(codec, dma_chan);

        if (dma_engine->dmab->area)
                snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
        kfree(dma_engine->dmab);
        kfree(dma_engine);

        return status;
}

/*
 * CA0132 DSP download stuffs.
 */
static void dspload_post_setup(struct hda_codec *codec)
{
        struct ca0132_spec *spec = codec->spec;
        codec_dbg(codec, "---- dspload_post_setup ------\n");
        if (!ca0132_use_alt_functions(spec)) {
                /*set DSP speaker to 2.0 configuration*/
                chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
                chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);

                /*update write pointer*/
                chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
        }
}

/**
 * dspload_image - Download DSP from a DSP Image Fast Load structure.
 *
 * @codec: the HDA codec
 * @fls: pointer to a fast load image
 * @ovly: TRUE if overlay format is required
 * @reloc: Relocation address for loading single-segment overlays, or 0 for
 *         no relocation
 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
 * @router_chans: number of audio router channels to be allocated (0 means use
 *                internal defaults; max is 32)
 *
 * Download DSP from a DSP Image Fast Load structure. This structure is a
 * linear, non-constant sized element array of structures, each of which
 * contain the count of the data to be loaded, the data itself, and the
 * corresponding starting chip address of the starting data location.
 * Returns zero or a negative error code.
 */
static int dspload_image(struct hda_codec *codec,
                        const struct dsp_image_seg *fls,
                        bool ovly,
                        unsigned int reloc,
                        bool autostart,
                        int router_chans)
{
        int status = 0;
        unsigned int sample_rate;
        unsigned short channels;

        codec_dbg(codec, "---- dspload_image begin ------\n");
        if (router_chans == 0) {
                if (!ovly)
                        router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
                else
                        router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
        }

        sample_rate = 48000;
        channels = (unsigned short)router_chans;

        while (channels > 16) {
                sample_rate *= 2;
                channels /= 2;
        }

        do {
                codec_dbg(codec, "Ready to program DMA\n");
                if (!ovly)
                        status = dsp_reset(codec);

                if (status < 0)
                        break;

                codec_dbg(codec, "dsp_reset() complete\n");
                status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
                                      ovly);

                if (status < 0)
                        break;

                codec_dbg(codec, "dspxfr_image() complete\n");
                if (autostart && !ovly) {
                        dspload_post_setup(codec);
                        status = dsp_set_run_state(codec);
                }

                codec_dbg(codec, "LOAD FINISHED\n");
        } while (0);

        return status;
}

#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
static bool dspload_is_loaded(struct hda_codec *codec)
{
        unsigned int data = 0;
        int status = 0;

        status = chipio_read(codec, 0x40004, &data);
        if ((status < 0) || (data != 1))
                return false;

        return true;
}
#else
#define dspload_is_loaded(codec)        false
#endif

static bool dspload_wait_loaded(struct hda_codec *codec)
{
        unsigned long timeout = jiffies + msecs_to_jiffies(2000);

        do {
                if (dspload_is_loaded(codec)) {
                        codec_info(codec, "ca0132 DSP downloaded and running\n");
                        return true;
                }
                msleep(20);
        } while (time_before(jiffies, timeout));

        codec_err(codec, "ca0132 failed to download DSP\n");
        return false;
}

/*
 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
 * based cards, and has a second mmio region, region2, that's used for special
 * commands.
 */

/*
 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
 * the mmio address 0x320 is used to set GPIO pins. The format for the data
 * The first eight bits are just the number of the pin. So far, I've only seen
 * this number go to 7.
 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
 * then off to send that bit.
 */
static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
                bool enable)
{
        struct ca0132_spec *spec = codec->spec;
        unsigned short gpio_data;

        gpio_data = gpio_pin & 0xF;
        gpio_data |= ((enable << 8) & 0x100);

        writew(gpio_data, spec->mem_base + 0x320);
}

/*
 * Special pci region2 commands that are only used by the AE-5. They follow
 * a set format, and require reads at certain points to seemingly 'clear'
 * the response data. My first tests didn't do these reads, and would cause
 * the card to get locked up until the memory was read. These commands
 * seem to work with three distinct values that I've taken to calling group,
 * target-id, and value.
 */
static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
                unsigned int target, unsigned int value)
{
        struct ca0132_spec *spec = codec->spec;
        unsigned int write_val;

        writel(0x0000007e, spec->mem_base + 0x210);
        readl(spec->mem_base + 0x210);
        writel(0x0000005a, spec->mem_base + 0x210);
        readl(spec->mem_base + 0x210);
        readl(spec->mem_base + 0x210);

        writel(0x00800005, spec->mem_base + 0x20c);
        writel(group, spec->mem_base + 0x804);

        writel(0x00800005, spec->mem_base + 0x20c);
        write_val = (target & 0xff);
        write_val |= (value << 8);


        writel(write_val, spec->mem_base + 0x204);
        /*
         * Need delay here or else it goes too fast and works inconsistently.
         */
        msleep(20);

        readl(spec->mem_base + 0x860);
        readl(spec->mem_base + 0x854);
        readl(spec->mem_base + 0x840);

        writel(0x00800004, spec->mem_base + 0x20c);
        writel(0x00000000, spec->mem_base + 0x210);
        readl(spec->mem_base + 0x210);
        readl(spec->mem_base + 0x210);
}

/*
 * This second type of command is used for setting the sound filter type.
 */
static void ca0113_mmio_command_set_type2(struct hda_codec *codec,
                unsigned int group, unsigned int target, unsigned int value)
{
        struct ca0132_spec *spec = codec->spec;
        unsigned int write_val;

        writel(0x0000007e, spec->mem_base + 0x210);
        readl(spec->mem_base + 0x210);
        writel(0x0000005a, spec->mem_base + 0x210);
        readl(spec->mem_base + 0x210);
        readl(spec->mem_base + 0x210);

        writel(0x00800003, spec->mem_base + 0x20c);
        writel(group, spec->mem_base + 0x804);

        writel(0x00800005, spec->mem_base + 0x20c);
        write_val = (target & 0xff);
        write_val |= (value << 8);


        writel(write_val, spec->mem_base + 0x204);
        msleep(20);
        readl(spec->mem_base + 0x860);
        readl(spec->mem_base + 0x854);
        readl(spec->mem_base + 0x840);

        writel(0x00800004, spec->mem_base + 0x20c);
        writel(0x00000000, spec->mem_base + 0x210);
        readl(spec->mem_base + 0x210);
        readl(spec->mem_base + 0x210);
}

/*
 * Setup GPIO for the other variants of Core3D.
 */

/*
 * Sets up the GPIO pins so that they are discoverable. If this isn't done,
 * the card shows as having no GPIO pins.
 */
static void ca0132_gpio_init(struct hda_codec *codec)
{
        struct ca0132_spec *spec = codec->spec;

        switch (ca0132_quirk(spec)) {
        case QUIRK_SBZ:
        case QUIRK_AE5:
        case QUIRK_AE7:
                snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
                snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
                snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
                break;
        case QUIRK_R3DI:
                snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
                snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
                break;
        default:
                break;
        }

}

/* Sets the GPIO for audio output. */
static void ca0132_gpio_setup(struct hda_codec *codec)
{
        struct ca0132_spec *spec = codec->spec;

        switch (ca0132_quirk(spec)) {
        case QUIRK_SBZ:
                snd_hda_codec_write(codec, 0x01, 0,
                                AC_VERB_SET_GPIO_DIRECTION, 0x07);
                snd_hda_codec_write(codec, 0x01, 0,
                                AC_VERB_SET_GPIO_MASK, 0x07);
                snd_hda_codec_write(codec, 0x01, 0,
                                AC_VERB_SET_GPIO_DATA, 0x04);
                snd_hda_codec_write(codec, 0x01, 0,
                                AC_VERB_SET_GPIO_DATA, 0x06);
                break;
        case QUIRK_R3DI:
                snd_hda_codec_write(codec, 0x01, 0,
                                AC_VERB_SET_GPIO_DIRECTION, 0x1E);
                snd_hda_codec_write(codec, 0x01, 0,
                                AC_VERB_SET_GPIO_MASK, 0x1F);
                snd_hda_codec_write(codec, 0x01, 0,
                                AC_VERB_SET_GPIO_DATA, 0x0C);
                break;
        default:
                break;
        }
}

/*
 * GPIO control functions for the Recon3D integrated.
 */

enum r3di_gpio_bit {
        /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
        R3DI_MIC_SELECT_BIT = 1,
        /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
        R3DI_OUT_SELECT_BIT = 2,
        /*
         * I dunno what this actually does, but it stays on until the dsp
         * is downloaded.
         */
        R3DI_GPIO_DSP_DOWNLOADING = 3,
        /*
         * Same as above, no clue what it does, but it comes on after the dsp
         * is downloaded.
         */
        R3DI_GPIO_DSP_DOWNLOADED = 4
};

enum r3di_mic_select {
        /* Set GPIO bit 1 to 0 for rear mic */
        R3DI_REAR_MIC = 0,
        /* Set GPIO bit 1 to 1 for front microphone*/
        R3DI_FRONT_MIC = 1
};

enum r3di_out_select {
        /* Set GPIO bit 2 to 0 for headphone */
        R3DI_HEADPHONE_OUT = 0,
        /* Set GPIO bit 2 to 1 for speaker */
        R3DI_LINE_OUT = 1
};
enum r3di_dsp_status {
        /* Set GPIO bit 3 to 1 until DSP is downloaded */
        R3DI_DSP_DOWNLOADING = 0,
        /* Set GPIO bit 4 to 1 once DSP is downloaded */
        R3DI_DSP_DOWNLOADED = 1
};


static void r3di_gpio_mic_set(struct hda_codec *codec,
                enum r3di_mic_select cur_mic)
{
        unsigned int cur_gpio;

        /* Get the current GPIO Data setup */
        cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);

        switch (cur_mic) {
        case R3DI_REAR_MIC:
                cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
                break;
        case R3DI_FRONT_MIC:
                cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
                break;
        }
        snd_hda_codec_write(codec, codec->core.afg, 0,
                            AC_VERB_SET_GPIO_DATA, cur_gpio);
}

static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
                enum r3di_dsp_status dsp_status)
{
        unsigned int cur_gpio;

        /* Get the current GPIO Data setup */
        cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);

        switch (dsp_status) {
        case R3DI_DSP_DOWNLOADING:
                cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
                snd_hda_codec_write(codec, codec->core.afg, 0,
                                AC_VERB_SET_GPIO_DATA, cur_gpio);
                break;
        case R3DI_DSP_DOWNLOADED:
                /* Set DOWNLOADING bit to 0. */
                cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);

                snd_hda_codec_write(codec, codec->core.afg, 0,
                                AC_VERB_SET_GPIO_DATA, cur_gpio);

                cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
                break;
        }

        snd_hda_codec_write(codec, codec->core.afg, 0,
                            AC_VERB_SET_GPIO_DATA, cur_gpio);
}

/*
 * PCM callbacks
 */
static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
                        struct hda_codec *codec,
                        unsigned int stream_tag,
                        unsigned int format,
                        struct snd_pcm_substream *substream)
{
        struct ca0132_spec *spec = codec->spec;

        snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);

        return 0;
}

static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
                        struct hda_codec *codec,
                        struct snd_pcm_substream *substream)
{
        struct ca0132_spec *spec = codec->spec;

        if (spec->dsp_state == DSP_DOWNLOADING)
                return 0;

        /*If Playback effects are on, allow stream some time to flush
         *effects tail*/
        if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
                msleep(50);

        snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);

        return 0;
}

static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
                        struct hda_codec *codec,
                        struct snd_pcm_substream *substream)
{
        struct ca0132_spec *spec = codec->spec;
        unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
        struct snd_pcm_runtime *runtime = substream->runtime;

        if (spec->dsp_state != DSP_DOWNLOADED)
                return 0;

        /* Add latency if playback enhancement and either effect is enabled. */
        if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
                if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
                    (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
                        latency += DSP_PLAY_ENHANCEMENT_LATENCY;
        }

        /* Applying Speaker EQ adds latency as well. */
        if (spec->cur_out_type == SPEAKER_OUT)
                latency += DSP_SPEAKER_OUT_LATENCY;

        return (latency * runtime->rate) / 1000;
}

/*
 * Digital out
 */
static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
                                        struct hda_codec *codec,
                                        struct snd_pcm_substream *substream)
{
        struct ca0132_spec *spec = codec->spec;
        return snd_hda_multi_out_dig_open(codec, &spec->multiout);
}

static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
                        struct hda_codec *codec,
                        unsigned int stream_tag,
                        unsigned int format,
                        struct snd_pcm_substream *substream)
{
        struct ca0132_spec *spec = codec->spec;
        return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
                                             stream_tag, format, substream);
}

static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
                        struct hda_codec *codec,
                        struct snd_pcm_substream *substream)
{
        struct ca0132_spec *spec = codec->spec;
        return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
}

static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
                                         struct hda_codec *codec,
                                         struct snd_pcm_substream *substream)
{
        struct ca0132_spec *spec = codec->spec;
        return snd_hda_multi_out_dig_close(codec, &spec->multiout);
}

/*
 * Analog capture
 */
static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
                                        struct hda_codec *codec,
                                        unsigned int stream_tag,
                                        unsigned int format,
                                        struct snd_pcm_substream *substream)
{
        snd_hda_codec_setup_stream(codec, hinfo->nid,
                                   stream_tag, 0, format);

        return 0;
}

static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
                        struct hda_codec *codec,
                        struct snd_pcm_substream *substream)
{
        struct ca0132_spec *spec = codec->spec;

        if (spec->dsp_state == DSP_DOWNLOADING)
                return 0;

        snd_hda_codec_cleanup_stream(codec, hinfo->nid);
        return 0;
}

static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
                        struct hda_codec *codec,
                        struct snd_pcm_substream *substream)
{
        struct ca0132_spec *spec = codec->spec;
        unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
        struct snd_pcm_runtime *runtime = substream->runtime;

        if (spec->dsp_state != DSP_DOWNLOADED)
                return 0;

        if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
                latency += DSP_CRYSTAL_VOICE_LATENCY;

        return (latency * runtime->rate) / 1000;
}

/*
 * Controls stuffs.
 */

/*
 * Mixer controls helpers.
 */
#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
        { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
          .name = xname, \
          .subdevice = HDA_SUBDEV_AMP_FLAG, \
          .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
                        SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
                        SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
          .info = ca0132_volume_info, \
          .get = ca0132_volume_get, \
          .put = ca0132_volume_put, \
          .tlv = { .c = ca0132_volume_tlv }, \
          .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }

/*
 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
 * volume put, which is used for setting the DSP volume. This was done because
 * the ca0132 functions were taking too much time and causing lag.
 */
#define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
        { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
          .name = xname, \
          .subdevice = HDA_SUBDEV_AMP_FLAG, \
          .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
                        SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
                        SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
          .info = snd_hda_mixer_amp_volume_info, \
          .get = snd_hda_mixer_amp_volume_get, \
          .put = ca0132_alt_volume_put, \
          .tlv = { .c = snd_hda_mixer_amp_tlv }, \
          .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }

#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
        { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
          .name = xname, \
          .subdevice = HDA_SUBDEV_AMP_FLAG, \
          .info = snd_hda_mixer_amp_switch_info, \
          .get = ca0132_switch_get, \
          .put = ca0132_switch_put, \
          .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }

/* stereo */
#define CA0132_CODEC_VOL(xname, nid, dir) \
        CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
#define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
        CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
#define CA0132_CODEC_MUTE(xname, nid, dir) \
        CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)

/* lookup tables */
/*
 * Lookup table with decibel values for the DSP. When volume is changed in
 * Windows, the DSP is also sent the dB value in floating point. In Windows,
 * these values have decimal points, probably because the Windows driver
 * actually uses floating point. We can't here, so I made a lookup table of
 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
 * DAC's, and 9 is the maximum.
 */
static const unsigned int float_vol_db_lookup[] = {
0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
0x40C00000, 0x40E00000, 0x41000000, 0x41100000
};

/*
 * This table counts from float 0 to 1 in increments of .01, which is
 * useful for a few different sliders.
 */
static const unsigned int float_zero_to_one_lookup[] = {
0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,