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11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/device.h>
14#include <linux/pm_runtime.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <sound/core.h>
18#include <sound/pcm.h>
19#include <sound/pcm_params.h>
20#include <sound/initval.h>
21#include <sound/soc.h>
22#include <sound/dmaengine_pcm.h>
23
24#include "omap-mcbsp-priv.h"
25#include "omap-mcbsp.h"
26#include "sdma-pcm.h"
27
28#define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
29
30enum {
31 OMAP_MCBSP_WORD_8 = 0,
32 OMAP_MCBSP_WORD_12,
33 OMAP_MCBSP_WORD_16,
34 OMAP_MCBSP_WORD_20,
35 OMAP_MCBSP_WORD_24,
36 OMAP_MCBSP_WORD_32,
37};
38
39static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp)
40{
41 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
42 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n", MCBSP_READ(mcbsp, DRR2));
43 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n", MCBSP_READ(mcbsp, DRR1));
44 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n", MCBSP_READ(mcbsp, DXR2));
45 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n", MCBSP_READ(mcbsp, DXR1));
46 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n", MCBSP_READ(mcbsp, SPCR2));
47 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n", MCBSP_READ(mcbsp, SPCR1));
48 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n", MCBSP_READ(mcbsp, RCR2));
49 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n", MCBSP_READ(mcbsp, RCR1));
50 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n", MCBSP_READ(mcbsp, XCR2));
51 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n", MCBSP_READ(mcbsp, XCR1));
52 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n", MCBSP_READ(mcbsp, SRGR2));
53 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n", MCBSP_READ(mcbsp, SRGR1));
54 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n", MCBSP_READ(mcbsp, PCR0));
55 dev_dbg(mcbsp->dev, "***********************\n");
56}
57
58static int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
59{
60 struct clk *fck_src;
61 const char *src;
62 int r;
63
64 if (fck_src_id == MCBSP_CLKS_PAD_SRC)
65 src = "pad_fck";
66 else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
67 src = "prcm_fck";
68 else
69 return -EINVAL;
70
71 fck_src = clk_get(mcbsp->dev, src);
72 if (IS_ERR(fck_src)) {
73 dev_err(mcbsp->dev, "CLKS: could not clk_get() %s\n", src);
74 return -EINVAL;
75 }
76
77 pm_runtime_put_sync(mcbsp->dev);
78
79 r = clk_set_parent(mcbsp->fclk, fck_src);
80 if (r)
81 dev_err(mcbsp->dev, "CLKS: could not clk_set_parent() to %s\n",
82 src);
83
84 pm_runtime_get_sync(mcbsp->dev);
85
86 clk_put(fck_src);
87
88 return r;
89}
90
91static irqreturn_t omap_mcbsp_irq_handler(int irq, void *data)
92{
93 struct omap_mcbsp *mcbsp = data;
94 u16 irqst;
95
96 irqst = MCBSP_READ(mcbsp, IRQST);
97 dev_dbg(mcbsp->dev, "IRQ callback : 0x%x\n", irqst);
98
99 if (irqst & RSYNCERREN)
100 dev_err(mcbsp->dev, "RX Frame Sync Error!\n");
101 if (irqst & RFSREN)
102 dev_dbg(mcbsp->dev, "RX Frame Sync\n");
103 if (irqst & REOFEN)
104 dev_dbg(mcbsp->dev, "RX End Of Frame\n");
105 if (irqst & RRDYEN)
106 dev_dbg(mcbsp->dev, "RX Buffer Threshold Reached\n");
107 if (irqst & RUNDFLEN)
108 dev_err(mcbsp->dev, "RX Buffer Underflow!\n");
109 if (irqst & ROVFLEN)
110 dev_err(mcbsp->dev, "RX Buffer Overflow!\n");
111
112 if (irqst & XSYNCERREN)
113 dev_err(mcbsp->dev, "TX Frame Sync Error!\n");
114 if (irqst & XFSXEN)
115 dev_dbg(mcbsp->dev, "TX Frame Sync\n");
116 if (irqst & XEOFEN)
117 dev_dbg(mcbsp->dev, "TX End Of Frame\n");
118 if (irqst & XRDYEN)
119 dev_dbg(mcbsp->dev, "TX Buffer threshold Reached\n");
120 if (irqst & XUNDFLEN)
121 dev_err(mcbsp->dev, "TX Buffer Underflow!\n");
122 if (irqst & XOVFLEN)
123 dev_err(mcbsp->dev, "TX Buffer Overflow!\n");
124 if (irqst & XEMPTYEOFEN)
125 dev_dbg(mcbsp->dev, "TX Buffer empty at end of frame\n");
126
127 MCBSP_WRITE(mcbsp, IRQST, irqst);
128
129 return IRQ_HANDLED;
130}
131
132static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *data)
133{
134 struct omap_mcbsp *mcbsp = data;
135 u16 irqst_spcr2;
136
137 irqst_spcr2 = MCBSP_READ(mcbsp, SPCR2);
138 dev_dbg(mcbsp->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
139
140 if (irqst_spcr2 & XSYNC_ERR) {
141 dev_err(mcbsp->dev, "TX Frame Sync Error! : 0x%x\n",
142 irqst_spcr2);
143
144 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
145 }
146
147 return IRQ_HANDLED;
148}
149
150static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *data)
151{
152 struct omap_mcbsp *mcbsp = data;
153 u16 irqst_spcr1;
154
155 irqst_spcr1 = MCBSP_READ(mcbsp, SPCR1);
156 dev_dbg(mcbsp->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
157
158 if (irqst_spcr1 & RSYNC_ERR) {
159 dev_err(mcbsp->dev, "RX Frame Sync Error! : 0x%x\n",
160 irqst_spcr1);
161
162 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
163 }
164
165 return IRQ_HANDLED;
166}
167
168
169
170
171
172
173
174static void omap_mcbsp_config(struct omap_mcbsp *mcbsp,
175 const struct omap_mcbsp_reg_cfg *config)
176{
177 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
178 mcbsp->id, mcbsp->phys_base);
179
180
181 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
182 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
183 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
184 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
185 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
186 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
187 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
188 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
189 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
190 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
191 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
192 if (mcbsp->pdata->has_ccr) {
193 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
194 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
195 }
196
197 if (mcbsp->pdata->has_wakeup)
198 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
199
200
201 if (mcbsp->irq)
202 MCBSP_WRITE(mcbsp, IRQEN, RSYNCERREN | XSYNCERREN |
203 RUNDFLEN | ROVFLEN | XUNDFLEN | XOVFLEN);
204}
205
206
207
208
209
210
211
212
213
214static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp,
215 unsigned int stream)
216{
217 int data_reg;
218
219 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
220 if (mcbsp->pdata->reg_size == 2)
221 data_reg = OMAP_MCBSP_REG_DXR1;
222 else
223 data_reg = OMAP_MCBSP_REG_DXR;
224 } else {
225 if (mcbsp->pdata->reg_size == 2)
226 data_reg = OMAP_MCBSP_REG_DRR1;
227 else
228 data_reg = OMAP_MCBSP_REG_DRR;
229 }
230
231 return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
232}
233
234
235
236
237
238
239static void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
240{
241 if (threshold && threshold <= mcbsp->max_tx_thres)
242 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
243}
244
245
246
247
248
249
250static void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
251{
252 if (threshold && threshold <= mcbsp->max_rx_thres)
253 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
254}
255
256
257
258
259static u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp)
260{
261 u16 buffstat;
262
263
264 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
265
266
267 return mcbsp->pdata->buffer_size - buffstat;
268}
269
270
271
272
273
274static u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp)
275{
276 u16 buffstat, threshold;
277
278
279 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
280
281 threshold = MCBSP_READ(mcbsp, THRSH1);
282
283
284 if (threshold <= buffstat)
285 return 0;
286 else
287 return threshold - buffstat;
288}
289
290static int omap_mcbsp_request(struct omap_mcbsp *mcbsp)
291{
292 void *reg_cache;
293 int err;
294
295 reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
296 if (!reg_cache)
297 return -ENOMEM;
298
299 spin_lock(&mcbsp->lock);
300 if (!mcbsp->free) {
301 dev_err(mcbsp->dev, "McBSP%d is currently in use\n", mcbsp->id);
302 err = -EBUSY;
303 goto err_kfree;
304 }
305
306 mcbsp->free = false;
307 mcbsp->reg_cache = reg_cache;
308 spin_unlock(&mcbsp->lock);
309
310 if(mcbsp->pdata->ops && mcbsp->pdata->ops->request)
311 mcbsp->pdata->ops->request(mcbsp->id - 1);
312
313
314
315
316
317 MCBSP_WRITE(mcbsp, SPCR1, 0);
318 MCBSP_WRITE(mcbsp, SPCR2, 0);
319
320 if (mcbsp->irq) {
321 err = request_irq(mcbsp->irq, omap_mcbsp_irq_handler, 0,
322 "McBSP", (void *)mcbsp);
323 if (err != 0) {
324 dev_err(mcbsp->dev, "Unable to request IRQ\n");
325 goto err_clk_disable;
326 }
327 } else {
328 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 0,
329 "McBSP TX", (void *)mcbsp);
330 if (err != 0) {
331 dev_err(mcbsp->dev, "Unable to request TX IRQ\n");
332 goto err_clk_disable;
333 }
334
335 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, 0,
336 "McBSP RX", (void *)mcbsp);
337 if (err != 0) {
338 dev_err(mcbsp->dev, "Unable to request RX IRQ\n");
339 goto err_free_irq;
340 }
341 }
342
343 return 0;
344err_free_irq:
345 free_irq(mcbsp->tx_irq, (void *)mcbsp);
346err_clk_disable:
347 if(mcbsp->pdata->ops && mcbsp->pdata->ops->free)
348 mcbsp->pdata->ops->free(mcbsp->id - 1);
349
350
351 if (mcbsp->pdata->has_wakeup)
352 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
353
354 spin_lock(&mcbsp->lock);
355 mcbsp->free = true;
356 mcbsp->reg_cache = NULL;
357err_kfree:
358 spin_unlock(&mcbsp->lock);
359 kfree(reg_cache);
360
361 return err;
362}
363
364static void omap_mcbsp_free(struct omap_mcbsp *mcbsp)
365{
366 void *reg_cache;
367
368 if(mcbsp->pdata->ops && mcbsp->pdata->ops->free)
369 mcbsp->pdata->ops->free(mcbsp->id - 1);
370
371
372 if (mcbsp->pdata->has_wakeup)
373 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
374
375
376 if (mcbsp->irq)
377 MCBSP_WRITE(mcbsp, IRQEN, 0);
378
379 if (mcbsp->irq) {
380 free_irq(mcbsp->irq, (void *)mcbsp);
381 } else {
382 free_irq(mcbsp->rx_irq, (void *)mcbsp);
383 free_irq(mcbsp->tx_irq, (void *)mcbsp);
384 }
385
386 reg_cache = mcbsp->reg_cache;
387
388
389
390
391
392
393
394
395 if (!mcbsp_omap1())
396 omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC);
397
398 spin_lock(&mcbsp->lock);
399 if (mcbsp->free)
400 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
401 else
402 mcbsp->free = true;
403 mcbsp->reg_cache = NULL;
404 spin_unlock(&mcbsp->lock);
405
406 kfree(reg_cache);
407}
408
409
410
411
412
413
414static void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int stream)
415{
416 int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK);
417 int rx = !tx;
418 int enable_srg = 0;
419 u16 w;
420
421 if (mcbsp->st_data)
422 omap_mcbsp_st_start(mcbsp);
423
424
425 w = MCBSP_READ_CACHE(mcbsp, PCR0);
426 if (w & (FSXM | FSRM | CLKXM | CLKRM))
427 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
428 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
429
430 if (enable_srg) {
431
432 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
433 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
434 }
435
436
437 tx &= 1;
438 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
439 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
440
441 rx &= 1;
442 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
443 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
444
445
446
447
448
449
450
451 udelay(500);
452
453 if (enable_srg) {
454
455 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
456 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
457 }
458
459 if (mcbsp->pdata->has_ccr) {
460
461 w = MCBSP_READ_CACHE(mcbsp, XCCR);
462 w &= ~(tx ? XDISABLE : 0);
463 MCBSP_WRITE(mcbsp, XCCR, w);
464 w = MCBSP_READ_CACHE(mcbsp, RCCR);
465 w &= ~(rx ? RDISABLE : 0);
466 MCBSP_WRITE(mcbsp, RCCR, w);
467 }
468
469
470 omap_mcbsp_dump_reg(mcbsp);
471}
472
473static void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int stream)
474{
475 int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK);
476 int rx = !tx;
477 int idle;
478 u16 w;
479
480
481 tx &= 1;
482 if (mcbsp->pdata->has_ccr) {
483 w = MCBSP_READ_CACHE(mcbsp, XCCR);
484 w |= (tx ? XDISABLE : 0);
485 MCBSP_WRITE(mcbsp, XCCR, w);
486 }
487 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
488 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
489
490
491 rx &= 1;
492 if (mcbsp->pdata->has_ccr) {
493 w = MCBSP_READ_CACHE(mcbsp, RCCR);
494 w |= (rx ? RDISABLE : 0);
495 MCBSP_WRITE(mcbsp, RCCR, w);
496 }
497 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
498 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
499
500 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
501 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
502
503 if (idle) {
504
505 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
506 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
507 }
508
509 if (mcbsp->st_data)
510 omap_mcbsp_st_stop(mcbsp);
511}
512
513#define max_thres(m) (mcbsp->pdata->buffer_size)
514#define valid_threshold(m, val) ((val) <= max_thres(m))
515#define THRESHOLD_PROP_BUILDER(prop) \
516static ssize_t prop##_show(struct device *dev, \
517 struct device_attribute *attr, char *buf) \
518{ \
519 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
520 \
521 return sprintf(buf, "%u\n", mcbsp->prop); \
522} \
523 \
524static ssize_t prop##_store(struct device *dev, \
525 struct device_attribute *attr, \
526 const char *buf, size_t size) \
527{ \
528 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
529 unsigned long val; \
530 int status; \
531 \
532 status = kstrtoul(buf, 0, &val); \
533 if (status) \
534 return status; \
535 \
536 if (!valid_threshold(mcbsp, val)) \
537 return -EDOM; \
538 \
539 mcbsp->prop = val; \
540 return size; \
541} \
542 \
543static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store)
544
545THRESHOLD_PROP_BUILDER(max_tx_thres);
546THRESHOLD_PROP_BUILDER(max_rx_thres);
547
548static const char * const dma_op_modes[] = {
549 "element", "threshold",
550};
551
552static ssize_t dma_op_mode_show(struct device *dev,
553 struct device_attribute *attr, char *buf)
554{
555 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
556 int dma_op_mode, i = 0;
557 ssize_t len = 0;
558 const char * const *s;
559
560 dma_op_mode = mcbsp->dma_op_mode;
561
562 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
563 if (dma_op_mode == i)
564 len += sprintf(buf + len, "[%s] ", *s);
565 else
566 len += sprintf(buf + len, "%s ", *s);
567 }
568 len += sprintf(buf + len, "\n");
569
570 return len;
571}
572
573static ssize_t dma_op_mode_store(struct device *dev,
574 struct device_attribute *attr, const char *buf,
575 size_t size)
576{
577 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
578 int i;
579
580 i = sysfs_match_string(dma_op_modes, buf);
581 if (i < 0)
582 return i;
583
584 spin_lock_irq(&mcbsp->lock);
585 if (!mcbsp->free) {
586 size = -EBUSY;
587 goto unlock;
588 }
589 mcbsp->dma_op_mode = i;
590
591unlock:
592 spin_unlock_irq(&mcbsp->lock);
593
594 return size;
595}
596
597static DEVICE_ATTR_RW(dma_op_mode);
598
599static const struct attribute *additional_attrs[] = {
600 &dev_attr_max_tx_thres.attr,
601 &dev_attr_max_rx_thres.attr,
602 &dev_attr_dma_op_mode.attr,
603 NULL,
604};
605
606static const struct attribute_group additional_attr_group = {
607 .attrs = (struct attribute **)additional_attrs,
608};
609
610
611
612
613
614static int omap_mcbsp_init(struct platform_device *pdev)
615{
616 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
617 struct resource *res;
618 int ret = 0;
619
620 spin_lock_init(&mcbsp->lock);
621 mcbsp->free = true;
622
623 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
624 if (!res)
625 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
626
627 mcbsp->io_base = devm_ioremap_resource(&pdev->dev, res);
628 if (IS_ERR(mcbsp->io_base))
629 return PTR_ERR(mcbsp->io_base);
630
631 mcbsp->phys_base = res->start;
632 mcbsp->reg_cache_size = resource_size(res);
633
634 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
635 if (!res)
636 mcbsp->phys_dma_base = mcbsp->phys_base;
637 else
638 mcbsp->phys_dma_base = res->start;
639
640
641
642
643
644
645
646
647 mcbsp->irq = platform_get_irq_byname(pdev, "common");
648 if (mcbsp->irq == -ENXIO) {
649 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
650
651 if (mcbsp->tx_irq == -ENXIO) {
652 mcbsp->irq = platform_get_irq(pdev, 0);
653 mcbsp->tx_irq = 0;
654 } else {
655 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
656 mcbsp->irq = 0;
657 }
658 }
659
660 if (!pdev->dev.of_node) {
661 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
662 if (!res) {
663 dev_err(&pdev->dev, "invalid tx DMA channel\n");
664 return -ENODEV;
665 }
666 mcbsp->dma_req[0] = res->start;
667 mcbsp->dma_data[0].filter_data = &mcbsp->dma_req[0];
668
669 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
670 if (!res) {
671 dev_err(&pdev->dev, "invalid rx DMA channel\n");
672 return -ENODEV;
673 }
674 mcbsp->dma_req[1] = res->start;
675 mcbsp->dma_data[1].filter_data = &mcbsp->dma_req[1];
676 } else {
677 mcbsp->dma_data[0].filter_data = "tx";
678 mcbsp->dma_data[1].filter_data = "rx";
679 }
680
681 mcbsp->dma_data[0].addr = omap_mcbsp_dma_reg_params(mcbsp,
682 SNDRV_PCM_STREAM_PLAYBACK);
683 mcbsp->dma_data[1].addr = omap_mcbsp_dma_reg_params(mcbsp,
684 SNDRV_PCM_STREAM_CAPTURE);
685
686 mcbsp->fclk = devm_clk_get(&pdev->dev, "fck");
687 if (IS_ERR(mcbsp->fclk)) {
688 ret = PTR_ERR(mcbsp->fclk);
689 dev_err(mcbsp->dev, "unable to get fck: %d\n", ret);
690 return ret;
691 }
692
693 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
694 if (mcbsp->pdata->buffer_size) {
695
696
697
698
699
700
701
702
703 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
704 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
705
706 ret = sysfs_create_group(&mcbsp->dev->kobj,
707 &additional_attr_group);
708 if (ret) {
709 dev_err(mcbsp->dev,
710 "Unable to create additional controls\n");
711 return ret;
712 }
713 }
714
715 ret = omap_mcbsp_st_init(pdev);
716 if (ret)
717 goto err_st;
718
719 return 0;
720
721err_st:
722 if (mcbsp->pdata->buffer_size)
723 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
724 return ret;
725}
726
727
728
729
730
731static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream,
732 unsigned int packet_size)
733{
734 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
735 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
736 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
737 int words;
738
739
740 if (mcbsp->pdata->buffer_size == 0)
741 return;
742
743
744
745
746
747
748
749 if (packet_size)
750 words = packet_size;
751 else
752 words = 1;
753
754
755 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
756 omap_mcbsp_set_tx_threshold(mcbsp, words);
757 else
758 omap_mcbsp_set_rx_threshold(mcbsp, words);
759}
760
761static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
762 struct snd_pcm_hw_rule *rule)
763{
764 struct snd_interval *buffer_size = hw_param_interval(params,
765 SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
766 struct snd_interval *channels = hw_param_interval(params,
767 SNDRV_PCM_HW_PARAM_CHANNELS);
768 struct omap_mcbsp *mcbsp = rule->private;
769 struct snd_interval frames;
770 int size;
771
772 snd_interval_any(&frames);
773 size = mcbsp->pdata->buffer_size;
774
775 frames.min = size / channels->min;
776 frames.integer = 1;
777 return snd_interval_refine(buffer_size, &frames);
778}
779
780static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
781 struct snd_soc_dai *cpu_dai)
782{
783 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
784 int err = 0;
785
786 if (!snd_soc_dai_active(cpu_dai))
787 err = omap_mcbsp_request(mcbsp);
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804 if (mcbsp->pdata->buffer_size) {
805
806
807
808
809
810 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
811 snd_pcm_hw_rule_add(substream->runtime, 0,
812 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
813 omap_mcbsp_hwrule_min_buffersize,
814 mcbsp,
815 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
816
817
818 snd_pcm_hw_constraint_step(substream->runtime, 0,
819 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
820 }
821
822 return err;
823}
824
825static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
826 struct snd_soc_dai *cpu_dai)
827{
828 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
829 int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
830 int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
831 int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
832
833 if (mcbsp->latency[stream2])
834 cpu_latency_qos_update_request(&mcbsp->pm_qos_req,
835 mcbsp->latency[stream2]);
836 else if (mcbsp->latency[stream1])
837 cpu_latency_qos_remove_request(&mcbsp->pm_qos_req);
838
839 mcbsp->latency[stream1] = 0;
840
841 if (!snd_soc_dai_active(cpu_dai)) {
842 omap_mcbsp_free(mcbsp);
843 mcbsp->configured = 0;
844 }
845}
846
847static int omap_mcbsp_dai_prepare(struct snd_pcm_substream *substream,
848 struct snd_soc_dai *cpu_dai)
849{
850 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
851 struct pm_qos_request *pm_qos_req = &mcbsp->pm_qos_req;
852 int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
853 int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
854 int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
855 int latency = mcbsp->latency[stream2];
856
857
858 if (!latency || mcbsp->latency[stream1] < latency)
859 latency = mcbsp->latency[stream1];
860
861 if (cpu_latency_qos_request_active(pm_qos_req))
862 cpu_latency_qos_update_request(pm_qos_req, latency);
863 else if (latency)
864 cpu_latency_qos_add_request(pm_qos_req, latency);
865
866 return 0;
867}
868
869static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
870 struct snd_soc_dai *cpu_dai)
871{
872 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
873
874 switch (cmd) {
875 case SNDRV_PCM_TRIGGER_START:
876 case SNDRV_PCM_TRIGGER_RESUME:
877 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
878 mcbsp->active++;
879 omap_mcbsp_start(mcbsp, substream->stream);
880 break;
881
882 case SNDRV_PCM_TRIGGER_STOP:
883 case SNDRV_PCM_TRIGGER_SUSPEND:
884 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
885 omap_mcbsp_stop(mcbsp, substream->stream);
886 mcbsp->active--;
887 break;
888 default:
889 return -EINVAL;
890 }
891
892 return 0;
893}
894
895static snd_pcm_sframes_t omap_mcbsp_dai_delay(
896 struct snd_pcm_substream *substream,
897 struct snd_soc_dai *dai)
898{
899 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
900 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
901 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
902 u16 fifo_use;
903 snd_pcm_sframes_t delay;
904
905
906 if (mcbsp->pdata->buffer_size == 0)
907 return 0;
908
909 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
910 fifo_use = omap_mcbsp_get_tx_delay(mcbsp);
911 else
912 fifo_use = omap_mcbsp_get_rx_delay(mcbsp);
913
914
915
916
917
918
919 delay = fifo_use / substream->runtime->channels;
920
921 return delay;
922}
923
924static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
925 struct snd_pcm_hw_params *params,
926 struct snd_soc_dai *cpu_dai)
927{
928 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
929 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
930 struct snd_dmaengine_dai_dma_data *dma_data;
931 int wlen, channels, wpf;
932 int pkt_size = 0;
933 unsigned int format, div, framesize, master;
934 unsigned int buffer_size = mcbsp->pdata->buffer_size;
935
936 dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
937 channels = params_channels(params);
938
939 switch (params_format(params)) {
940 case SNDRV_PCM_FORMAT_S16_LE:
941 wlen = 16;
942 break;
943 case SNDRV_PCM_FORMAT_S32_LE:
944 wlen = 32;
945 break;
946 default:
947 return -EINVAL;
948 }
949 if (buffer_size) {
950 int latency;
951
952 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
953 int period_words, max_thrsh;
954 int divider = 0;
955
956 period_words = params_period_bytes(params) / (wlen / 8);
957 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
958 max_thrsh = mcbsp->max_tx_thres;
959 else
960 max_thrsh = mcbsp->max_rx_thres;
961
962
963
964
965
966
967
968 divider = period_words / max_thrsh;
969 if (period_words % max_thrsh)
970 divider++;
971 while (period_words % divider &&
972 divider < period_words)
973 divider++;
974 if (divider == period_words)
975 return -EINVAL;
976
977 pkt_size = period_words / divider;
978 } else if (channels > 1) {
979
980 pkt_size = channels;
981 }
982
983 latency = (buffer_size - pkt_size) / channels;
984 latency = latency * USEC_PER_SEC /
985 (params->rate_num / params->rate_den);
986 mcbsp->latency[substream->stream] = latency;
987
988 omap_mcbsp_set_threshold(substream, pkt_size);
989 }
990
991 dma_data->maxburst = pkt_size;
992
993 if (mcbsp->configured) {
994
995 return 0;
996 }
997
998 regs->rcr2 &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7));
999 regs->xcr2 &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7));
1000 regs->rcr1 &= ~(RFRLEN1(0x7f) | RWDLEN1(7));
1001 regs->xcr1 &= ~(XFRLEN1(0x7f) | XWDLEN1(7));
1002 format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
1003 wpf = channels;
1004 if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
1005 format == SND_SOC_DAIFMT_LEFT_J)) {
1006
1007 regs->rcr2 |= RPHASE;
1008 regs->xcr2 |= XPHASE;
1009
1010 wpf--;
1011 regs->rcr2 |= RFRLEN2(wpf - 1);
1012 regs->xcr2 |= XFRLEN2(wpf - 1);
1013 }
1014
1015 regs->rcr1 |= RFRLEN1(wpf - 1);
1016 regs->xcr1 |= XFRLEN1(wpf - 1);
1017
1018 switch (params_format(params)) {
1019 case SNDRV_PCM_FORMAT_S16_LE:
1020
1021 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
1022 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
1023 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
1024 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
1025 break;
1026 case SNDRV_PCM_FORMAT_S32_LE:
1027
1028 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_32);
1029 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_32);
1030 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_32);
1031 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_32);
1032 break;
1033 default:
1034
1035 return -EINVAL;
1036 }
1037
1038
1039
1040 master = mcbsp->fmt & SND_SOC_DAIFMT_MASTER_MASK;
1041 if (master == SND_SOC_DAIFMT_CBS_CFS) {
1042 div = mcbsp->clk_div ? mcbsp->clk_div : 1;
1043 framesize = (mcbsp->in_freq / div) / params_rate(params);
1044
1045 if (framesize < wlen * channels) {
1046 printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
1047 "channels\n", __func__);
1048 return -EINVAL;
1049 }
1050 } else
1051 framesize = wlen * channels;
1052
1053
1054 regs->srgr2 &= ~FPER(0xfff);
1055 regs->srgr1 &= ~FWID(0xff);
1056 switch (format) {
1057 case SND_SOC_DAIFMT_I2S:
1058 case SND_SOC_DAIFMT_LEFT_J:
1059 regs->srgr2 |= FPER(framesize - 1);
1060 regs->srgr1 |= FWID((framesize >> 1) - 1);
1061 break;
1062 case SND_SOC_DAIFMT_DSP_A:
1063 case SND_SOC_DAIFMT_DSP_B:
1064 regs->srgr2 |= FPER(framesize - 1);
1065 regs->srgr1 |= FWID(0);
1066 break;
1067 }
1068
1069 omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs);
1070 mcbsp->wlen = wlen;
1071 mcbsp->configured = 1;
1072
1073 return 0;
1074}
1075
1076
1077
1078
1079
1080static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
1081 unsigned int fmt)
1082{
1083 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1084 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1085 bool inv_fs = false;
1086
1087 if (mcbsp->configured)
1088 return 0;
1089
1090 mcbsp->fmt = fmt;
1091 memset(regs, 0, sizeof(*regs));
1092
1093 regs->spcr2 |= XINTM(3) | FREE;
1094 regs->spcr1 |= RINTM(3);
1095
1096 if (!mcbsp->pdata->has_ccr) {
1097 regs->rcr2 |= RFIG;
1098 regs->xcr2 |= XFIG;
1099 }
1100
1101
1102 if (mcbsp->pdata->has_ccr) {
1103 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
1104 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
1105 }
1106
1107 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1108 case SND_SOC_DAIFMT_I2S:
1109
1110 regs->rcr2 |= RDATDLY(1);
1111 regs->xcr2 |= XDATDLY(1);
1112 break;
1113 case SND_SOC_DAIFMT_LEFT_J:
1114
1115 regs->rcr2 |= RDATDLY(0);
1116 regs->xcr2 |= XDATDLY(0);
1117 regs->spcr1 |= RJUST(2);
1118
1119 inv_fs = true;
1120 break;
1121 case SND_SOC_DAIFMT_DSP_A:
1122
1123 regs->rcr2 |= RDATDLY(1);
1124 regs->xcr2 |= XDATDLY(1);
1125
1126 inv_fs = true;
1127 break;
1128 case SND_SOC_DAIFMT_DSP_B:
1129
1130 regs->rcr2 |= RDATDLY(0);
1131 regs->xcr2 |= XDATDLY(0);
1132
1133 inv_fs = true;
1134 break;
1135 default:
1136
1137 return -EINVAL;
1138 }
1139
1140 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1141 case SND_SOC_DAIFMT_CBS_CFS:
1142
1143 regs->pcr0 |= FSXM | FSRM |
1144 CLKXM | CLKRM;
1145
1146 regs->srgr2 |= FSGM;
1147 break;
1148 case SND_SOC_DAIFMT_CBM_CFS:
1149
1150 regs->srgr2 |= FSGM;
1151 regs->pcr0 |= FSXM | FSRM;
1152 break;
1153 case SND_SOC_DAIFMT_CBM_CFM:
1154
1155 break;
1156 default:
1157
1158 return -EINVAL;
1159 }
1160
1161
1162 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1163 case SND_SOC_DAIFMT_NB_NF:
1164
1165
1166
1167
1168
1169 regs->pcr0 |= FSXP | FSRP |
1170 CLKXP | CLKRP;
1171 break;
1172 case SND_SOC_DAIFMT_NB_IF:
1173 regs->pcr0 |= CLKXP | CLKRP;
1174 break;
1175 case SND_SOC_DAIFMT_IB_NF:
1176 regs->pcr0 |= FSXP | FSRP;
1177 break;
1178 case SND_SOC_DAIFMT_IB_IF:
1179 break;
1180 default:
1181 return -EINVAL;
1182 }
1183 if (inv_fs)
1184 regs->pcr0 ^= FSXP | FSRP;
1185
1186 return 0;
1187}
1188
1189static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
1190 int div_id, int div)
1191{
1192 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1193 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1194
1195 if (div_id != OMAP_MCBSP_CLKGDV)
1196 return -ENODEV;
1197
1198 mcbsp->clk_div = div;
1199 regs->srgr1 &= ~CLKGDV(0xff);
1200 regs->srgr1 |= CLKGDV(div - 1);
1201
1202 return 0;
1203}
1204
1205static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
1206 int clk_id, unsigned int freq,
1207 int dir)
1208{
1209 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1210 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1211 int err = 0;
1212
1213 if (mcbsp->active) {
1214 if (freq == mcbsp->in_freq)
1215 return 0;
1216 else
1217 return -EBUSY;
1218 }
1219
1220 mcbsp->in_freq = freq;
1221 regs->srgr2 &= ~CLKSM;
1222 regs->pcr0 &= ~SCLKME;
1223
1224 switch (clk_id) {
1225 case OMAP_MCBSP_SYSCLK_CLK:
1226 regs->srgr2 |= CLKSM;
1227 break;
1228 case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
1229 if (mcbsp_omap1()) {
1230 err = -EINVAL;
1231 break;
1232 }
1233 err = omap2_mcbsp_set_clks_src(mcbsp,
1234 MCBSP_CLKS_PRCM_SRC);
1235 break;
1236 case OMAP_MCBSP_SYSCLK_CLKS_EXT:
1237 if (mcbsp_omap1()) {
1238 err = 0;
1239 break;
1240 }
1241 err = omap2_mcbsp_set_clks_src(mcbsp,
1242 MCBSP_CLKS_PAD_SRC);
1243 break;
1244
1245 case OMAP_MCBSP_SYSCLK_CLKX_EXT:
1246 regs->srgr2 |= CLKSM;
1247 regs->pcr0 |= SCLKME;
1248
1249
1250
1251
1252
1253
1254 regs->pcr0 &= ~CLKXM;
1255 break;
1256 case OMAP_MCBSP_SYSCLK_CLKR_EXT:
1257 regs->pcr0 |= SCLKME;
1258
1259 regs->pcr0 &= ~CLKRM;
1260 break;
1261 default:
1262 err = -ENODEV;
1263 }
1264
1265 return err;
1266}
1267
1268static const struct snd_soc_dai_ops mcbsp_dai_ops = {
1269 .startup = omap_mcbsp_dai_startup,
1270 .shutdown = omap_mcbsp_dai_shutdown,
1271 .prepare = omap_mcbsp_dai_prepare,
1272 .trigger = omap_mcbsp_dai_trigger,
1273 .delay = omap_mcbsp_dai_delay,
1274 .hw_params = omap_mcbsp_dai_hw_params,
1275 .set_fmt = omap_mcbsp_dai_set_dai_fmt,
1276 .set_clkdiv = omap_mcbsp_dai_set_clkdiv,
1277 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
1278};
1279
1280static int omap_mcbsp_probe(struct snd_soc_dai *dai)
1281{
1282 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
1283
1284 pm_runtime_enable(mcbsp->dev);
1285
1286 snd_soc_dai_init_dma_data(dai,
1287 &mcbsp->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
1288 &mcbsp->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
1289
1290 return 0;
1291}
1292
1293static int omap_mcbsp_remove(struct snd_soc_dai *dai)
1294{
1295 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
1296
1297 pm_runtime_disable(mcbsp->dev);
1298
1299 return 0;
1300}
1301
1302static struct snd_soc_dai_driver omap_mcbsp_dai = {
1303 .probe = omap_mcbsp_probe,
1304 .remove = omap_mcbsp_remove,
1305 .playback = {
1306 .channels_min = 1,
1307 .channels_max = 16,
1308 .rates = OMAP_MCBSP_RATES,
1309 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
1310 },
1311 .capture = {
1312 .channels_min = 1,
1313 .channels_max = 16,
1314 .rates = OMAP_MCBSP_RATES,
1315 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
1316 },
1317 .ops = &mcbsp_dai_ops,
1318};
1319
1320static const struct snd_soc_component_driver omap_mcbsp_component = {
1321 .name = "omap-mcbsp",
1322};
1323
1324static struct omap_mcbsp_platform_data omap2420_pdata = {
1325 .reg_step = 4,
1326 .reg_size = 2,
1327};
1328
1329static struct omap_mcbsp_platform_data omap2430_pdata = {
1330 .reg_step = 4,
1331 .reg_size = 4,
1332 .has_ccr = true,
1333};
1334
1335static struct omap_mcbsp_platform_data omap3_pdata = {
1336 .reg_step = 4,
1337 .reg_size = 4,
1338 .has_ccr = true,
1339 .has_wakeup = true,
1340};
1341
1342static struct omap_mcbsp_platform_data omap4_pdata = {
1343 .reg_step = 4,
1344 .reg_size = 4,
1345 .has_ccr = true,
1346 .has_wakeup = true,
1347};
1348
1349static const struct of_device_id omap_mcbsp_of_match[] = {
1350 {
1351 .compatible = "ti,omap2420-mcbsp",
1352 .data = &omap2420_pdata,
1353 },
1354 {
1355 .compatible = "ti,omap2430-mcbsp",
1356 .data = &omap2430_pdata,
1357 },
1358 {
1359 .compatible = "ti,omap3-mcbsp",
1360 .data = &omap3_pdata,
1361 },
1362 {
1363 .compatible = "ti,omap4-mcbsp",
1364 .data = &omap4_pdata,
1365 },
1366 { },
1367};
1368MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match);
1369
1370static int asoc_mcbsp_probe(struct platform_device *pdev)
1371{
1372 struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev);
1373 struct omap_mcbsp *mcbsp;
1374 const struct of_device_id *match;
1375 int ret;
1376
1377 match = of_match_device(omap_mcbsp_of_match, &pdev->dev);
1378 if (match) {
1379 struct device_node *node = pdev->dev.of_node;
1380 struct omap_mcbsp_platform_data *pdata_quirk = pdata;
1381 int buffer_size;
1382
1383 pdata = devm_kzalloc(&pdev->dev,
1384 sizeof(struct omap_mcbsp_platform_data),
1385 GFP_KERNEL);
1386 if (!pdata)
1387 return -ENOMEM;
1388
1389 memcpy(pdata, match->data, sizeof(*pdata));
1390 if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size))
1391 pdata->buffer_size = buffer_size;
1392 if (pdata_quirk)
1393 pdata->force_ick_on = pdata_quirk->force_ick_on;
1394 } else if (!pdata) {
1395 dev_err(&pdev->dev, "missing platform data.\n");
1396 return -EINVAL;
1397 }
1398 mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL);
1399 if (!mcbsp)
1400 return -ENOMEM;
1401
1402 mcbsp->id = pdev->id;
1403 mcbsp->pdata = pdata;
1404 mcbsp->dev = &pdev->dev;
1405 platform_set_drvdata(pdev, mcbsp);
1406
1407 ret = omap_mcbsp_init(pdev);
1408 if (ret)
1409 return ret;
1410
1411 if (mcbsp->pdata->reg_size == 2) {
1412 omap_mcbsp_dai.playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
1413 omap_mcbsp_dai.capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
1414 }
1415
1416 ret = devm_snd_soc_register_component(&pdev->dev,
1417 &omap_mcbsp_component,
1418 &omap_mcbsp_dai, 1);
1419 if (ret)
1420 return ret;
1421
1422 return sdma_pcm_platform_register(&pdev->dev, "tx", "rx");
1423}
1424
1425static int asoc_mcbsp_remove(struct platform_device *pdev)
1426{
1427 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1428
1429 if (mcbsp->pdata->ops && mcbsp->pdata->ops->free)
1430 mcbsp->pdata->ops->free(mcbsp->id);
1431
1432 if (cpu_latency_qos_request_active(&mcbsp->pm_qos_req))
1433 cpu_latency_qos_remove_request(&mcbsp->pm_qos_req);
1434
1435 if (mcbsp->pdata->buffer_size)
1436 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
1437
1438 omap_mcbsp_st_cleanup(pdev);
1439
1440 return 0;
1441}
1442
1443static struct platform_driver asoc_mcbsp_driver = {
1444 .driver = {
1445 .name = "omap-mcbsp",
1446 .of_match_table = omap_mcbsp_of_match,
1447 },
1448
1449 .probe = asoc_mcbsp_probe,
1450 .remove = asoc_mcbsp_remove,
1451};
1452
1453module_platform_driver(asoc_mcbsp_driver);
1454
1455MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>");
1456MODULE_DESCRIPTION("OMAP I2S SoC Interface");
1457MODULE_LICENSE("GPL");
1458MODULE_ALIAS("platform:omap-mcbsp");
1459