LXR linux/arch/powerpc/include/asm/processor.h

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2#ifndef _ASM_POWERPC_PROCESSOR_H
   3#define _ASM_POWERPC_PROCESSOR_H
   4
   5/*
   6 * Copyright (C) 2001 PPC 64 Team, IBM Corp
   7 */
   8
   9#include <asm/reg.h>
  10
  11#ifdef CONFIG_VSX
  12#define TS_FPRWIDTH 2
  13
  14#ifdef __BIG_ENDIAN__
  15#define TS_FPROFFSET 0
  16#define TS_VSRLOWOFFSET 1
  17#else
  18#define TS_FPROFFSET 1
  19#define TS_VSRLOWOFFSET 0
  20#endif
  21
  22#else
  23#define TS_FPRWIDTH 1
  24#define TS_FPROFFSET 0
  25#endif
  26
  27#ifdef CONFIG_PPC64
  28/* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
  29#define PPR_PRIORITY 3
  30#ifdef __ASSEMBLY__
  31#define DEFAULT_PPR (PPR_PRIORITY << 50)
  32#else
  33#define DEFAULT_PPR ((u64)PPR_PRIORITY << 50)
  34#endif /* __ASSEMBLY__ */
  35#endif /* CONFIG_PPC64 */
  36
  37#ifndef __ASSEMBLY__
  38#include <linux/types.h>
  39#include <linux/thread_info.h>
  40#include <asm/ptrace.h>
  41#include <asm/hw_breakpoint.h>
  42
  43/* We do _not_ want to define new machine types at all, those must die
  44 * in favor of using the device-tree
  45 * -- BenH.
  46 */
  47
  48/* PREP sub-platform types. Unused */
  49#define _PREP_Motorola  0x01    /* motorola prep */
  50#define _PREP_Firm      0x02    /* firmworks prep */
  51#define _PREP_IBM       0x00    /* ibm prep */
  52#define _PREP_Bull      0x03    /* bull prep */
  53
  54/* CHRP sub-platform types. These are arbitrary */
  55#define _CHRP_Motorola  0x04    /* motorola chrp, the cobra */
  56#define _CHRP_IBM       0x05    /* IBM chrp, the longtrail and longtrail 2 */
  57#define _CHRP_Pegasos   0x06    /* Genesi/bplan's Pegasos and Pegasos2 */
  58#define _CHRP_briq      0x07    /* TotalImpact's briQ */
  59
  60#if defined(__KERNEL__) && defined(CONFIG_PPC32)
  61
  62extern int _chrp_type;
  63
  64#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
  65
  66/* Macros for adjusting thread priority (hardware multi-threading) */
  67#define HMT_very_low()   asm volatile("or 31,31,31   # very low priority")
  68#define HMT_low()        asm volatile("or 1,1,1      # low priority")
  69#define HMT_medium_low() asm volatile("or 6,6,6      # medium low priority")
  70#define HMT_medium()     asm volatile("or 2,2,2      # medium priority")
  71#define HMT_medium_high() asm volatile("or 5,5,5      # medium high priority")
  72#define HMT_high()       asm volatile("or 3,3,3      # high priority")
  73
  74#ifdef __KERNEL__
  75
  76#ifdef CONFIG_PPC64
  77#include <asm/task_size_64.h>
  78#else
  79#include <asm/task_size_32.h>
  80#endif
  81
  82struct task_struct;
  83void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
  84void release_thread(struct task_struct *);
  85
  86#define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET]
  87#define TS_CKFPR(i) ckfp_state.fpr[i][TS_FPROFFSET]
  88
  89/* FP and VSX 0-31 register set */
  90struct thread_fp_state {
  91        u64     fpr[32][TS_FPRWIDTH] __attribute__((aligned(16)));
  92        u64     fpscr;          /* Floating point status */
  93};
  94
  95/* Complete AltiVec register set including VSCR */
  96struct thread_vr_state {
  97        vector128       vr[32] __attribute__((aligned(16)));
  98        vector128       vscr __attribute__((aligned(16)));
  99};
 100
 101struct debug_reg {
 102#ifdef CONFIG_PPC_ADV_DEBUG_REGS
 103        /*
 104         * The following help to manage the use of Debug Control Registers
 105         * om the BookE platforms.
 106         */
 107        uint32_t        dbcr0;
 108        uint32_t        dbcr1;
 109#ifdef CONFIG_BOOKE
 110        uint32_t        dbcr2;
 111#endif
 112        /*
 113         * The stored value of the DBSR register will be the value at the
 114         * last debug interrupt. This register can only be read from the
 115         * user (will never be written to) and has value while helping to
 116         * describe the reason for the last debug trap.  Torez
 117         */
 118        uint32_t        dbsr;
 119        /*
 120         * The following will contain addresses used by debug applications
 121         * to help trace and trap on particular address locations.
 122         * The bits in the Debug Control Registers above help define which
 123         * of the following registers will contain valid data and/or addresses.
 124         */
 125        unsigned long   iac1;
 126        unsigned long   iac2;
 127#if CONFIG_PPC_ADV_DEBUG_IACS > 2
 128        unsigned long   iac3;
 129        unsigned long   iac4;
 130#endif
 131        unsigned long   dac1;
 132        unsigned long   dac2;
 133#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 134        unsigned long   dvc1;
 135        unsigned long   dvc2;
 136#endif
 137#endif
 138};
 139
 140struct thread_struct {
 141        unsigned long   ksp;            /* Kernel stack pointer */
 142
 143#ifdef CONFIG_PPC64
 144        unsigned long   ksp_vsid;
 145#endif
 146        struct pt_regs  *regs;          /* Pointer to saved register state */
 147#ifdef CONFIG_BOOKE
 148        /* BookE base exception scratch space; align on cacheline */
 149        unsigned long   normsave[8] ____cacheline_aligned;
 150#endif
 151#ifdef CONFIG_PPC32
 152        void            *pgdir;         /* root of page-table tree */
 153        unsigned long   ksp_limit;      /* if ksp <= ksp_limit stack overflow */
 154#ifdef CONFIG_PPC_RTAS
 155        unsigned long   rtas_sp;        /* stack pointer for when in RTAS */
 156#endif
 157#endif
 158#if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP)
 159        unsigned long   kuap;           /* opened segments for user access */
 160#endif
 161#ifdef CONFIG_VMAP_STACK
 162        unsigned long   srr0;
 163        unsigned long   srr1;
 164        unsigned long   dar;
 165        unsigned long   dsisr;
 166#ifdef CONFIG_PPC_BOOK3S_32
 167        unsigned long   r0, r3, r4, r5, r6, r8, r9, r11;
 168        unsigned long   lr, ctr;
 169#endif
 170#endif
 171        /* Debug Registers */
 172        struct debug_reg debug;
 173        struct thread_fp_state  fp_state;
 174        struct thread_fp_state  *fp_save_area;
 175        int             fpexc_mode;     /* floating-point exception mode */
 176        unsigned int    align_ctl;      /* alignment handling control */
 177#ifdef CONFIG_HAVE_HW_BREAKPOINT
 178        struct perf_event *ptrace_bps[HBP_NUM_MAX];
 179        /*
 180         * Helps identify source of single-step exception and subsequent
 181         * hw-breakpoint enablement
 182         */
 183        struct perf_event *last_hit_ubp[HBP_NUM_MAX];
 184#endif /* CONFIG_HAVE_HW_BREAKPOINT */
 185        struct arch_hw_breakpoint hw_brk[HBP_NUM_MAX]; /* hardware breakpoint info */
 186        unsigned long   trap_nr;        /* last trap # on this thread */
 187        u8 load_slb;                    /* Ages out SLB preload cache entries */
 188        u8 load_fp;
 189#ifdef CONFIG_ALTIVEC
 190        u8 load_vec;
 191        struct thread_vr_state vr_state;
 192        struct thread_vr_state *vr_save_area;
 193        unsigned long   vrsave;
 194        int             used_vr;        /* set if process has used altivec */
 195#endif /* CONFIG_ALTIVEC */
 196#ifdef CONFIG_VSX
 197        /* VSR status */
 198        int             used_vsr;       /* set if process has used VSX */
 199#endif /* CONFIG_VSX */
 200#ifdef CONFIG_SPE
 201        unsigned long   evr[32];        /* upper 32-bits of SPE regs */
 202        u64             acc;            /* Accumulator */
 203        unsigned long   spefscr;        /* SPE & eFP status */
 204        unsigned long   spefscr_last;   /* SPEFSCR value on last prctl
 205                                           call or trap return */
 206        int             used_spe;       /* set if process has used spe */
 207#endif /* CONFIG_SPE */
 208#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 209        u8      load_tm;
 210        u64             tm_tfhar;       /* Transaction fail handler addr */
 211        u64             tm_texasr;      /* Transaction exception & summary */
 212        u64             tm_tfiar;       /* Transaction fail instr address reg */
 213        struct pt_regs  ckpt_regs;      /* Checkpointed registers */
 214
 215        unsigned long   tm_tar;
 216        unsigned long   tm_ppr;
 217        unsigned long   tm_dscr;
 218        unsigned long   tm_amr;
 219
 220        /*
 221         * Checkpointed FP and VSX 0-31 register set.
 222         *
 223         * When a transaction is active/signalled/scheduled etc., *regs is the
 224         * most recent set of/speculated GPRs with ckpt_regs being the older
 225         * checkpointed regs to which we roll back if transaction aborts.
 226         *
 227         * These are analogous to how ckpt_regs and pt_regs work
 228         */
 229        struct thread_fp_state ckfp_state; /* Checkpointed FP state */
 230        struct thread_vr_state ckvr_state; /* Checkpointed VR state */
 231        unsigned long   ckvrsave; /* Checkpointed VRSAVE */
 232#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 233#ifdef CONFIG_PPC_MEM_KEYS
 234        unsigned long   amr;
 235        unsigned long   iamr;
 236#endif
 237#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
 238        void*           kvm_shadow_vcpu; /* KVM internal data */
 239#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
 240#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
 241        struct kvm_vcpu *kvm_vcpu;
 242#endif
 243#ifdef CONFIG_PPC64
 244        unsigned long   dscr;
 245        unsigned long   fscr;
 246        /*
 247         * This member element dscr_inherit indicates that the process
 248         * has explicitly attempted and changed the DSCR register value
 249         * for itself. Hence kernel wont use the default CPU DSCR value
 250         * contained in the PACA structure anymore during process context
 251         * switch. Once this variable is set, this behaviour will also be
 252         * inherited to all the children of this process from that point
 253         * onwards.
 254         */
 255        int             dscr_inherit;
 256        unsigned long   tidr;
 257#endif
 258#ifdef CONFIG_PPC_BOOK3S_64
 259        unsigned long   tar;
 260        unsigned long   ebbrr;
 261        unsigned long   ebbhr;
 262        unsigned long   bescr;
 263        unsigned long   siar;
 264        unsigned long   sdar;
 265        unsigned long   sier;
 266        unsigned long   mmcr2;
 267        unsigned        mmcr0;
 268
 269        unsigned        used_ebb;
 270        unsigned long   mmcr3;
 271        unsigned long   sier2;
 272        unsigned long   sier3;
 273
 274#endif
 275};
 276
 277#define ARCH_MIN_TASKALIGN 16
 278
 279#define INIT_SP         (sizeof(init_stack) + (unsigned long) &init_stack)
 280#define INIT_SP_LIMIT   ((unsigned long)&init_stack)
 281
 282#ifdef CONFIG_SPE
 283#define SPEFSCR_INIT \
 284        .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \
 285        .spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
 286#else
 287#define SPEFSCR_INIT
 288#endif
 289
 290#ifdef CONFIG_PPC32
 291#define INIT_THREAD { \
 292        .ksp = INIT_SP, \
 293        .ksp_limit = INIT_SP_LIMIT, \
 294        .pgdir = swapper_pg_dir, \
 295        .fpexc_mode = MSR_FE0 | MSR_FE1, \
 296        SPEFSCR_INIT \
 297}
 298#else
 299#define INIT_THREAD  { \
 300        .ksp = INIT_SP, \
 301        .fpexc_mode = 0, \
 302}
 303#endif
 304
 305#define task_pt_regs(tsk)       ((tsk)->thread.regs)
 306
 307unsigned long get_wchan(struct task_struct *p);
 308
 309#define KSTK_EIP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
 310#define KSTK_ESP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
 311
 312/* Get/set floating-point exception mode */
 313#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
 314#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
 315
 316extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
 317extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
 318
 319#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
 320#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
 321
 322extern int get_endian(struct task_struct *tsk, unsigned long adr);
 323extern int set_endian(struct task_struct *tsk, unsigned int val);
 324
 325#define GET_UNALIGN_CTL(tsk, adr)       get_unalign_ctl((tsk), (adr))
 326#define SET_UNALIGN_CTL(tsk, val)       set_unalign_ctl((tsk), (val))
 327
 328extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
 329extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
 330
 331extern void load_fp_state(struct thread_fp_state *fp);
 332extern void store_fp_state(struct thread_fp_state *fp);
 333extern void load_vr_state(struct thread_vr_state *vr);
 334extern void store_vr_state(struct thread_vr_state *vr);
 335
 336static inline unsigned int __unpack_fe01(unsigned long msr_bits)
 337{
 338        return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
 339}
 340
 341static inline unsigned long __pack_fe01(unsigned int fpmode)
 342{
 343        return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
 344}
 345
 346#ifdef CONFIG_PPC64
 347#define cpu_relax()     do { HMT_low(); HMT_medium(); barrier(); } while (0)
 348
 349#define spin_begin()    HMT_low()
 350
 351#define spin_cpu_relax()        barrier()
 352
 353#define spin_end()      HMT_medium()
 354
 355#define spin_until_cond(cond)                                   \
 356do {                                                            \
 357        if (unlikely(!(cond))) {                                \
 358                spin_begin();                                   \
 359                do {                                            \
 360                        spin_cpu_relax();                       \
 361                } while (!(cond));                              \
 362                spin_end();                                     \
 363        }                                                       \
 364} while (0)
 365
 366#else
 367#define cpu_relax()     barrier()
 368#endif
 369
 370/* Check that a certain kernel stack pointer is valid in task_struct p */
 371int validate_sp(unsigned long sp, struct task_struct *p,
 372                       unsigned long nbytes);
 373
 374/*
 375 * Prefetch macros.
 376 */
 377#define ARCH_HAS_PREFETCH
 378#define ARCH_HAS_PREFETCHW
 379#define ARCH_HAS_SPINLOCK_PREFETCH
 380
 381static inline void prefetch(const void *x)
 382{
 383        if (unlikely(!x))
 384                return;
 385
 386        __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
 387}
 388
 389static inline void prefetchw(const void *x)
 390{
 391        if (unlikely(!x))
 392                return;
 393
 394        __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
 395}
 396
 397#define spin_lock_prefetch(x)   prefetchw(x)
 398
 399#define HAVE_ARCH_PICK_MMAP_LAYOUT
 400
 401#ifdef CONFIG_PPC64
 402static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
 403{
 404        if (is_32)
 405                return sp & 0x0ffffffffUL;
 406        return sp;
 407}
 408#else
 409static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
 410{
 411        return sp;
 412}
 413#endif
 414
 415/* asm stubs */
 416extern unsigned long isa300_idle_stop_noloss(unsigned long psscr_val);
 417extern unsigned long isa300_idle_stop_mayloss(unsigned long psscr_val);
 418extern unsigned long isa206_idle_insn_mayloss(unsigned long type);
 419#ifdef CONFIG_PPC_970_NAP
 420extern void power4_idle_nap(void);
 421#endif
 422
 423extern unsigned long cpuidle_disable;
 424enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
 425
 426extern int powersave_nap;       /* set if nap mode can be used in idle loop */
 427
 428extern void power7_idle_type(unsigned long type);
 429extern void arch300_idle_type(unsigned long stop_psscr_val,
 430                              unsigned long stop_psscr_mask);
 431
 432extern int fix_alignment(struct pt_regs *);
 433
 434#ifdef CONFIG_PPC64
 435/*
 436 * We handle most unaligned accesses in hardware. On the other hand 
 437 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
 438 * powers of 2 writes until it reaches sufficient alignment).
 439 *
 440 * Based on this we disable the IP header alignment in network drivers.
 441 */
 442#define NET_IP_ALIGN    0
 443#endif
 444
 445#endif /* __KERNEL__ */
 446#endif /* __ASSEMBLY__ */
 447#endif /* _ASM_POWERPC_PROCESSOR_H */
 448