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17#undef DEBUG
18#undef DEBUG_LOW
19
20#define pr_fmt(fmt) "hash-mmu: " fmt
21#include <linux/spinlock.h>
22#include <linux/errno.h>
23#include <linux/sched/mm.h>
24#include <linux/proc_fs.h>
25#include <linux/stat.h>
26#include <linux/sysctl.h>
27#include <linux/export.h>
28#include <linux/ctype.h>
29#include <linux/cache.h>
30#include <linux/init.h>
31#include <linux/signal.h>
32#include <linux/memblock.h>
33#include <linux/context_tracking.h>
34#include <linux/libfdt.h>
35#include <linux/pkeys.h>
36#include <linux/hugetlb.h>
37#include <linux/cpu.h>
38#include <linux/pgtable.h>
39
40#include <asm/debugfs.h>
41#include <asm/processor.h>
42#include <asm/mmu.h>
43#include <asm/mmu_context.h>
44#include <asm/page.h>
45#include <asm/types.h>
46#include <linux/uaccess.h>
47#include <asm/machdep.h>
48#include <asm/prom.h>
49#include <asm/io.h>
50#include <asm/eeh.h>
51#include <asm/tlb.h>
52#include <asm/cacheflush.h>
53#include <asm/cputable.h>
54#include <asm/sections.h>
55#include <asm/copro.h>
56#include <asm/udbg.h>
57#include <asm/code-patching.h>
58#include <asm/fadump.h>
59#include <asm/firmware.h>
60#include <asm/tm.h>
61#include <asm/trace.h>
62#include <asm/ps3.h>
63#include <asm/pte-walk.h>
64#include <asm/asm-prototypes.h>
65#include <asm/ultravisor.h>
66
67#include <mm/mmu_decl.h>
68
69#include "internal.h"
70
71
72#ifdef DEBUG
73#define DBG(fmt...) udbg_printf(fmt)
74#else
75#define DBG(fmt...)
76#endif
77
78#ifdef DEBUG_LOW
79#define DBG_LOW(fmt...) udbg_printf(fmt)
80#else
81#define DBG_LOW(fmt...)
82#endif
83
84#define KB (1024)
85#define MB (1024*KB)
86#define GB (1024L*MB)
87
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98
99
100static unsigned long _SDR1;
101struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
102EXPORT_SYMBOL_GPL(mmu_psize_defs);
103
104u8 hpte_page_sizes[1 << LP_BITS];
105EXPORT_SYMBOL_GPL(hpte_page_sizes);
106
107struct hash_pte *htab_address;
108unsigned long htab_size_bytes;
109unsigned long htab_hash_mask;
110EXPORT_SYMBOL_GPL(htab_hash_mask);
111int mmu_linear_psize = MMU_PAGE_4K;
112EXPORT_SYMBOL_GPL(mmu_linear_psize);
113int mmu_virtual_psize = MMU_PAGE_4K;
114int mmu_vmalloc_psize = MMU_PAGE_4K;
115#ifdef CONFIG_SPARSEMEM_VMEMMAP
116int mmu_vmemmap_psize = MMU_PAGE_4K;
117#endif
118int mmu_io_psize = MMU_PAGE_4K;
119int mmu_kernel_ssize = MMU_SEGSIZE_256M;
120EXPORT_SYMBOL_GPL(mmu_kernel_ssize);
121int mmu_highuser_ssize = MMU_SEGSIZE_256M;
122u16 mmu_slb_size = 64;
123EXPORT_SYMBOL_GPL(mmu_slb_size);
124#ifdef CONFIG_PPC_64K_PAGES
125int mmu_ci_restrictions;
126#endif
127#ifdef CONFIG_DEBUG_PAGEALLOC
128static u8 *linear_map_hash_slots;
129static unsigned long linear_map_hash_count;
130static DEFINE_SPINLOCK(linear_map_hash_lock);
131#endif
132struct mmu_hash_ops mmu_hash_ops;
133EXPORT_SYMBOL(mmu_hash_ops);
134
135
136
137
138
139
140
141
142
143static struct mmu_psize_def mmu_psize_defaults[] = {
144 [MMU_PAGE_4K] = {
145 .shift = 12,
146 .sllp = 0,
147 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
148 .avpnm = 0,
149 .tlbiel = 0,
150 },
151};
152
153
154
155
156
157
158static struct mmu_psize_def mmu_psize_defaults_gp[] = {
159 [MMU_PAGE_4K] = {
160 .shift = 12,
161 .sllp = 0,
162 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
163 .avpnm = 0,
164 .tlbiel = 1,
165 },
166 [MMU_PAGE_16M] = {
167 .shift = 24,
168 .sllp = SLB_VSID_L,
169 .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
170 [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
171 .avpnm = 0x1UL,
172 .tlbiel = 0,
173 },
174};
175
176
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185
186
187
188
189unsigned long htab_convert_pte_flags(unsigned long pteflags)
190{
191 unsigned long rflags = 0;
192
193
194 if ((pteflags & _PAGE_EXEC) == 0)
195 rflags |= HPTE_R_N;
196
197
198
199
200
201
202
203 if (pteflags & _PAGE_PRIVILEGED) {
204
205
206
207 if (!(pteflags & _PAGE_WRITE)) {
208 if (mmu_has_feature(MMU_FTR_KERNEL_RO))
209 rflags |= (HPTE_R_PP0 | 0x2);
210 else
211 rflags |= 0x3;
212 }
213 } else {
214 if (pteflags & _PAGE_RWX)
215 rflags |= 0x2;
216 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY)))
217 rflags |= 0x1;
218 }
219
220
221
222
223 rflags |= HPTE_R_R;
224
225 if (pteflags & _PAGE_DIRTY)
226 rflags |= HPTE_R_C;
227
228
229
230
231 if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT)
232 rflags |= HPTE_R_I;
233 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)
234 rflags |= (HPTE_R_I | HPTE_R_G);
235 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
236 rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M);
237 else
238
239
240
241 rflags |= HPTE_R_M;
242
243 rflags |= pte_to_hpte_pkey_bits(pteflags);
244 return rflags;
245}
246
247int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
248 unsigned long pstart, unsigned long prot,
249 int psize, int ssize)
250{
251 unsigned long vaddr, paddr;
252 unsigned int step, shift;
253 int ret = 0;
254
255 shift = mmu_psize_defs[psize].shift;
256 step = 1 << shift;
257
258 prot = htab_convert_pte_flags(prot);
259
260 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
261 vstart, vend, pstart, prot, psize, ssize);
262
263
264 vaddr = ALIGN(vstart, step);
265 paddr = ALIGN(pstart, step);
266 vend = ALIGN_DOWN(vend, step);
267
268 for (; vaddr < vend; vaddr += step, paddr += step) {
269 unsigned long hash, hpteg;
270 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
271 unsigned long vpn = hpt_vpn(vaddr, vsid, ssize);
272 unsigned long tprot = prot;
273 bool secondary_hash = false;
274
275
276
277
278 if (!vsid)
279 return -1;
280
281 if (overlaps_kernel_text(vaddr, vaddr + step))
282 tprot &= ~HPTE_R_N;
283
284
285
286
287
288
289
290
291
292
293
294 if ((PHYSICAL_START > MEMORY_START) &&
295 overlaps_interrupt_vector_text(vaddr, vaddr + step))
296 tprot &= ~HPTE_R_N;
297
298 hash = hpt_hash(vpn, shift, ssize);
299 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
300
301 BUG_ON(!mmu_hash_ops.hpte_insert);
302repeat:
303 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
304 HPTE_V_BOLTED, psize, psize,
305 ssize);
306 if (ret == -1) {
307
308
309
310
311 ret = mmu_hash_ops.hpte_remove(hpteg);
312 if (ret != -1)
313 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
314 HPTE_V_BOLTED, psize, psize,
315 ssize);
316 if (ret == -1 && !secondary_hash) {
317 secondary_hash = true;
318 hpteg = ((~hash & htab_hash_mask) * HPTES_PER_GROUP);
319 goto repeat;
320 }
321 }
322
323 if (ret < 0)
324 break;
325
326 cond_resched();
327#ifdef CONFIG_DEBUG_PAGEALLOC
328 if (debug_pagealloc_enabled() &&
329 (paddr >> PAGE_SHIFT) < linear_map_hash_count)
330 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
331#endif
332 }
333 return ret < 0 ? ret : 0;
334}
335
336int htab_remove_mapping(unsigned long vstart, unsigned long vend,
337 int psize, int ssize)
338{
339 unsigned long vaddr;
340 unsigned int step, shift;
341 int rc;
342 int ret = 0;
343
344 shift = mmu_psize_defs[psize].shift;
345 step = 1 << shift;
346
347 if (!mmu_hash_ops.hpte_removebolted)
348 return -ENODEV;
349
350
351 vaddr = ALIGN_DOWN(vstart, step);
352 for (;vaddr < vend; vaddr += step) {
353 rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize);
354 if (rc == -ENOENT) {
355 ret = -ENOENT;
356 continue;
357 }
358 if (rc < 0)
359 return rc;
360 }
361
362 return ret;
363}
364
365static bool disable_1tb_segments = false;
366
367static int __init parse_disable_1tb_segments(char *p)
368{
369 disable_1tb_segments = true;
370 return 0;
371}
372early_param("disable_1tb_segments", parse_disable_1tb_segments);
373
374static int __init htab_dt_scan_seg_sizes(unsigned long node,
375 const char *uname, int depth,
376 void *data)
377{
378 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
379 const __be32 *prop;
380 int size = 0;
381
382
383 if (type == NULL || strcmp(type, "cpu") != 0)
384 return 0;
385
386 prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
387 if (prop == NULL)
388 return 0;
389 for (; size >= 4; size -= 4, ++prop) {
390 if (be32_to_cpu(prop[0]) == 40) {
391 DBG("1T segment support detected\n");
392
393 if (disable_1tb_segments) {
394 DBG("1T segments disabled by command line\n");
395 break;
396 }
397
398 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
399 return 1;
400 }
401 }
402 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
403 return 0;
404}
405
406static int __init get_idx_from_shift(unsigned int shift)
407{
408 int idx = -1;
409
410 switch (shift) {
411 case 0xc:
412 idx = MMU_PAGE_4K;
413 break;
414 case 0x10:
415 idx = MMU_PAGE_64K;
416 break;
417 case 0x14:
418 idx = MMU_PAGE_1M;
419 break;
420 case 0x18:
421 idx = MMU_PAGE_16M;
422 break;
423 case 0x22:
424 idx = MMU_PAGE_16G;
425 break;
426 }
427 return idx;
428}
429
430static int __init htab_dt_scan_page_sizes(unsigned long node,
431 const char *uname, int depth,
432 void *data)
433{
434 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
435 const __be32 *prop;
436 int size = 0;
437
438
439 if (type == NULL || strcmp(type, "cpu") != 0)
440 return 0;
441
442 prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
443 if (!prop)
444 return 0;
445
446 pr_info("Page sizes from device-tree:\n");
447 size /= 4;
448 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
449 while(size > 0) {
450 unsigned int base_shift = be32_to_cpu(prop[0]);
451 unsigned int slbenc = be32_to_cpu(prop[1]);
452 unsigned int lpnum = be32_to_cpu(prop[2]);
453 struct mmu_psize_def *def;
454 int idx, base_idx;
455
456 size -= 3; prop += 3;
457 base_idx = get_idx_from_shift(base_shift);
458 if (base_idx < 0) {
459
460 prop += lpnum * 2; size -= lpnum * 2;
461 continue;
462 }
463 def = &mmu_psize_defs[base_idx];
464 if (base_idx == MMU_PAGE_16M)
465 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
466
467 def->shift = base_shift;
468 if (base_shift <= 23)
469 def->avpnm = 0;
470 else
471 def->avpnm = (1 << (base_shift - 23)) - 1;
472 def->sllp = slbenc;
473
474
475
476
477 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
478 def->tlbiel = 1;
479 else
480 def->tlbiel = 0;
481
482 while (size > 0 && lpnum) {
483 unsigned int shift = be32_to_cpu(prop[0]);
484 int penc = be32_to_cpu(prop[1]);
485
486 prop += 2; size -= 2;
487 lpnum--;
488
489 idx = get_idx_from_shift(shift);
490 if (idx < 0)
491 continue;
492
493 if (penc == -1)
494 pr_err("Invalid penc for base_shift=%d "
495 "shift=%d\n", base_shift, shift);
496
497 def->penc[idx] = penc;
498 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
499 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
500 base_shift, shift, def->sllp,
501 def->avpnm, def->tlbiel, def->penc[idx]);
502 }
503 }
504
505 return 1;
506}
507
508#ifdef CONFIG_HUGETLB_PAGE
509
510
511
512
513static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
514 const char *uname, int depth,
515 void *data) {
516 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
517 const __be64 *addr_prop;
518 const __be32 *page_count_prop;
519 unsigned int expected_pages;
520 long unsigned int phys_addr;
521 long unsigned int block_size;
522
523
524 if (type == NULL || strcmp(type, "memory") != 0)
525 return 0;
526
527
528
529
530
531 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
532 if (page_count_prop == NULL)
533 return 0;
534 expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
535 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
536 if (addr_prop == NULL)
537 return 0;
538 phys_addr = be64_to_cpu(addr_prop[0]);
539 block_size = be64_to_cpu(addr_prop[1]);
540 if (block_size != (16 * GB))
541 return 0;
542 printk(KERN_INFO "Huge page(16GB) memory: "
543 "addr = 0x%lX size = 0x%lX pages = %d\n",
544 phys_addr, block_size, expected_pages);
545 if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) {
546 memblock_reserve(phys_addr, block_size * expected_pages);
547 pseries_add_gpage(phys_addr, block_size, expected_pages);
548 }
549 return 0;
550}
551#endif
552
553static void mmu_psize_set_default_penc(void)
554{
555 int bpsize, apsize;
556 for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
557 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
558 mmu_psize_defs[bpsize].penc[apsize] = -1;
559}
560
561#ifdef CONFIG_PPC_64K_PAGES
562
563static bool might_have_hea(void)
564{
565
566
567
568
569
570#ifdef CONFIG_IBMEBUS
571 return !cpu_has_feature(CPU_FTR_ARCH_207S) &&
572 firmware_has_feature(FW_FEATURE_SPLPAR);
573#else
574 return false;
575#endif
576}
577
578#endif
579
580static void __init htab_scan_page_sizes(void)
581{
582 int rc;
583
584
585 mmu_psize_set_default_penc();
586
587
588 memcpy(mmu_psize_defs, mmu_psize_defaults,
589 sizeof(mmu_psize_defaults));
590
591
592
593
594 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
595 if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) {
596
597
598
599
600 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
601 sizeof(mmu_psize_defaults_gp));
602 }
603
604#ifdef CONFIG_HUGETLB_PAGE
605 if (!hugetlb_disabled && !early_radix_enabled() ) {
606
607 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
608 }
609#endif
610}
611
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619
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621
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631
632
633
634static void init_hpte_page_sizes(void)
635{
636 long int ap, bp;
637 long int shift, penc;
638
639 for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) {
640 if (!mmu_psize_defs[bp].shift)
641 continue;
642 for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) {
643 penc = mmu_psize_defs[bp].penc[ap];
644 if (penc == -1 || !mmu_psize_defs[ap].shift)
645 continue;
646 shift = mmu_psize_defs[ap].shift - LP_SHIFT;
647 if (shift <= 0)
648 continue;
649
650
651
652
653
654 while (penc < (1 << LP_BITS)) {
655 hpte_page_sizes[penc] = (ap << 4) | bp;
656 penc += 1 << shift;
657 }
658 }
659 }
660}
661
662static void __init htab_init_page_sizes(void)
663{
664 bool aligned = true;
665 init_hpte_page_sizes();
666
667 if (!debug_pagealloc_enabled()) {
668
669
670
671
672 if (IS_ENABLED(CONFIG_STRICT_KERNEL_RWX) &&
673 (unsigned long)_stext % 0x1000000) {
674 if (mmu_psize_defs[MMU_PAGE_16M].shift)
675 pr_warn("Kernel not 16M aligned, disabling 16M linear map alignment\n");
676 aligned = false;
677 }
678
679 if (mmu_psize_defs[MMU_PAGE_16M].shift && aligned)
680 mmu_linear_psize = MMU_PAGE_16M;
681 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
682 mmu_linear_psize = MMU_PAGE_1M;
683 }
684
685#ifdef CONFIG_PPC_64K_PAGES
686
687
688
689
690
691
692
693
694
695 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
696 mmu_virtual_psize = MMU_PAGE_64K;
697 mmu_vmalloc_psize = MMU_PAGE_64K;
698 if (mmu_linear_psize == MMU_PAGE_4K)
699 mmu_linear_psize = MMU_PAGE_64K;
700 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
701
702
703
704
705
706 if (!might_have_hea())
707 mmu_io_psize = MMU_PAGE_64K;
708 } else
709 mmu_ci_restrictions = 1;
710 }
711#endif
712
713#ifdef CONFIG_SPARSEMEM_VMEMMAP
714
715
716
717
718 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
719 memblock_phys_mem_size() >= 0x40000000)
720 mmu_vmemmap_psize = MMU_PAGE_16M;
721 else
722 mmu_vmemmap_psize = mmu_virtual_psize;
723#endif
724
725 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
726 "virtual = %d, io = %d"
727#ifdef CONFIG_SPARSEMEM_VMEMMAP
728 ", vmemmap = %d"
729#endif
730 "\n",
731 mmu_psize_defs[mmu_linear_psize].shift,
732 mmu_psize_defs[mmu_virtual_psize].shift,
733 mmu_psize_defs[mmu_io_psize].shift
734#ifdef CONFIG_SPARSEMEM_VMEMMAP
735 ,mmu_psize_defs[mmu_vmemmap_psize].shift
736#endif
737 );
738}
739
740static int __init htab_dt_scan_pftsize(unsigned long node,
741 const char *uname, int depth,
742 void *data)
743{
744 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
745 const __be32 *prop;
746
747
748 if (type == NULL || strcmp(type, "cpu") != 0)
749 return 0;
750
751 prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
752 if (prop != NULL) {
753
754 ppc64_pft_size = be32_to_cpu(prop[1]);
755 return 1;
756 }
757 return 0;
758}
759
760unsigned htab_shift_for_mem_size(unsigned long mem_size)
761{
762 unsigned memshift = __ilog2(mem_size);
763 unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift;
764 unsigned pteg_shift;
765
766
767 if ((1UL << memshift) < mem_size)
768 memshift += 1;
769
770
771 pteg_shift = memshift - (pshift + 1);
772
773
774
775
776
777 return max(pteg_shift + 7, 18U);
778}
779
780static unsigned long __init htab_get_table_size(void)
781{
782
783
784
785
786
787 if (ppc64_pft_size == 0)
788 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
789 if (ppc64_pft_size)
790 return 1UL << ppc64_pft_size;
791
792 return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size());
793}
794
795#ifdef CONFIG_MEMORY_HOTPLUG
796static int resize_hpt_for_hotplug(unsigned long new_mem_size)
797{
798 unsigned target_hpt_shift;
799
800 if (!mmu_hash_ops.resize_hpt)
801 return 0;
802
803 target_hpt_shift = htab_shift_for_mem_size(new_mem_size);
804
805
806
807
808
809
810
811
812
813 if (target_hpt_shift > ppc64_pft_size ||
814 target_hpt_shift < ppc64_pft_size - 1)
815 return mmu_hash_ops.resize_hpt(target_hpt_shift);
816
817 return 0;
818}
819
820int hash__create_section_mapping(unsigned long start, unsigned long end,
821 int nid, pgprot_t prot)
822{
823 int rc;
824
825 if (end >= H_VMALLOC_START) {
826 pr_warn("Outside the supported range\n");
827 return -1;
828 }
829
830 resize_hpt_for_hotplug(memblock_phys_mem_size());
831
832 rc = htab_bolt_mapping(start, end, __pa(start),
833 pgprot_val(prot), mmu_linear_psize,
834 mmu_kernel_ssize);
835
836 if (rc < 0) {
837 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize,
838 mmu_kernel_ssize);
839 BUG_ON(rc2 && (rc2 != -ENOENT));
840 }
841 return rc;
842}
843
844int hash__remove_section_mapping(unsigned long start, unsigned long end)
845{
846 int rc = htab_remove_mapping(start, end, mmu_linear_psize,
847 mmu_kernel_ssize);
848 WARN_ON(rc < 0);
849
850 if (resize_hpt_for_hotplug(memblock_phys_mem_size()) == -ENOSPC)
851 pr_warn("Hash collision while resizing HPT\n");
852
853 return rc;
854}
855#endif
856
857static void __init hash_init_partition_table(phys_addr_t hash_table,
858 unsigned long htab_size)
859{
860 mmu_partition_table_init();
861
862
863
864
865
866 htab_size = __ilog2(htab_size) - 18;
867 mmu_partition_table_set_entry(0, hash_table | htab_size, 0, false);
868 pr_info("Partition table %p\n", partition_tb);
869}
870
871static void __init htab_initialize(void)
872{
873 unsigned long table;
874 unsigned long pteg_count;
875 unsigned long prot;
876 phys_addr_t base = 0, size = 0, end;
877 u64 i;
878
879 DBG(" -> htab_initialize()\n");
880
881 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
882 mmu_kernel_ssize = MMU_SEGSIZE_1T;
883 mmu_highuser_ssize = MMU_SEGSIZE_1T;
884 printk(KERN_INFO "Using 1TB segments\n");
885 }
886
887 if (stress_slb_enabled)
888 static_branch_enable(&stress_slb_key);
889
890
891
892
893
894 htab_size_bytes = htab_get_table_size();
895 pteg_count = htab_size_bytes >> 7;
896
897 htab_hash_mask = pteg_count - 1;
898
899 if (firmware_has_feature(FW_FEATURE_LPAR) ||
900 firmware_has_feature(FW_FEATURE_PS3_LV1)) {
901
902 htab_address = NULL;
903 _SDR1 = 0;
904#ifdef CONFIG_FA_DUMP
905
906
907
908
909
910
911 if (is_fadump_active() && mmu_hash_ops.hpte_clear_all)
912 mmu_hash_ops.hpte_clear_all();
913#endif
914 } else {
915 unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE;
916
917#ifdef CONFIG_PPC_CELL
918
919
920
921
922
923 if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) {
924 limit = 0x80000000;
925 pr_info("Hash table forced below 2G for Axon IOMMU\n");
926 }
927#endif
928
929 table = memblock_phys_alloc_range(htab_size_bytes,
930 htab_size_bytes,
931 0, limit);
932 if (!table)
933 panic("ERROR: Failed to allocate %pa bytes below %pa\n",
934 &htab_size_bytes, &limit);
935
936 DBG("Hash table allocated at %lx, size: %lx\n", table,
937 htab_size_bytes);
938
939 htab_address = __va(table);
940
941
942 _SDR1 = table + __ilog2(htab_size_bytes) - 18;
943
944
945 memset((void *)table, 0, htab_size_bytes);
946
947 if (!cpu_has_feature(CPU_FTR_ARCH_300))
948
949 mtspr(SPRN_SDR1, _SDR1);
950 else
951 hash_init_partition_table(table, htab_size_bytes);
952 }
953
954 prot = pgprot_val(PAGE_KERNEL);
955
956#ifdef CONFIG_DEBUG_PAGEALLOC
957 if (debug_pagealloc_enabled()) {
958 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
959 linear_map_hash_slots = memblock_alloc_try_nid(
960 linear_map_hash_count, 1, MEMBLOCK_LOW_LIMIT,
961 ppc64_rma_size, NUMA_NO_NODE);
962 if (!linear_map_hash_slots)
963 panic("%s: Failed to allocate %lu bytes max_addr=%pa\n",
964 __func__, linear_map_hash_count, &ppc64_rma_size);
965 }
966#endif
967
968
969 for_each_mem_range(i, &base, &end) {
970 size = end - base;
971 base = (unsigned long)__va(base);
972
973 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
974 base, size, prot);
975
976 if ((base + size) >= H_VMALLOC_START) {
977 pr_warn("Outside the supported range\n");
978 continue;
979 }
980
981 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
982 prot, mmu_linear_psize, mmu_kernel_ssize));
983 }
984 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
985
986
987
988
989
990
991
992
993 if (tce_alloc_start) {
994 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
995 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
996
997 if (base + size >= tce_alloc_start)
998 tce_alloc_start = base + size + 1;
999
1000 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
1001 __pa(tce_alloc_start), prot,
1002 mmu_linear_psize, mmu_kernel_ssize));
1003 }
1004
1005
1006 DBG(" <- htab_initialize()\n");
1007}
1008#undef KB
1009#undef MB
1010
1011void __init hash__early_init_devtree(void)
1012{
1013
1014 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
1015
1016
1017 htab_scan_page_sizes();
1018}
1019
1020static struct hash_mm_context init_hash_mm_context;
1021void __init hash__early_init_mmu(void)
1022{
1023#ifndef CONFIG_PPC_64K_PAGES
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035 BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3)));
1036#endif
1037
1038 htab_init_page_sizes();
1039
1040
1041
1042
1043 __pte_frag_nr = H_PTE_FRAG_NR;
1044 __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
1045 __pmd_frag_nr = H_PMD_FRAG_NR;
1046 __pmd_frag_size_shift = H_PMD_FRAG_SIZE_SHIFT;
1047
1048 __pte_index_size = H_PTE_INDEX_SIZE;
1049 __pmd_index_size = H_PMD_INDEX_SIZE;
1050 __pud_index_size = H_PUD_INDEX_SIZE;
1051 __pgd_index_size = H_PGD_INDEX_SIZE;
1052 __pud_cache_index = H_PUD_CACHE_INDEX;
1053 __pte_table_size = H_PTE_TABLE_SIZE;
1054 __pmd_table_size = H_PMD_TABLE_SIZE;
1055 __pud_table_size = H_PUD_TABLE_SIZE;
1056 __pgd_table_size = H_PGD_TABLE_SIZE;
1057
1058
1059
1060
1061 __pmd_val_bits = HASH_PMD_VAL_BITS;
1062 __pud_val_bits = HASH_PUD_VAL_BITS;
1063 __pgd_val_bits = HASH_PGD_VAL_BITS;
1064
1065 __kernel_virt_start = H_KERN_VIRT_START;
1066 __vmalloc_start = H_VMALLOC_START;
1067 __vmalloc_end = H_VMALLOC_END;
1068 __kernel_io_start = H_KERN_IO_START;
1069 __kernel_io_end = H_KERN_IO_END;
1070 vmemmap = (struct page *)H_VMEMMAP_START;
1071 ioremap_bot = IOREMAP_BASE;
1072
1073#ifdef CONFIG_PCI
1074 pci_io_base = ISA_IO_BASE;
1075#endif
1076
1077
1078 if (firmware_has_feature(FW_FEATURE_PS3_LV1))
1079 ps3_early_mm_init();
1080 else if (firmware_has_feature(FW_FEATURE_LPAR))
1081 hpte_init_pseries();
1082 else if (IS_ENABLED(CONFIG_PPC_NATIVE))
1083 hpte_init_native();
1084
1085 if (!mmu_hash_ops.hpte_insert)
1086 panic("hash__early_init_mmu: No MMU hash ops defined!\n");
1087
1088
1089
1090
1091
1092
1093 htab_initialize();
1094
1095 init_mm.context.hash_context = &init_hash_mm_context;
1096 mm_ctx_set_slb_addr_limit(&init_mm.context, SLB_ADDR_LIMIT_DEFAULT);
1097
1098 pr_info("Initializing hash mmu with SLB\n");
1099
1100 slb_initialize();
1101
1102 if (cpu_has_feature(CPU_FTR_ARCH_206)
1103 && cpu_has_feature(CPU_FTR_HVMODE))
1104 tlbiel_all();
1105}
1106
1107#ifdef CONFIG_SMP
1108void hash__early_init_mmu_secondary(void)
1109{
1110
1111 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
1112
1113 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1114 mtspr(SPRN_SDR1, _SDR1);
1115 else
1116 set_ptcr_when_no_uv(__pa(partition_tb) |
1117 (PATB_SIZE_SHIFT - 12));
1118 }
1119
1120 slb_initialize();
1121
1122 if (cpu_has_feature(CPU_FTR_ARCH_206)
1123 && cpu_has_feature(CPU_FTR_HVMODE))
1124 tlbiel_all();
1125
1126#ifdef CONFIG_PPC_MEM_KEYS
1127 if (mmu_has_feature(MMU_FTR_PKEY))
1128 mtspr(SPRN_UAMOR, default_uamor);
1129#endif
1130}
1131#endif
1132
1133
1134
1135
1136unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
1137{
1138 struct page *page;
1139
1140 if (!pfn_valid(pte_pfn(pte)))
1141 return pp;
1142
1143 page = pte_page(pte);
1144
1145
1146 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
1147 if (trap == 0x400) {
1148 flush_dcache_icache_page(page);
1149 set_bit(PG_arch_1, &page->flags);
1150 } else
1151 pp |= HPTE_R_N;
1152 }
1153 return pp;
1154}
1155
1156#ifdef CONFIG_PPC_MM_SLICES
1157static unsigned int get_paca_psize(unsigned long addr)
1158{
1159 unsigned char *psizes;
1160 unsigned long index, mask_index;
1161
1162 if (addr < SLICE_LOW_TOP) {
1163 psizes = get_paca()->mm_ctx_low_slices_psize;
1164 index = GET_LOW_SLICE_INDEX(addr);
1165 } else {
1166 psizes = get_paca()->mm_ctx_high_slices_psize;
1167 index = GET_HIGH_SLICE_INDEX(addr);
1168 }
1169 mask_index = index & 0x1;
1170 return (psizes[index >> 1] >> (mask_index * 4)) & 0xF;
1171}
1172
1173#else
1174unsigned int get_paca_psize(unsigned long addr)
1175{
1176 return get_paca()->mm_ctx_user_psize;
1177}
1178#endif
1179
1180
1181
1182
1183
1184#ifdef CONFIG_PPC_64K_PAGES
1185void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
1186{
1187 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
1188 return;
1189 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
1190 copro_flush_all_slbs(mm);
1191 if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) {
1192
1193 copy_mm_to_paca(mm);
1194 slb_flush_and_restore_bolted();
1195 }
1196}
1197#endif
1198
1199#ifdef CONFIG_PPC_SUBPAGE_PROT
1200
1201
1202
1203
1204
1205
1206
1207static int subpage_protection(struct mm_struct *mm, unsigned long ea)
1208{
1209 struct subpage_prot_table *spt = mm_ctx_subpage_prot(&mm->context);
1210 u32 spp = 0;
1211 u32 **sbpm, *sbpp;
1212
1213 if (!spt)
1214 return 0;
1215
1216 if (ea >= spt->maxaddr)
1217 return 0;
1218 if (ea < 0x100000000UL) {
1219
1220 sbpm = spt->low_prot;
1221 } else {
1222 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
1223 if (!sbpm)
1224 return 0;
1225 }
1226 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
1227 if (!sbpp)
1228 return 0;
1229 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
1230
1231
1232 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
1233
1234
1235
1236
1237
1238
1239
1240 spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0);
1241 return spp;
1242}
1243
1244#else
1245static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
1246{
1247 return 0;
1248}
1249#endif
1250
1251void hash_failure_debug(unsigned long ea, unsigned long access,
1252 unsigned long vsid, unsigned long trap,
1253 int ssize, int psize, int lpsize, unsigned long pte)
1254{
1255 if (!printk_ratelimit())
1256 return;
1257 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
1258 ea, access, current->comm);
1259 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
1260 trap, vsid, ssize, psize, lpsize, pte);
1261}
1262
1263static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
1264 int psize, bool user_region)
1265{
1266 if (user_region) {
1267 if (psize != get_paca_psize(ea)) {
1268 copy_mm_to_paca(mm);
1269 slb_flush_and_restore_bolted();
1270 }
1271 } else if (get_paca()->vmalloc_sllp !=
1272 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1273 get_paca()->vmalloc_sllp =
1274 mmu_psize_defs[mmu_vmalloc_psize].sllp;
1275 slb_vmalloc_update();
1276 }
1277}
1278
1279
1280
1281
1282
1283
1284
1285
1286int hash_page_mm(struct mm_struct *mm, unsigned long ea,
1287 unsigned long access, unsigned long trap,
1288 unsigned long flags)
1289{
1290 bool is_thp;
1291 enum ctx_state prev_state = exception_enter();
1292 pgd_t *pgdir;
1293 unsigned long vsid;
1294 pte_t *ptep;
1295 unsigned hugeshift;
1296 int rc, user_region = 0;
1297 int psize, ssize;
1298
1299 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1300 ea, access, trap);
1301 trace_hash_fault(ea, access, trap);
1302
1303
1304 switch (get_region_id(ea)) {
1305 case USER_REGION_ID:
1306 user_region = 1;
1307 if (! mm) {
1308 DBG_LOW(" user region with no mm !\n");
1309 rc = 1;
1310 goto bail;
1311 }
1312 psize = get_slice_psize(mm, ea);
1313 ssize = user_segment_size(ea);
1314 vsid = get_user_vsid(&mm->context, ea, ssize);
1315 break;
1316 case VMALLOC_REGION_ID:
1317 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1318 psize = mmu_vmalloc_psize;
1319 ssize = mmu_kernel_ssize;
1320 break;
1321
1322 case IO_REGION_ID:
1323 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1324 psize = mmu_io_psize;
1325 ssize = mmu_kernel_ssize;
1326 break;
1327 default:
1328
1329
1330
1331
1332 rc = 1;
1333 goto bail;
1334 }
1335 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1336
1337
1338 if (!vsid) {
1339 DBG_LOW("Bad address!\n");
1340 rc = 1;
1341 goto bail;
1342 }
1343
1344 pgdir = mm->pgd;
1345 if (pgdir == NULL) {
1346 rc = 1;
1347 goto bail;
1348 }
1349
1350
1351 if (user_region && mm_is_thread_local(mm))
1352 flags |= HPTE_LOCAL_UPDATE;
1353
1354#ifndef CONFIG_PPC_64K_PAGES
1355
1356
1357
1358
1359
1360
1361
1362
1363 if (psize != MMU_PAGE_4K)
1364 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1365#endif
1366
1367
1368 ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift);
1369 if (ptep == NULL || !pte_present(*ptep)) {
1370 DBG_LOW(" no PTE !\n");
1371 rc = 1;
1372 goto bail;
1373 }
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383 access |= _PAGE_PRESENT | _PAGE_PTE;
1384
1385
1386
1387
1388
1389 if (!check_pte_access(access, pte_val(*ptep))) {
1390 DBG_LOW(" no access !\n");
1391 rc = 1;
1392 goto bail;
1393 }
1394
1395 if (hugeshift) {
1396 if (is_thp)
1397 rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1398 trap, flags, ssize, psize);
1399#ifdef CONFIG_HUGETLB_PAGE
1400 else
1401 rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1402 flags, ssize, hugeshift, psize);
1403#else
1404 else {
1405
1406
1407
1408
1409 rc = 1;
1410 WARN_ON(1);
1411 }
1412#endif
1413 if (current->mm == mm)
1414 check_paca_psize(ea, mm, psize, user_region);
1415
1416 goto bail;
1417 }
1418
1419#ifndef CONFIG_PPC_64K_PAGES
1420 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1421#else
1422 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1423 pte_val(*(ptep + PTRS_PER_PTE)));
1424#endif
1425
1426#ifdef CONFIG_PPC_64K_PAGES
1427
1428 if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1429 demote_segment_4k(mm, ea);
1430 psize = MMU_PAGE_4K;
1431 }
1432
1433
1434
1435
1436
1437 if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) {
1438 if (user_region) {
1439 demote_segment_4k(mm, ea);
1440 psize = MMU_PAGE_4K;
1441 } else if (ea < VMALLOC_END) {
1442
1443
1444
1445
1446
1447 printk(KERN_ALERT "Reducing vmalloc segment "
1448 "to 4kB pages because of "
1449 "non-cacheable mapping\n");
1450 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1451 copro_flush_all_slbs(mm);
1452 }
1453 }
1454
1455#endif
1456
1457 if (current->mm == mm)
1458 check_paca_psize(ea, mm, psize, user_region);
1459
1460#ifdef CONFIG_PPC_64K_PAGES
1461 if (psize == MMU_PAGE_64K)
1462 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1463 flags, ssize);
1464 else
1465#endif
1466 {
1467 int spp = subpage_protection(mm, ea);
1468 if (access & spp)
1469 rc = -2;
1470 else
1471 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1472 flags, ssize, spp);
1473 }
1474
1475
1476
1477
1478
1479 if (rc == -1)
1480 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1481 psize, pte_val(*ptep));
1482#ifndef CONFIG_PPC_64K_PAGES
1483 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1484#else
1485 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1486 pte_val(*(ptep + PTRS_PER_PTE)));
1487#endif
1488 DBG_LOW(" -> rc=%d\n", rc);
1489
1490bail:
1491 exception_exit(prev_state);
1492 return rc;
1493}
1494EXPORT_SYMBOL_GPL(hash_page_mm);
1495
1496int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
1497 unsigned long dsisr)
1498{
1499 unsigned long flags = 0;
1500 struct mm_struct *mm = current->mm;
1501
1502 if ((get_region_id(ea) == VMALLOC_REGION_ID) ||
1503 (get_region_id(ea) == IO_REGION_ID))
1504 mm = &init_mm;
1505
1506 if (dsisr & DSISR_NOHPTE)
1507 flags |= HPTE_NOHPTE_UPDATE;
1508
1509 return hash_page_mm(mm, ea, access, trap, flags);
1510}
1511EXPORT_SYMBOL_GPL(hash_page);
1512
1513int __hash_page(unsigned long trap, unsigned long ea, unsigned long dsisr,
1514 unsigned long msr)
1515{
1516 unsigned long access = _PAGE_PRESENT | _PAGE_READ;
1517 unsigned long flags = 0;
1518 struct mm_struct *mm = current->mm;
1519 unsigned int region_id = get_region_id(ea);
1520
1521 if ((region_id == VMALLOC_REGION_ID) || (region_id == IO_REGION_ID))
1522 mm = &init_mm;
1523
1524 if (dsisr & DSISR_NOHPTE)
1525 flags |= HPTE_NOHPTE_UPDATE;
1526
1527 if (dsisr & DSISR_ISSTORE)
1528 access |= _PAGE_WRITE;
1529
1530
1531
1532
1533
1534
1535
1536
1537 access |= _PAGE_PRIVILEGED;
1538 if ((msr & MSR_PR) || (region_id == USER_REGION_ID))
1539 access &= ~_PAGE_PRIVILEGED;
1540
1541 if (trap == 0x400)
1542 access |= _PAGE_EXEC;
1543
1544 return hash_page_mm(mm, ea, access, trap, flags);
1545}
1546
1547#ifdef CONFIG_PPC_MM_SLICES
1548static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1549{
1550 int psize = get_slice_psize(mm, ea);
1551
1552
1553 if (unlikely(psize != mm_ctx_user_psize(&mm->context)))
1554 return false;
1555
1556
1557
1558
1559 if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea)))
1560 return false;
1561
1562 return true;
1563}
1564#else
1565static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1566{
1567 return true;
1568}
1569#endif
1570
1571static void hash_preload(struct mm_struct *mm, pte_t *ptep, unsigned long ea,
1572 bool is_exec, unsigned long trap)
1573{
1574 unsigned long vsid;
1575 pgd_t *pgdir;
1576 int rc, ssize, update_flags = 0;
1577 unsigned long access = _PAGE_PRESENT | _PAGE_READ | (is_exec ? _PAGE_EXEC : 0);
1578 unsigned long flags;
1579
1580 BUG_ON(get_region_id(ea) != USER_REGION_ID);
1581
1582 if (!should_hash_preload(mm, ea))
1583 return;
1584
1585 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1586 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1587
1588
1589 pgdir = mm->pgd;
1590 if (pgdir == NULL)
1591 return;
1592
1593
1594 ssize = user_segment_size(ea);
1595 vsid = get_user_vsid(&mm->context, ea, ssize);
1596 if (!vsid)
1597 return;
1598
1599#ifdef CONFIG_PPC_64K_PAGES
1600
1601
1602
1603
1604
1605
1606
1607
1608 if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep))
1609 return;
1610#endif
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632 local_irq_save(flags);
1633
1634
1635 if (mm_is_thread_local(mm))
1636 update_flags |= HPTE_LOCAL_UPDATE;
1637
1638
1639#ifdef CONFIG_PPC_64K_PAGES
1640 if (mm_ctx_user_psize(&mm->context) == MMU_PAGE_64K)
1641 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1642 update_flags, ssize);
1643 else
1644#endif
1645 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,
1646 ssize, subpage_protection(mm, ea));
1647
1648
1649
1650
1651 if (rc == -1)
1652 hash_failure_debug(ea, access, vsid, trap, ssize,
1653 mm_ctx_user_psize(&mm->context),
1654 mm_ctx_user_psize(&mm->context),
1655 pte_val(*ptep));
1656
1657 local_irq_restore(flags);
1658}
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
1669 pte_t *ptep)
1670{
1671
1672
1673
1674
1675 unsigned long trap;
1676 bool is_exec;
1677
1678 if (radix_enabled())
1679 return;
1680
1681
1682 if (!pte_young(*ptep) || address >= TASK_SIZE)
1683 return;
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694 trap = current->thread.regs ? TRAP(current->thread.regs) : 0UL;
1695 switch (trap) {
1696 case 0x300:
1697 is_exec = false;
1698 break;
1699 case 0x400:
1700 is_exec = true;
1701 break;
1702 default:
1703 return;
1704 }
1705
1706 hash_preload(vma->vm_mm, ptep, address, is_exec, trap);
1707}
1708
1709#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1710static inline void tm_flush_hash_page(int local)
1711{
1712
1713
1714
1715
1716
1717
1718
1719
1720 if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs &&
1721 MSR_TM_ACTIVE(current->thread.regs->msr)) {
1722 tm_enable();
1723 tm_abort(TM_CAUSE_TLBI);
1724 }
1725}
1726#else
1727static inline void tm_flush_hash_page(int local)
1728{
1729}
1730#endif
1731
1732
1733
1734
1735
1736unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift,
1737 int ssize, real_pte_t rpte, unsigned int subpg_index)
1738{
1739 unsigned long hash, gslot, hidx;
1740
1741 hash = hpt_hash(vpn, shift, ssize);
1742 hidx = __rpte_to_hidx(rpte, subpg_index);
1743 if (hidx & _PTEIDX_SECONDARY)
1744 hash = ~hash;
1745 gslot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1746 gslot += hidx & _PTEIDX_GROUP_IX;
1747 return gslot;
1748}
1749
1750void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1751 unsigned long flags)
1752{
1753 unsigned long index, shift, gslot;
1754 int local = flags & HPTE_LOCAL_UPDATE;
1755
1756 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1757 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1758 gslot = pte_get_hash_gslot(vpn, shift, ssize, pte, index);
1759 DBG_LOW(" sub %ld: gslot=%lx\n", index, gslot);
1760
1761
1762
1763
1764 mmu_hash_ops.hpte_invalidate(gslot, vpn, psize, psize,
1765 ssize, local);
1766 } pte_iterate_hashed_end();
1767
1768 tm_flush_hash_page(local);
1769}
1770
1771#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1772void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
1773 pmd_t *pmdp, unsigned int psize, int ssize,
1774 unsigned long flags)
1775{
1776 int i, max_hpte_count, valid;
1777 unsigned long s_addr;
1778 unsigned char *hpte_slot_array;
1779 unsigned long hidx, shift, vpn, hash, slot;
1780 int local = flags & HPTE_LOCAL_UPDATE;
1781
1782 s_addr = addr & HPAGE_PMD_MASK;
1783 hpte_slot_array = get_hpte_slot_array(pmdp);
1784
1785
1786
1787
1788
1789 if (!hpte_slot_array)
1790 return;
1791
1792 if (mmu_hash_ops.hugepage_invalidate) {
1793 mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array,
1794 psize, ssize, local);
1795 goto tm_abort;
1796 }
1797
1798
1799
1800 shift = mmu_psize_defs[psize].shift;
1801 max_hpte_count = HPAGE_PMD_SIZE >> shift;
1802 for (i = 0; i < max_hpte_count; i++) {
1803
1804
1805
1806
1807 valid = hpte_valid(hpte_slot_array, i);
1808 if (!valid)
1809 continue;
1810 hidx = hpte_hash_index(hpte_slot_array, i);
1811
1812
1813 addr = s_addr + (i * (1ul << shift));
1814 vpn = hpt_vpn(addr, vsid, ssize);
1815 hash = hpt_hash(vpn, shift, ssize);
1816 if (hidx & _PTEIDX_SECONDARY)
1817 hash = ~hash;
1818
1819 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1820 slot += hidx & _PTEIDX_GROUP_IX;
1821 mmu_hash_ops.hpte_invalidate(slot, vpn, psize,
1822 MMU_PAGE_16M, ssize, local);
1823 }
1824tm_abort:
1825 tm_flush_hash_page(local);
1826}
1827#endif
1828
1829void flush_hash_range(unsigned long number, int local)
1830{
1831 if (mmu_hash_ops.flush_hash_range)
1832 mmu_hash_ops.flush_hash_range(number, local);
1833 else {
1834 int i;
1835 struct ppc64_tlb_batch *batch =
1836 this_cpu_ptr(&ppc64_tlb_batch);
1837
1838 for (i = 0; i < number; i++)
1839 flush_hash_page(batch->vpn[i], batch->pte[i],
1840 batch->psize, batch->ssize, local);
1841 }
1842}
1843
1844
1845
1846
1847
1848void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1849{
1850 enum ctx_state prev_state = exception_enter();
1851
1852 if (user_mode(regs)) {
1853#ifdef CONFIG_PPC_SUBPAGE_PROT
1854 if (rc == -2)
1855 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1856 else
1857#endif
1858 _exception(SIGBUS, regs, BUS_ADRERR, address);
1859 } else
1860 bad_page_fault(regs, address, SIGBUS);
1861
1862 exception_exit(prev_state);
1863}
1864
1865long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1866 unsigned long pa, unsigned long rflags,
1867 unsigned long vflags, int psize, int ssize)
1868{
1869 unsigned long hpte_group;
1870 long slot;
1871
1872repeat:
1873 hpte_group = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1874
1875
1876 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1877 psize, psize, ssize);
1878
1879
1880 if (unlikely(slot == -1)) {
1881 hpte_group = (~hash & htab_hash_mask) * HPTES_PER_GROUP;
1882 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags,
1883 vflags | HPTE_V_SECONDARY,
1884 psize, psize, ssize);
1885 if (slot == -1) {
1886 if (mftb() & 0x1)
1887 hpte_group = (hash & htab_hash_mask) *
1888 HPTES_PER_GROUP;
1889
1890 mmu_hash_ops.hpte_remove(hpte_group);
1891 goto repeat;
1892 }
1893 }
1894
1895 return slot;
1896}
1897
1898#ifdef CONFIG_DEBUG_PAGEALLOC
1899static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1900{
1901 unsigned long hash;
1902 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1903 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1904 unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL));
1905 long ret;
1906
1907 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1908
1909
1910 if (!vsid)
1911 return;
1912
1913 ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1914 HPTE_V_BOLTED,
1915 mmu_linear_psize, mmu_kernel_ssize);
1916
1917 BUG_ON (ret < 0);
1918 spin_lock(&linear_map_hash_lock);
1919 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1920 linear_map_hash_slots[lmi] = ret | 0x80;
1921 spin_unlock(&linear_map_hash_lock);
1922}
1923
1924static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1925{
1926 unsigned long hash, hidx, slot;
1927 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1928 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1929
1930 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1931 spin_lock(&linear_map_hash_lock);
1932 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1933 hidx = linear_map_hash_slots[lmi] & 0x7f;
1934 linear_map_hash_slots[lmi] = 0;
1935 spin_unlock(&linear_map_hash_lock);
1936 if (hidx & _PTEIDX_SECONDARY)
1937 hash = ~hash;
1938 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1939 slot += hidx & _PTEIDX_GROUP_IX;
1940 mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize,
1941 mmu_linear_psize,
1942 mmu_kernel_ssize, 0);
1943}
1944
1945void __kernel_map_pages(struct page *page, int numpages, int enable)
1946{
1947 unsigned long flags, vaddr, lmi;
1948 int i;
1949
1950 local_irq_save(flags);
1951 for (i = 0; i < numpages; i++, page++) {
1952 vaddr = (unsigned long)page_address(page);
1953 lmi = __pa(vaddr) >> PAGE_SHIFT;
1954 if (lmi >= linear_map_hash_count)
1955 continue;
1956 if (enable)
1957 kernel_map_linear_page(vaddr, lmi);
1958 else
1959 kernel_unmap_linear_page(vaddr, lmi);
1960 }
1961 local_irq_restore(flags);
1962}
1963#endif
1964
1965void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
1966 phys_addr_t first_memblock_size)
1967{
1968
1969
1970
1971
1972 BUG_ON(first_memblock_base != 0);
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988 if (!early_cpu_has_feature(CPU_FTR_HVMODE)) {
1989 ppc64_rma_size = first_memblock_size;
1990 if (!early_cpu_has_feature(CPU_FTR_ARCH_300))
1991 ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000);
1992 else
1993 ppc64_rma_size = min_t(u64, ppc64_rma_size,
1994 1UL << SID_SHIFT_1T);
1995
1996
1997 memblock_set_current_limit(ppc64_rma_size);
1998 } else {
1999 ppc64_rma_size = ULONG_MAX;
2000 }
2001}
2002
2003#ifdef CONFIG_DEBUG_FS
2004
2005static int hpt_order_get(void *data, u64 *val)
2006{
2007 *val = ppc64_pft_size;
2008 return 0;
2009}
2010
2011static int hpt_order_set(void *data, u64 val)
2012{
2013 int ret;
2014
2015 if (!mmu_hash_ops.resize_hpt)
2016 return -ENODEV;
2017
2018 cpus_read_lock();
2019 ret = mmu_hash_ops.resize_hpt(val);
2020 cpus_read_unlock();
2021
2022 return ret;
2023}
2024
2025DEFINE_DEBUGFS_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n");
2026
2027static int __init hash64_debugfs(void)
2028{
2029 debugfs_create_file("hpt_order", 0600, powerpc_debugfs_root, NULL,
2030 &fops_hpt_order);
2031 return 0;
2032}
2033machine_device_initcall(pseries, hash64_debugfs);
2034#endif
2035
2036void __init print_system_hash_info(void)
2037{
2038 pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size);
2039
2040 if (htab_hash_mask)
2041 pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask);
2042}
2043