linux/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
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   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * MPC85xx RDB Board Setup
   4 *
   5 * Copyright 2009,2012-2013 Freescale Semiconductor Inc.
   6 */
   7
   8#include <linux/stddef.h>
   9#include <linux/kernel.h>
  10#include <linux/pci.h>
  11#include <linux/kdev_t.h>
  12#include <linux/delay.h>
  13#include <linux/seq_file.h>
  14#include <linux/interrupt.h>
  15#include <linux/of_platform.h>
  16#include <linux/fsl/guts.h>
  17
  18#include <asm/time.h>
  19#include <asm/machdep.h>
  20#include <asm/pci-bridge.h>
  21#include <mm/mmu_decl.h>
  22#include <asm/prom.h>
  23#include <asm/udbg.h>
  24#include <asm/mpic.h>
  25#include <soc/fsl/qe/qe.h>
  26
  27#include <sysdev/fsl_soc.h>
  28#include <sysdev/fsl_pci.h>
  29#include "smp.h"
  30
  31#include "mpc85xx.h"
  32
  33#undef DEBUG
  34
  35#ifdef DEBUG
  36#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
  37#else
  38#define DBG(fmt, args...)
  39#endif
  40
  41
  42void __init mpc85xx_rdb_pic_init(void)
  43{
  44        struct mpic *mpic;
  45
  46        if (of_machine_is_compatible("fsl,MPC85XXRDB-CAMP")) {
  47                mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET |
  48                        MPIC_BIG_ENDIAN |
  49                        MPIC_SINGLE_DEST_CPU,
  50                        0, 256, " OpenPIC  ");
  51        } else {
  52                mpic = mpic_alloc(NULL, 0,
  53                  MPIC_BIG_ENDIAN |
  54                  MPIC_SINGLE_DEST_CPU,
  55                  0, 256, " OpenPIC  ");
  56        }
  57
  58        BUG_ON(mpic == NULL);
  59        mpic_init(mpic);
  60}
  61
  62/*
  63 * Setup the architecture
  64 */
  65static void __init mpc85xx_rdb_setup_arch(void)
  66{
  67        if (ppc_md.progress)
  68                ppc_md.progress("mpc85xx_rdb_setup_arch()", 0);
  69
  70        mpc85xx_smp_init();
  71
  72        fsl_pci_assign_primary();
  73
  74#ifdef CONFIG_QUICC_ENGINE
  75        mpc85xx_qe_par_io_init();
  76#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
  77        if (machine_is(p1025_rdb)) {
  78                struct device_node *np;
  79
  80                struct ccsr_guts __iomem *guts;
  81
  82                np = of_find_node_by_name(NULL, "global-utilities");
  83                if (np) {
  84                        guts = of_iomap(np, 0);
  85                        if (!guts) {
  86
  87                                pr_err("mpc85xx-rdb: could not map global utilities register\n");
  88
  89                        } else {
  90                        /* P1025 has pins muxed for QE and other functions. To
  91                        * enable QE UEC mode, we need to set bit QE0 for UCC1
  92                        * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
  93                        * and QE12 for QE MII management singals in PMUXCR
  94                        * register.
  95                        */
  96                                setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
  97                                                MPC85xx_PMUXCR_QE(3) |
  98                                                MPC85xx_PMUXCR_QE(9) |
  99                                                MPC85xx_PMUXCR_QE(12));
 100                                iounmap(guts);
 101                        }
 102                        of_node_put(np);
 103                }
 104
 105        }
 106#endif
 107#endif  /* CONFIG_QUICC_ENGINE */
 108
 109        printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n");
 110}
 111
 112machine_arch_initcall(p2020_rdb, mpc85xx_common_publish_devices);
 113machine_arch_initcall(p2020_rdb_pc, mpc85xx_common_publish_devices);
 114machine_arch_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices);
 115machine_arch_initcall(p1020_rdb, mpc85xx_common_publish_devices);
 116machine_arch_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
 117machine_arch_initcall(p1020_rdb_pd, mpc85xx_common_publish_devices);
 118machine_arch_initcall(p1020_utm_pc, mpc85xx_common_publish_devices);
 119machine_arch_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices);
 120machine_arch_initcall(p1025_rdb, mpc85xx_common_publish_devices);
 121machine_arch_initcall(p1024_rdb, mpc85xx_common_publish_devices);
 122
 123/*
 124 * Called very early, device-tree isn't unflattened
 125 */
 126static int __init p2020_rdb_probe(void)
 127{
 128        if (of_machine_is_compatible("fsl,P2020RDB"))
 129                return 1;
 130        return 0;
 131}
 132
 133static int __init p1020_rdb_probe(void)
 134{
 135        if (of_machine_is_compatible("fsl,P1020RDB"))
 136                return 1;
 137        return 0;
 138}
 139
 140static int __init p1020_rdb_pc_probe(void)
 141{
 142        return of_machine_is_compatible("fsl,P1020RDB-PC");
 143}
 144
 145static int __init p1020_rdb_pd_probe(void)
 146{
 147        return of_machine_is_compatible("fsl,P1020RDB-PD");
 148}
 149
 150static int __init p1021_rdb_pc_probe(void)
 151{
 152        if (of_machine_is_compatible("fsl,P1021RDB-PC"))
 153                return 1;
 154        return 0;
 155}
 156
 157static int __init p2020_rdb_pc_probe(void)
 158{
 159        if (of_machine_is_compatible("fsl,P2020RDB-PC"))
 160                return 1;
 161        return 0;
 162}
 163
 164static int __init p1025_rdb_probe(void)
 165{
 166        return of_machine_is_compatible("fsl,P1025RDB");
 167}
 168
 169static int __init p1020_mbg_pc_probe(void)
 170{
 171        return of_machine_is_compatible("fsl,P1020MBG-PC");
 172}
 173
 174static int __init p1020_utm_pc_probe(void)
 175{
 176        return of_machine_is_compatible("fsl,P1020UTM-PC");
 177}
 178
 179static int __init p1024_rdb_probe(void)
 180{
 181        return of_machine_is_compatible("fsl,P1024RDB");
 182}
 183
 184define_machine(p2020_rdb) {
 185        .name                   = "P2020 RDB",
 186        .probe                  = p2020_rdb_probe,
 187        .setup_arch             = mpc85xx_rdb_setup_arch,
 188        .init_IRQ               = mpc85xx_rdb_pic_init,
 189#ifdef CONFIG_PCI
 190        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 191        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 192#endif
 193        .get_irq                = mpic_get_irq,
 194        .calibrate_decr         = generic_calibrate_decr,
 195        .progress               = udbg_progress,
 196};
 197
 198define_machine(p1020_rdb) {
 199        .name                   = "P1020 RDB",
 200        .probe                  = p1020_rdb_probe,
 201        .setup_arch             = mpc85xx_rdb_setup_arch,
 202        .init_IRQ               = mpc85xx_rdb_pic_init,
 203#ifdef CONFIG_PCI
 204        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 205        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 206#endif
 207        .get_irq                = mpic_get_irq,
 208        .calibrate_decr         = generic_calibrate_decr,
 209        .progress               = udbg_progress,
 210};
 211
 212define_machine(p1021_rdb_pc) {
 213        .name                   = "P1021 RDB-PC",
 214        .probe                  = p1021_rdb_pc_probe,
 215        .setup_arch             = mpc85xx_rdb_setup_arch,
 216        .init_IRQ               = mpc85xx_rdb_pic_init,
 217#ifdef CONFIG_PCI
 218        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 219        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 220#endif
 221        .get_irq                = mpic_get_irq,
 222        .calibrate_decr         = generic_calibrate_decr,
 223        .progress               = udbg_progress,
 224};
 225
 226define_machine(p2020_rdb_pc) {
 227        .name                   = "P2020RDB-PC",
 228        .probe                  = p2020_rdb_pc_probe,
 229        .setup_arch             = mpc85xx_rdb_setup_arch,
 230        .init_IRQ               = mpc85xx_rdb_pic_init,
 231#ifdef CONFIG_PCI
 232        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 233        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 234#endif
 235        .get_irq                = mpic_get_irq,
 236        .calibrate_decr         = generic_calibrate_decr,
 237        .progress               = udbg_progress,
 238};
 239
 240define_machine(p1025_rdb) {
 241        .name                   = "P1025 RDB",
 242        .probe                  = p1025_rdb_probe,
 243        .setup_arch             = mpc85xx_rdb_setup_arch,
 244        .init_IRQ               = mpc85xx_rdb_pic_init,
 245#ifdef CONFIG_PCI
 246        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 247        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 248#endif
 249        .get_irq                = mpic_get_irq,
 250        .calibrate_decr         = generic_calibrate_decr,
 251        .progress               = udbg_progress,
 252};
 253
 254define_machine(p1020_mbg_pc) {
 255        .name                   = "P1020 MBG-PC",
 256        .probe                  = p1020_mbg_pc_probe,
 257        .setup_arch             = mpc85xx_rdb_setup_arch,
 258        .init_IRQ               = mpc85xx_rdb_pic_init,
 259#ifdef CONFIG_PCI
 260        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 261        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 262#endif
 263        .get_irq                = mpic_get_irq,
 264        .calibrate_decr         = generic_calibrate_decr,
 265        .progress               = udbg_progress,
 266};
 267
 268define_machine(p1020_utm_pc) {
 269        .name                   = "P1020 UTM-PC",
 270        .probe                  = p1020_utm_pc_probe,
 271        .setup_arch             = mpc85xx_rdb_setup_arch,
 272        .init_IRQ               = mpc85xx_rdb_pic_init,
 273#ifdef CONFIG_PCI
 274        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 275        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 276#endif
 277        .get_irq                = mpic_get_irq,
 278        .calibrate_decr         = generic_calibrate_decr,
 279        .progress               = udbg_progress,
 280};
 281
 282define_machine(p1020_rdb_pc) {
 283        .name                   = "P1020RDB-PC",
 284        .probe                  = p1020_rdb_pc_probe,
 285        .setup_arch             = mpc85xx_rdb_setup_arch,
 286        .init_IRQ               = mpc85xx_rdb_pic_init,
 287#ifdef CONFIG_PCI
 288        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 289        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 290#endif
 291        .get_irq                = mpic_get_irq,
 292        .calibrate_decr         = generic_calibrate_decr,
 293        .progress               = udbg_progress,
 294};
 295
 296define_machine(p1020_rdb_pd) {
 297        .name                   = "P1020RDB-PD",
 298        .probe                  = p1020_rdb_pd_probe,
 299        .setup_arch             = mpc85xx_rdb_setup_arch,
 300        .init_IRQ               = mpc85xx_rdb_pic_init,
 301#ifdef CONFIG_PCI
 302        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 303        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 304#endif
 305        .get_irq                = mpic_get_irq,
 306        .calibrate_decr         = generic_calibrate_decr,
 307        .progress               = udbg_progress,
 308};
 309
 310define_machine(p1024_rdb) {
 311        .name                   = "P1024 RDB",
 312        .probe                  = p1024_rdb_probe,
 313        .setup_arch             = mpc85xx_rdb_setup_arch,
 314        .init_IRQ               = mpc85xx_rdb_pic_init,
 315#ifdef CONFIG_PCI
 316        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 317        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 318#endif
 319        .get_irq                = mpic_get_irq,
 320        .calibrate_decr         = generic_calibrate_decr,
 321        .progress               = udbg_progress,
 322};
 323