LXR linux/drivers/clk/imx/clk-imx8qxp-lpcg.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2018 NXP
   4 *      Dong Aisheng <aisheng.dong@nxp.com>
   5 */
   6
   7#include <linux/clk-provider.h>
   8#include <linux/err.h>
   9#include <linux/io.h>
  10#include <linux/module.h>
  11#include <linux/of.h>
  12#include <linux/of_device.h>
  13#include <linux/platform_device.h>
  14#include <linux/slab.h>
  15
  16#include "clk-scu.h"
  17#include "clk-imx8qxp-lpcg.h"
  18
  19#include <dt-bindings/clock/imx8-clock.h>
  20
  21/*
  22 * struct imx8qxp_lpcg_data - Description of one LPCG clock
  23 * @id: clock ID
  24 * @name: clock name
  25 * @parent: parent clock name
  26 * @flags: common clock flags
  27 * @offset: offset of this LPCG clock
  28 * @bit_idx: bit index of this LPCG clock
  29 * @hw_gate: whether supports HW autogate
  30 *
  31 * This structure describes one LPCG clock
  32 */
  33struct imx8qxp_lpcg_data {
  34        int id;
  35        char *name;
  36        char *parent;
  37        unsigned long flags;
  38        u32 offset;
  39        u8 bit_idx;
  40        bool hw_gate;
  41};
  42
  43/*
  44 * struct imx8qxp_ss_lpcg - Description of one subsystem LPCG clocks
  45 * @lpcg: LPCG clocks array of one subsystem
  46 * @num_lpcg: the number of LPCG clocks
  47 * @num_max: the maximum number of LPCG clocks
  48 *
  49 * This structure describes each subsystem LPCG clocks information
  50 * which then will be used to create respective LPCGs clocks
  51 */
  52struct imx8qxp_ss_lpcg {
  53        const struct imx8qxp_lpcg_data *lpcg;
  54        u8 num_lpcg;
  55        u8 num_max;
  56};
  57
  58static const struct imx8qxp_lpcg_data imx8qxp_lpcg_adma[] = {
  59        { IMX_ADMA_LPCG_UART0_IPG_CLK, "uart0_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_0_LPCG, 16, 0, },
  60        { IMX_ADMA_LPCG_UART0_BAUD_CLK, "uart0_lpcg_baud_clk", "uart0_clk", 0, ADMA_LPUART_0_LPCG, 0, 0, },
  61        { IMX_ADMA_LPCG_UART1_IPG_CLK, "uart1_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_1_LPCG, 16, 0, },
  62        { IMX_ADMA_LPCG_UART1_BAUD_CLK, "uart1_lpcg_baud_clk", "uart1_clk", 0, ADMA_LPUART_1_LPCG, 0, 0, },
  63        { IMX_ADMA_LPCG_UART2_IPG_CLK, "uart2_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_2_LPCG, 16, 0, },
  64        { IMX_ADMA_LPCG_UART2_BAUD_CLK, "uart2_lpcg_baud_clk", "uart2_clk", 0, ADMA_LPUART_2_LPCG, 0, 0, },
  65        { IMX_ADMA_LPCG_UART3_IPG_CLK, "uart3_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_3_LPCG, 16, 0, },
  66        { IMX_ADMA_LPCG_UART3_BAUD_CLK, "uart3_lpcg_baud_clk", "uart3_clk", 0, ADMA_LPUART_3_LPCG, 0, 0, },
  67        { IMX_ADMA_LPCG_I2C0_IPG_CLK, "i2c0_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_0_LPCG, 16, 0, },
  68        { IMX_ADMA_LPCG_I2C0_CLK, "i2c0_lpcg_clk", "i2c0_clk", 0, ADMA_LPI2C_0_LPCG, 0, 0, },
  69        { IMX_ADMA_LPCG_I2C1_IPG_CLK, "i2c1_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_1_LPCG, 16, 0, },
  70        { IMX_ADMA_LPCG_I2C1_CLK, "i2c1_lpcg_clk", "i2c1_clk", 0, ADMA_LPI2C_1_LPCG, 0, 0, },
  71        { IMX_ADMA_LPCG_I2C2_IPG_CLK, "i2c2_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_2_LPCG, 16, 0, },
  72        { IMX_ADMA_LPCG_I2C2_CLK, "i2c2_lpcg_clk", "i2c2_clk", 0, ADMA_LPI2C_2_LPCG, 0, 0, },
  73        { IMX_ADMA_LPCG_I2C3_IPG_CLK, "i2c3_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_3_LPCG, 16, 0, },
  74        { IMX_ADMA_LPCG_I2C3_CLK, "i2c3_lpcg_clk", "i2c3_clk", 0, ADMA_LPI2C_3_LPCG, 0, 0, },
  75
  76        { IMX_ADMA_LPCG_DSP_CORE_CLK, "dsp_lpcg_core_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 28, 0, },
  77        { IMX_ADMA_LPCG_DSP_IPG_CLK, "dsp_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 20, 0, },
  78        { IMX_ADMA_LPCG_DSP_ADB_CLK, "dsp_lpcg_adb_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 16, 0, },
  79        { IMX_ADMA_LPCG_OCRAM_IPG_CLK, "ocram_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_OCRAM_LPCG, 16, 0, },
  80};
  81
  82static const struct imx8qxp_ss_lpcg imx8qxp_ss_adma = {
  83        .lpcg = imx8qxp_lpcg_adma,
  84        .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_adma),
  85        .num_max = IMX_ADMA_LPCG_CLK_END,
  86};
  87
  88static const struct imx8qxp_lpcg_data imx8qxp_lpcg_conn[] = {
  89        { IMX_CONN_LPCG_SDHC0_PER_CLK, "sdhc0_lpcg_per_clk", "sdhc0_clk", 0, CONN_USDHC_0_LPCG, 0, 0, },
  90        { IMX_CONN_LPCG_SDHC0_IPG_CLK, "sdhc0_lpcg_ipg_clk", "conn_ipg_clk_root", 0, CONN_USDHC_0_LPCG, 16, 0, },
  91        { IMX_CONN_LPCG_SDHC0_HCLK, "sdhc0_lpcg_ahb_clk", "conn_axi_clk_root", 0, CONN_USDHC_0_LPCG, 20, 0, },
  92        { IMX_CONN_LPCG_SDHC1_PER_CLK, "sdhc1_lpcg_per_clk", "sdhc1_clk", 0, CONN_USDHC_1_LPCG, 0, 0, },
  93        { IMX_CONN_LPCG_SDHC1_IPG_CLK, "sdhc1_lpcg_ipg_clk", "conn_ipg_clk_root", 0, CONN_USDHC_1_LPCG, 16, 0, },
  94        { IMX_CONN_LPCG_SDHC1_HCLK, "sdhc1_lpcg_ahb_clk", "conn_axi_clk_root", 0, CONN_USDHC_1_LPCG, 20, 0, },
  95        { IMX_CONN_LPCG_SDHC2_PER_CLK, "sdhc2_lpcg_per_clk", "sdhc2_clk", 0, CONN_USDHC_2_LPCG, 0, 0, },
  96        { IMX_CONN_LPCG_SDHC2_IPG_CLK, "sdhc2_lpcg_ipg_clk", "conn_ipg_clk_root", 0, CONN_USDHC_2_LPCG, 16, 0, },
  97        { IMX_CONN_LPCG_SDHC2_HCLK, "sdhc2_lpcg_ahb_clk", "conn_axi_clk_root", 0, CONN_USDHC_2_LPCG, 20, 0, },
  98        { IMX_CONN_LPCG_ENET0_ROOT_CLK, "enet0_ipg_root_clk", "enet0_clk", 0, CONN_ENET_0_LPCG, 0, 0, },
  99        { IMX_CONN_LPCG_ENET0_TX_CLK, "enet0_tx_clk", "enet0_clk", 0, CONN_ENET_0_LPCG, 4, 0, },
 100        { IMX_CONN_LPCG_ENET0_AHB_CLK, "enet0_ahb_clk", "conn_axi_clk_root", 0, CONN_ENET_0_LPCG, 8, 0, },
 101        { IMX_CONN_LPCG_ENET0_IPG_S_CLK, "enet0_ipg_s_clk", "conn_ipg_clk_root", 0, CONN_ENET_0_LPCG, 20, 0, },
 102        { IMX_CONN_LPCG_ENET0_IPG_CLK, "enet0_ipg_clk", "enet0_ipg_s_clk", 0, CONN_ENET_0_LPCG, 16, 0, },
 103        { IMX_CONN_LPCG_ENET1_ROOT_CLK, "enet1_ipg_root_clk", "enet1_clk", 0, CONN_ENET_1_LPCG, 0, 0, },
 104        { IMX_CONN_LPCG_ENET1_TX_CLK, "enet1_tx_clk", "enet1_clk", 0, CONN_ENET_1_LPCG, 4, 0, },
 105        { IMX_CONN_LPCG_ENET1_AHB_CLK, "enet1_ahb_clk", "conn_axi_clk_root", 0, CONN_ENET_1_LPCG, 8, 0, },
 106        { IMX_CONN_LPCG_ENET1_IPG_S_CLK, "enet1_ipg_s_clk", "conn_ipg_clk_root", 0, CONN_ENET_1_LPCG, 20, 0, },
 107        { IMX_CONN_LPCG_ENET1_IPG_CLK, "enet1_ipg_clk", "enet0_ipg_s_clk", 0, CONN_ENET_1_LPCG, 16, 0, },
 108};
 109
 110static const struct imx8qxp_ss_lpcg imx8qxp_ss_conn = {
 111        .lpcg = imx8qxp_lpcg_conn,
 112        .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_conn),
 113        .num_max = IMX_CONN_LPCG_CLK_END,
 114};
 115
 116static const struct imx8qxp_lpcg_data imx8qxp_lpcg_lsio[] = {
 117        { IMX_LSIO_LPCG_PWM0_IPG_CLK, "pwm0_lpcg_ipg_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 0, 0, },
 118        { IMX_LSIO_LPCG_PWM0_IPG_HF_CLK, "pwm0_lpcg_ipg_hf_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 4, 0, },
 119        { IMX_LSIO_LPCG_PWM0_IPG_S_CLK, "pwm0_lpcg_ipg_s_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 16, 0, },
 120        { IMX_LSIO_LPCG_PWM0_IPG_SLV_CLK, "pwm0_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_0_LPCG, 20, 0, },
 121        { IMX_LSIO_LPCG_PWM0_IPG_MSTR_CLK, "pwm0_lpcg_ipg_mstr_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 24, 0, },
 122        { IMX_LSIO_LPCG_PWM1_IPG_CLK, "pwm1_lpcg_ipg_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 0, 0, },
 123        { IMX_LSIO_LPCG_PWM1_IPG_HF_CLK, "pwm1_lpcg_ipg_hf_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 4, 0, },
 124        { IMX_LSIO_LPCG_PWM1_IPG_S_CLK, "pwm1_lpcg_ipg_s_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 16, 0, },
 125        { IMX_LSIO_LPCG_PWM1_IPG_SLV_CLK, "pwm1_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_1_LPCG, 20, 0, },
 126        { IMX_LSIO_LPCG_PWM1_IPG_MSTR_CLK, "pwm1_lpcg_ipg_mstr_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 24, 0, },
 127        { IMX_LSIO_LPCG_PWM2_IPG_CLK, "pwm2_lpcg_ipg_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 0, 0, },
 128        { IMX_LSIO_LPCG_PWM2_IPG_HF_CLK, "pwm2_lpcg_ipg_hf_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 4, 0, },
 129        { IMX_LSIO_LPCG_PWM2_IPG_S_CLK, "pwm2_lpcg_ipg_s_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 16, 0, },
 130        { IMX_LSIO_LPCG_PWM2_IPG_SLV_CLK, "pwm2_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_2_LPCG, 20, 0, },
 131        { IMX_LSIO_LPCG_PWM2_IPG_MSTR_CLK, "pwm2_lpcg_ipg_mstr_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 24, 0, },
 132        { IMX_LSIO_LPCG_PWM3_IPG_CLK, "pwm3_lpcg_ipg_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 0, 0, },
 133        { IMX_LSIO_LPCG_PWM3_IPG_HF_CLK, "pwm3_lpcg_ipg_hf_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 4, 0, },
 134        { IMX_LSIO_LPCG_PWM3_IPG_S_CLK, "pwm3_lpcg_ipg_s_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 16, 0, },
 135        { IMX_LSIO_LPCG_PWM3_IPG_SLV_CLK, "pwm3_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_3_LPCG, 20, 0, },
 136        { IMX_LSIO_LPCG_PWM3_IPG_MSTR_CLK, "pwm3_lpcg_ipg_mstr_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 24, 0, },
 137        { IMX_LSIO_LPCG_PWM4_IPG_CLK, "pwm4_lpcg_ipg_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 0, 0, },
 138        { IMX_LSIO_LPCG_PWM4_IPG_HF_CLK, "pwm4_lpcg_ipg_hf_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 4, 0, },
 139        { IMX_LSIO_LPCG_PWM4_IPG_S_CLK, "pwm4_lpcg_ipg_s_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 16, 0, },
 140        { IMX_LSIO_LPCG_PWM4_IPG_SLV_CLK, "pwm4_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_4_LPCG, 20, 0, },
 141        { IMX_LSIO_LPCG_PWM4_IPG_MSTR_CLK, "pwm4_lpcg_ipg_mstr_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 24, 0, },
 142        { IMX_LSIO_LPCG_PWM5_IPG_CLK, "pwm5_lpcg_ipg_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 0, 0, },
 143        { IMX_LSIO_LPCG_PWM5_IPG_HF_CLK, "pwm5_lpcg_ipg_hf_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 4, 0, },
 144        { IMX_LSIO_LPCG_PWM5_IPG_S_CLK, "pwm5_lpcg_ipg_s_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 16, 0, },
 145        { IMX_LSIO_LPCG_PWM5_IPG_SLV_CLK, "pwm5_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_5_LPCG, 20, 0, },
 146        { IMX_LSIO_LPCG_PWM5_IPG_MSTR_CLK, "pwm5_lpcg_ipg_mstr_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 24, 0, },
 147        { IMX_LSIO_LPCG_PWM6_IPG_CLK, "pwm6_lpcg_ipg_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 0, 0, },
 148        { IMX_LSIO_LPCG_PWM6_IPG_HF_CLK, "pwm6_lpcg_ipg_hf_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 4, 0, },
 149        { IMX_LSIO_LPCG_PWM6_IPG_S_CLK, "pwm6_lpcg_ipg_s_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 16, 0, },
 150        { IMX_LSIO_LPCG_PWM6_IPG_SLV_CLK, "pwm6_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_6_LPCG, 20, 0, },
 151        { IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK, "pwm6_lpcg_ipg_mstr_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 24, 0, },
 152};
 153
 154static const struct imx8qxp_ss_lpcg imx8qxp_ss_lsio = {
 155        .lpcg = imx8qxp_lpcg_lsio,
 156        .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_lsio),
 157        .num_max = IMX_LSIO_LPCG_CLK_END,
 158};
 159
 160static int imx8qxp_lpcg_clk_probe(struct platform_device *pdev)
 161{
 162        struct device *dev = &pdev->dev;
 163        struct device_node *np = dev->of_node;
 164        struct clk_hw_onecell_data *clk_data;
 165        const struct imx8qxp_ss_lpcg *ss_lpcg;
 166        const struct imx8qxp_lpcg_data *lpcg;
 167        struct resource *res;
 168        struct clk_hw **clks;
 169        void __iomem *base;
 170        int i;
 171
 172        ss_lpcg = of_device_get_match_data(dev);
 173        if (!ss_lpcg)
 174                return -ENODEV;
 175
 176        /*
 177         * Please don't replace this with devm_platform_ioremap_resource.
 178         *
 179         * devm_platform_ioremap_resource calls devm_ioremap_resource which
 180         * differs from devm_ioremap by also calling devm_request_mem_region
 181         * and preventing other mappings in the same area.
 182         *
 183         * On imx8 the LPCG nodes map entire subsystems and overlap
 184         * peripherals, this means that using devm_platform_ioremap_resource
 185         * will cause many devices to fail to probe including serial ports.
 186         */
 187        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 188        if (!res)
 189                return -EINVAL;
 190        base = devm_ioremap(dev, res->start, resource_size(res));
 191        if (!base)
 192                return -ENOMEM;
 193
 194        clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws,
 195                                ss_lpcg->num_max), GFP_KERNEL);
 196        if (!clk_data)
 197                return -ENOMEM;
 198
 199        clk_data->num = ss_lpcg->num_max;
 200        clks = clk_data->hws;
 201
 202        for (i = 0; i < ss_lpcg->num_lpcg; i++) {
 203                lpcg = ss_lpcg->lpcg + i;
 204                clks[lpcg->id] = imx_clk_lpcg_scu(lpcg->name, lpcg->parent,
 205                                                  lpcg->flags, base + lpcg->offset,
 206                                                  lpcg->bit_idx, lpcg->hw_gate);
 207        }
 208
 209        for (i = 0; i < clk_data->num; i++) {
 210                if (IS_ERR(clks[i]))
 211                        pr_warn("i.MX clk %u: register failed with %ld\n",
 212                                i, PTR_ERR(clks[i]));
 213        }
 214
 215        return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
 216}
 217
 218static const struct of_device_id imx8qxp_lpcg_match[] = {
 219        { .compatible = "fsl,imx8qxp-lpcg-adma", &imx8qxp_ss_adma, },
 220        { .compatible = "fsl,imx8qxp-lpcg-conn", &imx8qxp_ss_conn, },
 221        { .compatible = "fsl,imx8qxp-lpcg-lsio", &imx8qxp_ss_lsio, },
 222        { /* sentinel */ }
 223};
 224
 225static struct platform_driver imx8qxp_lpcg_clk_driver = {
 226        .driver = {
 227                .name = "imx8qxp-lpcg-clk",
 228                .of_match_table = imx8qxp_lpcg_match,
 229                .suppress_bind_attrs = true,
 230        },
 231        .probe = imx8qxp_lpcg_clk_probe,
 232};
 233
 234builtin_platform_driver(imx8qxp_lpcg_clk_driver);
 235
 236MODULE_AUTHOR("Aisheng Dong <aisheng.dong@nxp.com>");
 237MODULE_DESCRIPTION("NXP i.MX8QXP LPCG clock driver");
 238MODULE_LICENSE("GPL v2");
 239