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10#include <linux/debugfs.h>
11#include <linux/kernel.h>
12#include <linux/io.h>
13#include <linux/init.h>
14#include <linux/slab.h>
15#include <linux/module.h>
16#include <linux/string.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/dma-mapping.h>
20#include <linux/dmaengine.h>
21#include <linux/amba/bus.h>
22#include <linux/scatterlist.h>
23#include <linux/of.h>
24#include <linux/of_dma.h>
25#include <linux/err.h>
26#include <linux/pm_runtime.h>
27#include <linux/bug.h>
28#include <linux/reset.h>
29
30#include "dmaengine.h"
31#define PL330_MAX_CHAN 8
32#define PL330_MAX_IRQS 32
33#define PL330_MAX_PERI 32
34#define PL330_MAX_BURST 16
35
36#define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
37#define PL330_QUIRK_PERIPH_BURST BIT(1)
38
39enum pl330_cachectrl {
40 CCTRL0,
41 CCTRL1,
42 CCTRL2,
43 CCTRL3,
44 INVALID1,
45 INVALID2,
46 CCTRL6,
47 CCTRL7,
48};
49
50enum pl330_byteswap {
51 SWAP_NO,
52 SWAP_2,
53 SWAP_4,
54 SWAP_8,
55 SWAP_16,
56};
57
58
59#define DS 0x0
60#define DS_ST_STOP 0x0
61#define DS_ST_EXEC 0x1
62#define DS_ST_CMISS 0x2
63#define DS_ST_UPDTPC 0x3
64#define DS_ST_WFE 0x4
65#define DS_ST_ATBRR 0x5
66#define DS_ST_QBUSY 0x6
67#define DS_ST_WFP 0x7
68#define DS_ST_KILL 0x8
69#define DS_ST_CMPLT 0x9
70#define DS_ST_FLTCMP 0xe
71#define DS_ST_FAULT 0xf
72
73#define DPC 0x4
74#define INTEN 0x20
75#define ES 0x24
76#define INTSTATUS 0x28
77#define INTCLR 0x2c
78#define FSM 0x30
79#define FSC 0x34
80#define FTM 0x38
81
82#define _FTC 0x40
83#define FTC(n) (_FTC + (n)*0x4)
84
85#define _CS 0x100
86#define CS(n) (_CS + (n)*0x8)
87#define CS_CNS (1 << 21)
88
89#define _CPC 0x104
90#define CPC(n) (_CPC + (n)*0x8)
91
92#define _SA 0x400
93#define SA(n) (_SA + (n)*0x20)
94
95#define _DA 0x404
96#define DA(n) (_DA + (n)*0x20)
97
98#define _CC 0x408
99#define CC(n) (_CC + (n)*0x20)
100
101#define CC_SRCINC (1 << 0)
102#define CC_DSTINC (1 << 14)
103#define CC_SRCPRI (1 << 8)
104#define CC_DSTPRI (1 << 22)
105#define CC_SRCNS (1 << 9)
106#define CC_DSTNS (1 << 23)
107#define CC_SRCIA (1 << 10)
108#define CC_DSTIA (1 << 24)
109#define CC_SRCBRSTLEN_SHFT 4
110#define CC_DSTBRSTLEN_SHFT 18
111#define CC_SRCBRSTSIZE_SHFT 1
112#define CC_DSTBRSTSIZE_SHFT 15
113#define CC_SRCCCTRL_SHFT 11
114#define CC_SRCCCTRL_MASK 0x7
115#define CC_DSTCCTRL_SHFT 25
116#define CC_DRCCCTRL_MASK 0x7
117#define CC_SWAP_SHFT 28
118
119#define _LC0 0x40c
120#define LC0(n) (_LC0 + (n)*0x20)
121
122#define _LC1 0x410
123#define LC1(n) (_LC1 + (n)*0x20)
124
125#define DBGSTATUS 0xd00
126#define DBG_BUSY (1 << 0)
127
128#define DBGCMD 0xd04
129#define DBGINST0 0xd08
130#define DBGINST1 0xd0c
131
132#define CR0 0xe00
133#define CR1 0xe04
134#define CR2 0xe08
135#define CR3 0xe0c
136#define CR4 0xe10
137#define CRD 0xe14
138
139#define PERIPH_ID 0xfe0
140#define PERIPH_REV_SHIFT 20
141#define PERIPH_REV_MASK 0xf
142#define PERIPH_REV_R0P0 0
143#define PERIPH_REV_R1P0 1
144#define PERIPH_REV_R1P1 2
145
146#define CR0_PERIPH_REQ_SET (1 << 0)
147#define CR0_BOOT_EN_SET (1 << 1)
148#define CR0_BOOT_MAN_NS (1 << 2)
149#define CR0_NUM_CHANS_SHIFT 4
150#define CR0_NUM_CHANS_MASK 0x7
151#define CR0_NUM_PERIPH_SHIFT 12
152#define CR0_NUM_PERIPH_MASK 0x1f
153#define CR0_NUM_EVENTS_SHIFT 17
154#define CR0_NUM_EVENTS_MASK 0x1f
155
156#define CR1_ICACHE_LEN_SHIFT 0
157#define CR1_ICACHE_LEN_MASK 0x7
158#define CR1_NUM_ICACHELINES_SHIFT 4
159#define CR1_NUM_ICACHELINES_MASK 0xf
160
161#define CRD_DATA_WIDTH_SHIFT 0
162#define CRD_DATA_WIDTH_MASK 0x7
163#define CRD_WR_CAP_SHIFT 4
164#define CRD_WR_CAP_MASK 0x7
165#define CRD_WR_Q_DEP_SHIFT 8
166#define CRD_WR_Q_DEP_MASK 0xf
167#define CRD_RD_CAP_SHIFT 12
168#define CRD_RD_CAP_MASK 0x7
169#define CRD_RD_Q_DEP_SHIFT 16
170#define CRD_RD_Q_DEP_MASK 0xf
171#define CRD_DATA_BUFF_SHIFT 20
172#define CRD_DATA_BUFF_MASK 0x3ff
173
174#define PART 0x330
175#define DESIGNER 0x41
176#define REVISION 0x0
177#define INTEG_CFG 0x0
178#define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
179
180#define PL330_STATE_STOPPED (1 << 0)
181#define PL330_STATE_EXECUTING (1 << 1)
182#define PL330_STATE_WFE (1 << 2)
183#define PL330_STATE_FAULTING (1 << 3)
184#define PL330_STATE_COMPLETING (1 << 4)
185#define PL330_STATE_WFP (1 << 5)
186#define PL330_STATE_KILLING (1 << 6)
187#define PL330_STATE_FAULT_COMPLETING (1 << 7)
188#define PL330_STATE_CACHEMISS (1 << 8)
189#define PL330_STATE_UPDTPC (1 << 9)
190#define PL330_STATE_ATBARRIER (1 << 10)
191#define PL330_STATE_QUEUEBUSY (1 << 11)
192#define PL330_STATE_INVALID (1 << 15)
193
194#define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
195 | PL330_STATE_WFE | PL330_STATE_FAULTING)
196
197#define CMD_DMAADDH 0x54
198#define CMD_DMAEND 0x00
199#define CMD_DMAFLUSHP 0x35
200#define CMD_DMAGO 0xa0
201#define CMD_DMALD 0x04
202#define CMD_DMALDP 0x25
203#define CMD_DMALP 0x20
204#define CMD_DMALPEND 0x28
205#define CMD_DMAKILL 0x01
206#define CMD_DMAMOV 0xbc
207#define CMD_DMANOP 0x18
208#define CMD_DMARMB 0x12
209#define CMD_DMASEV 0x34
210#define CMD_DMAST 0x08
211#define CMD_DMASTP 0x29
212#define CMD_DMASTZ 0x0c
213#define CMD_DMAWFE 0x36
214#define CMD_DMAWFP 0x30
215#define CMD_DMAWMB 0x13
216
217#define SZ_DMAADDH 3
218#define SZ_DMAEND 1
219#define SZ_DMAFLUSHP 2
220#define SZ_DMALD 1
221#define SZ_DMALDP 2
222#define SZ_DMALP 2
223#define SZ_DMALPEND 2
224#define SZ_DMAKILL 1
225#define SZ_DMAMOV 6
226#define SZ_DMANOP 1
227#define SZ_DMARMB 1
228#define SZ_DMASEV 2
229#define SZ_DMAST 1
230#define SZ_DMASTP 2
231#define SZ_DMASTZ 1
232#define SZ_DMAWFE 2
233#define SZ_DMAWFP 2
234#define SZ_DMAWMB 1
235#define SZ_DMAGO 6
236
237#define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
238#define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
239
240#define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
241#define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
242
243
244
245
246
247
248
249#define MCODE_BUFF_PER_REQ 256
250
251
252#define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
253
254#ifdef PL330_DEBUG_MCGEN
255static unsigned cmd_line;
256#define PL330_DBGCMD_DUMP(off, x...) do { \
257 printk("%x:", cmd_line); \
258 printk(KERN_CONT x); \
259 cmd_line += off; \
260 } while (0)
261#define PL330_DBGMC_START(addr) (cmd_line = addr)
262#else
263#define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
264#define PL330_DBGMC_START(addr) do {} while (0)
265#endif
266
267
268
269#define NR_DEFAULT_DESC 16
270
271
272#define PL330_AUTOSUSPEND_DELAY 20
273
274
275struct pl330_config {
276 u32 periph_id;
277#define DMAC_MODE_NS (1 << 0)
278 unsigned int mode;
279 unsigned int data_bus_width:10;
280 unsigned int data_buf_dep:11;
281 unsigned int num_chan:4;
282 unsigned int num_peri:6;
283 u32 peri_ns;
284 unsigned int num_events:6;
285 u32 irq_ns;
286};
287
288
289
290
291
292
293
294
295
296struct pl330_reqcfg {
297
298 unsigned dst_inc:1;
299 unsigned src_inc:1;
300
301
302
303
304
305 bool nonsecure;
306 bool privileged;
307 bool insnaccess;
308 unsigned brst_len:5;
309 unsigned brst_size:3;
310
311 enum pl330_cachectrl dcctl;
312 enum pl330_cachectrl scctl;
313 enum pl330_byteswap swap;
314 struct pl330_config *pcfg;
315};
316
317
318
319
320
321struct pl330_xfer {
322 u32 src_addr;
323 u32 dst_addr;
324
325 u32 bytes;
326};
327
328
329enum pl330_op_err {
330
331 PL330_ERR_NONE,
332
333 PL330_ERR_ABORT,
334
335 PL330_ERR_FAIL,
336};
337
338enum dmamov_dst {
339 SAR = 0,
340 CCR,
341 DAR,
342};
343
344enum pl330_dst {
345 SRC = 0,
346 DST,
347};
348
349enum pl330_cond {
350 SINGLE,
351 BURST,
352 ALWAYS,
353};
354
355struct dma_pl330_desc;
356
357struct _pl330_req {
358 u32 mc_bus;
359 void *mc_cpu;
360 struct dma_pl330_desc *desc;
361};
362
363
364struct _pl330_tbd {
365 bool reset_dmac;
366 bool reset_mngr;
367 u8 reset_chan;
368};
369
370
371struct pl330_thread {
372 u8 id;
373 int ev;
374
375 bool free;
376
377 struct pl330_dmac *dmac;
378
379 struct _pl330_req req[2];
380
381 unsigned lstenq;
382
383 int req_running;
384};
385
386enum pl330_dmac_state {
387 UNINIT,
388 INIT,
389 DYING,
390};
391
392enum desc_status {
393
394 FREE,
395
396
397
398
399 PREP,
400
401
402
403
404
405 BUSY,
406
407
408
409
410 DONE,
411};
412
413struct dma_pl330_chan {
414
415 struct tasklet_struct task;
416
417
418 struct dma_chan chan;
419
420
421 struct list_head submitted_list;
422
423 struct list_head work_list;
424
425 struct list_head completed_list;
426
427
428
429
430
431
432 struct pl330_dmac *dmac;
433
434
435 spinlock_t lock;
436
437
438
439
440
441 struct pl330_thread *thread;
442
443
444 int burst_sz;
445 int burst_len;
446 phys_addr_t fifo_addr;
447
448 dma_addr_t fifo_dma;
449 enum dma_data_direction dir;
450 struct dma_slave_config slave_config;
451
452
453 bool cyclic;
454
455
456 bool active;
457};
458
459struct pl330_dmac {
460
461 struct dma_device ddma;
462
463
464 struct list_head desc_pool;
465
466 spinlock_t pool_lock;
467
468
469 unsigned mcbufsz;
470
471 void __iomem *base;
472
473 struct pl330_config pcfg;
474
475 spinlock_t lock;
476
477 int events[32];
478
479 dma_addr_t mcode_bus;
480
481 void *mcode_cpu;
482
483 struct pl330_thread *channels;
484
485 struct pl330_thread *manager;
486
487 struct tasklet_struct tasks;
488 struct _pl330_tbd dmac_tbd;
489
490 enum pl330_dmac_state state;
491
492 struct list_head req_done;
493
494
495 unsigned int num_peripherals;
496 struct dma_pl330_chan *peripherals;
497 int quirks;
498
499 struct reset_control *rstc;
500 struct reset_control *rstc_ocp;
501};
502
503static struct pl330_of_quirks {
504 char *quirk;
505 int id;
506} of_quirks[] = {
507 {
508 .quirk = "arm,pl330-broken-no-flushp",
509 .id = PL330_QUIRK_BROKEN_NO_FLUSHP,
510 },
511 {
512 .quirk = "arm,pl330-periph-burst",
513 .id = PL330_QUIRK_PERIPH_BURST,
514 }
515};
516
517struct dma_pl330_desc {
518
519 struct list_head node;
520
521
522 struct dma_async_tx_descriptor txd;
523
524
525 struct pl330_xfer px;
526
527 struct pl330_reqcfg rqcfg;
528
529 enum desc_status status;
530
531 int bytes_requested;
532 bool last;
533
534
535 struct dma_pl330_chan *pchan;
536
537 enum dma_transfer_direction rqtype;
538
539 unsigned peri:5;
540
541 struct list_head rqd;
542};
543
544struct _xfer_spec {
545 u32 ccr;
546 struct dma_pl330_desc *desc;
547};
548
549static int pl330_config_write(struct dma_chan *chan,
550 struct dma_slave_config *slave_config,
551 enum dma_transfer_direction direction);
552
553static inline bool _queue_full(struct pl330_thread *thrd)
554{
555 return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
556}
557
558static inline bool is_manager(struct pl330_thread *thrd)
559{
560 return thrd->dmac->manager == thrd;
561}
562
563
564static inline bool _manager_ns(struct pl330_thread *thrd)
565{
566 return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
567}
568
569static inline u32 get_revision(u32 periph_id)
570{
571 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
572}
573
574static inline u32 _emit_END(unsigned dry_run, u8 buf[])
575{
576 if (dry_run)
577 return SZ_DMAEND;
578
579 buf[0] = CMD_DMAEND;
580
581 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
582
583 return SZ_DMAEND;
584}
585
586static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
587{
588 if (dry_run)
589 return SZ_DMAFLUSHP;
590
591 buf[0] = CMD_DMAFLUSHP;
592
593 peri &= 0x1f;
594 peri <<= 3;
595 buf[1] = peri;
596
597 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
598
599 return SZ_DMAFLUSHP;
600}
601
602static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
603{
604 if (dry_run)
605 return SZ_DMALD;
606
607 buf[0] = CMD_DMALD;
608
609 if (cond == SINGLE)
610 buf[0] |= (0 << 1) | (1 << 0);
611 else if (cond == BURST)
612 buf[0] |= (1 << 1) | (1 << 0);
613
614 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
615 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
616
617 return SZ_DMALD;
618}
619
620static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
621 enum pl330_cond cond, u8 peri)
622{
623 if (dry_run)
624 return SZ_DMALDP;
625
626 buf[0] = CMD_DMALDP;
627
628 if (cond == BURST)
629 buf[0] |= (1 << 1);
630
631 peri &= 0x1f;
632 peri <<= 3;
633 buf[1] = peri;
634
635 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
636 cond == SINGLE ? 'S' : 'B', peri >> 3);
637
638 return SZ_DMALDP;
639}
640
641static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
642 unsigned loop, u8 cnt)
643{
644 if (dry_run)
645 return SZ_DMALP;
646
647 buf[0] = CMD_DMALP;
648
649 if (loop)
650 buf[0] |= (1 << 1);
651
652 cnt--;
653 buf[1] = cnt;
654
655 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
656
657 return SZ_DMALP;
658}
659
660struct _arg_LPEND {
661 enum pl330_cond cond;
662 bool forever;
663 unsigned loop;
664 u8 bjump;
665};
666
667static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
668 const struct _arg_LPEND *arg)
669{
670 enum pl330_cond cond = arg->cond;
671 bool forever = arg->forever;
672 unsigned loop = arg->loop;
673 u8 bjump = arg->bjump;
674
675 if (dry_run)
676 return SZ_DMALPEND;
677
678 buf[0] = CMD_DMALPEND;
679
680 if (loop)
681 buf[0] |= (1 << 2);
682
683 if (!forever)
684 buf[0] |= (1 << 4);
685
686 if (cond == SINGLE)
687 buf[0] |= (0 << 1) | (1 << 0);
688 else if (cond == BURST)
689 buf[0] |= (1 << 1) | (1 << 0);
690
691 buf[1] = bjump;
692
693 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
694 forever ? "FE" : "END",
695 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
696 loop ? '1' : '0',
697 bjump);
698
699 return SZ_DMALPEND;
700}
701
702static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
703{
704 if (dry_run)
705 return SZ_DMAKILL;
706
707 buf[0] = CMD_DMAKILL;
708
709 return SZ_DMAKILL;
710}
711
712static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
713 enum dmamov_dst dst, u32 val)
714{
715 if (dry_run)
716 return SZ_DMAMOV;
717
718 buf[0] = CMD_DMAMOV;
719 buf[1] = dst;
720 buf[2] = val;
721 buf[3] = val >> 8;
722 buf[4] = val >> 16;
723 buf[5] = val >> 24;
724
725 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
726 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
727
728 return SZ_DMAMOV;
729}
730
731static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
732{
733 if (dry_run)
734 return SZ_DMARMB;
735
736 buf[0] = CMD_DMARMB;
737
738 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
739
740 return SZ_DMARMB;
741}
742
743static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
744{
745 if (dry_run)
746 return SZ_DMASEV;
747
748 buf[0] = CMD_DMASEV;
749
750 ev &= 0x1f;
751 ev <<= 3;
752 buf[1] = ev;
753
754 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
755
756 return SZ_DMASEV;
757}
758
759static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
760{
761 if (dry_run)
762 return SZ_DMAST;
763
764 buf[0] = CMD_DMAST;
765
766 if (cond == SINGLE)
767 buf[0] |= (0 << 1) | (1 << 0);
768 else if (cond == BURST)
769 buf[0] |= (1 << 1) | (1 << 0);
770
771 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
772 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
773
774 return SZ_DMAST;
775}
776
777static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
778 enum pl330_cond cond, u8 peri)
779{
780 if (dry_run)
781 return SZ_DMASTP;
782
783 buf[0] = CMD_DMASTP;
784
785 if (cond == BURST)
786 buf[0] |= (1 << 1);
787
788 peri &= 0x1f;
789 peri <<= 3;
790 buf[1] = peri;
791
792 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
793 cond == SINGLE ? 'S' : 'B', peri >> 3);
794
795 return SZ_DMASTP;
796}
797
798static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
799 enum pl330_cond cond, u8 peri)
800{
801 if (dry_run)
802 return SZ_DMAWFP;
803
804 buf[0] = CMD_DMAWFP;
805
806 if (cond == SINGLE)
807 buf[0] |= (0 << 1) | (0 << 0);
808 else if (cond == BURST)
809 buf[0] |= (1 << 1) | (0 << 0);
810 else
811 buf[0] |= (0 << 1) | (1 << 0);
812
813 peri &= 0x1f;
814 peri <<= 3;
815 buf[1] = peri;
816
817 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
818 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
819
820 return SZ_DMAWFP;
821}
822
823static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
824{
825 if (dry_run)
826 return SZ_DMAWMB;
827
828 buf[0] = CMD_DMAWMB;
829
830 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
831
832 return SZ_DMAWMB;
833}
834
835struct _arg_GO {
836 u8 chan;
837 u32 addr;
838 unsigned ns;
839};
840
841static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
842 const struct _arg_GO *arg)
843{
844 u8 chan = arg->chan;
845 u32 addr = arg->addr;
846 unsigned ns = arg->ns;
847
848 if (dry_run)
849 return SZ_DMAGO;
850
851 buf[0] = CMD_DMAGO;
852 buf[0] |= (ns << 1);
853 buf[1] = chan & 0x7;
854 buf[2] = addr;
855 buf[3] = addr >> 8;
856 buf[4] = addr >> 16;
857 buf[5] = addr >> 24;
858
859 return SZ_DMAGO;
860}
861
862#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
863
864
865static bool _until_dmac_idle(struct pl330_thread *thrd)
866{
867 void __iomem *regs = thrd->dmac->base;
868 unsigned long loops = msecs_to_loops(5);
869
870 do {
871
872 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
873 break;
874
875 cpu_relax();
876 } while (--loops);
877
878 if (!loops)
879 return true;
880
881 return false;
882}
883
884static inline void _execute_DBGINSN(struct pl330_thread *thrd,
885 u8 insn[], bool as_manager)
886{
887 void __iomem *regs = thrd->dmac->base;
888 u32 val;
889
890
891 if (_until_dmac_idle(thrd)) {
892 dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
893 return;
894 }
895
896 val = (insn[0] << 16) | (insn[1] << 24);
897 if (!as_manager) {
898 val |= (1 << 0);
899 val |= (thrd->id << 8);
900 }
901 writel(val, regs + DBGINST0);
902
903 val = le32_to_cpu(*((__le32 *)&insn[2]));
904 writel(val, regs + DBGINST1);
905
906
907 writel(0, regs + DBGCMD);
908}
909
910static inline u32 _state(struct pl330_thread *thrd)
911{
912 void __iomem *regs = thrd->dmac->base;
913 u32 val;
914
915 if (is_manager(thrd))
916 val = readl(regs + DS) & 0xf;
917 else
918 val = readl(regs + CS(thrd->id)) & 0xf;
919
920 switch (val) {
921 case DS_ST_STOP:
922 return PL330_STATE_STOPPED;
923 case DS_ST_EXEC:
924 return PL330_STATE_EXECUTING;
925 case DS_ST_CMISS:
926 return PL330_STATE_CACHEMISS;
927 case DS_ST_UPDTPC:
928 return PL330_STATE_UPDTPC;
929 case DS_ST_WFE:
930 return PL330_STATE_WFE;
931 case DS_ST_FAULT:
932 return PL330_STATE_FAULTING;
933 case DS_ST_ATBRR:
934 if (is_manager(thrd))
935 return PL330_STATE_INVALID;
936 else
937 return PL330_STATE_ATBARRIER;
938 case DS_ST_QBUSY:
939 if (is_manager(thrd))
940 return PL330_STATE_INVALID;
941 else
942 return PL330_STATE_QUEUEBUSY;
943 case DS_ST_WFP:
944 if (is_manager(thrd))
945 return PL330_STATE_INVALID;
946 else
947 return PL330_STATE_WFP;
948 case DS_ST_KILL:
949 if (is_manager(thrd))
950 return PL330_STATE_INVALID;
951 else
952 return PL330_STATE_KILLING;
953 case DS_ST_CMPLT:
954 if (is_manager(thrd))
955 return PL330_STATE_INVALID;
956 else
957 return PL330_STATE_COMPLETING;
958 case DS_ST_FLTCMP:
959 if (is_manager(thrd))
960 return PL330_STATE_INVALID;
961 else
962 return PL330_STATE_FAULT_COMPLETING;
963 default:
964 return PL330_STATE_INVALID;
965 }
966}
967
968static void _stop(struct pl330_thread *thrd)
969{
970 void __iomem *regs = thrd->dmac->base;
971 u8 insn[6] = {0, 0, 0, 0, 0, 0};
972 u32 inten = readl(regs + INTEN);
973
974 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
975 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
976
977
978 if (_state(thrd) == PL330_STATE_COMPLETING
979 || _state(thrd) == PL330_STATE_KILLING
980 || _state(thrd) == PL330_STATE_STOPPED)
981 return;
982
983 _emit_KILL(0, insn);
984
985 _execute_DBGINSN(thrd, insn, is_manager(thrd));
986
987
988 if (inten & (1 << thrd->ev))
989 writel(1 << thrd->ev, regs + INTCLR);
990
991 writel(inten & ~(1 << thrd->ev), regs + INTEN);
992}
993
994
995static bool _trigger(struct pl330_thread *thrd)
996{
997 void __iomem *regs = thrd->dmac->base;
998 struct _pl330_req *req;
999 struct dma_pl330_desc *desc;
1000 struct _arg_GO go;
1001 unsigned ns;
1002 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1003 int idx;
1004
1005
1006 if (_state(thrd) != PL330_STATE_STOPPED)
1007 return true;
1008
1009 idx = 1 - thrd->lstenq;
1010 if (thrd->req[idx].desc != NULL) {
1011 req = &thrd->req[idx];
1012 } else {
1013 idx = thrd->lstenq;
1014 if (thrd->req[idx].desc != NULL)
1015 req = &thrd->req[idx];
1016 else
1017 req = NULL;
1018 }
1019
1020
1021 if (!req)
1022 return true;
1023
1024
1025 if (idx == thrd->req_running)
1026 return true;
1027
1028 desc = req->desc;
1029
1030 ns = desc->rqcfg.nonsecure ? 1 : 0;
1031
1032
1033 if (_manager_ns(thrd) && !ns)
1034 dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
1035 __func__, __LINE__);
1036
1037 go.chan = thrd->id;
1038 go.addr = req->mc_bus;
1039 go.ns = ns;
1040 _emit_GO(0, insn, &go);
1041
1042
1043 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1044
1045
1046 _execute_DBGINSN(thrd, insn, true);
1047
1048 thrd->req_running = idx;
1049
1050 return true;
1051}
1052
1053static bool _start(struct pl330_thread *thrd)
1054{
1055 switch (_state(thrd)) {
1056 case PL330_STATE_FAULT_COMPLETING:
1057 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1058
1059 if (_state(thrd) == PL330_STATE_KILLING)
1060 UNTIL(thrd, PL330_STATE_STOPPED)
1061 fallthrough;
1062
1063 case PL330_STATE_FAULTING:
1064 _stop(thrd);
1065 fallthrough;
1066
1067 case PL330_STATE_KILLING:
1068 case PL330_STATE_COMPLETING:
1069 UNTIL(thrd, PL330_STATE_STOPPED)
1070 fallthrough;
1071
1072 case PL330_STATE_STOPPED:
1073 return _trigger(thrd);
1074
1075 case PL330_STATE_WFP:
1076 case PL330_STATE_QUEUEBUSY:
1077 case PL330_STATE_ATBARRIER:
1078 case PL330_STATE_UPDTPC:
1079 case PL330_STATE_CACHEMISS:
1080 case PL330_STATE_EXECUTING:
1081 return true;
1082
1083 case PL330_STATE_WFE:
1084 default:
1085 return false;
1086 }
1087}
1088
1089static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1090 const struct _xfer_spec *pxs, int cyc)
1091{
1092 int off = 0;
1093 struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
1094
1095
1096 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1097 while (cyc--) {
1098 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1099 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1100 }
1101 } else {
1102 while (cyc--) {
1103 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1104 off += _emit_RMB(dry_run, &buf[off]);
1105 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1106 off += _emit_WMB(dry_run, &buf[off]);
1107 }
1108 }
1109
1110 return off;
1111}
1112
1113static u32 _emit_load(unsigned int dry_run, u8 buf[],
1114 enum pl330_cond cond, enum dma_transfer_direction direction,
1115 u8 peri)
1116{
1117 int off = 0;
1118
1119 switch (direction) {
1120 case DMA_MEM_TO_MEM:
1121 case DMA_MEM_TO_DEV:
1122 off += _emit_LD(dry_run, &buf[off], cond);
1123 break;
1124
1125 case DMA_DEV_TO_MEM:
1126 if (cond == ALWAYS) {
1127 off += _emit_LDP(dry_run, &buf[off], SINGLE,
1128 peri);
1129 off += _emit_LDP(dry_run, &buf[off], BURST,
1130 peri);
1131 } else {
1132 off += _emit_LDP(dry_run, &buf[off], cond,
1133 peri);
1134 }
1135 break;
1136
1137 default:
1138
1139 WARN_ON(1);
1140 break;
1141 }
1142
1143 return off;
1144}
1145
1146static inline u32 _emit_store(unsigned int dry_run, u8 buf[],
1147 enum pl330_cond cond, enum dma_transfer_direction direction,
1148 u8 peri)
1149{
1150 int off = 0;
1151
1152 switch (direction) {
1153 case DMA_MEM_TO_MEM:
1154 case DMA_DEV_TO_MEM:
1155 off += _emit_ST(dry_run, &buf[off], cond);
1156 break;
1157
1158 case DMA_MEM_TO_DEV:
1159 if (cond == ALWAYS) {
1160 off += _emit_STP(dry_run, &buf[off], SINGLE,
1161 peri);
1162 off += _emit_STP(dry_run, &buf[off], BURST,
1163 peri);
1164 } else {
1165 off += _emit_STP(dry_run, &buf[off], cond,
1166 peri);
1167 }
1168 break;
1169
1170 default:
1171
1172 WARN_ON(1);
1173 break;
1174 }
1175
1176 return off;
1177}
1178
1179static inline int _ldst_peripheral(struct pl330_dmac *pl330,
1180 unsigned dry_run, u8 buf[],
1181 const struct _xfer_spec *pxs, int cyc,
1182 enum pl330_cond cond)
1183{
1184 int off = 0;
1185
1186
1187
1188
1189
1190 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1191 off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri);
1192 while (cyc--) {
1193 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1194 off += _emit_load(dry_run, &buf[off], cond, pxs->desc->rqtype,
1195 pxs->desc->peri);
1196 off += _emit_store(dry_run, &buf[off], cond, pxs->desc->rqtype,
1197 pxs->desc->peri);
1198 }
1199
1200 return off;
1201}
1202
1203static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1204 const struct _xfer_spec *pxs, int cyc)
1205{
1206 int off = 0;
1207 enum pl330_cond cond = BRST_LEN(pxs->ccr) > 1 ? BURST : SINGLE;
1208
1209 if (pl330->quirks & PL330_QUIRK_PERIPH_BURST)
1210 cond = BURST;
1211
1212 switch (pxs->desc->rqtype) {
1213 case DMA_MEM_TO_DEV:
1214 case DMA_DEV_TO_MEM:
1215 off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, cyc,
1216 cond);
1217 break;
1218
1219 case DMA_MEM_TO_MEM:
1220 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1221 break;
1222
1223 default:
1224
1225 WARN_ON(1);
1226 break;
1227 }
1228
1229 return off;
1230}
1231
1232
1233
1234
1235
1236
1237static int _dregs(struct pl330_dmac *pl330, unsigned int dry_run, u8 buf[],
1238 const struct _xfer_spec *pxs, int transfer_length)
1239{
1240 int off = 0;
1241 int dregs_ccr;
1242
1243 if (transfer_length == 0)
1244 return off;
1245
1246
1247
1248
1249
1250
1251
1252
1253 dregs_ccr = pxs->ccr;
1254 dregs_ccr &= ~((0xf << CC_SRCBRSTLEN_SHFT) |
1255 (0xf << CC_DSTBRSTLEN_SHFT));
1256 dregs_ccr |= (((transfer_length - 1) & 0xf) <<
1257 CC_SRCBRSTLEN_SHFT);
1258 dregs_ccr |= (((transfer_length - 1) & 0xf) <<
1259 CC_DSTBRSTLEN_SHFT);
1260
1261 switch (pxs->desc->rqtype) {
1262 case DMA_MEM_TO_DEV:
1263 case DMA_DEV_TO_MEM:
1264 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr);
1265 off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, 1,
1266 BURST);
1267 break;
1268
1269 case DMA_MEM_TO_MEM:
1270 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr);
1271 off += _ldst_memtomem(dry_run, &buf[off], pxs, 1);
1272 break;
1273
1274 default:
1275
1276 WARN_ON(1);
1277 break;
1278 }
1279
1280 return off;
1281}
1282
1283
1284static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1285 unsigned long *bursts, const struct _xfer_spec *pxs)
1286{
1287 int cyc, cycmax, szlp, szlpend, szbrst, off;
1288 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1289 struct _arg_LPEND lpend;
1290
1291 if (*bursts == 1)
1292 return _bursts(pl330, dry_run, buf, pxs, 1);
1293
1294
1295 if (*bursts >= 256*256) {
1296 lcnt1 = 256;
1297 lcnt0 = 256;
1298 cyc = *bursts / lcnt1 / lcnt0;
1299 } else if (*bursts > 256) {
1300 lcnt1 = 256;
1301 lcnt0 = *bursts / lcnt1;
1302 cyc = 1;
1303 } else {
1304 lcnt1 = *bursts;
1305 lcnt0 = 0;
1306 cyc = 1;
1307 }
1308
1309 szlp = _emit_LP(1, buf, 0, 0);
1310 szbrst = _bursts(pl330, 1, buf, pxs, 1);
1311
1312 lpend.cond = ALWAYS;
1313 lpend.forever = false;
1314 lpend.loop = 0;
1315 lpend.bjump = 0;
1316 szlpend = _emit_LPEND(1, buf, &lpend);
1317
1318 if (lcnt0) {
1319 szlp *= 2;
1320 szlpend *= 2;
1321 }
1322
1323
1324
1325
1326
1327
1328 cycmax = (255 - (szlp + szlpend)) / szbrst;
1329
1330 cyc = (cycmax < cyc) ? cycmax : cyc;
1331
1332 off = 0;
1333
1334 if (lcnt0) {
1335 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1336 ljmp0 = off;
1337 }
1338
1339 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1340 ljmp1 = off;
1341
1342 off += _bursts(pl330, dry_run, &buf[off], pxs, cyc);
1343
1344 lpend.cond = ALWAYS;
1345 lpend.forever = false;
1346 lpend.loop = 1;
1347 lpend.bjump = off - ljmp1;
1348 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1349
1350 if (lcnt0) {
1351 lpend.cond = ALWAYS;
1352 lpend.forever = false;
1353 lpend.loop = 0;
1354 lpend.bjump = off - ljmp0;
1355 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1356 }
1357
1358 *bursts = lcnt1 * cyc;
1359 if (lcnt0)
1360 *bursts *= lcnt0;
1361
1362 return off;
1363}
1364
1365static inline int _setup_loops(struct pl330_dmac *pl330,
1366 unsigned dry_run, u8 buf[],
1367 const struct _xfer_spec *pxs)
1368{
1369 struct pl330_xfer *x = &pxs->desc->px;
1370 u32 ccr = pxs->ccr;
1371 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1372 int num_dregs = (x->bytes - BURST_TO_BYTE(bursts, ccr)) /
1373 BRST_SIZE(ccr);
1374 int off = 0;
1375
1376 while (bursts) {
1377 c = bursts;
1378 off += _loop(pl330, dry_run, &buf[off], &c, pxs);
1379 bursts -= c;
1380 }
1381 off += _dregs(pl330, dry_run, &buf[off], pxs, num_dregs);
1382
1383 return off;
1384}
1385
1386static inline int _setup_xfer(struct pl330_dmac *pl330,
1387 unsigned dry_run, u8 buf[],
1388 const struct _xfer_spec *pxs)
1389{
1390 struct pl330_xfer *x = &pxs->desc->px;
1391 int off = 0;
1392
1393
1394 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1395
1396 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1397
1398
1399 off += _setup_loops(pl330, dry_run, &buf[off], pxs);
1400
1401 return off;
1402}
1403
1404
1405
1406
1407
1408static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run,
1409 struct pl330_thread *thrd, unsigned index,
1410 struct _xfer_spec *pxs)
1411{
1412 struct _pl330_req *req = &thrd->req[index];
1413 u8 *buf = req->mc_cpu;
1414 int off = 0;
1415
1416 PL330_DBGMC_START(req->mc_bus);
1417
1418
1419 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1420
1421 off += _setup_xfer(pl330, dry_run, &buf[off], pxs);
1422
1423
1424 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1425
1426 off += _emit_END(dry_run, &buf[off]);
1427
1428 return off;
1429}
1430
1431static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1432{
1433 u32 ccr = 0;
1434
1435 if (rqc->src_inc)
1436 ccr |= CC_SRCINC;
1437
1438 if (rqc->dst_inc)
1439 ccr |= CC_DSTINC;
1440
1441
1442 if (rqc->privileged)
1443 ccr |= CC_SRCPRI | CC_DSTPRI;
1444 if (rqc->nonsecure)
1445 ccr |= CC_SRCNS | CC_DSTNS;
1446 if (rqc->insnaccess)
1447 ccr |= CC_SRCIA | CC_DSTIA;
1448
1449 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1450 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1451
1452 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1453 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1454
1455 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1456 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1457
1458 ccr |= (rqc->swap << CC_SWAP_SHFT);
1459
1460 return ccr;
1461}
1462
1463
1464
1465
1466
1467
1468static int pl330_submit_req(struct pl330_thread *thrd,
1469 struct dma_pl330_desc *desc)
1470{
1471 struct pl330_dmac *pl330 = thrd->dmac;
1472 struct _xfer_spec xs;
1473 unsigned long flags;
1474 unsigned idx;
1475 u32 ccr;
1476 int ret = 0;
1477
1478 switch (desc->rqtype) {
1479 case DMA_MEM_TO_DEV:
1480 break;
1481
1482 case DMA_DEV_TO_MEM:
1483 break;
1484
1485 case DMA_MEM_TO_MEM:
1486 break;
1487
1488 default:
1489 return -ENOTSUPP;
1490 }
1491
1492 if (pl330->state == DYING
1493 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1494 dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
1495 __func__, __LINE__);
1496 return -EAGAIN;
1497 }
1498
1499
1500 if (desc->rqtype != DMA_MEM_TO_MEM &&
1501 desc->peri >= pl330->pcfg.num_peri) {
1502 dev_info(thrd->dmac->ddma.dev,
1503 "%s:%d Invalid peripheral(%u)!\n",
1504 __func__, __LINE__, desc->peri);
1505 return -EINVAL;
1506 }
1507
1508 spin_lock_irqsave(&pl330->lock, flags);
1509
1510 if (_queue_full(thrd)) {
1511 ret = -EAGAIN;
1512 goto xfer_exit;
1513 }
1514
1515
1516 if (!_manager_ns(thrd))
1517 desc->rqcfg.nonsecure = 0;
1518 else
1519 desc->rqcfg.nonsecure = 1;
1520
1521 ccr = _prepare_ccr(&desc->rqcfg);
1522
1523 idx = thrd->req[0].desc == NULL ? 0 : 1;
1524
1525 xs.ccr = ccr;
1526 xs.desc = desc;
1527
1528
1529 ret = _setup_req(pl330, 1, thrd, idx, &xs);
1530
1531 if (ret > pl330->mcbufsz / 2) {
1532 dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n",
1533 __func__, __LINE__, ret, pl330->mcbufsz / 2);
1534 ret = -ENOMEM;
1535 goto xfer_exit;
1536 }
1537
1538
1539 thrd->lstenq = idx;
1540 thrd->req[idx].desc = desc;
1541 _setup_req(pl330, 0, thrd, idx, &xs);
1542
1543 ret = 0;
1544
1545xfer_exit:
1546 spin_unlock_irqrestore(&pl330->lock, flags);
1547
1548 return ret;
1549}
1550
1551static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
1552{
1553 struct dma_pl330_chan *pch;
1554 unsigned long flags;
1555
1556 if (!desc)
1557 return;
1558
1559 pch = desc->pchan;
1560
1561
1562 if (!pch)
1563 return;
1564
1565 spin_lock_irqsave(&pch->lock, flags);
1566
1567 desc->status = DONE;
1568
1569 spin_unlock_irqrestore(&pch->lock, flags);
1570
1571 tasklet_schedule(&pch->task);
1572}
1573
1574static void pl330_dotask(struct tasklet_struct *t)
1575{
1576 struct pl330_dmac *pl330 = from_tasklet(pl330, t, tasks);
1577 unsigned long flags;
1578 int i;
1579
1580 spin_lock_irqsave(&pl330->lock, flags);
1581
1582
1583 if (pl330->dmac_tbd.reset_dmac) {
1584 pl330->state = DYING;
1585
1586 pl330->dmac_tbd.reset_mngr = true;
1587
1588 pl330->dmac_tbd.reset_dmac = false;
1589 }
1590
1591 if (pl330->dmac_tbd.reset_mngr) {
1592 _stop(pl330->manager);
1593
1594 pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
1595
1596 pl330->dmac_tbd.reset_mngr = false;
1597 }
1598
1599 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1600
1601 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1602 struct pl330_thread *thrd = &pl330->channels[i];
1603 void __iomem *regs = pl330->base;
1604 enum pl330_op_err err;
1605
1606 _stop(thrd);
1607
1608 if (readl(regs + FSC) & (1 << thrd->id))
1609 err = PL330_ERR_FAIL;
1610 else
1611 err = PL330_ERR_ABORT;
1612
1613 spin_unlock_irqrestore(&pl330->lock, flags);
1614 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
1615 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
1616 spin_lock_irqsave(&pl330->lock, flags);
1617
1618 thrd->req[0].desc = NULL;
1619 thrd->req[1].desc = NULL;
1620 thrd->req_running = -1;
1621
1622
1623 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1624 }
1625 }
1626
1627 spin_unlock_irqrestore(&pl330->lock, flags);
1628
1629 return;
1630}
1631
1632
1633static int pl330_update(struct pl330_dmac *pl330)
1634{
1635 struct dma_pl330_desc *descdone;
1636 unsigned long flags;
1637 void __iomem *regs;
1638 u32 val;
1639 int id, ev, ret = 0;
1640
1641 regs = pl330->base;
1642
1643 spin_lock_irqsave(&pl330->lock, flags);
1644
1645 val = readl(regs + FSM) & 0x1;
1646 if (val)
1647 pl330->dmac_tbd.reset_mngr = true;
1648 else
1649 pl330->dmac_tbd.reset_mngr = false;
1650
1651 val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
1652 pl330->dmac_tbd.reset_chan |= val;
1653 if (val) {
1654 int i = 0;
1655 while (i < pl330->pcfg.num_chan) {
1656 if (val & (1 << i)) {
1657 dev_info(pl330->ddma.dev,
1658 "Reset Channel-%d\t CS-%x FTC-%x\n",
1659 i, readl(regs + CS(i)),
1660 readl(regs + FTC(i)));
1661 _stop(&pl330->channels[i]);
1662 }
1663 i++;
1664 }
1665 }
1666
1667
1668 val = readl(regs + ES);
1669 if (pl330->pcfg.num_events < 32
1670 && val & ~((1 << pl330->pcfg.num_events) - 1)) {
1671 pl330->dmac_tbd.reset_dmac = true;
1672 dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
1673 __LINE__);
1674 ret = 1;
1675 goto updt_exit;
1676 }
1677
1678 for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
1679 if (val & (1 << ev)) {
1680 struct pl330_thread *thrd;
1681 u32 inten = readl(regs + INTEN);
1682 int active;
1683
1684
1685 if (inten & (1 << ev))
1686 writel(1 << ev, regs + INTCLR);
1687
1688 ret = 1;
1689
1690 id = pl330->events[ev];
1691
1692 thrd = &pl330->channels[id];
1693
1694 active = thrd->req_running;
1695 if (active == -1)
1696 continue;
1697
1698
1699 descdone = thrd->req[active].desc;
1700 thrd->req[active].desc = NULL;
1701
1702 thrd->req_running = -1;
1703
1704
1705 _start(thrd);
1706
1707
1708 list_add_tail(&descdone->rqd, &pl330->req_done);
1709 }
1710 }
1711
1712
1713 while (!list_empty(&pl330->req_done)) {
1714 descdone = list_first_entry(&pl330->req_done,
1715 struct dma_pl330_desc, rqd);
1716 list_del(&descdone->rqd);
1717 spin_unlock_irqrestore(&pl330->lock, flags);
1718 dma_pl330_rqcb(descdone, PL330_ERR_NONE);
1719 spin_lock_irqsave(&pl330->lock, flags);
1720 }
1721
1722updt_exit:
1723 spin_unlock_irqrestore(&pl330->lock, flags);
1724
1725 if (pl330->dmac_tbd.reset_dmac
1726 || pl330->dmac_tbd.reset_mngr
1727 || pl330->dmac_tbd.reset_chan) {
1728 ret = 1;
1729 tasklet_schedule(&pl330->tasks);
1730 }
1731
1732 return ret;
1733}
1734
1735
1736static inline int _alloc_event(struct pl330_thread *thrd)
1737{
1738 struct pl330_dmac *pl330 = thrd->dmac;
1739 int ev;
1740
1741 for (ev = 0; ev < pl330->pcfg.num_events; ev++)
1742 if (pl330->events[ev] == -1) {
1743 pl330->events[ev] = thrd->id;
1744 return ev;
1745 }
1746
1747 return -1;
1748}
1749
1750static bool _chan_ns(const struct pl330_dmac *pl330, int i)
1751{
1752 return pl330->pcfg.irq_ns & (1 << i);
1753}
1754
1755
1756
1757
1758static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330)
1759{
1760 struct pl330_thread *thrd = NULL;
1761 int chans, i;
1762
1763 if (pl330->state == DYING)
1764 return NULL;
1765
1766 chans = pl330->pcfg.num_chan;
1767
1768 for (i = 0; i < chans; i++) {
1769 thrd = &pl330->channels[i];
1770 if ((thrd->free) && (!_manager_ns(thrd) ||
1771 _chan_ns(pl330, i))) {
1772 thrd->ev = _alloc_event(thrd);
1773 if (thrd->ev >= 0) {
1774 thrd->free = false;
1775 thrd->lstenq = 1;
1776 thrd->req[0].desc = NULL;
1777 thrd->req[1].desc = NULL;
1778 thrd->req_running = -1;
1779 break;
1780 }
1781 }
1782 thrd = NULL;
1783 }
1784
1785 return thrd;
1786}
1787
1788
1789static inline void _free_event(struct pl330_thread *thrd, int ev)
1790{
1791 struct pl330_dmac *pl330 = thrd->dmac;
1792
1793
1794 if (ev >= 0 && ev < pl330->pcfg.num_events
1795 && pl330->events[ev] == thrd->id)
1796 pl330->events[ev] = -1;
1797}
1798
1799static void pl330_release_channel(struct pl330_thread *thrd)
1800{
1801 if (!thrd || thrd->free)
1802 return;
1803
1804 _stop(thrd);
1805
1806 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
1807 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
1808
1809 _free_event(thrd, thrd->ev);
1810 thrd->free = true;
1811}
1812
1813
1814
1815
1816static void read_dmac_config(struct pl330_dmac *pl330)
1817{
1818 void __iomem *regs = pl330->base;
1819 u32 val;
1820
1821 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1822 val &= CRD_DATA_WIDTH_MASK;
1823 pl330->pcfg.data_bus_width = 8 * (1 << val);
1824
1825 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1826 val &= CRD_DATA_BUFF_MASK;
1827 pl330->pcfg.data_buf_dep = val + 1;
1828
1829 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1830 val &= CR0_NUM_CHANS_MASK;
1831 val += 1;
1832 pl330->pcfg.num_chan = val;
1833
1834 val = readl(regs + CR0);
1835 if (val & CR0_PERIPH_REQ_SET) {
1836 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1837 val += 1;
1838 pl330->pcfg.num_peri = val;
1839 pl330->pcfg.peri_ns = readl(regs + CR4);
1840 } else {
1841 pl330->pcfg.num_peri = 0;
1842 }
1843
1844 val = readl(regs + CR0);
1845 if (val & CR0_BOOT_MAN_NS)
1846 pl330->pcfg.mode |= DMAC_MODE_NS;
1847 else
1848 pl330->pcfg.mode &= ~DMAC_MODE_NS;
1849
1850 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1851 val &= CR0_NUM_EVENTS_MASK;
1852 val += 1;
1853 pl330->pcfg.num_events = val;
1854
1855 pl330->pcfg.irq_ns = readl(regs + CR3);
1856}
1857
1858static inline void _reset_thread(struct pl330_thread *thrd)
1859{
1860 struct pl330_dmac *pl330 = thrd->dmac;
1861
1862 thrd->req[0].mc_cpu = pl330->mcode_cpu
1863 + (thrd->id * pl330->mcbufsz);
1864 thrd->req[0].mc_bus = pl330->mcode_bus
1865 + (thrd->id * pl330->mcbufsz);
1866 thrd->req[0].desc = NULL;
1867
1868 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
1869 + pl330->mcbufsz / 2;
1870 thrd->req[1].mc_bus = thrd->req[0].mc_bus
1871 + pl330->mcbufsz / 2;
1872 thrd->req[1].desc = NULL;
1873
1874 thrd->req_running = -1;
1875}
1876
1877static int dmac_alloc_threads(struct pl330_dmac *pl330)
1878{
1879 int chans = pl330->pcfg.num_chan;
1880 struct pl330_thread *thrd;
1881 int i;
1882
1883
1884 pl330->channels = kcalloc(1 + chans, sizeof(*thrd),
1885 GFP_KERNEL);
1886 if (!pl330->channels)
1887 return -ENOMEM;
1888
1889
1890 for (i = 0; i < chans; i++) {
1891 thrd = &pl330->channels[i];
1892 thrd->id = i;
1893 thrd->dmac = pl330;
1894 _reset_thread(thrd);
1895 thrd->free = true;
1896 }
1897
1898
1899 thrd = &pl330->channels[chans];
1900 thrd->id = chans;
1901 thrd->dmac = pl330;
1902 thrd->free = false;
1903 pl330->manager = thrd;
1904
1905 return 0;
1906}
1907
1908static int dmac_alloc_resources(struct pl330_dmac *pl330)
1909{
1910 int chans = pl330->pcfg.num_chan;
1911 int ret;
1912
1913
1914
1915
1916
1917 pl330->mcode_cpu = dma_alloc_attrs(pl330->ddma.dev,
1918 chans * pl330->mcbufsz,
1919 &pl330->mcode_bus, GFP_KERNEL,
1920 DMA_ATTR_PRIVILEGED);
1921 if (!pl330->mcode_cpu) {
1922 dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
1923 __func__, __LINE__);
1924 return -ENOMEM;
1925 }
1926
1927 ret = dmac_alloc_threads(pl330);
1928 if (ret) {
1929 dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
1930 __func__, __LINE__);
1931 dma_free_attrs(pl330->ddma.dev,
1932 chans * pl330->mcbufsz,
1933 pl330->mcode_cpu, pl330->mcode_bus,
1934 DMA_ATTR_PRIVILEGED);
1935 return ret;
1936 }
1937
1938 return 0;
1939}
1940
1941static int pl330_add(struct pl330_dmac *pl330)
1942{
1943 int i, ret;
1944
1945
1946 if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
1947 dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
1948 pl330->pcfg.periph_id);
1949 return -EINVAL;
1950 }
1951
1952
1953 read_dmac_config(pl330);
1954
1955 if (pl330->pcfg.num_events == 0) {
1956 dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
1957 __func__, __LINE__);
1958 return -EINVAL;
1959 }
1960
1961 spin_lock_init(&pl330->lock);
1962
1963 INIT_LIST_HEAD(&pl330->req_done);
1964
1965
1966 if (!pl330->mcbufsz)
1967 pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
1968
1969
1970 for (i = 0; i < pl330->pcfg.num_events; i++)
1971 pl330->events[i] = -1;
1972
1973
1974 ret = dmac_alloc_resources(pl330);
1975 if (ret) {
1976 dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
1977 return ret;
1978 }
1979
1980 tasklet_setup(&pl330->tasks, pl330_dotask);
1981
1982 pl330->state = INIT;
1983
1984 return 0;
1985}
1986
1987static int dmac_free_threads(struct pl330_dmac *pl330)
1988{
1989 struct pl330_thread *thrd;
1990 int i;
1991
1992
1993 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1994 thrd = &pl330->channels[i];
1995 pl330_release_channel(thrd);
1996 }
1997
1998
1999 kfree(pl330->channels);
2000
2001 return 0;
2002}
2003
2004static void pl330_del(struct pl330_dmac *pl330)
2005{
2006 pl330->state = UNINIT;
2007
2008 tasklet_kill(&pl330->tasks);
2009
2010
2011 dmac_free_threads(pl330);
2012
2013 dma_free_attrs(pl330->ddma.dev,
2014 pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
2015 pl330->mcode_bus, DMA_ATTR_PRIVILEGED);
2016}
2017
2018
2019static struct amba_driver pl330_driver;
2020
2021static inline struct dma_pl330_chan *
2022to_pchan(struct dma_chan *ch)
2023{
2024 if (!ch)
2025 return NULL;
2026
2027 return container_of(ch, struct dma_pl330_chan, chan);
2028}
2029
2030static inline struct dma_pl330_desc *
2031to_desc(struct dma_async_tx_descriptor *tx)
2032{
2033 return container_of(tx, struct dma_pl330_desc, txd);
2034}
2035
2036static inline void fill_queue(struct dma_pl330_chan *pch)
2037{
2038 struct dma_pl330_desc *desc;
2039 int ret;
2040
2041 list_for_each_entry(desc, &pch->work_list, node) {
2042
2043
2044 if (desc->status == BUSY)
2045 continue;
2046
2047 ret = pl330_submit_req(pch->thread, desc);
2048 if (!ret) {
2049 desc->status = BUSY;
2050 } else if (ret == -EAGAIN) {
2051
2052 break;
2053 } else {
2054
2055 desc->status = DONE;
2056 dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
2057 __func__, __LINE__, desc->txd.cookie);
2058 tasklet_schedule(&pch->task);
2059 }
2060 }
2061}
2062
2063static void pl330_tasklet(struct tasklet_struct *t)
2064{
2065 struct dma_pl330_chan *pch = from_tasklet(pch, t, task);
2066 struct dma_pl330_desc *desc, *_dt;
2067 unsigned long flags;
2068 bool power_down = false;
2069
2070 spin_lock_irqsave(&pch->lock, flags);
2071
2072
2073 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
2074 if (desc->status == DONE) {
2075 if (!pch->cyclic)
2076 dma_cookie_complete(&desc->txd);
2077 list_move_tail(&desc->node, &pch->completed_list);
2078 }
2079
2080
2081 fill_queue(pch);
2082
2083 if (list_empty(&pch->work_list)) {
2084 spin_lock(&pch->thread->dmac->lock);
2085 _stop(pch->thread);
2086 spin_unlock(&pch->thread->dmac->lock);
2087 power_down = true;
2088 pch->active = false;
2089 } else {
2090
2091 spin_lock(&pch->thread->dmac->lock);
2092 _start(pch->thread);
2093 spin_unlock(&pch->thread->dmac->lock);
2094 }
2095
2096 while (!list_empty(&pch->completed_list)) {
2097 struct dmaengine_desc_callback cb;
2098
2099 desc = list_first_entry(&pch->completed_list,
2100 struct dma_pl330_desc, node);
2101
2102 dmaengine_desc_get_callback(&desc->txd, &cb);
2103
2104 if (pch->cyclic) {
2105 desc->status = PREP;
2106 list_move_tail(&desc->node, &pch->work_list);
2107 if (power_down) {
2108 pch->active = true;
2109 spin_lock(&pch->thread->dmac->lock);
2110 _start(pch->thread);
2111 spin_unlock(&pch->thread->dmac->lock);
2112 power_down = false;
2113 }
2114 } else {
2115 desc->status = FREE;
2116 list_move_tail(&desc->node, &pch->dmac->desc_pool);
2117 }
2118
2119 dma_descriptor_unmap(&desc->txd);
2120
2121 if (dmaengine_desc_callback_valid(&cb)) {
2122 spin_unlock_irqrestore(&pch->lock, flags);
2123 dmaengine_desc_callback_invoke(&cb, NULL);
2124 spin_lock_irqsave(&pch->lock, flags);
2125 }
2126 }
2127 spin_unlock_irqrestore(&pch->lock, flags);
2128
2129
2130 if (power_down) {
2131 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2132 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2133 }
2134}
2135
2136static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2137 struct of_dma *ofdma)
2138{
2139 int count = dma_spec->args_count;
2140 struct pl330_dmac *pl330 = ofdma->of_dma_data;
2141 unsigned int chan_id;
2142
2143 if (!pl330)
2144 return NULL;
2145
2146 if (count != 1)
2147 return NULL;
2148
2149 chan_id = dma_spec->args[0];
2150 if (chan_id >= pl330->num_peripherals)
2151 return NULL;
2152
2153 return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
2154}
2155
2156static int pl330_alloc_chan_resources(struct dma_chan *chan)
2157{
2158 struct dma_pl330_chan *pch = to_pchan(chan);
2159 struct pl330_dmac *pl330 = pch->dmac;
2160 unsigned long flags;
2161
2162 spin_lock_irqsave(&pl330->lock, flags);
2163
2164 dma_cookie_init(chan);
2165 pch->cyclic = false;
2166
2167 pch->thread = pl330_request_channel(pl330);
2168 if (!pch->thread) {
2169 spin_unlock_irqrestore(&pl330->lock, flags);
2170 return -ENOMEM;
2171 }
2172
2173 tasklet_setup(&pch->task, pl330_tasklet);
2174
2175 spin_unlock_irqrestore(&pl330->lock, flags);
2176
2177 return 1;
2178}
2179
2180
2181
2182
2183
2184static enum dma_data_direction
2185pl330_dma_slave_map_dir(enum dma_transfer_direction dir)
2186{
2187 switch (dir) {
2188 case DMA_MEM_TO_DEV:
2189 return DMA_FROM_DEVICE;
2190 case DMA_DEV_TO_MEM:
2191 return DMA_TO_DEVICE;
2192 case DMA_DEV_TO_DEV:
2193 return DMA_BIDIRECTIONAL;
2194 default:
2195 return DMA_NONE;
2196 }
2197}
2198
2199static void pl330_unprep_slave_fifo(struct dma_pl330_chan *pch)
2200{
2201 if (pch->dir != DMA_NONE)
2202 dma_unmap_resource(pch->chan.device->dev, pch->fifo_dma,
2203 1 << pch->burst_sz, pch->dir, 0);
2204 pch->dir = DMA_NONE;
2205}
2206
2207
2208static bool pl330_prep_slave_fifo(struct dma_pl330_chan *pch,
2209 enum dma_transfer_direction dir)
2210{
2211 struct device *dev = pch->chan.device->dev;
2212 enum dma_data_direction dma_dir = pl330_dma_slave_map_dir(dir);
2213
2214
2215 if (pch->dir == dma_dir)
2216 return true;
2217
2218 pl330_unprep_slave_fifo(pch);
2219 pch->fifo_dma = dma_map_resource(dev, pch->fifo_addr,
2220 1 << pch->burst_sz, dma_dir, 0);
2221 if (dma_mapping_error(dev, pch->fifo_dma))
2222 return false;
2223
2224 pch->dir = dma_dir;
2225 return true;
2226}
2227
2228static int fixup_burst_len(int max_burst_len, int quirks)
2229{
2230 if (max_burst_len > PL330_MAX_BURST)
2231 return PL330_MAX_BURST;
2232 else if (max_burst_len < 1)
2233 return 1;
2234 else
2235 return max_burst_len;
2236}
2237
2238static int pl330_config_write(struct dma_chan *chan,
2239 struct dma_slave_config *slave_config,
2240 enum dma_transfer_direction direction)
2241{
2242 struct dma_pl330_chan *pch = to_pchan(chan);
2243
2244 pl330_unprep_slave_fifo(pch);
2245 if (direction == DMA_MEM_TO_DEV) {
2246 if (slave_config->dst_addr)
2247 pch->fifo_addr = slave_config->dst_addr;
2248 if (slave_config->dst_addr_width)
2249 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2250 pch->burst_len = fixup_burst_len(slave_config->dst_maxburst,
2251 pch->dmac->quirks);
2252 } else if (direction == DMA_DEV_TO_MEM) {
2253 if (slave_config->src_addr)
2254 pch->fifo_addr = slave_config->src_addr;
2255 if (slave_config->src_addr_width)
2256 pch->burst_sz = __ffs(slave_config->src_addr_width);
2257 pch->burst_len = fixup_burst_len(slave_config->src_maxburst,
2258 pch->dmac->quirks);
2259 }
2260
2261 return 0;
2262}
2263
2264static int pl330_config(struct dma_chan *chan,
2265 struct dma_slave_config *slave_config)
2266{
2267 struct dma_pl330_chan *pch = to_pchan(chan);
2268
2269 memcpy(&pch->slave_config, slave_config, sizeof(*slave_config));
2270
2271 return 0;
2272}
2273
2274static int pl330_terminate_all(struct dma_chan *chan)
2275{
2276 struct dma_pl330_chan *pch = to_pchan(chan);
2277 struct dma_pl330_desc *desc;
2278 unsigned long flags;
2279 struct pl330_dmac *pl330 = pch->dmac;
2280 bool power_down = false;
2281
2282 pm_runtime_get_sync(pl330->ddma.dev);
2283 spin_lock_irqsave(&pch->lock, flags);
2284
2285 spin_lock(&pl330->lock);
2286 _stop(pch->thread);
2287 pch->thread->req[0].desc = NULL;
2288 pch->thread->req[1].desc = NULL;
2289 pch->thread->req_running = -1;
2290 spin_unlock(&pl330->lock);
2291
2292 power_down = pch->active;
2293 pch->active = false;
2294
2295
2296 list_for_each_entry(desc, &pch->submitted_list, node) {
2297 desc->status = FREE;
2298 dma_cookie_complete(&desc->txd);
2299 }
2300
2301 list_for_each_entry(desc, &pch->work_list , node) {
2302 desc->status = FREE;
2303 dma_cookie_complete(&desc->txd);
2304 }
2305
2306 list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
2307 list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
2308 list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
2309 spin_unlock_irqrestore(&pch->lock, flags);
2310 pm_runtime_mark_last_busy(pl330->ddma.dev);
2311 if (power_down)
2312 pm_runtime_put_autosuspend(pl330->ddma.dev);
2313 pm_runtime_put_autosuspend(pl330->ddma.dev);
2314
2315 return 0;
2316}
2317
2318
2319
2320
2321
2322
2323
2324
2325static int pl330_pause(struct dma_chan *chan)
2326{
2327 struct dma_pl330_chan *pch = to_pchan(chan);
2328 struct pl330_dmac *pl330 = pch->dmac;
2329 unsigned long flags;
2330
2331 pm_runtime_get_sync(pl330->ddma.dev);
2332 spin_lock_irqsave(&pch->lock, flags);
2333
2334 spin_lock(&pl330->lock);
2335 _stop(pch->thread);
2336 spin_unlock(&pl330->lock);
2337
2338 spin_unlock_irqrestore(&pch->lock, flags);
2339 pm_runtime_mark_last_busy(pl330->ddma.dev);
2340 pm_runtime_put_autosuspend(pl330->ddma.dev);
2341
2342 return 0;
2343}
2344
2345static void pl330_free_chan_resources(struct dma_chan *chan)
2346{
2347 struct dma_pl330_chan *pch = to_pchan(chan);
2348 struct pl330_dmac *pl330 = pch->dmac;
2349 unsigned long flags;
2350
2351 tasklet_kill(&pch->task);
2352
2353 pm_runtime_get_sync(pch->dmac->ddma.dev);
2354 spin_lock_irqsave(&pl330->lock, flags);
2355
2356 pl330_release_channel(pch->thread);
2357 pch->thread = NULL;
2358
2359 if (pch->cyclic)
2360 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2361
2362 spin_unlock_irqrestore(&pl330->lock, flags);
2363 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2364 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2365 pl330_unprep_slave_fifo(pch);
2366}
2367
2368static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch,
2369 struct dma_pl330_desc *desc)
2370{
2371 struct pl330_thread *thrd = pch->thread;
2372 struct pl330_dmac *pl330 = pch->dmac;
2373 void __iomem *regs = thrd->dmac->base;
2374 u32 val, addr;
2375
2376 pm_runtime_get_sync(pl330->ddma.dev);
2377 val = addr = 0;
2378 if (desc->rqcfg.src_inc) {
2379 val = readl(regs + SA(thrd->id));
2380 addr = desc->px.src_addr;
2381 } else {
2382 val = readl(regs + DA(thrd->id));
2383 addr = desc->px.dst_addr;
2384 }
2385 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2386 pm_runtime_put_autosuspend(pl330->ddma.dev);
2387
2388
2389 if (!val)
2390 return 0;
2391
2392 return val - addr;
2393}
2394
2395static enum dma_status
2396pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2397 struct dma_tx_state *txstate)
2398{
2399 enum dma_status ret;
2400 unsigned long flags;
2401 struct dma_pl330_desc *desc, *running = NULL, *last_enq = NULL;
2402 struct dma_pl330_chan *pch = to_pchan(chan);
2403 unsigned int transferred, residual = 0;
2404
2405 ret = dma_cookie_status(chan, cookie, txstate);
2406
2407 if (!txstate)
2408 return ret;
2409
2410 if (ret == DMA_COMPLETE)
2411 goto out;
2412
2413 spin_lock_irqsave(&pch->lock, flags);
2414 spin_lock(&pch->thread->dmac->lock);
2415
2416 if (pch->thread->req_running != -1)
2417 running = pch->thread->req[pch->thread->req_running].desc;
2418
2419 last_enq = pch->thread->req[pch->thread->lstenq].desc;
2420
2421
2422 list_for_each_entry(desc, &pch->work_list, node) {
2423 if (desc->status == DONE)
2424 transferred = desc->bytes_requested;
2425 else if (running && desc == running)
2426 transferred =
2427 pl330_get_current_xferred_count(pch, desc);
2428 else if (desc->status == BUSY)
2429
2430
2431
2432
2433 if (desc == last_enq)
2434 transferred = 0;
2435 else
2436 transferred = desc->bytes_requested;
2437 else
2438 transferred = 0;
2439 residual += desc->bytes_requested - transferred;
2440 if (desc->txd.cookie == cookie) {
2441 switch (desc->status) {
2442 case DONE:
2443 ret = DMA_COMPLETE;
2444 break;
2445 case PREP:
2446 case BUSY:
2447 ret = DMA_IN_PROGRESS;
2448 break;
2449 default:
2450 WARN_ON(1);
2451 }
2452 break;
2453 }
2454 if (desc->last)
2455 residual = 0;
2456 }
2457 spin_unlock(&pch->thread->dmac->lock);
2458 spin_unlock_irqrestore(&pch->lock, flags);
2459
2460out:
2461 dma_set_residue(txstate, residual);
2462
2463 return ret;
2464}
2465
2466static void pl330_issue_pending(struct dma_chan *chan)
2467{
2468 struct dma_pl330_chan *pch = to_pchan(chan);
2469 unsigned long flags;
2470
2471 spin_lock_irqsave(&pch->lock, flags);
2472 if (list_empty(&pch->work_list)) {
2473
2474
2475
2476
2477
2478 WARN_ON(list_empty(&pch->submitted_list));
2479 pch->active = true;
2480 pm_runtime_get_sync(pch->dmac->ddma.dev);
2481 }
2482 list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2483 spin_unlock_irqrestore(&pch->lock, flags);
2484
2485 pl330_tasklet(&pch->task);
2486}
2487
2488
2489
2490
2491
2492
2493static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2494{
2495 struct dma_pl330_desc *desc, *last = to_desc(tx);
2496 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2497 dma_cookie_t cookie;
2498 unsigned long flags;
2499
2500 spin_lock_irqsave(&pch->lock, flags);
2501
2502
2503 while (!list_empty(&last->node)) {
2504 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
2505 if (pch->cyclic) {
2506 desc->txd.callback = last->txd.callback;
2507 desc->txd.callback_param = last->txd.callback_param;
2508 }
2509 desc->last = false;
2510
2511 dma_cookie_assign(&desc->txd);
2512
2513 list_move_tail(&desc->node, &pch->submitted_list);
2514 }
2515
2516 last->last = true;
2517 cookie = dma_cookie_assign(&last->txd);
2518 list_add_tail(&last->node, &pch->submitted_list);
2519 spin_unlock_irqrestore(&pch->lock, flags);
2520
2521 return cookie;
2522}
2523
2524static inline void _init_desc(struct dma_pl330_desc *desc)
2525{
2526 desc->rqcfg.swap = SWAP_NO;
2527 desc->rqcfg.scctl = CCTRL0;
2528 desc->rqcfg.dcctl = CCTRL0;
2529 desc->txd.tx_submit = pl330_tx_submit;
2530
2531 INIT_LIST_HEAD(&desc->node);
2532}
2533
2534
2535static int add_desc(struct list_head *pool, spinlock_t *lock,
2536 gfp_t flg, int count)
2537{
2538 struct dma_pl330_desc *desc;
2539 unsigned long flags;
2540 int i;
2541
2542 desc = kcalloc(count, sizeof(*desc), flg);
2543 if (!desc)
2544 return 0;
2545
2546 spin_lock_irqsave(lock, flags);
2547
2548 for (i = 0; i < count; i++) {
2549 _init_desc(&desc[i]);
2550 list_add_tail(&desc[i].node, pool);
2551 }
2552
2553 spin_unlock_irqrestore(lock, flags);
2554
2555 return count;
2556}
2557
2558static struct dma_pl330_desc *pluck_desc(struct list_head *pool,
2559 spinlock_t *lock)
2560{
2561 struct dma_pl330_desc *desc = NULL;
2562 unsigned long flags;
2563
2564 spin_lock_irqsave(lock, flags);
2565
2566 if (!list_empty(pool)) {
2567 desc = list_entry(pool->next,
2568 struct dma_pl330_desc, node);
2569
2570 list_del_init(&desc->node);
2571
2572 desc->status = PREP;
2573 desc->txd.callback = NULL;
2574 }
2575
2576 spin_unlock_irqrestore(lock, flags);
2577
2578 return desc;
2579}
2580
2581static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2582{
2583 struct pl330_dmac *pl330 = pch->dmac;
2584 u8 *peri_id = pch->chan.private;
2585 struct dma_pl330_desc *desc;
2586
2587
2588 desc = pluck_desc(&pl330->desc_pool, &pl330->pool_lock);
2589
2590
2591 if (!desc) {
2592 DEFINE_SPINLOCK(lock);
2593 LIST_HEAD(pool);
2594
2595 if (!add_desc(&pool, &lock, GFP_ATOMIC, 1))
2596 return NULL;
2597
2598 desc = pluck_desc(&pool, &lock);
2599 WARN_ON(!desc || !list_empty(&pool));
2600 }
2601
2602
2603 desc->pchan = pch;
2604 desc->txd.cookie = 0;
2605 async_tx_ack(&desc->txd);
2606
2607 desc->peri = peri_id ? pch->chan.chan_id : 0;
2608 desc->rqcfg.pcfg = &pch->dmac->pcfg;
2609
2610 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2611
2612 return desc;
2613}
2614
2615static inline void fill_px(struct pl330_xfer *px,
2616 dma_addr_t dst, dma_addr_t src, size_t len)
2617{
2618 px->bytes = len;
2619 px->dst_addr = dst;
2620 px->src_addr = src;
2621}
2622
2623static struct dma_pl330_desc *
2624__pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2625 dma_addr_t src, size_t len)
2626{
2627 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2628
2629 if (!desc) {
2630 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2631 __func__, __LINE__);
2632 return NULL;
2633 }
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645 fill_px(&desc->px, dst, src, len);
2646
2647 return desc;
2648}
2649
2650
2651static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2652{
2653 struct dma_pl330_chan *pch = desc->pchan;
2654 struct pl330_dmac *pl330 = pch->dmac;
2655 int burst_len;
2656
2657 burst_len = pl330->pcfg.data_bus_width / 8;
2658 burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan;
2659 burst_len >>= desc->rqcfg.brst_size;
2660
2661
2662 if (burst_len > PL330_MAX_BURST)
2663 burst_len = PL330_MAX_BURST;
2664
2665 return burst_len;
2666}
2667
2668static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2669 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
2670 size_t period_len, enum dma_transfer_direction direction,
2671 unsigned long flags)
2672{
2673 struct dma_pl330_desc *desc = NULL, *first = NULL;
2674 struct dma_pl330_chan *pch = to_pchan(chan);
2675 struct pl330_dmac *pl330 = pch->dmac;
2676 unsigned int i;
2677 dma_addr_t dst;
2678 dma_addr_t src;
2679
2680 if (len % period_len != 0)
2681 return NULL;
2682
2683 if (!is_slave_direction(direction)) {
2684 dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
2685 __func__, __LINE__);
2686 return NULL;
2687 }
2688
2689 pl330_config_write(chan, &pch->slave_config, direction);
2690
2691 if (!pl330_prep_slave_fifo(pch, direction))
2692 return NULL;
2693
2694 for (i = 0; i < len / period_len; i++) {
2695 desc = pl330_get_desc(pch);
2696 if (!desc) {
2697 unsigned long iflags;
2698
2699 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2700 __func__, __LINE__);
2701
2702 if (!first)
2703 return NULL;
2704
2705 spin_lock_irqsave(&pl330->pool_lock, iflags);
2706
2707 while (!list_empty(&first->node)) {
2708 desc = list_entry(first->node.next,
2709 struct dma_pl330_desc, node);
2710 list_move_tail(&desc->node, &pl330->desc_pool);
2711 }
2712
2713 list_move_tail(&first->node, &pl330->desc_pool);
2714
2715 spin_unlock_irqrestore(&pl330->pool_lock, iflags);
2716
2717 return NULL;
2718 }
2719
2720 switch (direction) {
2721 case DMA_MEM_TO_DEV:
2722 desc->rqcfg.src_inc = 1;
2723 desc->rqcfg.dst_inc = 0;
2724 src = dma_addr;
2725 dst = pch->fifo_dma;
2726 break;
2727 case DMA_DEV_TO_MEM:
2728 desc->rqcfg.src_inc = 0;
2729 desc->rqcfg.dst_inc = 1;
2730 src = pch->fifo_dma;
2731 dst = dma_addr;
2732 break;
2733 default:
2734 break;
2735 }
2736
2737 desc->rqtype = direction;
2738 desc->rqcfg.brst_size = pch->burst_sz;
2739 desc->rqcfg.brst_len = pch->burst_len;
2740 desc->bytes_requested = period_len;
2741 fill_px(&desc->px, dst, src, period_len);
2742
2743 if (!first)
2744 first = desc;
2745 else
2746 list_add_tail(&desc->node, &first->node);
2747
2748 dma_addr += period_len;
2749 }
2750
2751 if (!desc)
2752 return NULL;
2753
2754 pch->cyclic = true;
2755 desc->txd.flags = (enum dma_ctrl_flags) flags;
2756
2757 return &desc->txd;
2758}
2759
2760static struct dma_async_tx_descriptor *
2761pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2762 dma_addr_t src, size_t len, unsigned long flags)
2763{
2764 struct dma_pl330_desc *desc;
2765 struct dma_pl330_chan *pch = to_pchan(chan);
2766 struct pl330_dmac *pl330;
2767 int burst;
2768
2769 if (unlikely(!pch || !len))
2770 return NULL;
2771
2772 pl330 = pch->dmac;
2773
2774 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2775 if (!desc)
2776 return NULL;
2777
2778 desc->rqcfg.src_inc = 1;
2779 desc->rqcfg.dst_inc = 1;
2780 desc->rqtype = DMA_MEM_TO_MEM;
2781
2782
2783 burst = pl330->pcfg.data_bus_width / 8;
2784
2785
2786
2787
2788
2789
2790 while ((src | dst | len) & (burst - 1))
2791 burst /= 2;
2792
2793 desc->rqcfg.brst_size = 0;
2794 while (burst != (1 << desc->rqcfg.brst_size))
2795 desc->rqcfg.brst_size++;
2796
2797 desc->rqcfg.brst_len = get_burst_len(desc, len);
2798
2799
2800
2801
2802 if (burst * 8 < pl330->pcfg.data_bus_width)
2803 desc->rqcfg.brst_len = 1;
2804
2805 desc->bytes_requested = len;
2806
2807 desc->txd.flags = (enum dma_ctrl_flags) flags;
2808
2809 return &desc->txd;
2810}
2811
2812static void __pl330_giveback_desc(struct pl330_dmac *pl330,
2813 struct dma_pl330_desc *first)
2814{
2815 unsigned long flags;
2816 struct dma_pl330_desc *desc;
2817
2818 if (!first)
2819 return;
2820
2821 spin_lock_irqsave(&pl330->pool_lock, flags);
2822
2823 while (!list_empty(&first->node)) {
2824 desc = list_entry(first->node.next,
2825 struct dma_pl330_desc, node);
2826 list_move_tail(&desc->node, &pl330->desc_pool);
2827 }
2828
2829 list_move_tail(&first->node, &pl330->desc_pool);
2830
2831 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2832}
2833
2834static struct dma_async_tx_descriptor *
2835pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2836 unsigned int sg_len, enum dma_transfer_direction direction,
2837 unsigned long flg, void *context)
2838{
2839 struct dma_pl330_desc *first, *desc = NULL;
2840 struct dma_pl330_chan *pch = to_pchan(chan);
2841 struct scatterlist *sg;
2842 int i;
2843
2844 if (unlikely(!pch || !sgl || !sg_len))
2845 return NULL;
2846
2847 pl330_config_write(chan, &pch->slave_config, direction);
2848
2849 if (!pl330_prep_slave_fifo(pch, direction))
2850 return NULL;
2851
2852 first = NULL;
2853
2854 for_each_sg(sgl, sg, sg_len, i) {
2855
2856 desc = pl330_get_desc(pch);
2857 if (!desc) {
2858 struct pl330_dmac *pl330 = pch->dmac;
2859
2860 dev_err(pch->dmac->ddma.dev,
2861 "%s:%d Unable to fetch desc\n",
2862 __func__, __LINE__);
2863 __pl330_giveback_desc(pl330, first);
2864
2865 return NULL;
2866 }
2867
2868 if (!first)
2869 first = desc;
2870 else
2871 list_add_tail(&desc->node, &first->node);
2872
2873 if (direction == DMA_MEM_TO_DEV) {
2874 desc->rqcfg.src_inc = 1;
2875 desc->rqcfg.dst_inc = 0;
2876 fill_px(&desc->px, pch->fifo_dma, sg_dma_address(sg),
2877 sg_dma_len(sg));
2878 } else {
2879 desc->rqcfg.src_inc = 0;
2880 desc->rqcfg.dst_inc = 1;
2881 fill_px(&desc->px, sg_dma_address(sg), pch->fifo_dma,
2882 sg_dma_len(sg));
2883 }
2884
2885 desc->rqcfg.brst_size = pch->burst_sz;
2886 desc->rqcfg.brst_len = pch->burst_len;
2887 desc->rqtype = direction;
2888 desc->bytes_requested = sg_dma_len(sg);
2889 }
2890
2891
2892 desc->txd.flags = (enum dma_ctrl_flags) flg;
2893 return &desc->txd;
2894}
2895
2896static irqreturn_t pl330_irq_handler(int irq, void *data)
2897{
2898 if (pl330_update(data))
2899 return IRQ_HANDLED;
2900 else
2901 return IRQ_NONE;
2902}
2903
2904#define PL330_DMA_BUSWIDTHS \
2905 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2906 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2907 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2908 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2909 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2910
2911#ifdef CONFIG_DEBUG_FS
2912static int pl330_debugfs_show(struct seq_file *s, void *data)
2913{
2914 struct pl330_dmac *pl330 = s->private;
2915 int chans, pchs, ch, pr;
2916
2917 chans = pl330->pcfg.num_chan;
2918 pchs = pl330->num_peripherals;
2919
2920 seq_puts(s, "PL330 physical channels:\n");
2921 seq_puts(s, "THREAD:\t\tCHANNEL:\n");
2922 seq_puts(s, "--------\t-----\n");
2923 for (ch = 0; ch < chans; ch++) {
2924 struct pl330_thread *thrd = &pl330->channels[ch];
2925 int found = -1;
2926
2927 for (pr = 0; pr < pchs; pr++) {
2928 struct dma_pl330_chan *pch = &pl330->peripherals[pr];
2929
2930 if (!pch->thread || thrd->id != pch->thread->id)
2931 continue;
2932
2933 found = pr;
2934 }
2935
2936 seq_printf(s, "%d\t\t", thrd->id);
2937 if (found == -1)
2938 seq_puts(s, "--\n");
2939 else
2940 seq_printf(s, "%d\n", found);
2941 }
2942
2943 return 0;
2944}
2945
2946DEFINE_SHOW_ATTRIBUTE(pl330_debugfs);
2947
2948static inline void init_pl330_debugfs(struct pl330_dmac *pl330)
2949{
2950 debugfs_create_file(dev_name(pl330->ddma.dev),
2951 S_IFREG | 0444, NULL, pl330,
2952 &pl330_debugfs_fops);
2953}
2954#else
2955static inline void init_pl330_debugfs(struct pl330_dmac *pl330)
2956{
2957}
2958#endif
2959
2960
2961
2962
2963
2964
2965
2966static int __maybe_unused pl330_suspend(struct device *dev)
2967{
2968 struct amba_device *pcdev = to_amba_device(dev);
2969
2970 pm_runtime_force_suspend(dev);
2971 amba_pclk_unprepare(pcdev);
2972
2973 return 0;
2974}
2975
2976static int __maybe_unused pl330_resume(struct device *dev)
2977{
2978 struct amba_device *pcdev = to_amba_device(dev);
2979 int ret;
2980
2981 ret = amba_pclk_prepare(pcdev);
2982 if (ret)
2983 return ret;
2984
2985 pm_runtime_force_resume(dev);
2986
2987 return ret;
2988}
2989
2990static const struct dev_pm_ops pl330_pm = {
2991 SET_LATE_SYSTEM_SLEEP_PM_OPS(pl330_suspend, pl330_resume)
2992};
2993
2994static int
2995pl330_probe(struct amba_device *adev, const struct amba_id *id)
2996{
2997 struct pl330_config *pcfg;
2998 struct pl330_dmac *pl330;
2999 struct dma_pl330_chan *pch, *_p;
3000 struct dma_device *pd;
3001 struct resource *res;
3002 int i, ret, irq;
3003 int num_chan;
3004 struct device_node *np = adev->dev.of_node;
3005
3006 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
3007 if (ret)
3008 return ret;
3009
3010
3011 pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
3012 if (!pl330)
3013 return -ENOMEM;
3014
3015 pd = &pl330->ddma;
3016 pd->dev = &adev->dev;
3017
3018 pl330->mcbufsz = 0;
3019
3020
3021 for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
3022 if (of_property_read_bool(np, of_quirks[i].quirk))
3023 pl330->quirks |= of_quirks[i].id;
3024
3025 res = &adev->res;
3026 pl330->base = devm_ioremap_resource(&adev->dev, res);
3027 if (IS_ERR(pl330->base))
3028 return PTR_ERR(pl330->base);
3029
3030 amba_set_drvdata(adev, pl330);
3031
3032 pl330->rstc = devm_reset_control_get_optional(&adev->dev, "dma");
3033 if (IS_ERR(pl330->rstc)) {
3034 return dev_err_probe(&adev->dev, PTR_ERR(pl330->rstc), "Failed to get reset!\n");
3035 } else {
3036 ret = reset_control_deassert(pl330->rstc);
3037 if (ret) {
3038 dev_err(&adev->dev, "Couldn't deassert the device from reset!\n");
3039 return ret;
3040 }
3041 }
3042
3043 pl330->rstc_ocp = devm_reset_control_get_optional(&adev->dev, "dma-ocp");
3044 if (IS_ERR(pl330->rstc_ocp)) {
3045 return dev_err_probe(&adev->dev, PTR_ERR(pl330->rstc_ocp),
3046 "Failed to get OCP reset!\n");
3047 } else {
3048 ret = reset_control_deassert(pl330->rstc_ocp);
3049 if (ret) {
3050 dev_err(&adev->dev, "Couldn't deassert the device from OCP reset!\n");
3051 return ret;
3052 }
3053 }
3054
3055 for (i = 0; i < AMBA_NR_IRQS; i++) {
3056 irq = adev->irq[i];
3057 if (irq) {
3058 ret = devm_request_irq(&adev->dev, irq,
3059 pl330_irq_handler, 0,
3060 dev_name(&adev->dev), pl330);
3061 if (ret)
3062 return ret;
3063 } else {
3064 break;
3065 }
3066 }
3067
3068 pcfg = &pl330->pcfg;
3069
3070 pcfg->periph_id = adev->periphid;
3071 ret = pl330_add(pl330);
3072 if (ret)
3073 return ret;
3074
3075 INIT_LIST_HEAD(&pl330->desc_pool);
3076 spin_lock_init(&pl330->pool_lock);
3077
3078
3079 if (!add_desc(&pl330->desc_pool, &pl330->pool_lock,
3080 GFP_KERNEL, NR_DEFAULT_DESC))
3081 dev_warn(&adev->dev, "unable to allocate desc\n");
3082
3083 INIT_LIST_HEAD(&pd->channels);
3084
3085
3086 num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
3087
3088 pl330->num_peripherals = num_chan;
3089
3090 pl330->peripherals = kcalloc(num_chan, sizeof(*pch), GFP_KERNEL);
3091 if (!pl330->peripherals) {
3092 ret = -ENOMEM;
3093 goto probe_err2;
3094 }
3095
3096 for (i = 0; i < num_chan; i++) {
3097 pch = &pl330->peripherals[i];
3098
3099 pch->chan.private = adev->dev.of_node;
3100 INIT_LIST_HEAD(&pch->submitted_list);
3101 INIT_LIST_HEAD(&pch->work_list);
3102 INIT_LIST_HEAD(&pch->completed_list);
3103 spin_lock_init(&pch->lock);
3104 pch->thread = NULL;
3105 pch->chan.device = pd;
3106 pch->dmac = pl330;
3107 pch->dir = DMA_NONE;
3108
3109
3110 list_add_tail(&pch->chan.device_node, &pd->channels);
3111 }
3112
3113 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
3114 if (pcfg->num_peri) {
3115 dma_cap_set(DMA_SLAVE, pd->cap_mask);
3116 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
3117 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
3118 }
3119
3120 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
3121 pd->device_free_chan_resources = pl330_free_chan_resources;
3122 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
3123 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
3124 pd->device_tx_status = pl330_tx_status;
3125 pd->device_prep_slave_sg = pl330_prep_slave_sg;
3126 pd->device_config = pl330_config;
3127 pd->device_pause = pl330_pause;
3128 pd->device_terminate_all = pl330_terminate_all;
3129 pd->device_issue_pending = pl330_issue_pending;
3130 pd->src_addr_widths = PL330_DMA_BUSWIDTHS;
3131 pd->dst_addr_widths = PL330_DMA_BUSWIDTHS;
3132 pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
3133 pd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
3134 pd->max_burst = PL330_MAX_BURST;
3135
3136 ret = dma_async_device_register(pd);
3137 if (ret) {
3138 dev_err(&adev->dev, "unable to register DMAC\n");
3139 goto probe_err3;
3140 }
3141
3142 if (adev->dev.of_node) {
3143 ret = of_dma_controller_register(adev->dev.of_node,
3144 of_dma_pl330_xlate, pl330);
3145 if (ret) {
3146 dev_err(&adev->dev,
3147 "unable to register DMA to the generic DT DMA helpers\n");
3148 }
3149 }
3150
3151
3152
3153
3154
3155 ret = dma_set_max_seg_size(&adev->dev, 1900800);
3156 if (ret)
3157 dev_err(&adev->dev, "unable to set the seg size\n");
3158
3159
3160 init_pl330_debugfs(pl330);
3161 dev_info(&adev->dev,
3162 "Loaded driver for PL330 DMAC-%x\n", adev->periphid);
3163 dev_info(&adev->dev,
3164 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
3165 pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
3166 pcfg->num_peri, pcfg->num_events);
3167
3168 pm_runtime_irq_safe(&adev->dev);
3169 pm_runtime_use_autosuspend(&adev->dev);
3170 pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
3171 pm_runtime_mark_last_busy(&adev->dev);
3172 pm_runtime_put_autosuspend(&adev->dev);
3173
3174 return 0;
3175probe_err3:
3176
3177 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3178 chan.device_node) {
3179
3180
3181 list_del(&pch->chan.device_node);
3182
3183
3184 if (pch->thread) {
3185 pl330_terminate_all(&pch->chan);
3186 pl330_free_chan_resources(&pch->chan);
3187 }
3188 }
3189probe_err2:
3190 pl330_del(pl330);
3191
3192 if (pl330->rstc_ocp)
3193 reset_control_assert(pl330->rstc_ocp);
3194
3195 if (pl330->rstc)
3196 reset_control_assert(pl330->rstc);
3197 return ret;
3198}
3199
3200static int pl330_remove(struct amba_device *adev)
3201{
3202 struct pl330_dmac *pl330 = amba_get_drvdata(adev);
3203 struct dma_pl330_chan *pch, *_p;
3204 int i, irq;
3205
3206 pm_runtime_get_noresume(pl330->ddma.dev);
3207
3208 if (adev->dev.of_node)
3209 of_dma_controller_free(adev->dev.of_node);
3210
3211 for (i = 0; i < AMBA_NR_IRQS; i++) {
3212 irq = adev->irq[i];
3213 if (irq)
3214 devm_free_irq(&adev->dev, irq, pl330);
3215 }
3216
3217 dma_async_device_unregister(&pl330->ddma);
3218
3219
3220 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3221 chan.device_node) {
3222
3223
3224 list_del(&pch->chan.device_node);
3225
3226
3227 if (pch->thread) {
3228 pl330_terminate_all(&pch->chan);
3229 pl330_free_chan_resources(&pch->chan);
3230 }
3231 }
3232
3233 pl330_del(pl330);
3234
3235 if (pl330->rstc_ocp)
3236 reset_control_assert(pl330->rstc_ocp);
3237
3238 if (pl330->rstc)
3239 reset_control_assert(pl330->rstc);
3240 return 0;
3241}
3242
3243static const struct amba_id pl330_ids[] = {
3244 {
3245 .id = 0x00041330,
3246 .mask = 0x000fffff,
3247 },
3248 { 0, 0 },
3249};
3250
3251MODULE_DEVICE_TABLE(amba, pl330_ids);
3252
3253static struct amba_driver pl330_driver = {
3254 .drv = {
3255 .owner = THIS_MODULE,
3256 .name = "dma-pl330",
3257 .pm = &pl330_pm,
3258 },
3259 .id_table = pl330_ids,
3260 .probe = pl330_probe,
3261 .remove = pl330_remove,
3262};
3263
3264module_amba_driver(pl330_driver);
3265
3266MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
3267MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3268MODULE_LICENSE("GPL");
3269