LXR linux/drivers/gpu/drm/i915/display/intel_dpll

   1/*
   2 * Copyright © 2012-2016 Intel Corporation
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21 * IN THE SOFTWARE.
  22 *
  23 */
  24
  25#ifndef _INTEL_DPLL_MGR_H_
  26#define _INTEL_DPLL_MGR_H_
  27
  28#include <linux/types.h>
  29
  30#include "intel_display.h"
  31#include "intel_wakeref.h"
  32
  33/*FIXME: Move this to a more appropriate place. */
  34#define abs_diff(a, b) ({                       \
  35        typeof(a) __a = (a);                    \
  36        typeof(b) __b = (b);                    \
  37        (void) (&__a == &__b);                  \
  38        __a > __b ? (__a - __b) : (__b - __a); })
  39
  40struct drm_device;
  41struct drm_i915_private;
  42struct intel_atomic_state;
  43struct intel_crtc;
  44struct intel_crtc_state;
  45struct intel_encoder;
  46struct intel_shared_dpll;
  47
  48/**
  49 * enum intel_dpll_id - possible DPLL ids
  50 *
  51 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.
  52 */
  53enum intel_dpll_id {
  54        /**
  55         * @DPLL_ID_PRIVATE: non-shared dpll in use
  56         */
  57        DPLL_ID_PRIVATE = -1,
  58
  59        /**
  60         * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB
  61         */
  62        DPLL_ID_PCH_PLL_A = 0,
  63        /**
  64         * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB
  65         */
  66        DPLL_ID_PCH_PLL_B = 1,
  67
  68
  69        /**
  70         * @DPLL_ID_WRPLL1: HSW and BDW WRPLL1
  71         */
  72        DPLL_ID_WRPLL1 = 0,
  73        /**
  74         * @DPLL_ID_WRPLL2: HSW and BDW WRPLL2
  75         */
  76        DPLL_ID_WRPLL2 = 1,
  77        /**
  78         * @DPLL_ID_SPLL: HSW and BDW SPLL
  79         */
  80        DPLL_ID_SPLL = 2,
  81        /**
  82         * @DPLL_ID_LCPLL_810: HSW and BDW 0.81 GHz LCPLL
  83         */
  84        DPLL_ID_LCPLL_810 = 3,
  85        /**
  86         * @DPLL_ID_LCPLL_1350: HSW and BDW 1.35 GHz LCPLL
  87         */
  88        DPLL_ID_LCPLL_1350 = 4,
  89        /**
  90         * @DPLL_ID_LCPLL_2700: HSW and BDW 2.7 GHz LCPLL
  91         */
  92        DPLL_ID_LCPLL_2700 = 5,
  93
  94
  95        /**
  96         * @DPLL_ID_SKL_DPLL0: SKL and later DPLL0
  97         */
  98        DPLL_ID_SKL_DPLL0 = 0,
  99        /**
 100         * @DPLL_ID_SKL_DPLL1: SKL and later DPLL1
 101         */
 102        DPLL_ID_SKL_DPLL1 = 1,
 103        /**
 104         * @DPLL_ID_SKL_DPLL2: SKL and later DPLL2
 105         */
 106        DPLL_ID_SKL_DPLL2 = 2,
 107        /**
 108         * @DPLL_ID_SKL_DPLL3: SKL and later DPLL3
 109         */
 110        DPLL_ID_SKL_DPLL3 = 3,
 111
 112
 113        /**
 114         * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0
 115         */
 116        DPLL_ID_ICL_DPLL0 = 0,
 117        /**
 118         * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1
 119         */
 120        DPLL_ID_ICL_DPLL1 = 1,
 121        /**
 122         * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4
 123         */
 124        DPLL_ID_EHL_DPLL4 = 2,
 125        /**
 126         * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL
 127         */
 128        DPLL_ID_ICL_TBTPLL = 2,
 129        /**
 130         * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C),
 131         *                      TGL TC PLL 1 port 1 (TC1)
 132         */
 133        DPLL_ID_ICL_MGPLL1 = 3,
 134        /**
 135         * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
 136         *                      TGL TC PLL 1 port 2 (TC2)
 137         */
 138        DPLL_ID_ICL_MGPLL2 = 4,
 139        /**
 140         * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
 141         *                      TGL TC PLL 1 port 3 (TC3)
 142         */
 143        DPLL_ID_ICL_MGPLL3 = 5,
 144        /**
 145         * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
 146         *                      TGL TC PLL 1 port 4 (TC4)
 147         */
 148        DPLL_ID_ICL_MGPLL4 = 6,
 149        /**
 150         * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5)
 151         */
 152        DPLL_ID_TGL_MGPLL5 = 7,
 153        /**
 154         * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
 155         */
 156        DPLL_ID_TGL_MGPLL6 = 8,
 157};
 158
 159#define I915_NUM_PLLS 9
 160
 161enum icl_port_dpll_id {
 162        ICL_PORT_DPLL_DEFAULT,
 163        ICL_PORT_DPLL_MG_PHY,
 164
 165        ICL_PORT_DPLL_COUNT,
 166};
 167
 168struct intel_dpll_hw_state {
 169        /* i9xx, pch plls */
 170        u32 dpll;
 171        u32 dpll_md;
 172        u32 fp0;
 173        u32 fp1;
 174
 175        /* hsw, bdw */
 176        u32 wrpll;
 177        u32 spll;
 178
 179        /* skl */
 180        /*
 181         * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
 182         * lower part of ctrl1 and they get shifted into position when writing
 183         * the register.  This allows us to easily compare the state to share
 184         * the DPLL.
 185         */
 186        u32 ctrl1;
 187        /* HDMI only, 0 when used for DP */
 188        u32 cfgcr1, cfgcr2;
 189
 190        /* cnl */
 191        u32 cfgcr0;
 192        /* CNL also uses cfgcr1 */
 193
 194        /* bxt */
 195        u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;
 196
 197        /*
 198         * ICL uses the following, already defined:
 199         * u32 cfgcr0, cfgcr1;
 200         */
 201        u32 mg_refclkin_ctl;
 202        u32 mg_clktop2_coreclkctl1;
 203        u32 mg_clktop2_hsclkctl;
 204        u32 mg_pll_div0;
 205        u32 mg_pll_div1;
 206        u32 mg_pll_lf;
 207        u32 mg_pll_frac_lock;
 208        u32 mg_pll_ssc;
 209        u32 mg_pll_bias;
 210        u32 mg_pll_tdc_coldst_bias;
 211        u32 mg_pll_bias_mask;
 212        u32 mg_pll_tdc_coldst_bias_mask;
 213};
 214
 215/**
 216 * struct intel_shared_dpll_state - hold the DPLL atomic state
 217 *
 218 * This structure holds an atomic state for the DPLL, that can represent
 219 * either its current state (in struct &intel_shared_dpll) or a desired
 220 * future state which would be applied by an atomic mode set (stored in
 221 * a struct &intel_atomic_state).
 222 *
 223 * See also intel_reserve_shared_dplls() and intel_release_shared_dplls().
 224 */
 225struct intel_shared_dpll_state {
 226        /**
 227         * @crtc_mask: mask of CRTC using this DPLL, active or not
 228         */
 229        unsigned crtc_mask;
 230
 231        /**
 232         * @hw_state: hardware configuration for the DPLL stored in
 233         * struct &intel_dpll_hw_state.
 234         */
 235        struct intel_dpll_hw_state hw_state;
 236};
 237
 238/**
 239 * struct intel_shared_dpll_funcs - platform specific hooks for managing DPLLs
 240 */
 241struct intel_shared_dpll_funcs {
 242        /**
 243         * @prepare:
 244         *
 245         * Optional hook to perform operations prior to enabling the PLL.
 246         * Called from intel_prepare_shared_dpll() function unless the PLL
 247         * is already enabled.
 248         */
 249        void (*prepare)(struct drm_i915_private *dev_priv,
 250                        struct intel_shared_dpll *pll);
 251
 252        /**
 253         * @enable:
 254         *
 255         * Hook for enabling the pll, called from intel_enable_shared_dpll()
 256         * if the pll is not already enabled.
 257         */
 258        void (*enable)(struct drm_i915_private *dev_priv,
 259                       struct intel_shared_dpll *pll);
 260
 261        /**
 262         * @disable:
 263         *
 264         * Hook for disabling the pll, called from intel_disable_shared_dpll()
 265         * only when it is safe to disable the pll, i.e., there are no more
 266         * tracked users for it.
 267         */
 268        void (*disable)(struct drm_i915_private *dev_priv,
 269                        struct intel_shared_dpll *pll);
 270
 271        /**
 272         * @get_hw_state:
 273         *
 274         * Hook for reading the values currently programmed to the DPLL
 275         * registers. This is used for initial hw state readout and state
 276         * verification after a mode set.
 277         */
 278        bool (*get_hw_state)(struct drm_i915_private *dev_priv,
 279                             struct intel_shared_dpll *pll,
 280                             struct intel_dpll_hw_state *hw_state);
 281
 282        /**
 283         * @get_freq:
 284         *
 285         * Hook for calculating the pll's output frequency based on its
 286         * current state.
 287         */
 288        int (*get_freq)(struct drm_i915_private *i915,
 289                        const struct intel_shared_dpll *pll);
 290};
 291
 292/**
 293 * struct dpll_info - display PLL platform specific info
 294 */
 295struct dpll_info {
 296        /**
 297         * @name: DPLL name; used for logging
 298         */
 299        const char *name;
 300
 301        /**
 302         * @funcs: platform specific hooks
 303         */
 304        const struct intel_shared_dpll_funcs *funcs;
 305
 306        /**
 307         * @id: unique indentifier for this DPLL; should match the index in the
 308         * dev_priv->shared_dplls array
 309         */
 310        enum intel_dpll_id id;
 311
 312#define INTEL_DPLL_ALWAYS_ON    (1 << 0)
 313        /**
 314         * @flags:
 315         *
 316         * INTEL_DPLL_ALWAYS_ON
 317         *     Inform the state checker that the DPLL is kept enabled even if
 318         *     not in use by any CRTC.
 319         */
 320        u32 flags;
 321};
 322
 323/**
 324 * struct intel_shared_dpll - display PLL with tracked state and users
 325 */
 326struct intel_shared_dpll {
 327        /**
 328         * @state:
 329         *
 330         * Store the state for the pll, including its hw state
 331         * and CRTCs using it.
 332         */
 333        struct intel_shared_dpll_state state;
 334
 335        /**
 336         * @active_mask: mask of active CRTCs (i.e. DPMS on) using this DPLL
 337         */
 338        unsigned active_mask;
 339
 340        /**
 341         * @on: is the PLL actually active? Disabled during modeset
 342         */
 343        bool on;
 344
 345        /**
 346         * @info: platform specific info
 347         */
 348        const struct dpll_info *info;
 349
 350        /**
 351         * @wakeref: In some platforms a device-level runtime pm reference may
 352         * need to be grabbed to disable DC states while this DPLL is enabled
 353         */
 354        intel_wakeref_t wakeref;
 355};
 356
 357#define SKL_DPLL0 0
 358#define SKL_DPLL1 1
 359#define SKL_DPLL2 2
 360#define SKL_DPLL3 3
 361
 362/* shared dpll functions */
 363struct intel_shared_dpll *
 364intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
 365                            enum intel_dpll_id id);
 366enum intel_dpll_id
 367intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
 368                         struct intel_shared_dpll *pll);
 369void assert_shared_dpll(struct drm_i915_private *dev_priv,
 370                        struct intel_shared_dpll *pll,
 371                        bool state);
 372#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 373#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 374bool intel_reserve_shared_dplls(struct intel_atomic_state *state,
 375                                struct intel_crtc *crtc,
 376                                struct intel_encoder *encoder);
 377void intel_release_shared_dplls(struct intel_atomic_state *state,
 378                                struct intel_crtc *crtc);
 379void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
 380                              enum icl_port_dpll_id port_dpll_id);
 381void intel_update_active_dpll(struct intel_atomic_state *state,
 382                              struct intel_crtc *crtc,
 383                              struct intel_encoder *encoder);
 384int intel_dpll_get_freq(struct drm_i915_private *i915,
 385                        const struct intel_shared_dpll *pll);
 386void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state);
 387void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
 388void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
 389void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
 390void intel_shared_dpll_init(struct drm_device *dev);
 391void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv);
 392void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv);
 393
 394void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
 395                              const struct intel_dpll_hw_state *hw_state);
 396enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
 397bool intel_dpll_is_combophy(enum intel_dpll_id id);
 398
 399#endif /* _INTEL_DPLL_MGR_H_ */
 400