linux/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
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   1/*
   2 * Copyright © 2014 Intel Corporation
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21 * DEALINGS IN THE SOFTWARE.
  22 *
  23 * Author: Shobhit Kumar <shobhit.kumar@intel.com>
  24 *
  25 */
  26
  27#include <linux/gpio/consumer.h>
  28#include <linux/gpio/machine.h>
  29#include <linux/mfd/intel_soc_pmic.h>
  30#include <linux/pinctrl/consumer.h>
  31#include <linux/pinctrl/machine.h>
  32#include <linux/slab.h>
  33
  34#include <asm/intel-mid.h>
  35#include <asm/unaligned.h>
  36
  37#include <drm/drm_crtc.h>
  38#include <drm/drm_edid.h>
  39
  40#include <video/mipi_display.h>
  41
  42#include "i915_drv.h"
  43#include "intel_display_types.h"
  44#include "intel_dsi.h"
  45#include "intel_sideband.h"
  46
  47#define MIPI_TRANSFER_MODE_SHIFT        0
  48#define MIPI_VIRTUAL_CHANNEL_SHIFT      1
  49#define MIPI_PORT_SHIFT                 3
  50
  51/* base offsets for gpio pads */
  52#define VLV_GPIO_NC_0_HV_DDI0_HPD       0x4130
  53#define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA   0x4120
  54#define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL   0x4110
  55#define VLV_GPIO_NC_3_PANEL0_VDDEN      0x4140
  56#define VLV_GPIO_NC_4_PANEL0_BKLTEN     0x4150
  57#define VLV_GPIO_NC_5_PANEL0_BKLTCTL    0x4160
  58#define VLV_GPIO_NC_6_HV_DDI1_HPD       0x4180
  59#define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA   0x4190
  60#define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL   0x4170
  61#define VLV_GPIO_NC_9_PANEL1_VDDEN      0x4100
  62#define VLV_GPIO_NC_10_PANEL1_BKLTEN    0x40E0
  63#define VLV_GPIO_NC_11_PANEL1_BKLTCTL   0x40F0
  64
  65#define VLV_GPIO_PCONF0(base_offset)    (base_offset)
  66#define VLV_GPIO_PAD_VAL(base_offset)   ((base_offset) + 8)
  67
  68struct gpio_map {
  69        u16 base_offset;
  70        bool init;
  71};
  72
  73static struct gpio_map vlv_gpio_table[] = {
  74        { VLV_GPIO_NC_0_HV_DDI0_HPD },
  75        { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA },
  76        { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL },
  77        { VLV_GPIO_NC_3_PANEL0_VDDEN },
  78        { VLV_GPIO_NC_4_PANEL0_BKLTEN },
  79        { VLV_GPIO_NC_5_PANEL0_BKLTCTL },
  80        { VLV_GPIO_NC_6_HV_DDI1_HPD },
  81        { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA },
  82        { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL },
  83        { VLV_GPIO_NC_9_PANEL1_VDDEN },
  84        { VLV_GPIO_NC_10_PANEL1_BKLTEN },
  85        { VLV_GPIO_NC_11_PANEL1_BKLTCTL },
  86};
  87
  88struct i2c_adapter_lookup {
  89        u16 slave_addr;
  90        struct intel_dsi *intel_dsi;
  91        acpi_handle dev_handle;
  92};
  93
  94#define CHV_GPIO_IDX_START_N            0
  95#define CHV_GPIO_IDX_START_E            73
  96#define CHV_GPIO_IDX_START_SW           100
  97#define CHV_GPIO_IDX_START_SE           198
  98
  99#define CHV_VBT_MAX_PINS_PER_FMLY       15
 100
 101#define CHV_GPIO_PAD_CFG0(f, i)         (0x4400 + (f) * 0x400 + (i) * 8)
 102#define  CHV_GPIO_GPIOEN                (1 << 15)
 103#define  CHV_GPIO_GPIOCFG_GPIO          (0 << 8)
 104#define  CHV_GPIO_GPIOCFG_GPO           (1 << 8)
 105#define  CHV_GPIO_GPIOCFG_GPI           (2 << 8)
 106#define  CHV_GPIO_GPIOCFG_HIZ           (3 << 8)
 107#define  CHV_GPIO_GPIOTXSTATE(state)    ((!!(state)) << 1)
 108
 109#define CHV_GPIO_PAD_CFG1(f, i)         (0x4400 + (f) * 0x400 + (i) * 8 + 4)
 110#define  CHV_GPIO_CFGLOCK               (1 << 31)
 111
 112/* ICL DSI Display GPIO Pins */
 113#define  ICL_GPIO_DDSP_HPD_A            0
 114#define  ICL_GPIO_L_VDDEN_1             1
 115#define  ICL_GPIO_L_BKLTEN_1            2
 116#define  ICL_GPIO_DDPA_CTRLCLK_1        3
 117#define  ICL_GPIO_DDPA_CTRLDATA_1       4
 118#define  ICL_GPIO_DDSP_HPD_B            5
 119#define  ICL_GPIO_L_VDDEN_2             6
 120#define  ICL_GPIO_L_BKLTEN_2            7
 121#define  ICL_GPIO_DDPA_CTRLCLK_2        8
 122#define  ICL_GPIO_DDPA_CTRLDATA_2       9
 123
 124static enum port intel_dsi_seq_port_to_port(u8 port)
 125{
 126        return port ? PORT_C : PORT_A;
 127}
 128
 129static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
 130                                       const u8 *data)
 131{
 132        struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
 133        struct mipi_dsi_device *dsi_device;
 134        u8 type, flags, seq_port;
 135        u16 len;
 136        enum port port;
 137
 138        drm_dbg_kms(&dev_priv->drm, "\n");
 139
 140        flags = *data++;
 141        type = *data++;
 142
 143        len = *((u16 *) data);
 144        data += 2;
 145
 146        seq_port = (flags >> MIPI_PORT_SHIFT) & 3;
 147
 148        /* For DSI single link on Port A & C, the seq_port value which is
 149         * parsed from Sequence Block#53 of VBT has been set to 0
 150         * Now, read/write of packets for the DSI single link on Port A and
 151         * Port C will based on the DVO port from VBT block 2.
 152         */
 153        if (intel_dsi->ports == (1 << PORT_C))
 154                port = PORT_C;
 155        else
 156                port = intel_dsi_seq_port_to_port(seq_port);
 157
 158        dsi_device = intel_dsi->dsi_hosts[port]->device;
 159        if (!dsi_device) {
 160                drm_dbg_kms(&dev_priv->drm, "no dsi device for port %c\n",
 161                            port_name(port));
 162                goto out;
 163        }
 164
 165        if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1)
 166                dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM;
 167        else
 168                dsi_device->mode_flags |= MIPI_DSI_MODE_LPM;
 169
 170        dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3;
 171
 172        switch (type) {
 173        case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
 174                mipi_dsi_generic_write(dsi_device, NULL, 0);
 175                break;
 176        case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
 177                mipi_dsi_generic_write(dsi_device, data, 1);
 178                break;
 179        case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
 180                mipi_dsi_generic_write(dsi_device, data, 2);
 181                break;
 182        case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
 183        case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
 184        case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
 185                drm_dbg(&dev_priv->drm,
 186                        "Generic Read not yet implemented or used\n");
 187                break;
 188        case MIPI_DSI_GENERIC_LONG_WRITE:
 189                mipi_dsi_generic_write(dsi_device, data, len);
 190                break;
 191        case MIPI_DSI_DCS_SHORT_WRITE:
 192                mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
 193                break;
 194        case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
 195                mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
 196                break;
 197        case MIPI_DSI_DCS_READ:
 198                drm_dbg(&dev_priv->drm,
 199                        "DCS Read not yet implemented or used\n");
 200                break;
 201        case MIPI_DSI_DCS_LONG_WRITE:
 202                mipi_dsi_dcs_write_buffer(dsi_device, data, len);
 203                break;
 204        }
 205
 206        if (INTEL_GEN(dev_priv) < 11)
 207                vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
 208
 209out:
 210        data += len;
 211
 212        return data;
 213}
 214
 215static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
 216{
 217        struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
 218        u32 delay = *((const u32 *) data);
 219
 220        drm_dbg_kms(&i915->drm, "\n");
 221
 222        usleep_range(delay, delay + 10);
 223        data += 4;
 224
 225        return data;
 226}
 227
 228static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
 229                          u8 gpio_source, u8 gpio_index, bool value)
 230{
 231        struct gpio_map *map;
 232        u16 pconf0, padval;
 233        u32 tmp;
 234        u8 port;
 235
 236        if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) {
 237                drm_dbg_kms(&dev_priv->drm, "unknown gpio index %u\n",
 238                            gpio_index);
 239                return;
 240        }
 241
 242        map = &vlv_gpio_table[gpio_index];
 243
 244        if (dev_priv->vbt.dsi.seq_version >= 3) {
 245                /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
 246                port = IOSF_PORT_GPIO_NC;
 247        } else {
 248                if (gpio_source == 0) {
 249                        port = IOSF_PORT_GPIO_NC;
 250                } else if (gpio_source == 1) {
 251                        drm_dbg_kms(&dev_priv->drm, "SC gpio not supported\n");
 252                        return;
 253                } else {
 254                        drm_dbg_kms(&dev_priv->drm,
 255                                    "unknown gpio source %u\n", gpio_source);
 256                        return;
 257                }
 258        }
 259
 260        pconf0 = VLV_GPIO_PCONF0(map->base_offset);
 261        padval = VLV_GPIO_PAD_VAL(map->base_offset);
 262
 263        vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO));
 264        if (!map->init) {
 265                /* FIXME: remove constant below */
 266                vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00);
 267                map->init = true;
 268        }
 269
 270        tmp = 0x4 | value;
 271        vlv_iosf_sb_write(dev_priv, port, padval, tmp);
 272        vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
 273}
 274
 275static void chv_exec_gpio(struct drm_i915_private *dev_priv,
 276                          u8 gpio_source, u8 gpio_index, bool value)
 277{
 278        u16 cfg0, cfg1;
 279        u16 family_num;
 280        u8 port;
 281
 282        if (dev_priv->vbt.dsi.seq_version >= 3) {
 283                if (gpio_index >= CHV_GPIO_IDX_START_SE) {
 284                        /* XXX: it's unclear whether 255->57 is part of SE. */
 285                        gpio_index -= CHV_GPIO_IDX_START_SE;
 286                        port = CHV_IOSF_PORT_GPIO_SE;
 287                } else if (gpio_index >= CHV_GPIO_IDX_START_SW) {
 288                        gpio_index -= CHV_GPIO_IDX_START_SW;
 289                        port = CHV_IOSF_PORT_GPIO_SW;
 290                } else if (gpio_index >= CHV_GPIO_IDX_START_E) {
 291                        gpio_index -= CHV_GPIO_IDX_START_E;
 292                        port = CHV_IOSF_PORT_GPIO_E;
 293                } else {
 294                        port = CHV_IOSF_PORT_GPIO_N;
 295                }
 296        } else {
 297                /* XXX: The spec is unclear about CHV GPIO on seq v2 */
 298                if (gpio_source != 0) {
 299                        drm_dbg_kms(&dev_priv->drm,
 300                                    "unknown gpio source %u\n", gpio_source);
 301                        return;
 302                }
 303
 304                if (gpio_index >= CHV_GPIO_IDX_START_E) {
 305                        drm_dbg_kms(&dev_priv->drm,
 306                                    "invalid gpio index %u for GPIO N\n",
 307                                    gpio_index);
 308                        return;
 309                }
 310
 311                port = CHV_IOSF_PORT_GPIO_N;
 312        }
 313
 314        family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY;
 315        gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY;
 316
 317        cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index);
 318        cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index);
 319
 320        vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO));
 321        vlv_iosf_sb_write(dev_priv, port, cfg1, 0);
 322        vlv_iosf_sb_write(dev_priv, port, cfg0,
 323                          CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO |
 324                          CHV_GPIO_GPIOTXSTATE(value));
 325        vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
 326}
 327
 328static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
 329                          u8 gpio_source, u8 gpio_index, bool value)
 330{
 331        /* XXX: this table is a quick ugly hack. */
 332        static struct gpio_desc *bxt_gpio_table[U8_MAX + 1];
 333        struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index];
 334
 335        if (!gpio_desc) {
 336                gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev,
 337                                                 NULL, gpio_index,
 338                                                 value ? GPIOD_OUT_LOW :
 339                                                 GPIOD_OUT_HIGH);
 340
 341                if (IS_ERR_OR_NULL(gpio_desc)) {
 342                        drm_err(&dev_priv->drm,
 343                                "GPIO index %u request failed (%ld)\n",
 344                                gpio_index, PTR_ERR(gpio_desc));
 345                        return;
 346                }
 347
 348                bxt_gpio_table[gpio_index] = gpio_desc;
 349        }
 350
 351        gpiod_set_value(gpio_desc, value);
 352}
 353
 354static void icl_exec_gpio(struct drm_i915_private *dev_priv,
 355                          u8 gpio_source, u8 gpio_index, bool value)
 356{
 357        drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n");
 358}
 359
 360static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 361{
 362        struct drm_device *dev = intel_dsi->base.base.dev;
 363        struct drm_i915_private *dev_priv = to_i915(dev);
 364        u8 gpio_source, gpio_index = 0, gpio_number;
 365        bool value;
 366
 367        drm_dbg_kms(&dev_priv->drm, "\n");
 368
 369        if (dev_priv->vbt.dsi.seq_version >= 3)
 370                gpio_index = *data++;
 371
 372        gpio_number = *data++;
 373
 374        /* gpio source in sequence v2 only */
 375        if (dev_priv->vbt.dsi.seq_version == 2)
 376                gpio_source = (*data >> 1) & 3;
 377        else
 378                gpio_source = 0;
 379
 380        /* pull up/down */
 381        value = *data++ & 1;
 382
 383        if (INTEL_GEN(dev_priv) >= 11)
 384                icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
 385        else if (IS_VALLEYVIEW(dev_priv))
 386                vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
 387        else if (IS_CHERRYVIEW(dev_priv))
 388                chv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
 389        else
 390                bxt_exec_gpio(dev_priv, gpio_source, gpio_index, value);
 391
 392        return data;
 393}
 394
 395#ifdef CONFIG_ACPI
 396static int i2c_adapter_lookup(struct acpi_resource *ares, void *data)
 397{
 398        struct i2c_adapter_lookup *lookup = data;
 399        struct intel_dsi *intel_dsi = lookup->intel_dsi;
 400        struct acpi_resource_i2c_serialbus *sb;
 401        struct i2c_adapter *adapter;
 402        acpi_handle adapter_handle;
 403        acpi_status status;
 404
 405        if (!i2c_acpi_get_i2c_resource(ares, &sb))
 406                return 1;
 407
 408        if (lookup->slave_addr != sb->slave_address)
 409                return 1;
 410
 411        status = acpi_get_handle(lookup->dev_handle,
 412                                 sb->resource_source.string_ptr,
 413                                 &adapter_handle);
 414        if (ACPI_FAILURE(status))
 415                return 1;
 416
 417        adapter = i2c_acpi_find_adapter_by_handle(adapter_handle);
 418        if (adapter)
 419                intel_dsi->i2c_bus_num = adapter->nr;
 420
 421        return 1;
 422}
 423
 424static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
 425                                  const u16 slave_addr)
 426{
 427        struct drm_device *drm_dev = intel_dsi->base.base.dev;
 428        struct device *dev = &drm_dev->pdev->dev;
 429        struct acpi_device *acpi_dev;
 430        struct list_head resource_list;
 431        struct i2c_adapter_lookup lookup;
 432
 433        acpi_dev = ACPI_COMPANION(dev);
 434        if (acpi_dev) {
 435                memset(&lookup, 0, sizeof(lookup));
 436                lookup.slave_addr = slave_addr;
 437                lookup.intel_dsi = intel_dsi;
 438                lookup.dev_handle = acpi_device_handle(acpi_dev);
 439
 440                INIT_LIST_HEAD(&resource_list);
 441                acpi_dev_get_resources(acpi_dev, &resource_list,
 442                                       i2c_adapter_lookup,
 443                                       &lookup);
 444                acpi_dev_free_resource_list(&resource_list);
 445        }
 446}
 447#else
 448static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
 449                                         const u16 slave_addr)
 450{
 451}
 452#endif
 453
 454static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
 455{
 456        struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
 457        struct i2c_adapter *adapter;
 458        struct i2c_msg msg;
 459        int ret;
 460        u8 vbt_i2c_bus_num = *(data + 2);
 461        u16 slave_addr = *(u16 *)(data + 3);
 462        u8 reg_offset = *(data + 5);
 463        u8 payload_size = *(data + 6);
 464        u8 *payload_data;
 465
 466        if (intel_dsi->i2c_bus_num < 0) {
 467                intel_dsi->i2c_bus_num = vbt_i2c_bus_num;
 468                i2c_acpi_find_adapter(intel_dsi, slave_addr);
 469        }
 470
 471        adapter = i2c_get_adapter(intel_dsi->i2c_bus_num);
 472        if (!adapter) {
 473                drm_err(&i915->drm, "Cannot find a valid i2c bus for xfer\n");
 474                goto err_bus;
 475        }
 476
 477        payload_data = kzalloc(payload_size + 1, GFP_KERNEL);
 478        if (!payload_data)
 479                goto err_alloc;
 480
 481        payload_data[0] = reg_offset;
 482        memcpy(&payload_data[1], (data + 7), payload_size);
 483
 484        msg.addr = slave_addr;
 485        msg.flags = 0;
 486        msg.len = payload_size + 1;
 487        msg.buf = payload_data;
 488
 489        ret = i2c_transfer(adapter, &msg, 1);
 490        if (ret < 0)
 491                drm_err(&i915->drm,
 492                        "Failed to xfer payload of size (%u) to reg (%u)\n",
 493                        payload_size, reg_offset);
 494
 495        kfree(payload_data);
 496err_alloc:
 497        i2c_put_adapter(adapter);
 498err_bus:
 499        return data + payload_size + 7;
 500}
 501
 502static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data)
 503{
 504        struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
 505
 506        drm_dbg_kms(&i915->drm, "Skipping SPI element execution\n");
 507
 508        return data + *(data + 5) + 6;
 509}
 510
 511static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data)
 512{
 513        struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
 514#ifdef CONFIG_PMIC_OPREGION
 515        u32 value, mask, reg_address;
 516        u16 i2c_address;
 517        int ret;
 518
 519        /* byte 0 aka PMIC Flag is reserved */
 520        i2c_address     = get_unaligned_le16(data + 1);
 521        reg_address     = get_unaligned_le32(data + 3);
 522        value           = get_unaligned_le32(data + 7);
 523        mask            = get_unaligned_le32(data + 11);
 524
 525        ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address,
 526                                                        reg_address,
 527                                                        value, mask);
 528        if (ret)
 529                drm_err(&i915->drm, "%s failed, error: %d\n", __func__, ret);
 530#else
 531        drm_err(&i915->drm,
 532                "Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n");
 533#endif
 534
 535        return data + 15;
 536}
 537
 538typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
 539                                        const u8 *data);
 540static const fn_mipi_elem_exec exec_elem[] = {
 541        [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
 542        [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
 543        [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
 544        [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c,
 545        [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi,
 546        [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic,
 547};
 548
 549/*
 550 * MIPI Sequence from VBT #53 parsing logic
 551 * We have already separated each seqence during bios parsing
 552 * Following is generic execution function for any sequence
 553 */
 554
 555static const char * const seq_name[] = {
 556        [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET",
 557        [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP",
 558        [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON",
 559        [MIPI_SEQ_DISPLAY_OFF]  = "MIPI_SEQ_DISPLAY_OFF",
 560        [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET",
 561        [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON",
 562        [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF",
 563        [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON",
 564        [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF",
 565        [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON",
 566        [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF",
 567};
 568
 569static const char *sequence_name(enum mipi_seq seq_id)
 570{
 571        if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id])
 572                return seq_name[seq_id];
 573        else
 574                return "(unknown)";
 575}
 576
 577static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi,
 578                               enum mipi_seq seq_id)
 579{
 580        struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
 581        const u8 *data;
 582        fn_mipi_elem_exec mipi_elem_exec;
 583
 584        if (drm_WARN_ON(&dev_priv->drm,
 585                        seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence)))
 586                return;
 587
 588        data = dev_priv->vbt.dsi.sequence[seq_id];
 589        if (!data)
 590                return;
 591
 592        drm_WARN_ON(&dev_priv->drm, *data != seq_id);
 593
 594        drm_dbg_kms(&dev_priv->drm, "Starting MIPI sequence %d - %s\n",
 595                    seq_id, sequence_name(seq_id));
 596
 597        /* Skip Sequence Byte. */
 598        data++;
 599
 600        /* Skip Size of Sequence. */
 601        if (dev_priv->vbt.dsi.seq_version >= 3)
 602                data += 4;
 603
 604        while (1) {
 605                u8 operation_byte = *data++;
 606                u8 operation_size = 0;
 607
 608                if (operation_byte == MIPI_SEQ_ELEM_END)
 609                        break;
 610
 611                if (operation_byte < ARRAY_SIZE(exec_elem))
 612                        mipi_elem_exec = exec_elem[operation_byte];
 613                else
 614                        mipi_elem_exec = NULL;
 615
 616                /* Size of Operation. */
 617                if (dev_priv->vbt.dsi.seq_version >= 3)
 618                        operation_size = *data++;
 619
 620                if (mipi_elem_exec) {
 621                        const u8 *next = data + operation_size;
 622
 623                        data = mipi_elem_exec(intel_dsi, data);
 624
 625                        /* Consistency check if we have size. */
 626                        if (operation_size && data != next) {
 627                                drm_err(&dev_priv->drm,
 628                                        "Inconsistent operation size\n");
 629                                return;
 630                        }
 631                } else if (operation_size) {
 632                        /* We have size, skip. */
 633                        drm_dbg_kms(&dev_priv->drm,
 634                                    "Unsupported MIPI operation byte %u\n",
 635                                    operation_byte);
 636                        data += operation_size;
 637                } else {
 638                        /* No size, can't skip without parsing. */
 639                        drm_err(&dev_priv->drm,
 640                                "Unsupported MIPI operation byte %u\n",
 641                                operation_byte);
 642                        return;
 643                }
 644        }
 645}
 646
 647void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
 648                                 enum mipi_seq seq_id)
 649{
 650        if (seq_id == MIPI_SEQ_POWER_ON && intel_dsi->gpio_panel)
 651                gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
 652        if (seq_id == MIPI_SEQ_BACKLIGHT_ON && intel_dsi->gpio_backlight)
 653                gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 1);
 654
 655        intel_dsi_vbt_exec(intel_dsi, seq_id);
 656
 657        if (seq_id == MIPI_SEQ_POWER_OFF && intel_dsi->gpio_panel)
 658                gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
 659        if (seq_id == MIPI_SEQ_BACKLIGHT_OFF && intel_dsi->gpio_backlight)
 660                gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0);
 661}
 662
 663void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
 664{
 665        struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
 666
 667        /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
 668        if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
 669                return;
 670
 671        msleep(msec);
 672}
 673
 674void intel_dsi_log_params(struct intel_dsi *intel_dsi)
 675{
 676        struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
 677
 678        drm_dbg_kms(&i915->drm, "Pclk %d\n", intel_dsi->pclk);
 679        drm_dbg_kms(&i915->drm, "Pixel overlap %d\n",
 680                    intel_dsi->pixel_overlap);
 681        drm_dbg_kms(&i915->drm, "Lane count %d\n", intel_dsi->lane_count);
 682        drm_dbg_kms(&i915->drm, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg);
 683        drm_dbg_kms(&i915->drm, "Video mode format %s\n",
 684                    intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ?
 685                    "non-burst with sync pulse" :
 686                    intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS ?
 687                    "non-burst with sync events" :
 688                    intel_dsi->video_mode_format == VIDEO_MODE_BURST ?
 689                    "burst" : "<unknown>");
 690        drm_dbg_kms(&i915->drm, "Burst mode ratio %d\n",
 691                    intel_dsi->burst_mode_ratio);
 692        drm_dbg_kms(&i915->drm, "Reset timer %d\n", intel_dsi->rst_timer_val);
 693        drm_dbg_kms(&i915->drm, "Eot %s\n",
 694                    enableddisabled(intel_dsi->eotp_pkt));
 695        drm_dbg_kms(&i915->drm, "Clockstop %s\n",
 696                    enableddisabled(!intel_dsi->clock_stop));
 697        drm_dbg_kms(&i915->drm, "Mode %s\n",
 698                    intel_dsi->operation_mode ? "command" : "video");
 699        if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
 700                drm_dbg_kms(&i915->drm,
 701                            "Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
 702        else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
 703                drm_dbg_kms(&i915->drm,
 704                            "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
 705        else
 706                drm_dbg_kms(&i915->drm, "Dual link: NONE\n");
 707        drm_dbg_kms(&i915->drm, "Pixel Format %d\n", intel_dsi->pixel_format);
 708        drm_dbg_kms(&i915->drm, "TLPX %d\n", intel_dsi->escape_clk_div);
 709        drm_dbg_kms(&i915->drm, "LP RX Timeout 0x%x\n",
 710                    intel_dsi->lp_rx_timeout);
 711        drm_dbg_kms(&i915->drm, "Turnaround Timeout 0x%x\n",
 712                    intel_dsi->turn_arnd_val);
 713        drm_dbg_kms(&i915->drm, "Init Count 0x%x\n", intel_dsi->init_count);
 714        drm_dbg_kms(&i915->drm, "HS to LP Count 0x%x\n",
 715                    intel_dsi->hs_to_lp_count);
 716        drm_dbg_kms(&i915->drm, "LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
 717        drm_dbg_kms(&i915->drm, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
 718        drm_dbg_kms(&i915->drm, "LP to HS Clock Count 0x%x\n",
 719                    intel_dsi->clk_lp_to_hs_count);
 720        drm_dbg_kms(&i915->drm, "HS to LP Clock Count 0x%x\n",
 721                    intel_dsi->clk_hs_to_lp_count);
 722        drm_dbg_kms(&i915->drm, "BTA %s\n",
 723                    enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)));
 724}
 725
 726bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 727{
 728        struct drm_device *dev = intel_dsi->base.base.dev;
 729        struct drm_i915_private *dev_priv = to_i915(dev);
 730        struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
 731        struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
 732        struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
 733        u16 burst_mode_ratio;
 734        enum port port;
 735
 736        drm_dbg_kms(&dev_priv->drm, "\n");
 737
 738        intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
 739        intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
 740        intel_dsi->lane_count = mipi_config->lane_cnt + 1;
 741        intel_dsi->pixel_format =
 742                        pixel_format_from_register_bits(
 743                                mipi_config->videomode_color_format << 7);
 744
 745        intel_dsi->dual_link = mipi_config->dual_link;
 746        intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
 747        intel_dsi->operation_mode = mipi_config->is_cmd_mode;
 748        intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
 749        intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
 750        intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
 751        intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout;
 752        intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
 753        intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
 754        intel_dsi->init_count = mipi_config->master_init_timer;
 755        intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
 756        intel_dsi->video_frmt_cfg_bits =
 757                mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
 758        intel_dsi->bgr_enabled = mipi_config->rgb_flip;
 759
 760        /* Starting point, adjusted depending on dual link and burst mode */
 761        intel_dsi->pclk = mode->clock;
 762
 763        /* In dual link mode each port needs half of pixel clock */
 764        if (intel_dsi->dual_link) {
 765                intel_dsi->pclk /= 2;
 766
 767                /* we can enable pixel_overlap if needed by panel. In this
 768                 * case we need to increase the pixelclock for extra pixels
 769                 */
 770                if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 771                        intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);
 772                }
 773        }
 774
 775        /* Burst Mode Ratio
 776         * Target ddr frequency from VBT / non burst ddr freq
 777         * multiply by 100 to preserve remainder
 778         */
 779        if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
 780                if (mipi_config->target_burst_mode_freq) {
 781                        u32 bitrate = intel_dsi_bitrate(intel_dsi);
 782
 783                        /*
 784                         * Sometimes the VBT contains a slightly lower clock,
 785                         * then the bitrate we have calculated, in this case
 786                         * just replace it with the calculated bitrate.
 787                         */
 788                        if (mipi_config->target_burst_mode_freq < bitrate &&
 789                            intel_fuzzy_clock_check(
 790                                        mipi_config->target_burst_mode_freq,
 791                                        bitrate))
 792                                mipi_config->target_burst_mode_freq = bitrate;
 793
 794                        if (mipi_config->target_burst_mode_freq < bitrate) {
 795                                drm_err(&dev_priv->drm,
 796                                        "Burst mode freq is less than computed\n");
 797                                return false;
 798                        }
 799
 800                        burst_mode_ratio = DIV_ROUND_UP(
 801                                mipi_config->target_burst_mode_freq * 100,
 802                                bitrate);
 803
 804                        intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100);
 805                } else {
 806                        drm_err(&dev_priv->drm,
 807                                "Burst mode target is not set\n");
 808                        return false;
 809                }
 810        } else
 811                burst_mode_ratio = 100;
 812
 813        intel_dsi->burst_mode_ratio = burst_mode_ratio;
 814
 815        /* delays in VBT are in unit of 100us, so need to convert
 816         * here in ms
 817         * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
 818        intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
 819        intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
 820        intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
 821        intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
 822        intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
 823
 824        intel_dsi->i2c_bus_num = -1;
 825
 826        /* a regular driver would get the device in probe */
 827        for_each_dsi_port(port, intel_dsi->ports) {
 828                mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
 829        }
 830
 831        return true;
 832}
 833
 834/*
 835 * On some BYT/CHT devs some sequences are incomplete and we need to manually
 836 * control some GPIOs. We need to add a GPIO lookup table before we get these.
 837 * If the GOP did not initialize the panel (HDMI inserted) we may need to also
 838 * change the pinmux for the SoC's PWM0 pin from GPIO to PWM.
 839 */
 840static struct gpiod_lookup_table pmic_panel_gpio_table = {
 841        /* Intel GFX is consumer */
 842        .dev_id = "0000:00:02.0",
 843        .table = {
 844                /* Panel EN/DISABLE */
 845                GPIO_LOOKUP("gpio_crystalcove", 94, "panel", GPIO_ACTIVE_HIGH),
 846                { }
 847        },
 848};
 849
 850static struct gpiod_lookup_table soc_panel_gpio_table = {
 851        .dev_id = "0000:00:02.0",
 852        .table = {
 853                GPIO_LOOKUP("INT33FC:01", 10, "backlight", GPIO_ACTIVE_HIGH),
 854                GPIO_LOOKUP("INT33FC:01", 11, "panel", GPIO_ACTIVE_HIGH),
 855                { }
 856        },
 857};
 858
 859static const struct pinctrl_map soc_pwm_pinctrl_map[] = {
 860        PIN_MAP_MUX_GROUP("0000:00:02.0", "soc_pwm0", "INT33FC:00",
 861                          "pwm0_grp", "pwm"),
 862};
 863
 864void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on)
 865{
 866        struct drm_device *dev = intel_dsi->base.base.dev;
 867        struct drm_i915_private *dev_priv = to_i915(dev);
 868        struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
 869        enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
 870        bool want_backlight_gpio = false;
 871        bool want_panel_gpio = false;
 872        struct pinctrl *pinctrl;
 873        int ret;
 874
 875        if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 876            mipi_config->pwm_blc == PPS_BLC_PMIC) {
 877                gpiod_add_lookup_table(&pmic_panel_gpio_table);
 878                want_panel_gpio = true;
 879        }
 880
 881        if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) {
 882                gpiod_add_lookup_table(&soc_panel_gpio_table);
 883                want_panel_gpio = true;
 884                want_backlight_gpio = true;
 885
 886                /* Ensure PWM0 pin is muxed as PWM instead of GPIO */
 887                ret = pinctrl_register_mappings(soc_pwm_pinctrl_map,
 888                                             ARRAY_SIZE(soc_pwm_pinctrl_map));
 889                if (ret)
 890                        drm_err(&dev_priv->drm,
 891                                "Failed to register pwm0 pinmux mapping\n");
 892
 893                pinctrl = devm_pinctrl_get_select(dev->dev, "soc_pwm0");
 894                if (IS_ERR(pinctrl))
 895                        drm_err(&dev_priv->drm,
 896                                "Failed to set pinmux to PWM\n");
 897        }
 898
 899        if (want_panel_gpio) {
 900                intel_dsi->gpio_panel = gpiod_get(dev->dev, "panel", flags);
 901                if (IS_ERR(intel_dsi->gpio_panel)) {
 902                        drm_err(&dev_priv->drm,
 903                                "Failed to own gpio for panel control\n");
 904                        intel_dsi->gpio_panel = NULL;
 905                }
 906        }
 907
 908        if (want_backlight_gpio) {
 909                intel_dsi->gpio_backlight =
 910                        gpiod_get(dev->dev, "backlight", flags);
 911                if (IS_ERR(intel_dsi->gpio_backlight)) {
 912                        drm_err(&dev_priv->drm,
 913                                "Failed to own gpio for backlight control\n");
 914                        intel_dsi->gpio_backlight = NULL;
 915                }
 916        }
 917}
 918
 919void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi)
 920{
 921        struct drm_device *dev = intel_dsi->base.base.dev;
 922        struct drm_i915_private *dev_priv = to_i915(dev);
 923        struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
 924
 925        if (intel_dsi->gpio_panel) {
 926                gpiod_put(intel_dsi->gpio_panel);
 927                intel_dsi->gpio_panel = NULL;
 928        }
 929
 930        if (intel_dsi->gpio_backlight) {
 931                gpiod_put(intel_dsi->gpio_backlight);
 932                intel_dsi->gpio_backlight = NULL;
 933        }
 934
 935        if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 936            mipi_config->pwm_blc == PPS_BLC_PMIC)
 937                gpiod_remove_lookup_table(&pmic_panel_gpio_table);
 938
 939        if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) {
 940                pinctrl_unregister_mappings(soc_pwm_pinctrl_map);
 941                gpiod_remove_lookup_table(&soc_panel_gpio_table);
 942        }
 943}
 944