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6
7
8#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
9
10#include <linux/debugfs.h>
11#include <linux/dma-buf.h>
12
13#include <drm/drm_atomic_uapi.h>
14#include <drm/drm_damage_helper.h>
15#include <drm/drm_file.h>
16#include <drm/drm_gem_framebuffer_helper.h>
17
18#include "msm_drv.h"
19#include "dpu_kms.h"
20#include "dpu_formats.h"
21#include "dpu_hw_sspp.h"
22#include "dpu_hw_catalog_format.h"
23#include "dpu_trace.h"
24#include "dpu_crtc.h"
25#include "dpu_vbif.h"
26#include "dpu_plane.h"
27
28#define DPU_DEBUG_PLANE(pl, fmt, ...) DPU_DEBUG("plane%d " fmt,\
29 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
30
31#define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\
32 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
33
34#define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
35#define PHASE_STEP_SHIFT 21
36#define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
37#define PHASE_RESIDUAL 15
38
39#define SHARP_STRENGTH_DEFAULT 32
40#define SHARP_EDGE_THR_DEFAULT 112
41#define SHARP_SMOOTH_THR_DEFAULT 8
42#define SHARP_NOISE_THR_DEFAULT 2
43
44#define DPU_NAME_SIZE 12
45
46#define DPU_PLANE_COLOR_FILL_FLAG BIT(31)
47#define DPU_ZPOS_MAX 255
48
49
50enum {
51 R0,
52 R1,
53 R_MAX
54};
55
56
57
58
59#define DPU_QSEED3_DEFAULT_PRELOAD_H 0x4
60#define DPU_QSEED3_DEFAULT_PRELOAD_V 0x3
61#define DPU_QSEED4_DEFAULT_PRELOAD_V 0x2
62#define DPU_QSEED4_DEFAULT_PRELOAD_H 0x4
63
64#define DEFAULT_REFRESH_RATE 60
65
66
67
68
69
70
71
72
73
74enum dpu_plane_qos {
75 DPU_PLANE_QOS_VBLANK_CTRL = BIT(0),
76 DPU_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
77 DPU_PLANE_QOS_PANIC_CTRL = BIT(2),
78};
79
80
81
82
83
84
85
86
87
88struct dpu_plane {
89 struct drm_plane base;
90
91 struct mutex lock;
92
93 enum dpu_sspp pipe;
94 uint32_t features;
95
96 struct dpu_hw_pipe *pipe_hw;
97 struct dpu_hw_pipe_cfg pipe_cfg;
98 struct dpu_hw_pipe_qos_cfg pipe_qos_cfg;
99 uint32_t color_fill;
100 bool is_error;
101 bool is_rt_pipe;
102 bool is_virtual;
103 struct list_head mplane_list;
104 struct dpu_mdss_cfg *catalog;
105
106 struct dpu_csc_cfg *csc_ptr;
107
108 const struct dpu_sspp_sub_blks *pipe_sblk;
109 char pipe_name[DPU_NAME_SIZE];
110
111
112 struct dentry *debugfs_root;
113 struct dpu_debugfs_regset32 debugfs_src;
114 struct dpu_debugfs_regset32 debugfs_scaler;
115 struct dpu_debugfs_regset32 debugfs_csc;
116 bool debugfs_default_scale;
117};
118
119static const uint64_t supported_format_modifiers[] = {
120 DRM_FORMAT_MOD_QCOM_COMPRESSED,
121 DRM_FORMAT_MOD_LINEAR,
122 DRM_FORMAT_MOD_INVALID
123};
124
125#define to_dpu_plane(x) container_of(x, struct dpu_plane, base)
126
127static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane)
128{
129 struct msm_drm_private *priv = plane->dev->dev_private;
130
131 return to_dpu_kms(priv->kms);
132}
133
134
135
136
137
138
139
140
141static void _dpu_plane_calc_bw(struct drm_plane *plane,
142 struct drm_framebuffer *fb)
143{
144 struct dpu_plane *pdpu = to_dpu_plane(plane);
145 struct dpu_plane_state *pstate;
146 struct drm_display_mode *mode;
147 const struct dpu_format *fmt = NULL;
148 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
149 int src_width, src_height, dst_height, fps;
150 u64 plane_prefill_bw;
151 u64 plane_bw;
152 u32 hw_latency_lines;
153 u64 scale_factor;
154 int vbp, vpw;
155
156 pstate = to_dpu_plane_state(plane->state);
157 mode = &plane->state->crtc->mode;
158
159 fmt = dpu_get_dpu_format_ext(fb->format->format, fb->modifier);
160
161 src_width = drm_rect_width(&pdpu->pipe_cfg.src_rect);
162 src_height = drm_rect_height(&pdpu->pipe_cfg.src_rect);
163 dst_height = drm_rect_height(&pdpu->pipe_cfg.dst_rect);
164 fps = drm_mode_vrefresh(mode);
165 vbp = mode->vtotal - mode->vsync_end;
166 vpw = mode->vsync_end - mode->vsync_start;
167 hw_latency_lines = dpu_kms->catalog->perf.min_prefill_lines;
168 scale_factor = src_height > dst_height ?
169 mult_frac(src_height, 1, dst_height) : 1;
170
171 plane_bw =
172 src_width * mode->vtotal * fps * fmt->bpp *
173 scale_factor;
174
175 plane_prefill_bw =
176 src_width * hw_latency_lines * fps * fmt->bpp *
177 scale_factor * mode->vtotal;
178
179 do_div(plane_prefill_bw, (vbp+vpw));
180
181 pstate->plane_fetch_bw = max(plane_bw, plane_prefill_bw);
182}
183
184
185
186
187
188
189
190static void _dpu_plane_calc_clk(struct drm_plane *plane)
191{
192 struct dpu_plane *pdpu = to_dpu_plane(plane);
193 struct dpu_plane_state *pstate;
194 struct drm_display_mode *mode;
195 int dst_width, src_height, dst_height, fps;
196
197 pstate = to_dpu_plane_state(plane->state);
198 mode = &plane->state->crtc->mode;
199
200 src_height = drm_rect_height(&pdpu->pipe_cfg.src_rect);
201 dst_width = drm_rect_width(&pdpu->pipe_cfg.dst_rect);
202 dst_height = drm_rect_height(&pdpu->pipe_cfg.dst_rect);
203 fps = drm_mode_vrefresh(mode);
204
205 pstate->plane_clk =
206 dst_width * mode->vtotal * fps;
207
208 if (src_height > dst_height) {
209 pstate->plane_clk *= src_height;
210 do_div(pstate->plane_clk, dst_height);
211 }
212}
213
214
215
216
217
218
219
220
221static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
222 const struct dpu_format *fmt, u32 src_width)
223{
224 struct dpu_plane *pdpu, *tmp;
225 struct dpu_plane_state *pstate;
226 u32 fixed_buff_size;
227 u32 total_fl;
228
229 if (!fmt || !plane->state || !src_width || !fmt->bpp) {
230 DPU_ERROR("invalid arguments\n");
231 return 0;
232 }
233
234 pdpu = to_dpu_plane(plane);
235 pstate = to_dpu_plane_state(plane->state);
236 fixed_buff_size = pdpu->catalog->caps->pixel_ram_size;
237
238 list_for_each_entry(tmp, &pdpu->mplane_list, mplane_list) {
239 if (!tmp->base.state->visible)
240 continue;
241 DPU_DEBUG("plane%d/%d src_width:%d/%d\n",
242 pdpu->base.base.id, tmp->base.base.id,
243 src_width,
244 drm_rect_width(&tmp->pipe_cfg.src_rect));
245 src_width = max_t(u32, src_width,
246 drm_rect_width(&tmp->pipe_cfg.src_rect));
247 }
248
249 if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) {
250 if (fmt->chroma_sample == DPU_CHROMA_420) {
251
252 total_fl = (fixed_buff_size / 2) /
253 ((src_width + 32) * fmt->bpp);
254 } else {
255
256 total_fl = (fixed_buff_size / 2) * 2 /
257 ((src_width + 32) * fmt->bpp);
258 }
259 } else {
260 if (pstate->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) {
261 total_fl = (fixed_buff_size / 2) * 2 /
262 ((src_width + 32) * fmt->bpp);
263 } else {
264 total_fl = (fixed_buff_size) * 2 /
265 ((src_width + 32) * fmt->bpp);
266 }
267 }
268
269 DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s w:%u fl:%u\n",
270 plane->base.id, pdpu->pipe - SSPP_VIG0,
271 (char *)&fmt->base.pixel_format,
272 src_width, total_fl);
273
274 return total_fl;
275}
276
277
278
279
280
281
282
283static u64 _dpu_plane_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
284 u32 total_fl)
285{
286 int i;
287
288 if (!tbl || !tbl->nentry || !tbl->entries)
289 return 0;
290
291 for (i = 0; i < tbl->nentry; i++)
292 if (total_fl <= tbl->entries[i].fl)
293 return tbl->entries[i].lut;
294
295
296 if (!tbl->entries[i-1].fl)
297 return tbl->entries[i-1].lut;
298
299 return 0;
300}
301
302
303
304
305
306
307static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
308 struct drm_framebuffer *fb)
309{
310 struct dpu_plane *pdpu = to_dpu_plane(plane);
311 const struct dpu_format *fmt = NULL;
312 u64 qos_lut;
313 u32 total_fl = 0, lut_usage;
314
315 if (!pdpu->is_rt_pipe) {
316 lut_usage = DPU_QOS_LUT_USAGE_NRT;
317 } else {
318 fmt = dpu_get_dpu_format_ext(
319 fb->format->format,
320 fb->modifier);
321 total_fl = _dpu_plane_calc_fill_level(plane, fmt,
322 drm_rect_width(&pdpu->pipe_cfg.src_rect));
323
324 if (fmt && DPU_FORMAT_IS_LINEAR(fmt))
325 lut_usage = DPU_QOS_LUT_USAGE_LINEAR;
326 else
327 lut_usage = DPU_QOS_LUT_USAGE_MACROTILE;
328 }
329
330 qos_lut = _dpu_plane_get_qos_lut(
331 &pdpu->catalog->perf.qos_lut_tbl[lut_usage], total_fl);
332
333 pdpu->pipe_qos_cfg.creq_lut = qos_lut;
334
335 trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0,
336 (fmt) ? fmt->base.pixel_format : 0,
337 pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage);
338
339 DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n",
340 plane->base.id,
341 pdpu->pipe - SSPP_VIG0,
342 fmt ? (char *)&fmt->base.pixel_format : NULL,
343 pdpu->is_rt_pipe, total_fl, qos_lut);
344
345 pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, &pdpu->pipe_qos_cfg);
346}
347
348
349
350
351
352
353static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
354 struct drm_framebuffer *fb)
355{
356 struct dpu_plane *pdpu = to_dpu_plane(plane);
357 const struct dpu_format *fmt = NULL;
358 u32 danger_lut, safe_lut;
359
360 if (!pdpu->is_rt_pipe) {
361 danger_lut = pdpu->catalog->perf.danger_lut_tbl
362 [DPU_QOS_LUT_USAGE_NRT];
363 safe_lut = pdpu->catalog->perf.safe_lut_tbl
364 [DPU_QOS_LUT_USAGE_NRT];
365 } else {
366 fmt = dpu_get_dpu_format_ext(
367 fb->format->format,
368 fb->modifier);
369
370 if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) {
371 danger_lut = pdpu->catalog->perf.danger_lut_tbl
372 [DPU_QOS_LUT_USAGE_LINEAR];
373 safe_lut = pdpu->catalog->perf.safe_lut_tbl
374 [DPU_QOS_LUT_USAGE_LINEAR];
375 } else {
376 danger_lut = pdpu->catalog->perf.danger_lut_tbl
377 [DPU_QOS_LUT_USAGE_MACROTILE];
378 safe_lut = pdpu->catalog->perf.safe_lut_tbl
379 [DPU_QOS_LUT_USAGE_MACROTILE];
380 }
381 }
382
383 pdpu->pipe_qos_cfg.danger_lut = danger_lut;
384 pdpu->pipe_qos_cfg.safe_lut = safe_lut;
385
386 trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0,
387 (fmt) ? fmt->base.pixel_format : 0,
388 (fmt) ? fmt->fetch_mode : 0,
389 pdpu->pipe_qos_cfg.danger_lut,
390 pdpu->pipe_qos_cfg.safe_lut);
391
392 DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n",
393 plane->base.id,
394 pdpu->pipe - SSPP_VIG0,
395 fmt ? (char *)&fmt->base.pixel_format : NULL,
396 fmt ? fmt->fetch_mode : -1,
397 pdpu->pipe_qos_cfg.danger_lut,
398 pdpu->pipe_qos_cfg.safe_lut);
399
400 pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw,
401 &pdpu->pipe_qos_cfg);
402}
403
404
405
406
407
408
409
410static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
411 bool enable, u32 flags)
412{
413 struct dpu_plane *pdpu = to_dpu_plane(plane);
414
415 if (flags & DPU_PLANE_QOS_VBLANK_CTRL) {
416 pdpu->pipe_qos_cfg.creq_vblank = pdpu->pipe_sblk->creq_vblank;
417 pdpu->pipe_qos_cfg.danger_vblank =
418 pdpu->pipe_sblk->danger_vblank;
419 pdpu->pipe_qos_cfg.vblank_en = enable;
420 }
421
422 if (flags & DPU_PLANE_QOS_VBLANK_AMORTIZE) {
423
424 pdpu->pipe_qos_cfg.vblank_en = false;
425 pdpu->pipe_qos_cfg.creq_vblank = 0;
426 }
427
428 if (flags & DPU_PLANE_QOS_PANIC_CTRL)
429 pdpu->pipe_qos_cfg.danger_safe_en = enable;
430
431 if (!pdpu->is_rt_pipe) {
432 pdpu->pipe_qos_cfg.vblank_en = false;
433 pdpu->pipe_qos_cfg.danger_safe_en = false;
434 }
435
436 DPU_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
437 plane->base.id,
438 pdpu->pipe - SSPP_VIG0,
439 pdpu->pipe_qos_cfg.danger_safe_en,
440 pdpu->pipe_qos_cfg.vblank_en,
441 pdpu->pipe_qos_cfg.creq_vblank,
442 pdpu->pipe_qos_cfg.danger_vblank,
443 pdpu->is_rt_pipe);
444
445 pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw,
446 &pdpu->pipe_qos_cfg);
447}
448
449
450
451
452
453
454static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
455 struct drm_crtc *crtc)
456{
457 struct dpu_plane *pdpu = to_dpu_plane(plane);
458 struct dpu_vbif_set_ot_params ot_params;
459 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
460
461 memset(&ot_params, 0, sizeof(ot_params));
462 ot_params.xin_id = pdpu->pipe_hw->cap->xin_id;
463 ot_params.num = pdpu->pipe_hw->idx - SSPP_NONE;
464 ot_params.width = drm_rect_width(&pdpu->pipe_cfg.src_rect);
465 ot_params.height = drm_rect_height(&pdpu->pipe_cfg.src_rect);
466 ot_params.is_wfd = !pdpu->is_rt_pipe;
467 ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
468 ot_params.vbif_idx = VBIF_RT;
469 ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
470 ot_params.rd = true;
471
472 dpu_vbif_set_ot_limit(dpu_kms, &ot_params);
473}
474
475
476
477
478
479static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
480{
481 struct dpu_plane *pdpu = to_dpu_plane(plane);
482 struct dpu_vbif_set_qos_params qos_params;
483 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
484
485 memset(&qos_params, 0, sizeof(qos_params));
486 qos_params.vbif_idx = VBIF_RT;
487 qos_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
488 qos_params.xin_id = pdpu->pipe_hw->cap->xin_id;
489 qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0;
490 qos_params.is_rt = pdpu->is_rt_pipe;
491
492 DPU_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
493 plane->base.id, qos_params.num,
494 qos_params.vbif_idx,
495 qos_params.xin_id, qos_params.is_rt,
496 qos_params.clk_ctrl);
497
498 dpu_vbif_set_qos_remap(dpu_kms, &qos_params);
499}
500
501static void _dpu_plane_set_scanout(struct drm_plane *plane,
502 struct dpu_plane_state *pstate,
503 struct dpu_hw_pipe_cfg *pipe_cfg,
504 struct drm_framebuffer *fb)
505{
506 struct dpu_plane *pdpu = to_dpu_plane(plane);
507 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
508 struct msm_gem_address_space *aspace = kms->base.aspace;
509 int ret;
510
511 ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
512 if (ret == -EAGAIN)
513 DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n");
514 else if (ret)
515 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
516 else if (pdpu->pipe_hw->ops.setup_sourceaddress) {
517 trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx,
518 &pipe_cfg->layout,
519 pstate->multirect_index);
520 pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg,
521 pstate->multirect_index);
522 }
523}
524
525static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
526 struct dpu_plane_state *pstate,
527 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
528 struct dpu_hw_scaler3_cfg *scale_cfg,
529 const struct dpu_format *fmt,
530 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
531{
532 uint32_t i;
533
534 memset(scale_cfg, 0, sizeof(*scale_cfg));
535 memset(&pstate->pixel_ext, 0, sizeof(struct dpu_hw_pixel_ext));
536
537 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] =
538 mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w);
539 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] =
540 mult_frac((1 << PHASE_STEP_SHIFT), src_h, dst_h);
541
542
543 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2] =
544 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] / chroma_subsmpl_v;
545 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2] =
546 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] / chroma_subsmpl_h;
547
548 scale_cfg->phase_step_x[DPU_SSPP_COMP_2] =
549 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2];
550 scale_cfg->phase_step_y[DPU_SSPP_COMP_2] =
551 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2];
552
553 scale_cfg->phase_step_x[DPU_SSPP_COMP_3] =
554 scale_cfg->phase_step_x[DPU_SSPP_COMP_0];
555 scale_cfg->phase_step_y[DPU_SSPP_COMP_3] =
556 scale_cfg->phase_step_y[DPU_SSPP_COMP_0];
557
558 for (i = 0; i < DPU_MAX_PLANES; i++) {
559 scale_cfg->src_width[i] = src_w;
560 scale_cfg->src_height[i] = src_h;
561 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) {
562 scale_cfg->src_width[i] /= chroma_subsmpl_h;
563 scale_cfg->src_height[i] /= chroma_subsmpl_v;
564 }
565
566 if (pdpu->pipe_hw->cap->features &
567 BIT(DPU_SSPP_SCALER_QSEED4)) {
568 scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H;
569 scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V;
570 } else {
571 scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H;
572 scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V;
573 }
574
575 pstate->pixel_ext.num_ext_pxls_top[i] =
576 scale_cfg->src_height[i];
577 pstate->pixel_ext.num_ext_pxls_left[i] =
578 scale_cfg->src_width[i];
579 }
580 if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
581 && (src_w == dst_w))
582 return;
583
584 scale_cfg->dst_width = dst_w;
585 scale_cfg->dst_height = dst_h;
586 scale_cfg->y_rgb_filter_cfg = DPU_SCALE_BIL;
587 scale_cfg->uv_filter_cfg = DPU_SCALE_BIL;
588 scale_cfg->alpha_filter_cfg = DPU_SCALE_ALPHA_BIL;
589 scale_cfg->lut_flag = 0;
590 scale_cfg->blend_cfg = 1;
591 scale_cfg->enable = 1;
592}
593
594static void _dpu_plane_setup_csc(struct dpu_plane *pdpu)
595{
596 static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = {
597 {
598
599 0x00012A00, 0x00000000, 0x00019880,
600 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
601 0x00012A00, 0x00020480, 0x00000000,
602 },
603
604 { 0xfff0, 0xff80, 0xff80,},
605 { 0x0, 0x0, 0x0,},
606
607 { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
608 { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
609 };
610 static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = {
611 {
612
613 0x00012A00, 0x00000000, 0x00019880,
614 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
615 0x00012A00, 0x00020480, 0x00000000,
616 },
617
618 { 0xffc0, 0xfe00, 0xfe00,},
619 { 0x0, 0x0, 0x0,},
620
621 { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
622 { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
623 };
624
625 if (!pdpu) {
626 DPU_ERROR("invalid plane\n");
627 return;
628 }
629
630 if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->features)
631 pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc10_YUV2RGB_601L;
632 else
633 pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc_YUV2RGB_601L;
634
635 DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n",
636 pdpu->csc_ptr->csc_mv[0],
637 pdpu->csc_ptr->csc_mv[1],
638 pdpu->csc_ptr->csc_mv[2]);
639}
640
641static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
642 struct dpu_plane_state *pstate,
643 const struct dpu_format *fmt, bool color_fill)
644{
645 const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format);
646
647
648
649 _dpu_plane_setup_scaler3(pdpu, pstate,
650 drm_rect_width(&pdpu->pipe_cfg.src_rect),
651 drm_rect_height(&pdpu->pipe_cfg.src_rect),
652 drm_rect_width(&pdpu->pipe_cfg.dst_rect),
653 drm_rect_height(&pdpu->pipe_cfg.dst_rect),
654 &pstate->scaler3_cfg, fmt,
655 info->hsub, info->vsub);
656}
657
658
659
660
661
662
663
664
665static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
666 uint32_t color, uint32_t alpha)
667{
668 const struct dpu_format *fmt;
669 const struct drm_plane *plane = &pdpu->base;
670 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
671
672 DPU_DEBUG_PLANE(pdpu, "\n");
673
674
675
676
677
678 fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888);
679
680
681 if (fmt && pdpu->pipe_hw->ops.setup_solidfill) {
682 pdpu->pipe_hw->ops.setup_solidfill(pdpu->pipe_hw,
683 (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
684 pstate->multirect_index);
685
686
687 pdpu->pipe_cfg.src_rect.x1 = 0;
688 pdpu->pipe_cfg.src_rect.y1 = 0;
689 pdpu->pipe_cfg.src_rect.x2 =
690 drm_rect_width(&pdpu->pipe_cfg.dst_rect);
691 pdpu->pipe_cfg.src_rect.y2 =
692 drm_rect_height(&pdpu->pipe_cfg.dst_rect);
693 _dpu_plane_setup_scaler(pdpu, pstate, fmt, true);
694
695 if (pdpu->pipe_hw->ops.setup_format)
696 pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw,
697 fmt, DPU_SSPP_SOLID_FILL,
698 pstate->multirect_index);
699
700 if (pdpu->pipe_hw->ops.setup_rects)
701 pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
702 &pdpu->pipe_cfg,
703 pstate->multirect_index);
704
705 if (pdpu->pipe_hw->ops.setup_pe)
706 pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
707 &pstate->pixel_ext);
708
709 if (pdpu->pipe_hw->ops.setup_scaler &&
710 pstate->multirect_index != DPU_SSPP_RECT_1)
711 pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
712 &pdpu->pipe_cfg, &pstate->pixel_ext,
713 &pstate->scaler3_cfg);
714 }
715
716 return 0;
717}
718
719void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state)
720{
721 struct dpu_plane_state *pstate = to_dpu_plane_state(drm_state);
722
723 pstate->multirect_index = DPU_SSPP_RECT_SOLO;
724 pstate->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
725}
726
727int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane)
728{
729 struct dpu_plane_state *pstate[R_MAX];
730 const struct drm_plane_state *drm_state[R_MAX];
731 struct drm_rect src[R_MAX], dst[R_MAX];
732 struct dpu_plane *dpu_plane[R_MAX];
733 const struct dpu_format *fmt[R_MAX];
734 int i, buffer_lines;
735 unsigned int max_tile_height = 1;
736 bool parallel_fetch_qualified = true;
737 bool has_tiled_rect = false;
738
739 for (i = 0; i < R_MAX; i++) {
740 const struct msm_format *msm_fmt;
741
742 drm_state[i] = i ? plane->r1 : plane->r0;
743 msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
744 fmt[i] = to_dpu_format(msm_fmt);
745
746 if (DPU_FORMAT_IS_UBWC(fmt[i])) {
747 has_tiled_rect = true;
748 if (fmt[i]->tile_height > max_tile_height)
749 max_tile_height = fmt[i]->tile_height;
750 }
751 }
752
753 for (i = 0; i < R_MAX; i++) {
754 int width_threshold;
755
756 pstate[i] = to_dpu_plane_state(drm_state[i]);
757 dpu_plane[i] = to_dpu_plane(drm_state[i]->plane);
758
759 if (pstate[i] == NULL) {
760 DPU_ERROR("DPU plane state of plane id %d is NULL\n",
761 drm_state[i]->plane->base.id);
762 return -EINVAL;
763 }
764
765 src[i].x1 = drm_state[i]->src_x >> 16;
766 src[i].y1 = drm_state[i]->src_y >> 16;
767 src[i].x2 = src[i].x1 + (drm_state[i]->src_w >> 16);
768 src[i].y2 = src[i].y1 + (drm_state[i]->src_h >> 16);
769
770 dst[i] = drm_plane_state_dest(drm_state[i]);
771
772 if (drm_rect_calc_hscale(&src[i], &dst[i], 1, 1) != 1 ||
773 drm_rect_calc_vscale(&src[i], &dst[i], 1, 1) != 1) {
774 DPU_ERROR_PLANE(dpu_plane[i],
775 "scaling is not supported in multirect mode\n");
776 return -EINVAL;
777 }
778
779 if (DPU_FORMAT_IS_YUV(fmt[i])) {
780 DPU_ERROR_PLANE(dpu_plane[i],
781 "Unsupported format for multirect mode\n");
782 return -EINVAL;
783 }
784
785
786
787
788
789
790
791
792 width_threshold = dpu_plane[i]->catalog->caps->max_linewidth;
793 if (has_tiled_rect)
794 width_threshold /= 2;
795
796 if (parallel_fetch_qualified &&
797 drm_rect_width(&src[i]) > width_threshold)
798 parallel_fetch_qualified = false;
799
800 }
801
802
803
804
805 if (parallel_fetch_qualified) {
806 pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
807 pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
808
809 goto done;
810 }
811
812
813 buffer_lines = 2 * max_tile_height;
814
815 if (dst[R1].y1 >= dst[R0].y2 + buffer_lines ||
816 dst[R0].y1 >= dst[R1].y2 + buffer_lines) {
817 pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX;
818 pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX;
819 } else {
820 DPU_ERROR(
821 "No multirect mode possible for the planes (%d - %d)\n",
822 drm_state[R0]->plane->base.id,
823 drm_state[R1]->plane->base.id);
824 return -EINVAL;
825 }
826
827done:
828 if (dpu_plane[R0]->is_virtual) {
829 pstate[R0]->multirect_index = DPU_SSPP_RECT_1;
830 pstate[R1]->multirect_index = DPU_SSPP_RECT_0;
831 } else {
832 pstate[R0]->multirect_index = DPU_SSPP_RECT_0;
833 pstate[R1]->multirect_index = DPU_SSPP_RECT_1;
834 }
835
836 DPU_DEBUG_PLANE(dpu_plane[R0], "R0: %d - %d\n",
837 pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
838 DPU_DEBUG_PLANE(dpu_plane[R1], "R1: %d - %d\n",
839 pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
840 return 0;
841}
842
843
844
845
846
847
848
849void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl,
850 u32 *flush_sspp)
851{
852 *flush_sspp = ctl->ops.get_bitmask_sspp(ctl, dpu_plane_pipe(plane));
853}
854
855static int dpu_plane_prepare_fb(struct drm_plane *plane,
856 struct drm_plane_state *new_state)
857{
858 struct drm_framebuffer *fb = new_state->fb;
859 struct dpu_plane *pdpu = to_dpu_plane(plane);
860 struct dpu_plane_state *pstate = to_dpu_plane_state(new_state);
861 struct dpu_hw_fmt_layout layout;
862 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
863 int ret;
864
865 if (!new_state->fb)
866 return 0;
867
868 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id);
869
870
871 pstate->aspace = kms->base.aspace;
872
873
874
875
876
877
878 drm_gem_fb_prepare_fb(plane, new_state);
879
880 if (pstate->aspace) {
881 ret = msm_framebuffer_prepare(new_state->fb,
882 pstate->aspace);
883 if (ret) {
884 DPU_ERROR("failed to prepare framebuffer\n");
885 return ret;
886 }
887 }
888
889
890 ret = dpu_format_populate_layout(pstate->aspace,
891 new_state->fb, &layout);
892 if (ret) {
893 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
894 return ret;
895 }
896
897 return 0;
898}
899
900static void dpu_plane_cleanup_fb(struct drm_plane *plane,
901 struct drm_plane_state *old_state)
902{
903 struct dpu_plane *pdpu = to_dpu_plane(plane);
904 struct dpu_plane_state *old_pstate;
905
906 if (!old_state || !old_state->fb)
907 return;
908
909 old_pstate = to_dpu_plane_state(old_state);
910
911 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id);
912
913 msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace);
914}
915
916static bool dpu_plane_validate_src(struct drm_rect *src,
917 struct drm_rect *fb_rect,
918 uint32_t min_src_size)
919{
920
921 if (drm_rect_width(fb_rect) > MAX_IMG_WIDTH ||
922 drm_rect_height(fb_rect) > MAX_IMG_HEIGHT)
923 return false;
924
925
926 if (drm_rect_width(src) < min_src_size ||
927 drm_rect_height(src) < min_src_size)
928 return false;
929
930
931 return drm_rect_intersect(fb_rect, src) &&
932 drm_rect_equals(fb_rect, src);
933}
934
935static int dpu_plane_atomic_check(struct drm_plane *plane,
936 struct drm_plane_state *state)
937{
938 int ret = 0, min_scale;
939 struct dpu_plane *pdpu = to_dpu_plane(plane);
940 const struct drm_crtc_state *crtc_state = NULL;
941 const struct dpu_format *fmt;
942 struct drm_rect src, dst, fb_rect = { 0 };
943 uint32_t min_src_size, max_linewidth;
944
945 if (state->crtc)
946 crtc_state = drm_atomic_get_new_crtc_state(state->state,
947 state->crtc);
948
949 min_scale = FRAC_16_16(1, pdpu->pipe_sblk->maxupscale);
950 ret = drm_atomic_helper_check_plane_state(state, crtc_state, min_scale,
951 pdpu->pipe_sblk->maxdwnscale << 16,
952 true, true);
953 if (ret) {
954 DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret);
955 return ret;
956 }
957 if (!state->visible)
958 return 0;
959
960 src.x1 = state->src_x >> 16;
961 src.y1 = state->src_y >> 16;
962 src.x2 = src.x1 + (state->src_w >> 16);
963 src.y2 = src.y1 + (state->src_h >> 16);
964
965 dst = drm_plane_state_dest(state);
966
967 fb_rect.x2 = state->fb->width;
968 fb_rect.y2 = state->fb->height;
969
970 max_linewidth = pdpu->catalog->caps->max_linewidth;
971
972 fmt = to_dpu_format(msm_framebuffer_format(state->fb));
973
974 min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1;
975
976 if (DPU_FORMAT_IS_YUV(fmt) &&
977 (!(pdpu->features & DPU_SSPP_SCALER) ||
978 !(pdpu->features & (BIT(DPU_SSPP_CSC)
979 | BIT(DPU_SSPP_CSC_10BIT))))) {
980 DPU_DEBUG_PLANE(pdpu,
981 "plane doesn't have scaler/csc for yuv\n");
982 return -EINVAL;
983
984
985 } else if (!dpu_plane_validate_src(&src, &fb_rect, min_src_size)) {
986 DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n",
987 DRM_RECT_ARG(&src));
988 return -E2BIG;
989
990
991 } else if (DPU_FORMAT_IS_YUV(fmt) &&
992 (src.x1 & 0x1 || src.y1 & 0x1 ||
993 drm_rect_width(&src) & 0x1 ||
994 drm_rect_height(&src) & 0x1)) {
995 DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n",
996 DRM_RECT_ARG(&src));
997 return -EINVAL;
998
999
1000 } else if (drm_rect_width(&dst) < 0x1 || drm_rect_height(&dst) < 0x1) {
1001 DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n",
1002 DRM_RECT_ARG(&dst));
1003 return -EINVAL;
1004
1005
1006 } else if (drm_rect_width(&src) > max_linewidth) {
1007 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
1008 DRM_RECT_ARG(&src), max_linewidth);
1009 return -E2BIG;
1010 }
1011
1012 return 0;
1013}
1014
1015void dpu_plane_flush(struct drm_plane *plane)
1016{
1017 struct dpu_plane *pdpu;
1018 struct dpu_plane_state *pstate;
1019
1020 if (!plane || !plane->state) {
1021 DPU_ERROR("invalid plane\n");
1022 return;
1023 }
1024
1025 pdpu = to_dpu_plane(plane);
1026 pstate = to_dpu_plane_state(plane->state);
1027
1028
1029
1030
1031
1032 if (pdpu->is_error)
1033
1034 _dpu_plane_color_fill(pdpu, 0xFFFFFF, 0xFF);
1035 else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG)
1036
1037 _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
1038 else if (pdpu->pipe_hw && pdpu->csc_ptr && pdpu->pipe_hw->ops.setup_csc)
1039 pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, pdpu->csc_ptr);
1040
1041
1042 if (plane->state)
1043 pstate->pending = false;
1044}
1045
1046
1047
1048
1049
1050void dpu_plane_set_error(struct drm_plane *plane, bool error)
1051{
1052 struct dpu_plane *pdpu;
1053
1054 if (!plane)
1055 return;
1056
1057 pdpu = to_dpu_plane(plane);
1058 pdpu->is_error = error;
1059}
1060
1061static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
1062{
1063 uint32_t src_flags;
1064 struct dpu_plane *pdpu = to_dpu_plane(plane);
1065 struct drm_plane_state *state = plane->state;
1066 struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1067 struct drm_crtc *crtc = state->crtc;
1068 struct drm_framebuffer *fb = state->fb;
1069 const struct dpu_format *fmt =
1070 to_dpu_format(msm_framebuffer_format(fb));
1071
1072 memset(&(pdpu->pipe_cfg), 0, sizeof(struct dpu_hw_pipe_cfg));
1073
1074 _dpu_plane_set_scanout(plane, pstate, &pdpu->pipe_cfg, fb);
1075
1076 pstate->pending = true;
1077
1078 pdpu->is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT);
1079 _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);
1080
1081 DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
1082 ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src),
1083 crtc->base.id, DRM_RECT_ARG(&state->dst),
1084 (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt));
1085
1086 pdpu->pipe_cfg.src_rect = state->src;
1087
1088
1089 pdpu->pipe_cfg.src_rect.x1 >>= 16;
1090 pdpu->pipe_cfg.src_rect.x2 >>= 16;
1091 pdpu->pipe_cfg.src_rect.y1 >>= 16;
1092 pdpu->pipe_cfg.src_rect.y2 >>= 16;
1093
1094 pdpu->pipe_cfg.dst_rect = state->dst;
1095
1096 _dpu_plane_setup_scaler(pdpu, pstate, fmt, false);
1097
1098
1099 if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) {
1100
1101 return;
1102 }
1103
1104 if (pdpu->pipe_hw->ops.setup_rects) {
1105 pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
1106 &pdpu->pipe_cfg,
1107 pstate->multirect_index);
1108 }
1109
1110 if (pdpu->pipe_hw->ops.setup_pe &&
1111 (pstate->multirect_index != DPU_SSPP_RECT_1))
1112 pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
1113 &pstate->pixel_ext);
1114
1115
1116
1117
1118
1119
1120 if (pdpu->pipe_hw->ops.setup_scaler &&
1121 pstate->multirect_index != DPU_SSPP_RECT_1)
1122 pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
1123 &pdpu->pipe_cfg, &pstate->pixel_ext,
1124 &pstate->scaler3_cfg);
1125
1126 if (pdpu->pipe_hw->ops.setup_multirect)
1127 pdpu->pipe_hw->ops.setup_multirect(
1128 pdpu->pipe_hw,
1129 pstate->multirect_index,
1130 pstate->multirect_mode);
1131
1132 if (pdpu->pipe_hw->ops.setup_format) {
1133 unsigned int rotation;
1134
1135 src_flags = 0x0;
1136
1137 rotation = drm_rotation_simplify(state->rotation,
1138 DRM_MODE_ROTATE_0 |
1139 DRM_MODE_REFLECT_X |
1140 DRM_MODE_REFLECT_Y);
1141
1142 if (rotation & DRM_MODE_REFLECT_X)
1143 src_flags |= DPU_SSPP_FLIP_LR;
1144
1145 if (rotation & DRM_MODE_REFLECT_Y)
1146 src_flags |= DPU_SSPP_FLIP_UD;
1147
1148
1149 pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags,
1150 pstate->multirect_index);
1151
1152 if (pdpu->pipe_hw->ops.setup_cdp) {
1153 struct dpu_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
1154
1155 memset(cdp_cfg, 0, sizeof(struct dpu_hw_pipe_cdp_cfg));
1156
1157 cdp_cfg->enable = pdpu->catalog->perf.cdp_cfg
1158 [DPU_PERF_CDP_USAGE_RT].rd_enable;
1159 cdp_cfg->ubwc_meta_enable =
1160 DPU_FORMAT_IS_UBWC(fmt);
1161 cdp_cfg->tile_amortize_enable =
1162 DPU_FORMAT_IS_UBWC(fmt) ||
1163 DPU_FORMAT_IS_TILE(fmt);
1164 cdp_cfg->preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64;
1165
1166 pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, cdp_cfg);
1167 }
1168
1169
1170 if (DPU_FORMAT_IS_YUV(fmt))
1171 _dpu_plane_setup_csc(pdpu);
1172 else
1173 pdpu->csc_ptr = 0;
1174 }
1175
1176 _dpu_plane_set_qos_lut(plane, fb);
1177 _dpu_plane_set_danger_lut(plane, fb);
1178
1179 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
1180 _dpu_plane_set_qos_ctrl(plane, true, DPU_PLANE_QOS_PANIC_CTRL);
1181 _dpu_plane_set_ot_limit(plane, crtc);
1182 }
1183
1184 _dpu_plane_set_qos_remap(plane);
1185
1186 _dpu_plane_calc_bw(plane, fb);
1187
1188 _dpu_plane_calc_clk(plane);
1189}
1190
1191static void _dpu_plane_atomic_disable(struct drm_plane *plane)
1192{
1193 struct dpu_plane *pdpu = to_dpu_plane(plane);
1194 struct drm_plane_state *state = plane->state;
1195 struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1196
1197 trace_dpu_plane_disable(DRMID(plane), is_dpu_plane_virtual(plane),
1198 pstate->multirect_mode);
1199
1200 pstate->pending = true;
1201
1202 if (is_dpu_plane_virtual(plane) &&
1203 pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_multirect)
1204 pdpu->pipe_hw->ops.setup_multirect(pdpu->pipe_hw,
1205 DPU_SSPP_RECT_SOLO, DPU_SSPP_MULTIRECT_NONE);
1206}
1207
1208static void dpu_plane_atomic_update(struct drm_plane *plane,
1209 struct drm_plane_state *old_state)
1210{
1211 struct dpu_plane *pdpu = to_dpu_plane(plane);
1212 struct drm_plane_state *state = plane->state;
1213
1214 pdpu->is_error = false;
1215
1216 DPU_DEBUG_PLANE(pdpu, "\n");
1217
1218 if (!state->visible) {
1219 _dpu_plane_atomic_disable(plane);
1220 } else {
1221 dpu_plane_sspp_atomic_update(plane);
1222 }
1223}
1224
1225void dpu_plane_restore(struct drm_plane *plane)
1226{
1227 struct dpu_plane *pdpu;
1228
1229 if (!plane || !plane->state) {
1230 DPU_ERROR("invalid plane\n");
1231 return;
1232 }
1233
1234 pdpu = to_dpu_plane(plane);
1235
1236 DPU_DEBUG_PLANE(pdpu, "\n");
1237
1238
1239 dpu_plane_atomic_update(plane, plane->state);
1240}
1241
1242static void dpu_plane_destroy(struct drm_plane *plane)
1243{
1244 struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL;
1245
1246 DPU_DEBUG_PLANE(pdpu, "\n");
1247
1248 if (pdpu) {
1249 _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);
1250
1251 mutex_destroy(&pdpu->lock);
1252
1253
1254 drm_plane_cleanup(plane);
1255
1256 dpu_hw_sspp_destroy(pdpu->pipe_hw);
1257
1258 kfree(pdpu);
1259 }
1260}
1261
1262static void dpu_plane_destroy_state(struct drm_plane *plane,
1263 struct drm_plane_state *state)
1264{
1265 __drm_atomic_helper_plane_destroy_state(state);
1266 kfree(to_dpu_plane_state(state));
1267}
1268
1269static struct drm_plane_state *
1270dpu_plane_duplicate_state(struct drm_plane *plane)
1271{
1272 struct dpu_plane *pdpu;
1273 struct dpu_plane_state *pstate;
1274 struct dpu_plane_state *old_state;
1275
1276 if (!plane) {
1277 DPU_ERROR("invalid plane\n");
1278 return NULL;
1279 } else if (!plane->state) {
1280 DPU_ERROR("invalid plane state\n");
1281 return NULL;
1282 }
1283
1284 old_state = to_dpu_plane_state(plane->state);
1285 pdpu = to_dpu_plane(plane);
1286 pstate = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
1287 if (!pstate) {
1288 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n");
1289 return NULL;
1290 }
1291
1292 DPU_DEBUG_PLANE(pdpu, "\n");
1293
1294 pstate->pending = false;
1295
1296 __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
1297
1298 return &pstate->base;
1299}
1300
1301static void dpu_plane_reset(struct drm_plane *plane)
1302{
1303 struct dpu_plane *pdpu;
1304 struct dpu_plane_state *pstate;
1305
1306 if (!plane) {
1307 DPU_ERROR("invalid plane\n");
1308 return;
1309 }
1310
1311 pdpu = to_dpu_plane(plane);
1312 DPU_DEBUG_PLANE(pdpu, "\n");
1313
1314
1315 if (plane->state) {
1316 dpu_plane_destroy_state(plane, plane->state);
1317 plane->state = 0;
1318 }
1319
1320 pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);
1321 if (!pstate) {
1322 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n");
1323 return;
1324 }
1325
1326 pstate->base.plane = plane;
1327
1328 plane->state = &pstate->base;
1329}
1330
1331#ifdef CONFIG_DEBUG_FS
1332static void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
1333{
1334 struct dpu_plane *pdpu = to_dpu_plane(plane);
1335 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
1336
1337 if (!pdpu->is_rt_pipe)
1338 return;
1339
1340 pm_runtime_get_sync(&dpu_kms->pdev->dev);
1341 _dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL);
1342 pm_runtime_put_sync(&dpu_kms->pdev->dev);
1343}
1344
1345static ssize_t _dpu_plane_danger_read(struct file *file,
1346 char __user *buff, size_t count, loff_t *ppos)
1347{
1348 struct dpu_kms *kms = file->private_data;
1349 int len;
1350 char buf[40];
1351
1352 len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
1353
1354 return simple_read_from_buffer(buff, count, ppos, buf, len);
1355}
1356
1357static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool enable)
1358{
1359 struct drm_plane *plane;
1360
1361 drm_for_each_plane(plane, kms->dev) {
1362 if (plane->fb && plane->state) {
1363 dpu_plane_danger_signal_ctrl(plane, enable);
1364 DPU_DEBUG("plane:%d img:%dx%d ",
1365 plane->base.id, plane->fb->width,
1366 plane->fb->height);
1367 DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
1368 plane->state->src_x >> 16,
1369 plane->state->src_y >> 16,
1370 plane->state->src_w >> 16,
1371 plane->state->src_h >> 16,
1372 plane->state->crtc_x, plane->state->crtc_y,
1373 plane->state->crtc_w, plane->state->crtc_h);
1374 } else {
1375 DPU_DEBUG("Inactive plane:%d\n", plane->base.id);
1376 }
1377 }
1378}
1379
1380static ssize_t _dpu_plane_danger_write(struct file *file,
1381 const char __user *user_buf, size_t count, loff_t *ppos)
1382{
1383 struct dpu_kms *kms = file->private_data;
1384 int disable_panic;
1385 int ret;
1386
1387 ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic);
1388 if (ret)
1389 return ret;
1390
1391 if (disable_panic) {
1392
1393 DPU_DEBUG("Disabling danger:\n");
1394 _dpu_plane_set_danger_state(kms, false);
1395 kms->has_danger_ctrl = false;
1396 } else {
1397
1398 DPU_DEBUG("Enabling danger:\n");
1399 kms->has_danger_ctrl = true;
1400 _dpu_plane_set_danger_state(kms, true);
1401 }
1402
1403 return count;
1404}
1405
1406static const struct file_operations dpu_plane_danger_enable = {
1407 .open = simple_open,
1408 .read = _dpu_plane_danger_read,
1409 .write = _dpu_plane_danger_write,
1410};
1411
1412static int _dpu_plane_init_debugfs(struct drm_plane *plane)
1413{
1414 struct dpu_plane *pdpu = to_dpu_plane(plane);
1415 struct dpu_kms *kms = _dpu_plane_get_kms(plane);
1416 const struct dpu_sspp_cfg *cfg = pdpu->pipe_hw->cap;
1417 const struct dpu_sspp_sub_blks *sblk = cfg->sblk;
1418
1419
1420 pdpu->debugfs_root =
1421 debugfs_create_dir(pdpu->pipe_name,
1422 plane->dev->primary->debugfs_root);
1423
1424
1425 debugfs_create_x32("features", 0600,
1426 pdpu->debugfs_root, &pdpu->features);
1427
1428
1429 dpu_debugfs_setup_regset32(&pdpu->debugfs_src,
1430 sblk->src_blk.base + cfg->base,
1431 sblk->src_blk.len,
1432 kms);
1433 dpu_debugfs_create_regset32("src_blk", 0400,
1434 pdpu->debugfs_root, &pdpu->debugfs_src);
1435
1436 if (cfg->features & BIT(DPU_SSPP_SCALER_QSEED3) ||
1437 cfg->features & BIT(DPU_SSPP_SCALER_QSEED2) ||
1438 cfg->features & BIT(DPU_SSPP_SCALER_QSEED4)) {
1439 dpu_debugfs_setup_regset32(&pdpu->debugfs_scaler,
1440 sblk->scaler_blk.base + cfg->base,
1441 sblk->scaler_blk.len,
1442 kms);
1443 dpu_debugfs_create_regset32("scaler_blk", 0400,
1444 pdpu->debugfs_root,
1445 &pdpu->debugfs_scaler);
1446 debugfs_create_bool("default_scaling",
1447 0600,
1448 pdpu->debugfs_root,
1449 &pdpu->debugfs_default_scale);
1450 }
1451
1452 if (cfg->features & BIT(DPU_SSPP_CSC) ||
1453 cfg->features & BIT(DPU_SSPP_CSC_10BIT)) {
1454 dpu_debugfs_setup_regset32(&pdpu->debugfs_csc,
1455 sblk->csc_blk.base + cfg->base,
1456 sblk->csc_blk.len,
1457 kms);
1458 dpu_debugfs_create_regset32("csc_blk", 0400,
1459 pdpu->debugfs_root, &pdpu->debugfs_csc);
1460 }
1461
1462 debugfs_create_u32("xin_id",
1463 0400,
1464 pdpu->debugfs_root,
1465 (u32 *) &cfg->xin_id);
1466 debugfs_create_u32("clk_ctrl",
1467 0400,
1468 pdpu->debugfs_root,
1469 (u32 *) &cfg->clk_ctrl);
1470 debugfs_create_x32("creq_vblank",
1471 0600,
1472 pdpu->debugfs_root,
1473 (u32 *) &sblk->creq_vblank);
1474 debugfs_create_x32("danger_vblank",
1475 0600,
1476 pdpu->debugfs_root,
1477 (u32 *) &sblk->danger_vblank);
1478
1479 debugfs_create_file("disable_danger",
1480 0600,
1481 pdpu->debugfs_root,
1482 kms, &dpu_plane_danger_enable);
1483
1484 return 0;
1485}
1486#else
1487static int _dpu_plane_init_debugfs(struct drm_plane *plane)
1488{
1489 return 0;
1490}
1491#endif
1492
1493static int dpu_plane_late_register(struct drm_plane *plane)
1494{
1495 return _dpu_plane_init_debugfs(plane);
1496}
1497
1498static void dpu_plane_early_unregister(struct drm_plane *plane)
1499{
1500 struct dpu_plane *pdpu = to_dpu_plane(plane);
1501
1502 debugfs_remove_recursive(pdpu->debugfs_root);
1503}
1504
1505static bool dpu_plane_format_mod_supported(struct drm_plane *plane,
1506 uint32_t format, uint64_t modifier)
1507{
1508 if (modifier == DRM_FORMAT_MOD_LINEAR)
1509 return true;
1510
1511 if (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED) {
1512 int i;
1513 for (i = 0; i < ARRAY_SIZE(qcom_compressed_supported_formats); i++) {
1514 if (format == qcom_compressed_supported_formats[i])
1515 return true;
1516 }
1517 }
1518
1519 return false;
1520}
1521
1522static const struct drm_plane_funcs dpu_plane_funcs = {
1523 .update_plane = drm_atomic_helper_update_plane,
1524 .disable_plane = drm_atomic_helper_disable_plane,
1525 .destroy = dpu_plane_destroy,
1526 .reset = dpu_plane_reset,
1527 .atomic_duplicate_state = dpu_plane_duplicate_state,
1528 .atomic_destroy_state = dpu_plane_destroy_state,
1529 .late_register = dpu_plane_late_register,
1530 .early_unregister = dpu_plane_early_unregister,
1531 .format_mod_supported = dpu_plane_format_mod_supported,
1532};
1533
1534static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = {
1535 .prepare_fb = dpu_plane_prepare_fb,
1536 .cleanup_fb = dpu_plane_cleanup_fb,
1537 .atomic_check = dpu_plane_atomic_check,
1538 .atomic_update = dpu_plane_atomic_update,
1539};
1540
1541enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane)
1542{
1543 return plane ? to_dpu_plane(plane)->pipe : SSPP_NONE;
1544}
1545
1546bool is_dpu_plane_virtual(struct drm_plane *plane)
1547{
1548 return plane ? to_dpu_plane(plane)->is_virtual : false;
1549}
1550
1551
1552struct drm_plane *dpu_plane_init(struct drm_device *dev,
1553 uint32_t pipe, enum drm_plane_type type,
1554 unsigned long possible_crtcs, u32 master_plane_id)
1555{
1556 struct drm_plane *plane = NULL, *master_plane = NULL;
1557 const uint32_t *format_list;
1558 struct dpu_plane *pdpu;
1559 struct msm_drm_private *priv = dev->dev_private;
1560 struct dpu_kms *kms = to_dpu_kms(priv->kms);
1561 int zpos_max = DPU_ZPOS_MAX;
1562 uint32_t num_formats;
1563 int ret = -EINVAL;
1564
1565
1566 pdpu = kzalloc(sizeof(*pdpu), GFP_KERNEL);
1567 if (!pdpu) {
1568 DPU_ERROR("[%u]failed to allocate local plane struct\n", pipe);
1569 ret = -ENOMEM;
1570 return ERR_PTR(ret);
1571 }
1572
1573
1574 plane = &pdpu->base;
1575 pdpu->pipe = pipe;
1576 pdpu->is_virtual = (master_plane_id != 0);
1577 INIT_LIST_HEAD(&pdpu->mplane_list);
1578 master_plane = drm_plane_find(dev, NULL, master_plane_id);
1579 if (master_plane) {
1580 struct dpu_plane *mpdpu = to_dpu_plane(master_plane);
1581
1582 list_add_tail(&pdpu->mplane_list, &mpdpu->mplane_list);
1583 }
1584
1585
1586 pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog,
1587 master_plane_id != 0);
1588 if (IS_ERR(pdpu->pipe_hw)) {
1589 DPU_ERROR("[%u]SSPP init failed\n", pipe);
1590 ret = PTR_ERR(pdpu->pipe_hw);
1591 goto clean_plane;
1592 } else if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
1593 DPU_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
1594 goto clean_sspp;
1595 }
1596
1597
1598 pdpu->features = pdpu->pipe_hw->cap->features;
1599 pdpu->pipe_sblk = pdpu->pipe_hw->cap->sblk;
1600 if (!pdpu->pipe_sblk) {
1601 DPU_ERROR("[%u]invalid sblk\n", pipe);
1602 goto clean_sspp;
1603 }
1604
1605 if (pdpu->is_virtual) {
1606 format_list = pdpu->pipe_sblk->virt_format_list;
1607 num_formats = pdpu->pipe_sblk->virt_num_formats;
1608 }
1609 else {
1610 format_list = pdpu->pipe_sblk->format_list;
1611 num_formats = pdpu->pipe_sblk->num_formats;
1612 }
1613
1614 ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs,
1615 format_list, num_formats,
1616 supported_format_modifiers, type, NULL);
1617 if (ret)
1618 goto clean_sspp;
1619
1620 pdpu->catalog = kms->catalog;
1621
1622 if (kms->catalog->mixer_count &&
1623 kms->catalog->mixer[0].sblk->maxblendstages) {
1624 zpos_max = kms->catalog->mixer[0].sblk->maxblendstages - 1;
1625 if (zpos_max > DPU_STAGE_MAX - DPU_STAGE_0 - 1)
1626 zpos_max = DPU_STAGE_MAX - DPU_STAGE_0 - 1;
1627 }
1628
1629 ret = drm_plane_create_zpos_property(plane, 0, 0, zpos_max);
1630 if (ret)
1631 DPU_ERROR("failed to install zpos property, rc = %d\n", ret);
1632
1633 drm_plane_create_rotation_property(plane,
1634 DRM_MODE_ROTATE_0,
1635 DRM_MODE_ROTATE_0 |
1636 DRM_MODE_ROTATE_180 |
1637 DRM_MODE_REFLECT_X |
1638 DRM_MODE_REFLECT_Y);
1639
1640 drm_plane_enable_fb_damage_clips(plane);
1641
1642
1643 drm_plane_helper_add(plane, &dpu_plane_helper_funcs);
1644
1645
1646 snprintf(pdpu->pipe_name, DPU_NAME_SIZE, "plane%u", plane->base.id);
1647
1648 mutex_init(&pdpu->lock);
1649
1650 DPU_DEBUG("%s created for pipe:%u id:%u virtual:%u\n", pdpu->pipe_name,
1651 pipe, plane->base.id, master_plane_id);
1652 return plane;
1653
1654clean_sspp:
1655 if (pdpu && pdpu->pipe_hw)
1656 dpu_hw_sspp_destroy(pdpu->pipe_hw);
1657clean_plane:
1658 kfree(pdpu);
1659 return ERR_PTR(ret);
1660}
1661
