linux/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (C) 2013 Red Hat
   4 * Author: Rob Clark <robdclark@gmail.com>
   5 */
   6
   7#include <drm/drm_damage_helper.h>
   8#include <drm/drm_fourcc.h>
   9
  10#include "mdp4_kms.h"
  11
  12#define DOWN_SCALE_MAX  8
  13#define UP_SCALE_MAX    8
  14
  15struct mdp4_plane {
  16        struct drm_plane base;
  17        const char *name;
  18
  19        enum mdp4_pipe pipe;
  20
  21        uint32_t caps;
  22        uint32_t nformats;
  23        uint32_t formats[32];
  24
  25        bool enabled;
  26};
  27#define to_mdp4_plane(x) container_of(x, struct mdp4_plane, base)
  28
  29/* MDP format helper functions */
  30static inline
  31enum mdp4_frame_format mdp4_get_frame_format(struct drm_framebuffer *fb)
  32{
  33        bool is_tile = false;
  34
  35        if (fb->modifier == DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
  36                is_tile = true;
  37
  38        if (fb->format->format == DRM_FORMAT_NV12 && is_tile)
  39                return FRAME_TILE_YCBCR_420;
  40
  41        return FRAME_LINEAR;
  42}
  43
  44static void mdp4_plane_set_scanout(struct drm_plane *plane,
  45                struct drm_framebuffer *fb);
  46static int mdp4_plane_mode_set(struct drm_plane *plane,
  47                struct drm_crtc *crtc, struct drm_framebuffer *fb,
  48                int crtc_x, int crtc_y,
  49                unsigned int crtc_w, unsigned int crtc_h,
  50                uint32_t src_x, uint32_t src_y,
  51                uint32_t src_w, uint32_t src_h);
  52
  53static struct mdp4_kms *get_kms(struct drm_plane *plane)
  54{
  55        struct msm_drm_private *priv = plane->dev->dev_private;
  56        return to_mdp4_kms(to_mdp_kms(priv->kms));
  57}
  58
  59static void mdp4_plane_destroy(struct drm_plane *plane)
  60{
  61        struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
  62
  63        drm_plane_cleanup(plane);
  64
  65        kfree(mdp4_plane);
  66}
  67
  68/* helper to install properties which are common to planes and crtcs */
  69static void mdp4_plane_install_properties(struct drm_plane *plane,
  70                struct drm_mode_object *obj)
  71{
  72        // XXX
  73}
  74
  75static int mdp4_plane_set_property(struct drm_plane *plane,
  76                struct drm_property *property, uint64_t val)
  77{
  78        // XXX
  79        return -EINVAL;
  80}
  81
  82static const struct drm_plane_funcs mdp4_plane_funcs = {
  83                .update_plane = drm_atomic_helper_update_plane,
  84                .disable_plane = drm_atomic_helper_disable_plane,
  85                .destroy = mdp4_plane_destroy,
  86                .set_property = mdp4_plane_set_property,
  87                .reset = drm_atomic_helper_plane_reset,
  88                .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
  89                .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
  90};
  91
  92static void mdp4_plane_cleanup_fb(struct drm_plane *plane,
  93                                  struct drm_plane_state *old_state)
  94{
  95        struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
  96        struct mdp4_kms *mdp4_kms = get_kms(plane);
  97        struct msm_kms *kms = &mdp4_kms->base.base;
  98        struct drm_framebuffer *fb = old_state->fb;
  99
 100        if (!fb)
 101                return;
 102
 103        DBG("%s: cleanup: FB[%u]", mdp4_plane->name, fb->base.id);
 104        msm_framebuffer_cleanup(fb, kms->aspace);
 105}
 106
 107
 108static int mdp4_plane_atomic_check(struct drm_plane *plane,
 109                struct drm_plane_state *state)
 110{
 111        return 0;
 112}
 113
 114static void mdp4_plane_atomic_update(struct drm_plane *plane,
 115                                     struct drm_plane_state *old_state)
 116{
 117        struct drm_plane_state *state = plane->state;
 118        int ret;
 119
 120        ret = mdp4_plane_mode_set(plane,
 121                        state->crtc, state->fb,
 122                        state->crtc_x, state->crtc_y,
 123                        state->crtc_w, state->crtc_h,
 124                        state->src_x,  state->src_y,
 125                        state->src_w, state->src_h);
 126        /* atomic_check should have ensured that this doesn't fail */
 127        WARN_ON(ret < 0);
 128}
 129
 130static const struct drm_plane_helper_funcs mdp4_plane_helper_funcs = {
 131                .prepare_fb = msm_atomic_prepare_fb,
 132                .cleanup_fb = mdp4_plane_cleanup_fb,
 133                .atomic_check = mdp4_plane_atomic_check,
 134                .atomic_update = mdp4_plane_atomic_update,
 135};
 136
 137static void mdp4_plane_set_scanout(struct drm_plane *plane,
 138                struct drm_framebuffer *fb)
 139{
 140        struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
 141        struct mdp4_kms *mdp4_kms = get_kms(plane);
 142        struct msm_kms *kms = &mdp4_kms->base.base;
 143        enum mdp4_pipe pipe = mdp4_plane->pipe;
 144
 145        mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_A(pipe),
 146                        MDP4_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) |
 147                        MDP4_PIPE_SRC_STRIDE_A_P1(fb->pitches[1]));
 148
 149        mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_B(pipe),
 150                        MDP4_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) |
 151                        MDP4_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
 152
 153        mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP0_BASE(pipe),
 154                        msm_framebuffer_iova(fb, kms->aspace, 0));
 155        mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP1_BASE(pipe),
 156                        msm_framebuffer_iova(fb, kms->aspace, 1));
 157        mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP2_BASE(pipe),
 158                        msm_framebuffer_iova(fb, kms->aspace, 2));
 159        mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP3_BASE(pipe),
 160                        msm_framebuffer_iova(fb, kms->aspace, 3));
 161}
 162
 163static void mdp4_write_csc_config(struct mdp4_kms *mdp4_kms,
 164                enum mdp4_pipe pipe, struct csc_cfg *csc)
 165{
 166        int i;
 167
 168        for (i = 0; i < ARRAY_SIZE(csc->matrix); i++) {
 169                mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_MV(pipe, i),
 170                                csc->matrix[i]);
 171        }
 172
 173        for (i = 0; i < ARRAY_SIZE(csc->post_bias) ; i++) {
 174                mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_PRE_BV(pipe, i),
 175                                csc->pre_bias[i]);
 176
 177                mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_POST_BV(pipe, i),
 178                                csc->post_bias[i]);
 179        }
 180
 181        for (i = 0; i < ARRAY_SIZE(csc->post_clamp) ; i++) {
 182                mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_PRE_LV(pipe, i),
 183                                csc->pre_clamp[i]);
 184
 185                mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_POST_LV(pipe, i),
 186                                csc->post_clamp[i]);
 187        }
 188}
 189
 190#define MDP4_VG_PHASE_STEP_DEFAULT      0x20000000
 191
 192static int mdp4_plane_mode_set(struct drm_plane *plane,
 193                struct drm_crtc *crtc, struct drm_framebuffer *fb,
 194                int crtc_x, int crtc_y,
 195                unsigned int crtc_w, unsigned int crtc_h,
 196                uint32_t src_x, uint32_t src_y,
 197                uint32_t src_w, uint32_t src_h)
 198{
 199        struct drm_device *dev = plane->dev;
 200        struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
 201        struct mdp4_kms *mdp4_kms = get_kms(plane);
 202        enum mdp4_pipe pipe = mdp4_plane->pipe;
 203        const struct mdp_format *format;
 204        uint32_t op_mode = 0;
 205        uint32_t phasex_step = MDP4_VG_PHASE_STEP_DEFAULT;
 206        uint32_t phasey_step = MDP4_VG_PHASE_STEP_DEFAULT;
 207        enum mdp4_frame_format frame_type;
 208
 209        if (!(crtc && fb)) {
 210                DBG("%s: disabled!", mdp4_plane->name);
 211                return 0;
 212        }
 213
 214        frame_type = mdp4_get_frame_format(fb);
 215
 216        /* src values are in Q16 fixed point, convert to integer: */
 217        src_x = src_x >> 16;
 218        src_y = src_y >> 16;
 219        src_w = src_w >> 16;
 220        src_h = src_h >> 16;
 221
 222        DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", mdp4_plane->name,
 223                        fb->base.id, src_x, src_y, src_w, src_h,
 224                        crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
 225
 226        format = to_mdp_format(msm_framebuffer_format(fb));
 227
 228        if (src_w > (crtc_w * DOWN_SCALE_MAX)) {
 229                DRM_DEV_ERROR(dev->dev, "Width down scaling exceeds limits!\n");
 230                return -ERANGE;
 231        }
 232
 233        if (src_h > (crtc_h * DOWN_SCALE_MAX)) {
 234                DRM_DEV_ERROR(dev->dev, "Height down scaling exceeds limits!\n");
 235                return -ERANGE;
 236        }
 237
 238        if (crtc_w > (src_w * UP_SCALE_MAX)) {
 239                DRM_DEV_ERROR(dev->dev, "Width up scaling exceeds limits!\n");
 240                return -ERANGE;
 241        }
 242
 243        if (crtc_h > (src_h * UP_SCALE_MAX)) {
 244                DRM_DEV_ERROR(dev->dev, "Height up scaling exceeds limits!\n");
 245                return -ERANGE;
 246        }
 247
 248        if (src_w != crtc_w) {
 249                uint32_t sel_unit = SCALE_FIR;
 250                op_mode |= MDP4_PIPE_OP_MODE_SCALEX_EN;
 251
 252                if (MDP_FORMAT_IS_YUV(format)) {
 253                        if (crtc_w > src_w)
 254                                sel_unit = SCALE_PIXEL_RPT;
 255                        else if (crtc_w <= (src_w / 4))
 256                                sel_unit = SCALE_MN_PHASE;
 257
 258                        op_mode |= MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(sel_unit);
 259                        phasex_step = mult_frac(MDP4_VG_PHASE_STEP_DEFAULT,
 260                                        src_w, crtc_w);
 261                }
 262        }
 263
 264        if (src_h != crtc_h) {
 265                uint32_t sel_unit = SCALE_FIR;
 266                op_mode |= MDP4_PIPE_OP_MODE_SCALEY_EN;
 267
 268                if (MDP_FORMAT_IS_YUV(format)) {
 269
 270                        if (crtc_h > src_h)
 271                                sel_unit = SCALE_PIXEL_RPT;
 272                        else if (crtc_h <= (src_h / 4))
 273                                sel_unit = SCALE_MN_PHASE;
 274
 275                        op_mode |= MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(sel_unit);
 276                        phasey_step = mult_frac(MDP4_VG_PHASE_STEP_DEFAULT,
 277                                        src_h, crtc_h);
 278                }
 279        }
 280
 281        mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_SIZE(pipe),
 282                        MDP4_PIPE_SRC_SIZE_WIDTH(src_w) |
 283                        MDP4_PIPE_SRC_SIZE_HEIGHT(src_h));
 284
 285        mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_XY(pipe),
 286                        MDP4_PIPE_SRC_XY_X(src_x) |
 287                        MDP4_PIPE_SRC_XY_Y(src_y));
 288
 289        mdp4_write(mdp4_kms, REG_MDP4_PIPE_DST_SIZE(pipe),
 290                        MDP4_PIPE_DST_SIZE_WIDTH(crtc_w) |
 291                        MDP4_PIPE_DST_SIZE_HEIGHT(crtc_h));
 292
 293        mdp4_write(mdp4_kms, REG_MDP4_PIPE_DST_XY(pipe),
 294                        MDP4_PIPE_DST_XY_X(crtc_x) |
 295                        MDP4_PIPE_DST_XY_Y(crtc_y));
 296
 297        mdp4_plane_set_scanout(plane, fb);
 298
 299        mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_FORMAT(pipe),
 300                        MDP4_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
 301                        MDP4_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
 302                        MDP4_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
 303                        MDP4_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
 304                        COND(format->alpha_enable, MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
 305                        MDP4_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
 306                        MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
 307                        MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(format->fetch_type) |
 308                        MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample) |
 309                        MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(frame_type) |
 310                        COND(format->unpack_tight, MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT));
 311
 312        mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_UNPACK(pipe),
 313                        MDP4_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
 314                        MDP4_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
 315                        MDP4_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
 316                        MDP4_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
 317
 318        if (MDP_FORMAT_IS_YUV(format)) {
 319                struct csc_cfg *csc = mdp_get_default_csc_cfg(CSC_YUV2RGB);
 320
 321                op_mode |= MDP4_PIPE_OP_MODE_SRC_YCBCR;
 322                op_mode |= MDP4_PIPE_OP_MODE_CSC_EN;
 323                mdp4_write_csc_config(mdp4_kms, pipe, csc);
 324        }
 325
 326        mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(pipe), op_mode);
 327        mdp4_write(mdp4_kms, REG_MDP4_PIPE_PHASEX_STEP(pipe), phasex_step);
 328        mdp4_write(mdp4_kms, REG_MDP4_PIPE_PHASEY_STEP(pipe), phasey_step);
 329
 330        if (frame_type != FRAME_LINEAR)
 331                mdp4_write(mdp4_kms, REG_MDP4_PIPE_SSTILE_FRAME_SIZE(pipe),
 332                                MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(src_w) |
 333                                MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(src_h));
 334
 335        return 0;
 336}
 337
 338static const char *pipe_names[] = {
 339                "VG1", "VG2",
 340                "RGB1", "RGB2", "RGB3",
 341                "VG3", "VG4",
 342};
 343
 344enum mdp4_pipe mdp4_plane_pipe(struct drm_plane *plane)
 345{
 346        struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
 347        return mdp4_plane->pipe;
 348}
 349
 350/* initialize plane */
 351struct drm_plane *mdp4_plane_init(struct drm_device *dev,
 352                enum mdp4_pipe pipe_id, bool private_plane)
 353{
 354        struct drm_plane *plane = NULL;
 355        struct mdp4_plane *mdp4_plane;
 356        int ret;
 357        enum drm_plane_type type;
 358
 359        mdp4_plane = kzalloc(sizeof(*mdp4_plane), GFP_KERNEL);
 360        if (!mdp4_plane) {
 361                ret = -ENOMEM;
 362                goto fail;
 363        }
 364
 365        plane = &mdp4_plane->base;
 366
 367        mdp4_plane->pipe = pipe_id;
 368        mdp4_plane->name = pipe_names[pipe_id];
 369        mdp4_plane->caps = mdp4_pipe_caps(pipe_id);
 370
 371        mdp4_plane->nformats = mdp_get_formats(mdp4_plane->formats,
 372                        ARRAY_SIZE(mdp4_plane->formats),
 373                        !pipe_supports_yuv(mdp4_plane->caps));
 374
 375        type = private_plane ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
 376        ret = drm_universal_plane_init(dev, plane, 0xff, &mdp4_plane_funcs,
 377                                 mdp4_plane->formats, mdp4_plane->nformats,
 378                                 NULL, type, NULL);
 379        if (ret)
 380                goto fail;
 381
 382        drm_plane_helper_add(plane, &mdp4_plane_helper_funcs);
 383
 384        mdp4_plane_install_properties(plane, &plane->base);
 385
 386        drm_plane_enable_fb_damage_clips(plane);
 387
 388        return plane;
 389
 390fail:
 391        if (plane)
 392                mdp4_plane_destroy(plane);
 393
 394        return ERR_PTR(ret);
 395}
 396