1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (c) 2016 MediaTek Inc. 4 * Author: Ming Hsiu Tsai <minghsiu.tsai@mediatek.com> 5 * Rick Chang <rick.chang@mediatek.com> 6 * Xia Jiang <xia.jiang@mediatek.com> 7 */ 8 9#ifndef _MTK_JPEG_DEC_HW_H 10#define _MTK_JPEG_DEC_HW_H 11 12#include <media/videobuf2-core.h> 13 14#include "mtk_jpeg_core.h" 15#include "mtk_jpeg_dec_reg.h" 16 17enum { 18 MTK_JPEG_DEC_RESULT_EOF_DONE = 0, 19 MTK_JPEG_DEC_RESULT_PAUSE = 1, 20 MTK_JPEG_DEC_RESULT_UNDERFLOW = 2, 21 MTK_JPEG_DEC_RESULT_OVERFLOW = 3, 22 MTK_JPEG_DEC_RESULT_ERROR_BS = 4, 23 MTK_JPEG_DEC_RESULT_ERROR_UNKNOWN = 6 24}; 25 26struct mtk_jpeg_dec_param { 27 u32 pic_w; 28 u32 pic_h; 29 u32 dec_w; 30 u32 dec_h; 31 u32 src_color; 32 u32 dst_fourcc; 33 u32 mcu_w; 34 u32 mcu_h; 35 u32 total_mcu; 36 u32 unit_num; 37 u32 comp_num; 38 u32 comp_id[MTK_JPEG_COMP_MAX]; 39 u32 sampling_w[MTK_JPEG_COMP_MAX]; 40 u32 sampling_h[MTK_JPEG_COMP_MAX]; 41 u32 qtbl_num[MTK_JPEG_COMP_MAX]; 42 u32 blk_num; 43 u32 blk_comp[MTK_JPEG_COMP_MAX]; 44 u32 membership; 45 u32 dma_mcu; 46 u32 dma_group; 47 u32 dma_last_mcu; 48 u32 img_stride[MTK_JPEG_COMP_MAX]; 49 u32 mem_stride[MTK_JPEG_COMP_MAX]; 50 u32 comp_w[MTK_JPEG_COMP_MAX]; 51 u32 comp_size[MTK_JPEG_COMP_MAX]; 52 u32 y_size; 53 u32 uv_size; 54 u32 dec_size; 55 u8 uv_brz_w; 56}; 57 58struct mtk_jpeg_bs { 59 dma_addr_t str_addr; 60 dma_addr_t end_addr; 61 size_t size; 62}; 63 64struct mtk_jpeg_fb { 65 dma_addr_t plane_addr[MTK_JPEG_COMP_MAX]; 66 size_t size; 67}; 68 69int mtk_jpeg_dec_fill_param(struct mtk_jpeg_dec_param *param); 70u32 mtk_jpeg_dec_get_int_status(void __iomem *dec_reg_base); 71u32 mtk_jpeg_dec_enum_result(u32 irq_result); 72void mtk_jpeg_dec_set_config(void __iomem *base, 73 struct mtk_jpeg_dec_param *config, 74 struct mtk_jpeg_bs *bs, 75 struct mtk_jpeg_fb *fb); 76void mtk_jpeg_dec_reset(void __iomem *dec_reg_base); 77void mtk_jpeg_dec_start(void __iomem *dec_reg_base); 78 79#endif /* _MTK_JPEG_HW_H */ 80