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5
6#ifndef ENA_H
7#define ENA_H
8
9#include <linux/bitops.h>
10#include <linux/dim.h>
11#include <linux/etherdevice.h>
12#include <linux/if_vlan.h>
13#include <linux/inetdevice.h>
14#include <linux/interrupt.h>
15#include <linux/netdevice.h>
16#include <linux/skbuff.h>
17
18#include "ena_com.h"
19#include "ena_eth_com.h"
20
21#define DRV_MODULE_GEN_MAJOR 2
22#define DRV_MODULE_GEN_MINOR 1
23#define DRV_MODULE_GEN_SUBMINOR 0
24
25#define DRV_MODULE_NAME "ena"
26
27#define DEVICE_NAME "Elastic Network Adapter (ENA)"
28
29
30#define ENA_ADMIN_MSIX_VEC 1
31#define ENA_MAX_MSIX_VEC(io_queues) (ENA_ADMIN_MSIX_VEC + (io_queues))
32
33
34
35
36
37
38#if PAGE_SIZE > SZ_16K
39#define ENA_PAGE_SIZE (_AC(SZ_16K, UL))
40#else
41#define ENA_PAGE_SIZE PAGE_SIZE
42#endif
43
44#define ENA_MIN_MSIX_VEC 2
45
46#define ENA_REG_BAR 0
47#define ENA_MEM_BAR 2
48#define ENA_BAR_MASK (BIT(ENA_REG_BAR) | BIT(ENA_MEM_BAR))
49
50#define ENA_DEFAULT_RING_SIZE (1024)
51#define ENA_MIN_RING_SIZE (256)
52
53#define ENA_MIN_NUM_IO_QUEUES (1)
54
55#define ENA_TX_WAKEUP_THRESH (MAX_SKB_FRAGS + 2)
56#define ENA_DEFAULT_RX_COPYBREAK (256 - NET_IP_ALIGN)
57
58
59
60
61
62#define ENA_DEFAULT_MIN_RX_BUFF_ALLOC_SIZE 600
63
64#define ENA_MIN_MTU 128
65
66#define ENA_NAME_MAX_LEN 20
67#define ENA_IRQNAME_SIZE 40
68
69#define ENA_PKT_MAX_BUFS 19
70
71#define ENA_RX_RSS_TABLE_LOG_SIZE 7
72#define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
73
74
75
76
77#define ENA_TX_POLL_BUDGET_DIVIDER 4
78
79
80
81
82#define ENA_RX_REFILL_THRESH_DIVIDER 8
83#define ENA_RX_REFILL_THRESH_PACKET 256
84
85
86#define ENA_MONITORED_TX_QUEUES 4
87
88#define MAX_NUM_OF_TIMEOUTED_PACKETS 128
89
90#define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
91
92#define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
93#define ENA_RX_RING_IDX_ADD(idx, n, ring_size) \
94 (((idx) + (n)) & ((ring_size) - 1))
95
96#define ENA_IO_TXQ_IDX(q) (2 * (q))
97#define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
98#define ENA_IO_TXQ_IDX_TO_COMBINED_IDX(q) ((q) / 2)
99#define ENA_IO_RXQ_IDX_TO_COMBINED_IDX(q) (((q) - 1) / 2)
100
101#define ENA_MGMNT_IRQ_IDX 0
102#define ENA_IO_IRQ_FIRST_IDX 1
103#define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q))
104
105#define ENA_ADMIN_POLL_DELAY_US 100
106
107
108
109
110#define ENA_DEVICE_KALIVE_TIMEOUT (6 * HZ)
111#define ENA_MAX_NO_INTERRUPT_ITERATIONS 3
112
113#define ENA_MMIO_DISABLE_REG_READ BIT(0)
114
115
116
117
118
119
120
121#define ENA_XDP_MAX_MTU (ENA_PAGE_SIZE - ETH_HLEN - ETH_FCS_LEN - \
122 VLAN_HLEN - XDP_PACKET_HEADROOM - \
123 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
124
125#define ENA_IS_XDP_INDEX(adapter, index) (((index) >= (adapter)->xdp_first_ring) && \
126 ((index) < (adapter)->xdp_first_ring + (adapter)->xdp_num_queues))
127
128struct ena_irq {
129 irq_handler_t handler;
130 void *data;
131 int cpu;
132 u32 vector;
133 cpumask_t affinity_hint_mask;
134 char name[ENA_IRQNAME_SIZE];
135};
136
137struct ena_napi {
138 struct napi_struct napi ____cacheline_aligned;
139 struct ena_ring *tx_ring;
140 struct ena_ring *rx_ring;
141 struct ena_ring *xdp_ring;
142 bool first_interrupt;
143 bool interrupts_masked;
144 u32 qid;
145 struct dim dim;
146};
147
148struct ena_calc_queue_size_ctx {
149 struct ena_com_dev_get_features_ctx *get_feat_ctx;
150 struct ena_com_dev *ena_dev;
151 struct pci_dev *pdev;
152 u32 tx_queue_size;
153 u32 rx_queue_size;
154 u32 max_tx_queue_size;
155 u32 max_rx_queue_size;
156 u16 max_tx_sgl_size;
157 u16 max_rx_sgl_size;
158};
159
160struct ena_tx_buffer {
161 struct sk_buff *skb;
162
163
164
165 u32 tx_descs;
166
167 u32 num_of_bufs;
168
169
170
171
172 struct xdp_frame *xdpf;
173
174
175
176
177
178 struct page *xdp_rx_page;
179
180
181 u8 map_linear_data;
182
183
184 u32 print_once;
185
186
187
188
189
190
191
192
193
194 unsigned long last_jiffies;
195 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
196} ____cacheline_aligned;
197
198struct ena_rx_buffer {
199 struct sk_buff *skb;
200 struct page *page;
201 u32 page_offset;
202 struct ena_com_buf ena_buf;
203} ____cacheline_aligned;
204
205struct ena_stats_tx {
206 u64 cnt;
207 u64 bytes;
208 u64 queue_stop;
209 u64 prepare_ctx_err;
210 u64 queue_wakeup;
211 u64 dma_mapping_err;
212 u64 linearize;
213 u64 linearize_failed;
214 u64 napi_comp;
215 u64 tx_poll;
216 u64 doorbells;
217 u64 bad_req_id;
218 u64 llq_buffer_copy;
219 u64 missed_tx;
220 u64 unmask_interrupt;
221};
222
223struct ena_stats_rx {
224 u64 cnt;
225 u64 bytes;
226 u64 rx_copybreak_pkt;
227 u64 csum_good;
228 u64 refil_partial;
229 u64 bad_csum;
230 u64 page_alloc_fail;
231 u64 skb_alloc_fail;
232 u64 dma_mapping_err;
233 u64 bad_desc_num;
234 u64 bad_req_id;
235 u64 empty_rx_ring;
236 u64 csum_unchecked;
237 u64 xdp_aborted;
238 u64 xdp_drop;
239 u64 xdp_pass;
240 u64 xdp_tx;
241 u64 xdp_invalid;
242};
243
244struct ena_ring {
245
246
247
248 u16 *free_ids;
249
250 union {
251 struct ena_tx_buffer *tx_buffer_info;
252 struct ena_rx_buffer *rx_buffer_info;
253 };
254
255
256 struct device *dev;
257 struct pci_dev *pdev;
258 struct napi_struct *napi;
259 struct net_device *netdev;
260 struct ena_com_dev *ena_dev;
261 struct ena_adapter *adapter;
262 struct ena_com_io_cq *ena_com_io_cq;
263 struct ena_com_io_sq *ena_com_io_sq;
264 struct bpf_prog *xdp_bpf_prog;
265 struct xdp_rxq_info xdp_rxq;
266
267 u16 next_to_use;
268 u16 next_to_clean;
269 u16 rx_copybreak;
270 u16 rx_headroom;
271 u16 qid;
272 u16 mtu;
273 u16 sgl_size;
274
275
276 u8 tx_max_header_size;
277
278 bool first_interrupt;
279 bool disable_meta_caching;
280 u16 no_interrupt_event_cnt;
281
282
283 int cpu;
284
285 int ring_size;
286
287 enum ena_admin_placement_policy_type tx_mem_queue_type;
288
289 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS];
290 u32 smoothed_interval;
291 u32 per_napi_packets;
292 u16 non_empty_napi_events;
293 struct u64_stats_sync syncp;
294 union {
295 struct ena_stats_tx tx_stats;
296 struct ena_stats_rx rx_stats;
297 };
298
299 u8 *push_buf_intermediate_buf;
300 int empty_rx_queue;
301} ____cacheline_aligned;
302
303struct ena_stats_dev {
304 u64 tx_timeout;
305 u64 suspend;
306 u64 resume;
307 u64 wd_expired;
308 u64 interface_up;
309 u64 interface_down;
310 u64 admin_q_pause;
311 u64 rx_drops;
312 u64 tx_drops;
313};
314
315enum ena_flags_t {
316 ENA_FLAG_DEVICE_RUNNING,
317 ENA_FLAG_DEV_UP,
318 ENA_FLAG_LINK_UP,
319 ENA_FLAG_MSIX_ENABLED,
320 ENA_FLAG_TRIGGER_RESET,
321 ENA_FLAG_ONGOING_RESET
322};
323
324
325struct ena_adapter {
326 struct ena_com_dev *ena_dev;
327
328 struct net_device *netdev;
329 struct pci_dev *pdev;
330
331
332
333
334 u32 rx_copybreak;
335 u32 max_mtu;
336
337 u32 num_io_queues;
338 u32 max_num_io_queues;
339
340 int msix_vecs;
341
342 u32 missing_tx_completion_threshold;
343
344 u32 requested_tx_ring_size;
345 u32 requested_rx_ring_size;
346
347 u32 max_tx_ring_size;
348 u32 max_rx_ring_size;
349
350 u32 msg_enable;
351
352 u16 max_tx_sgl_size;
353 u16 max_rx_sgl_size;
354
355 u8 mac_addr[ETH_ALEN];
356
357 unsigned long keep_alive_timeout;
358 unsigned long missing_tx_completion_to;
359
360 char name[ENA_NAME_MAX_LEN];
361
362 unsigned long flags;
363
364 struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES]
365 ____cacheline_aligned_in_smp;
366
367
368 struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES]
369 ____cacheline_aligned_in_smp;
370
371 struct ena_napi ena_napi[ENA_MAX_NUM_IO_QUEUES];
372
373 struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)];
374
375
376 struct work_struct reset_task;
377 struct timer_list timer_service;
378
379 bool wd_state;
380 bool dev_up_before_reset;
381 bool disable_meta_caching;
382 unsigned long last_keep_alive_jiffies;
383
384 struct u64_stats_sync syncp;
385 struct ena_stats_dev dev_stats;
386 struct ena_admin_eni_stats eni_stats;
387 bool eni_stats_supported;
388
389
390 u32 last_monitored_tx_qid;
391
392 enum ena_regs_reset_reason_types reset_reason;
393
394 struct bpf_prog *xdp_bpf_prog;
395 u32 xdp_first_ring;
396 u32 xdp_num_queues;
397};
398
399void ena_set_ethtool_ops(struct net_device *netdev);
400
401void ena_dump_stats_to_dmesg(struct ena_adapter *adapter);
402
403void ena_dump_stats_to_buf(struct ena_adapter *adapter, u8 *buf);
404
405int ena_update_hw_stats(struct ena_adapter *adapter);
406
407int ena_update_queue_sizes(struct ena_adapter *adapter,
408 u32 new_tx_size,
409 u32 new_rx_size);
410
411int ena_update_queue_count(struct ena_adapter *adapter, u32 new_channel_count);
412
413int ena_get_sset_count(struct net_device *netdev, int sset);
414
415enum ena_xdp_errors_t {
416 ENA_XDP_ALLOWED = 0,
417 ENA_XDP_CURRENT_MTU_TOO_LARGE,
418 ENA_XDP_NO_ENOUGH_QUEUES,
419};
420
421static inline bool ena_xdp_queues_present(struct ena_adapter *adapter)
422{
423 return adapter->xdp_first_ring != 0;
424}
425
426static inline bool ena_xdp_present(struct ena_adapter *adapter)
427{
428 return !!adapter->xdp_bpf_prog;
429}
430
431static inline bool ena_xdp_present_ring(struct ena_ring *ring)
432{
433 return !!ring->xdp_bpf_prog;
434}
435
436static inline int ena_xdp_legal_queue_count(struct ena_adapter *adapter,
437 u32 queues)
438{
439 return 2 * queues <= adapter->max_num_io_queues;
440}
441
442static inline enum ena_xdp_errors_t ena_xdp_allowed(struct ena_adapter *adapter)
443{
444 enum ena_xdp_errors_t rc = ENA_XDP_ALLOWED;
445
446 if (adapter->netdev->mtu > ENA_XDP_MAX_MTU)
447 rc = ENA_XDP_CURRENT_MTU_TOO_LARGE;
448 else if (!ena_xdp_legal_queue_count(adapter, adapter->num_io_queues))
449 rc = ENA_XDP_NO_ENOUGH_QUEUES;
450
451 return rc;
452}
453
454#endif
455