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13#include <linux/crc32.h>
14#include <linux/etherdevice.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
20#include <linux/of_mdio.h>
21#include <linux/of_net.h>
22#include <linux/of_platform.h>
23
24#include "emac.h"
25
26static void arc_emac_restart(struct net_device *ndev);
27
28
29
30
31
32
33
34static inline int arc_emac_tx_avail(struct arc_emac_priv *priv)
35{
36 return (priv->txbd_dirty + TX_BD_NUM - priv->txbd_curr - 1) % TX_BD_NUM;
37}
38
39
40
41
42
43
44
45
46static void arc_emac_adjust_link(struct net_device *ndev)
47{
48 struct arc_emac_priv *priv = netdev_priv(ndev);
49 struct phy_device *phy_dev = ndev->phydev;
50 unsigned int reg, state_changed = 0;
51
52 if (priv->link != phy_dev->link) {
53 priv->link = phy_dev->link;
54 state_changed = 1;
55 }
56
57 if (priv->speed != phy_dev->speed) {
58 priv->speed = phy_dev->speed;
59 state_changed = 1;
60 if (priv->set_mac_speed)
61 priv->set_mac_speed(priv, priv->speed);
62 }
63
64 if (priv->duplex != phy_dev->duplex) {
65 reg = arc_reg_get(priv, R_CTRL);
66
67 if (phy_dev->duplex == DUPLEX_FULL)
68 reg |= ENFL_MASK;
69 else
70 reg &= ~ENFL_MASK;
71
72 arc_reg_set(priv, R_CTRL, reg);
73 priv->duplex = phy_dev->duplex;
74 state_changed = 1;
75 }
76
77 if (state_changed)
78 phy_print_status(phy_dev);
79}
80
81
82
83
84
85
86
87
88
89static void arc_emac_get_drvinfo(struct net_device *ndev,
90 struct ethtool_drvinfo *info)
91{
92 struct arc_emac_priv *priv = netdev_priv(ndev);
93
94 strlcpy(info->driver, priv->drv_name, sizeof(info->driver));
95}
96
97static const struct ethtool_ops arc_emac_ethtool_ops = {
98 .get_drvinfo = arc_emac_get_drvinfo,
99 .get_link = ethtool_op_get_link,
100 .get_link_ksettings = phy_ethtool_get_link_ksettings,
101 .set_link_ksettings = phy_ethtool_set_link_ksettings,
102};
103
104#define FIRST_OR_LAST_MASK (FIRST_MASK | LAST_MASK)
105
106
107
108
109
110static void arc_emac_tx_clean(struct net_device *ndev)
111{
112 struct arc_emac_priv *priv = netdev_priv(ndev);
113 struct net_device_stats *stats = &ndev->stats;
114 unsigned int i;
115
116 for (i = 0; i < TX_BD_NUM; i++) {
117 unsigned int *txbd_dirty = &priv->txbd_dirty;
118 struct arc_emac_bd *txbd = &priv->txbd[*txbd_dirty];
119 struct buffer_state *tx_buff = &priv->tx_buff[*txbd_dirty];
120 struct sk_buff *skb = tx_buff->skb;
121 unsigned int info = le32_to_cpu(txbd->info);
122
123 if ((info & FOR_EMAC) || !txbd->data || !skb)
124 break;
125
126 if (unlikely(info & (DROP | DEFR | LTCL | UFLO))) {
127 stats->tx_errors++;
128 stats->tx_dropped++;
129
130 if (info & DEFR)
131 stats->tx_carrier_errors++;
132
133 if (info & LTCL)
134 stats->collisions++;
135
136 if (info & UFLO)
137 stats->tx_fifo_errors++;
138 } else if (likely(info & FIRST_OR_LAST_MASK)) {
139 stats->tx_packets++;
140 stats->tx_bytes += skb->len;
141 }
142
143 dma_unmap_single(&ndev->dev, dma_unmap_addr(tx_buff, addr),
144 dma_unmap_len(tx_buff, len), DMA_TO_DEVICE);
145
146
147 dev_consume_skb_irq(skb);
148
149 txbd->data = 0;
150 txbd->info = 0;
151 tx_buff->skb = NULL;
152
153 *txbd_dirty = (*txbd_dirty + 1) % TX_BD_NUM;
154 }
155
156
157
158
159 smp_mb();
160
161 if (netif_queue_stopped(ndev) && arc_emac_tx_avail(priv))
162 netif_wake_queue(ndev);
163}
164
165
166
167
168
169
170
171
172
173
174static int arc_emac_rx(struct net_device *ndev, int budget)
175{
176 struct arc_emac_priv *priv = netdev_priv(ndev);
177 unsigned int work_done;
178
179 for (work_done = 0; work_done < budget; work_done++) {
180 unsigned int *last_rx_bd = &priv->last_rx_bd;
181 struct net_device_stats *stats = &ndev->stats;
182 struct buffer_state *rx_buff = &priv->rx_buff[*last_rx_bd];
183 struct arc_emac_bd *rxbd = &priv->rxbd[*last_rx_bd];
184 unsigned int pktlen, info = le32_to_cpu(rxbd->info);
185 struct sk_buff *skb;
186 dma_addr_t addr;
187
188 if (unlikely((info & OWN_MASK) == FOR_EMAC))
189 break;
190
191
192
193
194 *last_rx_bd = (*last_rx_bd + 1) % RX_BD_NUM;
195
196 if (unlikely((info & FIRST_OR_LAST_MASK) !=
197 FIRST_OR_LAST_MASK)) {
198
199
200
201 if (net_ratelimit())
202 netdev_err(ndev, "incomplete packet received\n");
203
204
205 rxbd->info = cpu_to_le32(FOR_EMAC | EMAC_BUFFER_SIZE);
206 stats->rx_errors++;
207 stats->rx_length_errors++;
208 continue;
209 }
210
211
212
213
214
215 skb = netdev_alloc_skb_ip_align(ndev, EMAC_BUFFER_SIZE);
216 if (unlikely(!skb)) {
217 if (net_ratelimit())
218 netdev_err(ndev, "cannot allocate skb\n");
219
220 rxbd->info = cpu_to_le32(FOR_EMAC | EMAC_BUFFER_SIZE);
221 stats->rx_errors++;
222 stats->rx_dropped++;
223 continue;
224 }
225
226 addr = dma_map_single(&ndev->dev, (void *)skb->data,
227 EMAC_BUFFER_SIZE, DMA_FROM_DEVICE);
228 if (dma_mapping_error(&ndev->dev, addr)) {
229 if (net_ratelimit())
230 netdev_err(ndev, "cannot map dma buffer\n");
231 dev_kfree_skb(skb);
232
233 rxbd->info = cpu_to_le32(FOR_EMAC | EMAC_BUFFER_SIZE);
234 stats->rx_errors++;
235 stats->rx_dropped++;
236 continue;
237 }
238
239
240 dma_unmap_single(&ndev->dev, dma_unmap_addr(rx_buff, addr),
241 dma_unmap_len(rx_buff, len), DMA_FROM_DEVICE);
242
243 pktlen = info & LEN_MASK;
244 stats->rx_packets++;
245 stats->rx_bytes += pktlen;
246 skb_put(rx_buff->skb, pktlen);
247 rx_buff->skb->dev = ndev;
248 rx_buff->skb->protocol = eth_type_trans(rx_buff->skb, ndev);
249
250 netif_receive_skb(rx_buff->skb);
251
252 rx_buff->skb = skb;
253 dma_unmap_addr_set(rx_buff, addr, addr);
254 dma_unmap_len_set(rx_buff, len, EMAC_BUFFER_SIZE);
255
256 rxbd->data = cpu_to_le32(addr);
257
258
259 wmb();
260
261
262 rxbd->info = cpu_to_le32(FOR_EMAC | EMAC_BUFFER_SIZE);
263 }
264
265 return work_done;
266}
267
268
269
270
271
272static void arc_emac_rx_miss_handle(struct net_device *ndev)
273{
274 struct arc_emac_priv *priv = netdev_priv(ndev);
275 struct net_device_stats *stats = &ndev->stats;
276 unsigned int miss;
277
278 miss = arc_reg_get(priv, R_MISS);
279 if (miss) {
280 stats->rx_errors += miss;
281 stats->rx_missed_errors += miss;
282 priv->rx_missed_errors += miss;
283 }
284}
285
286
287
288
289
290
291
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293
294
295
296
297static void arc_emac_rx_stall_check(struct net_device *ndev,
298 int budget, unsigned int work_done)
299{
300 struct arc_emac_priv *priv = netdev_priv(ndev);
301 struct arc_emac_bd *rxbd;
302
303 if (work_done)
304 priv->rx_missed_errors = 0;
305
306 if (priv->rx_missed_errors && budget) {
307 rxbd = &priv->rxbd[priv->last_rx_bd];
308 if (le32_to_cpu(rxbd->info) & FOR_EMAC) {
309 arc_emac_restart(ndev);
310 priv->rx_missed_errors = 0;
311 }
312 }
313}
314
315
316
317
318
319
320
321
322static int arc_emac_poll(struct napi_struct *napi, int budget)
323{
324 struct net_device *ndev = napi->dev;
325 struct arc_emac_priv *priv = netdev_priv(ndev);
326 unsigned int work_done;
327
328 arc_emac_tx_clean(ndev);
329 arc_emac_rx_miss_handle(ndev);
330
331 work_done = arc_emac_rx(ndev, budget);
332 if (work_done < budget) {
333 napi_complete_done(napi, work_done);
334 arc_reg_or(priv, R_ENABLE, RXINT_MASK | TXINT_MASK);
335 }
336
337 arc_emac_rx_stall_check(ndev, budget, work_done);
338
339 return work_done;
340}
341
342
343
344
345
346
347
348
349
350
351
352static irqreturn_t arc_emac_intr(int irq, void *dev_instance)
353{
354 struct net_device *ndev = dev_instance;
355 struct arc_emac_priv *priv = netdev_priv(ndev);
356 struct net_device_stats *stats = &ndev->stats;
357 unsigned int status;
358
359 status = arc_reg_get(priv, R_STATUS);
360 status &= ~MDIO_MASK;
361
362
363 arc_reg_set(priv, R_STATUS, status);
364
365 if (status & (RXINT_MASK | TXINT_MASK)) {
366 if (likely(napi_schedule_prep(&priv->napi))) {
367 arc_reg_clr(priv, R_ENABLE, RXINT_MASK | TXINT_MASK);
368 __napi_schedule(&priv->napi);
369 }
370 }
371
372 if (status & ERR_MASK) {
373
374
375
376
377 if (status & MSER_MASK) {
378 stats->rx_missed_errors += 0x100;
379 stats->rx_errors += 0x100;
380 priv->rx_missed_errors += 0x100;
381 napi_schedule(&priv->napi);
382 }
383
384 if (status & RXCR_MASK) {
385 stats->rx_crc_errors += 0x100;
386 stats->rx_errors += 0x100;
387 }
388
389 if (status & RXFR_MASK) {
390 stats->rx_frame_errors += 0x100;
391 stats->rx_errors += 0x100;
392 }
393
394 if (status & RXFL_MASK) {
395 stats->rx_over_errors += 0x100;
396 stats->rx_errors += 0x100;
397 }
398 }
399
400 return IRQ_HANDLED;
401}
402
403#ifdef CONFIG_NET_POLL_CONTROLLER
404static void arc_emac_poll_controller(struct net_device *dev)
405{
406 disable_irq(dev->irq);
407 arc_emac_intr(dev->irq, dev);
408 enable_irq(dev->irq);
409}
410#endif
411
412
413
414
415
416
417
418
419
420
421
422static int arc_emac_open(struct net_device *ndev)
423{
424 struct arc_emac_priv *priv = netdev_priv(ndev);
425 struct phy_device *phy_dev = ndev->phydev;
426 int i;
427
428 phy_dev->autoneg = AUTONEG_ENABLE;
429 phy_dev->speed = 0;
430 phy_dev->duplex = 0;
431 linkmode_and(phy_dev->advertising, phy_dev->advertising,
432 phy_dev->supported);
433
434 priv->last_rx_bd = 0;
435
436
437 for (i = 0; i < RX_BD_NUM; i++) {
438 dma_addr_t addr;
439 unsigned int *last_rx_bd = &priv->last_rx_bd;
440 struct arc_emac_bd *rxbd = &priv->rxbd[*last_rx_bd];
441 struct buffer_state *rx_buff = &priv->rx_buff[*last_rx_bd];
442
443 rx_buff->skb = netdev_alloc_skb_ip_align(ndev,
444 EMAC_BUFFER_SIZE);
445 if (unlikely(!rx_buff->skb))
446 return -ENOMEM;
447
448 addr = dma_map_single(&ndev->dev, (void *)rx_buff->skb->data,
449 EMAC_BUFFER_SIZE, DMA_FROM_DEVICE);
450 if (dma_mapping_error(&ndev->dev, addr)) {
451 netdev_err(ndev, "cannot dma map\n");
452 dev_kfree_skb(rx_buff->skb);
453 return -ENOMEM;
454 }
455 dma_unmap_addr_set(rx_buff, addr, addr);
456 dma_unmap_len_set(rx_buff, len, EMAC_BUFFER_SIZE);
457
458 rxbd->data = cpu_to_le32(addr);
459
460
461 wmb();
462
463
464 rxbd->info = cpu_to_le32(FOR_EMAC | EMAC_BUFFER_SIZE);
465
466 *last_rx_bd = (*last_rx_bd + 1) % RX_BD_NUM;
467 }
468
469 priv->txbd_curr = 0;
470 priv->txbd_dirty = 0;
471
472
473 memset(priv->txbd, 0, TX_RING_SZ);
474
475
476 arc_reg_set(priv, R_LAFL, 0);
477 arc_reg_set(priv, R_LAFH, 0);
478
479
480 arc_reg_set(priv, R_RX_RING, (unsigned int)priv->rxbd_dma);
481 arc_reg_set(priv, R_TX_RING, (unsigned int)priv->txbd_dma);
482
483
484 arc_reg_set(priv, R_ENABLE, RXINT_MASK | TXINT_MASK | ERR_MASK);
485
486
487 arc_reg_set(priv, R_CTRL,
488 (RX_BD_NUM << 24) |
489 (TX_BD_NUM << 16) |
490 TXRN_MASK | RXRN_MASK);
491
492 napi_enable(&priv->napi);
493
494
495 arc_reg_or(priv, R_CTRL, EN_MASK);
496
497 phy_start(ndev->phydev);
498
499 netif_start_queue(ndev);
500
501 return 0;
502}
503
504
505
506
507
508
509
510
511static void arc_emac_set_rx_mode(struct net_device *ndev)
512{
513 struct arc_emac_priv *priv = netdev_priv(ndev);
514
515 if (ndev->flags & IFF_PROMISC) {
516 arc_reg_or(priv, R_CTRL, PROM_MASK);
517 } else {
518 arc_reg_clr(priv, R_CTRL, PROM_MASK);
519
520 if (ndev->flags & IFF_ALLMULTI) {
521 arc_reg_set(priv, R_LAFL, ~0);
522 arc_reg_set(priv, R_LAFH, ~0);
523 } else if (ndev->flags & IFF_MULTICAST) {
524 struct netdev_hw_addr *ha;
525 unsigned int filter[2] = { 0, 0 };
526 int bit;
527
528 netdev_for_each_mc_addr(ha, ndev) {
529 bit = ether_crc_le(ETH_ALEN, ha->addr) >> 26;
530 filter[bit >> 5] |= 1 << (bit & 31);
531 }
532
533 arc_reg_set(priv, R_LAFL, filter[0]);
534 arc_reg_set(priv, R_LAFH, filter[1]);
535 } else {
536 arc_reg_set(priv, R_LAFL, 0);
537 arc_reg_set(priv, R_LAFH, 0);
538 }
539 }
540}
541
542
543
544
545
546
547
548static void arc_free_tx_queue(struct net_device *ndev)
549{
550 struct arc_emac_priv *priv = netdev_priv(ndev);
551 unsigned int i;
552
553 for (i = 0; i < TX_BD_NUM; i++) {
554 struct arc_emac_bd *txbd = &priv->txbd[i];
555 struct buffer_state *tx_buff = &priv->tx_buff[i];
556
557 if (tx_buff->skb) {
558 dma_unmap_single(&ndev->dev,
559 dma_unmap_addr(tx_buff, addr),
560 dma_unmap_len(tx_buff, len),
561 DMA_TO_DEVICE);
562
563
564 dev_kfree_skb_irq(tx_buff->skb);
565 }
566
567 txbd->info = 0;
568 txbd->data = 0;
569 tx_buff->skb = NULL;
570 }
571}
572
573
574
575
576
577
578
579static void arc_free_rx_queue(struct net_device *ndev)
580{
581 struct arc_emac_priv *priv = netdev_priv(ndev);
582 unsigned int i;
583
584 for (i = 0; i < RX_BD_NUM; i++) {
585 struct arc_emac_bd *rxbd = &priv->rxbd[i];
586 struct buffer_state *rx_buff = &priv->rx_buff[i];
587
588 if (rx_buff->skb) {
589 dma_unmap_single(&ndev->dev,
590 dma_unmap_addr(rx_buff, addr),
591 dma_unmap_len(rx_buff, len),
592 DMA_FROM_DEVICE);
593
594
595 dev_kfree_skb_irq(rx_buff->skb);
596 }
597
598 rxbd->info = 0;
599 rxbd->data = 0;
600 rx_buff->skb = NULL;
601 }
602}
603
604
605
606
607
608
609
610
611
612static int arc_emac_stop(struct net_device *ndev)
613{
614 struct arc_emac_priv *priv = netdev_priv(ndev);
615
616 napi_disable(&priv->napi);
617 netif_stop_queue(ndev);
618
619 phy_stop(ndev->phydev);
620
621
622 arc_reg_clr(priv, R_ENABLE, RXINT_MASK | TXINT_MASK | ERR_MASK);
623
624
625 arc_reg_clr(priv, R_CTRL, EN_MASK);
626
627
628 arc_free_tx_queue(ndev);
629 arc_free_rx_queue(ndev);
630
631 return 0;
632}
633
634
635
636
637
638
639
640
641static struct net_device_stats *arc_emac_stats(struct net_device *ndev)
642{
643 struct arc_emac_priv *priv = netdev_priv(ndev);
644 struct net_device_stats *stats = &ndev->stats;
645 unsigned long miss, rxerr;
646 u8 rxcrc, rxfram, rxoflow;
647
648 rxerr = arc_reg_get(priv, R_RXERR);
649 miss = arc_reg_get(priv, R_MISS);
650
651 rxcrc = rxerr;
652 rxfram = rxerr >> 8;
653 rxoflow = rxerr >> 16;
654
655 stats->rx_errors += miss;
656 stats->rx_errors += rxcrc + rxfram + rxoflow;
657
658 stats->rx_over_errors += rxoflow;
659 stats->rx_frame_errors += rxfram;
660 stats->rx_crc_errors += rxcrc;
661 stats->rx_missed_errors += miss;
662
663 return stats;
664}
665
666
667
668
669
670
671
672
673
674
675
676static netdev_tx_t arc_emac_tx(struct sk_buff *skb, struct net_device *ndev)
677{
678 struct arc_emac_priv *priv = netdev_priv(ndev);
679 unsigned int len, *txbd_curr = &priv->txbd_curr;
680 struct net_device_stats *stats = &ndev->stats;
681 __le32 *info = &priv->txbd[*txbd_curr].info;
682 dma_addr_t addr;
683
684 if (skb_padto(skb, ETH_ZLEN))
685 return NETDEV_TX_OK;
686
687 len = max_t(unsigned int, ETH_ZLEN, skb->len);
688
689 if (unlikely(!arc_emac_tx_avail(priv))) {
690 netif_stop_queue(ndev);
691 netdev_err(ndev, "BUG! Tx Ring full when queue awake!\n");
692 return NETDEV_TX_BUSY;
693 }
694
695 addr = dma_map_single(&ndev->dev, (void *)skb->data, len,
696 DMA_TO_DEVICE);
697
698 if (unlikely(dma_mapping_error(&ndev->dev, addr))) {
699 stats->tx_dropped++;
700 stats->tx_errors++;
701 dev_kfree_skb_any(skb);
702 return NETDEV_TX_OK;
703 }
704 dma_unmap_addr_set(&priv->tx_buff[*txbd_curr], addr, addr);
705 dma_unmap_len_set(&priv->tx_buff[*txbd_curr], len, len);
706
707 priv->txbd[*txbd_curr].data = cpu_to_le32(addr);
708
709
710 wmb();
711
712 skb_tx_timestamp(skb);
713
714 *info = cpu_to_le32(FOR_EMAC | FIRST_OR_LAST_MASK | len);
715
716
717 wmb();
718
719 priv->tx_buff[*txbd_curr].skb = skb;
720
721
722 *txbd_curr = (*txbd_curr + 1) % TX_BD_NUM;
723
724
725
726
727
728 smp_mb();
729
730 if (!arc_emac_tx_avail(priv)) {
731 netif_stop_queue(ndev);
732
733 smp_mb();
734 if (arc_emac_tx_avail(priv))
735 netif_start_queue(ndev);
736 }
737
738 arc_reg_set(priv, R_STATUS, TXPL_MASK);
739
740 return NETDEV_TX_OK;
741}
742
743static void arc_emac_set_address_internal(struct net_device *ndev)
744{
745 struct arc_emac_priv *priv = netdev_priv(ndev);
746 unsigned int addr_low, addr_hi;
747
748 addr_low = le32_to_cpu(*(__le32 *)&ndev->dev_addr[0]);
749 addr_hi = le16_to_cpu(*(__le16 *)&ndev->dev_addr[4]);
750
751 arc_reg_set(priv, R_ADDRL, addr_low);
752 arc_reg_set(priv, R_ADDRH, addr_hi);
753}
754
755
756
757
758
759
760
761
762
763
764
765
766static int arc_emac_set_address(struct net_device *ndev, void *p)
767{
768 struct sockaddr *addr = p;
769
770 if (netif_running(ndev))
771 return -EBUSY;
772
773 if (!is_valid_ether_addr(addr->sa_data))
774 return -EADDRNOTAVAIL;
775
776 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
777
778 arc_emac_set_address_internal(ndev);
779
780 return 0;
781}
782
783
784
785
786
787
788
789
790static void arc_emac_restart(struct net_device *ndev)
791{
792 struct arc_emac_priv *priv = netdev_priv(ndev);
793 struct net_device_stats *stats = &ndev->stats;
794 int i;
795
796 if (net_ratelimit())
797 netdev_warn(ndev, "restarting stalled EMAC\n");
798
799 netif_stop_queue(ndev);
800
801
802 arc_reg_clr(priv, R_ENABLE, RXINT_MASK | TXINT_MASK | ERR_MASK);
803
804
805 arc_reg_clr(priv, R_CTRL, EN_MASK);
806
807
808 arc_free_tx_queue(ndev);
809
810
811 priv->txbd_curr = 0;
812 priv->txbd_dirty = 0;
813 memset(priv->txbd, 0, TX_RING_SZ);
814
815 for (i = 0; i < RX_BD_NUM; i++) {
816 struct arc_emac_bd *rxbd = &priv->rxbd[i];
817 unsigned int info = le32_to_cpu(rxbd->info);
818
819 if (!(info & FOR_EMAC)) {
820 stats->rx_errors++;
821 stats->rx_dropped++;
822 }
823
824 rxbd->info = cpu_to_le32(FOR_EMAC | EMAC_BUFFER_SIZE);
825 }
826 priv->last_rx_bd = 0;
827
828
829 wmb();
830
831
832 arc_reg_set(priv, R_ENABLE, RXINT_MASK | TXINT_MASK | ERR_MASK);
833
834
835 arc_reg_or(priv, R_CTRL, EN_MASK);
836
837 netif_start_queue(ndev);
838}
839
840static const struct net_device_ops arc_emac_netdev_ops = {
841 .ndo_open = arc_emac_open,
842 .ndo_stop = arc_emac_stop,
843 .ndo_start_xmit = arc_emac_tx,
844 .ndo_set_mac_address = arc_emac_set_address,
845 .ndo_get_stats = arc_emac_stats,
846 .ndo_set_rx_mode = arc_emac_set_rx_mode,
847 .ndo_do_ioctl = phy_do_ioctl_running,
848#ifdef CONFIG_NET_POLL_CONTROLLER
849 .ndo_poll_controller = arc_emac_poll_controller,
850#endif
851};
852
853int arc_emac_probe(struct net_device *ndev, int interface)
854{
855 struct device *dev = ndev->dev.parent;
856 struct resource res_regs;
857 struct device_node *phy_node;
858 struct phy_device *phydev = NULL;
859 struct arc_emac_priv *priv;
860 const char *mac_addr;
861 unsigned int id, clock_frequency, irq;
862 int err;
863
864
865 phy_node = of_parse_phandle(dev->of_node, "phy", 0);
866 if (!phy_node) {
867 dev_err(dev, "failed to retrieve phy description from device tree\n");
868 return -ENODEV;
869 }
870
871
872 err = of_address_to_resource(dev->of_node, 0, &res_regs);
873 if (err) {
874 dev_err(dev, "failed to retrieve registers base from device tree\n");
875 err = -ENODEV;
876 goto out_put_node;
877 }
878
879
880 irq = irq_of_parse_and_map(dev->of_node, 0);
881 if (!irq) {
882 dev_err(dev, "failed to retrieve <irq> value from device tree\n");
883 err = -ENODEV;
884 goto out_put_node;
885 }
886
887 ndev->netdev_ops = &arc_emac_netdev_ops;
888 ndev->ethtool_ops = &arc_emac_ethtool_ops;
889 ndev->watchdog_timeo = TX_TIMEOUT;
890
891 priv = netdev_priv(ndev);
892 priv->dev = dev;
893
894 priv->regs = devm_ioremap_resource(dev, &res_regs);
895 if (IS_ERR(priv->regs)) {
896 err = PTR_ERR(priv->regs);
897 goto out_put_node;
898 }
899
900 dev_dbg(dev, "Registers base address is 0x%p\n", priv->regs);
901
902 if (priv->clk) {
903 err = clk_prepare_enable(priv->clk);
904 if (err) {
905 dev_err(dev, "failed to enable clock\n");
906 goto out_put_node;
907 }
908
909 clock_frequency = clk_get_rate(priv->clk);
910 } else {
911
912 if (of_property_read_u32(dev->of_node, "clock-frequency",
913 &clock_frequency)) {
914 dev_err(dev, "failed to retrieve <clock-frequency> from device tree\n");
915 err = -EINVAL;
916 goto out_put_node;
917 }
918 }
919
920 id = arc_reg_get(priv, R_ID);
921
922
923 if (!(id == 0x0005fd02 || id == 0x0007fd02)) {
924 dev_err(dev, "ARC EMAC not detected, id=0x%x\n", id);
925 err = -ENODEV;
926 goto out_clken;
927 }
928 dev_info(dev, "ARC EMAC detected with id: 0x%x\n", id);
929
930
931 arc_reg_set(priv, R_POLLRATE, clock_frequency / 1000000);
932
933 ndev->irq = irq;
934 dev_info(dev, "IRQ is %d\n", ndev->irq);
935
936
937 err = devm_request_irq(dev, ndev->irq, arc_emac_intr, 0,
938 ndev->name, ndev);
939 if (err) {
940 dev_err(dev, "could not allocate IRQ\n");
941 goto out_clken;
942 }
943
944
945 mac_addr = of_get_mac_address(dev->of_node);
946
947 if (!IS_ERR(mac_addr))
948 ether_addr_copy(ndev->dev_addr, mac_addr);
949 else
950 eth_hw_addr_random(ndev);
951
952 arc_emac_set_address_internal(ndev);
953 dev_info(dev, "MAC address is now %pM\n", ndev->dev_addr);
954
955
956 priv->rxbd = dmam_alloc_coherent(dev, RX_RING_SZ + TX_RING_SZ,
957 &priv->rxbd_dma, GFP_KERNEL);
958
959 if (!priv->rxbd) {
960 dev_err(dev, "failed to allocate data buffers\n");
961 err = -ENOMEM;
962 goto out_clken;
963 }
964
965 priv->txbd = priv->rxbd + RX_BD_NUM;
966
967 priv->txbd_dma = priv->rxbd_dma + RX_RING_SZ;
968 dev_dbg(dev, "EMAC Device addr: Rx Ring [0x%x], Tx Ring[%x]\n",
969 (unsigned int)priv->rxbd_dma, (unsigned int)priv->txbd_dma);
970
971 err = arc_mdio_probe(priv);
972 if (err) {
973 dev_err(dev, "failed to probe MII bus\n");
974 goto out_clken;
975 }
976
977 phydev = of_phy_connect(ndev, phy_node, arc_emac_adjust_link, 0,
978 interface);
979 if (!phydev) {
980 dev_err(dev, "of_phy_connect() failed\n");
981 err = -ENODEV;
982 goto out_mdio;
983 }
984
985 dev_info(dev, "connected to %s phy with id 0x%x\n",
986 phydev->drv->name, phydev->phy_id);
987
988 netif_napi_add(ndev, &priv->napi, arc_emac_poll, ARC_EMAC_NAPI_WEIGHT);
989
990 err = register_netdev(ndev);
991 if (err) {
992 dev_err(dev, "failed to register network device\n");
993 goto out_netif_api;
994 }
995
996 of_node_put(phy_node);
997 return 0;
998
999out_netif_api:
1000 netif_napi_del(&priv->napi);
1001 phy_disconnect(phydev);
1002out_mdio:
1003 arc_mdio_remove(priv);
1004out_clken:
1005 if (priv->clk)
1006 clk_disable_unprepare(priv->clk);
1007out_put_node:
1008 of_node_put(phy_node);
1009
1010 return err;
1011}
1012EXPORT_SYMBOL_GPL(arc_emac_probe);
1013
1014int arc_emac_remove(struct net_device *ndev)
1015{
1016 struct arc_emac_priv *priv = netdev_priv(ndev);
1017
1018 phy_disconnect(ndev->phydev);
1019 arc_mdio_remove(priv);
1020 unregister_netdev(ndev);
1021 netif_napi_del(&priv->napi);
1022
1023 if (!IS_ERR(priv->clk))
1024 clk_disable_unprepare(priv->clk);
1025
1026 return 0;
1027}
1028EXPORT_SYMBOL_GPL(arc_emac_remove);
1029
1030MODULE_AUTHOR("Alexey Brodkin <abrodkin@synopsys.com>");
1031MODULE_DESCRIPTION("ARC EMAC driver");
1032MODULE_LICENSE("GPL");
1033