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19#ifndef __GIANFAR_H
20#define __GIANFAR_H
21
22#include <linux/kernel.h>
23#include <linux/sched.h>
24#include <linux/string.h>
25#include <linux/errno.h>
26#include <linux/slab.h>
27#include <linux/interrupt.h>
28#include <linux/delay.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
31#include <linux/skbuff.h>
32#include <linux/spinlock.h>
33#include <linux/mm.h>
34#include <linux/mii.h>
35#include <linux/phy.h>
36
37#include <asm/io.h>
38#include <asm/irq.h>
39#include <linux/uaccess.h>
40#include <linux/module.h>
41#include <linux/crc32.h>
42#include <linux/workqueue.h>
43#include <linux/ethtool.h>
44
45struct ethtool_flow_spec_container {
46 struct ethtool_rx_flow_spec fs;
47 struct list_head list;
48};
49
50struct ethtool_rx_list {
51 struct list_head list;
52 unsigned int count;
53};
54
55
56#define GFAR_DEV_WEIGHT 64
57
58
59#define GMAC_FCB_LEN 8
60
61
62#define GMAC_TXPAL_LEN 16
63
64
65#define DEFAULT_PADDING 2
66
67
68#define RXBUF_ALIGNMENT 64
69
70#define DRV_NAME "gfar-enet"
71
72
73#define MAX_TX_QS 0x8
74#define MAX_RX_QS 0x8
75
76
77#define MAXGROUPS 0x2
78
79
80#define DEFAULT_TX_RING_SIZE 256
81#define DEFAULT_RX_RING_SIZE 256
82
83#define GFAR_RX_BUFF_ALLOC 16
84
85#define GFAR_RX_MAX_RING_SIZE 256
86#define GFAR_TX_MAX_RING_SIZE 256
87
88#define FBTHR_SHIFT 24
89#define DEFAULT_RX_LFC_THR 16
90#define DEFAULT_LFC_PTVVAL 4
91
92#define GFAR_RXB_TRUESIZE 2048
93#define GFAR_SKBFRAG_OVR (RXBUF_ALIGNMENT \
94 + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
95#define GFAR_RXB_SIZE rounddown(GFAR_RXB_TRUESIZE - GFAR_SKBFRAG_OVR, 64)
96#define GFAR_SKBFRAG_SIZE (GFAR_RXB_SIZE + GFAR_SKBFRAG_OVR)
97
98#define TX_RING_MOD_MASK(size) (size-1)
99#define RX_RING_MOD_MASK(size) (size-1)
100#define GFAR_JUMBO_FRAME_SIZE 9600
101
102#define DEFAULT_FIFO_TX_THR 0x100
103#define DEFAULT_FIFO_TX_STARVE 0x40
104#define DEFAULT_FIFO_TX_STARVE_OFF 0x80
105
106
107#define GFAR_EM_NUM 15
108
109
110
111
112
113
114
115
116
117
118
119#define GFAR_GBIT_TIME 512
120#define GFAR_100_TIME 2560
121#define GFAR_10_TIME 25600
122
123#define DEFAULT_TX_COALESCE 1
124#define DEFAULT_TXCOUNT 16
125#define DEFAULT_TXTIME 21
126
127#define DEFAULT_RXTIME 21
128
129#define DEFAULT_RX_COALESCE 0
130#define DEFAULT_RXCOUNT 0
131
132
133#define MII_TBICON 0x11
134
135
136#define TBICON_CLK_SELECT 0x0020
137
138
139#define MACCFG1_SOFT_RESET 0x80000000
140#define MACCFG1_RESET_RX_MC 0x00080000
141#define MACCFG1_RESET_TX_MC 0x00040000
142#define MACCFG1_RESET_RX_FUN 0x00020000
143#define MACCFG1_RESET_TX_FUN 0x00010000
144#define MACCFG1_LOOPBACK 0x00000100
145#define MACCFG1_RX_FLOW 0x00000020
146#define MACCFG1_TX_FLOW 0x00000010
147#define MACCFG1_SYNCD_RX_EN 0x00000008
148#define MACCFG1_RX_EN 0x00000004
149#define MACCFG1_SYNCD_TX_EN 0x00000002
150#define MACCFG1_TX_EN 0x00000001
151
152#define MACCFG2_INIT_SETTINGS 0x00007205
153#define MACCFG2_FULL_DUPLEX 0x00000001
154#define MACCFG2_IF 0x00000300
155#define MACCFG2_MII 0x00000100
156#define MACCFG2_GMII 0x00000200
157#define MACCFG2_HUGEFRAME 0x00000020
158#define MACCFG2_LENGTHCHECK 0x00000010
159#define MACCFG2_MPEN 0x00000008
160
161#define ECNTRL_FIFM 0x00008000
162#define ECNTRL_INIT_SETTINGS 0x00001000
163#define ECNTRL_TBI_MODE 0x00000020
164#define ECNTRL_REDUCED_MODE 0x00000010
165#define ECNTRL_R100 0x00000008
166#define ECNTRL_REDUCED_MII_MODE 0x00000004
167#define ECNTRL_SGMII_MODE 0x00000002
168
169#define MINFLR_INIT_SETTINGS 0x00000040
170
171
172#define TQUEUE_EN0 0x00008000
173#define TQUEUE_EN1 0x00004000
174#define TQUEUE_EN2 0x00002000
175#define TQUEUE_EN3 0x00001000
176#define TQUEUE_EN4 0x00000800
177#define TQUEUE_EN5 0x00000400
178#define TQUEUE_EN6 0x00000200
179#define TQUEUE_EN7 0x00000100
180#define TQUEUE_EN_ALL 0x0000FF00
181
182#define TR03WT_WT0_MASK 0xFF000000
183#define TR03WT_WT1_MASK 0x00FF0000
184#define TR03WT_WT2_MASK 0x0000FF00
185#define TR03WT_WT3_MASK 0x000000FF
186
187#define TR47WT_WT4_MASK 0xFF000000
188#define TR47WT_WT5_MASK 0x00FF0000
189#define TR47WT_WT6_MASK 0x0000FF00
190#define TR47WT_WT7_MASK 0x000000FF
191
192
193#define RQUEUE_EX0 0x00800000
194#define RQUEUE_EX1 0x00400000
195#define RQUEUE_EX2 0x00200000
196#define RQUEUE_EX3 0x00100000
197#define RQUEUE_EX4 0x00080000
198#define RQUEUE_EX5 0x00040000
199#define RQUEUE_EX6 0x00020000
200#define RQUEUE_EX7 0x00010000
201#define RQUEUE_EX_ALL 0x00FF0000
202
203#define RQUEUE_EN0 0x00000080
204#define RQUEUE_EN1 0x00000040
205#define RQUEUE_EN2 0x00000020
206#define RQUEUE_EN3 0x00000010
207#define RQUEUE_EN4 0x00000008
208#define RQUEUE_EN5 0x00000004
209#define RQUEUE_EN6 0x00000002
210#define RQUEUE_EN7 0x00000001
211#define RQUEUE_EN_ALL 0x000000FF
212
213
214#define DMACTRL_INIT_SETTINGS 0x000000c3
215#define DMACTRL_GRS 0x00000010
216#define DMACTRL_GTS 0x00000008
217
218#define TSTAT_CLEAR_THALT_ALL 0xFF000000
219#define TSTAT_CLEAR_THALT 0x80000000
220#define TSTAT_CLEAR_THALT0 0x80000000
221#define TSTAT_CLEAR_THALT1 0x40000000
222#define TSTAT_CLEAR_THALT2 0x20000000
223#define TSTAT_CLEAR_THALT3 0x10000000
224#define TSTAT_CLEAR_THALT4 0x08000000
225#define TSTAT_CLEAR_THALT5 0x04000000
226#define TSTAT_CLEAR_THALT6 0x02000000
227#define TSTAT_CLEAR_THALT7 0x01000000
228
229
230#define IC_ICEN 0x80000000
231#define IC_ICFT_MASK 0x1fe00000
232#define IC_ICFT_SHIFT 21
233#define mk_ic_icft(x) \
234 (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK)
235#define IC_ICTT_MASK 0x0000ffff
236#define mk_ic_ictt(x) (x&IC_ICTT_MASK)
237
238#define mk_ic_value(count, time) (IC_ICEN | \
239 mk_ic_icft(count) | \
240 mk_ic_ictt(time))
241#define get_icft_value(ic) (((unsigned long)ic & IC_ICFT_MASK) >> \
242 IC_ICFT_SHIFT)
243#define get_ictt_value(ic) ((unsigned long)ic & IC_ICTT_MASK)
244
245#define DEFAULT_TXIC mk_ic_value(DEFAULT_TXCOUNT, DEFAULT_TXTIME)
246#define DEFAULT_RXIC mk_ic_value(DEFAULT_RXCOUNT, DEFAULT_RXTIME)
247
248#define RCTRL_TS_ENABLE 0x01000000
249#define RCTRL_PAL_MASK 0x001f0000
250#define RCTRL_LFC 0x00004000
251#define RCTRL_VLEX 0x00002000
252#define RCTRL_FILREN 0x00001000
253#define RCTRL_GHTX 0x00000400
254#define RCTRL_IPCSEN 0x00000200
255#define RCTRL_TUCSEN 0x00000100
256#define RCTRL_PRSDEP_MASK 0x000000c0
257#define RCTRL_PRSDEP_INIT 0x000000c0
258#define RCTRL_PRSFM 0x00000020
259#define RCTRL_PROM 0x00000008
260#define RCTRL_EMEN 0x00000002
261#define RCTRL_REQ_PARSER (RCTRL_VLEX | RCTRL_IPCSEN | \
262 RCTRL_TUCSEN | RCTRL_FILREN)
263#define RCTRL_CHECKSUMMING (RCTRL_IPCSEN | RCTRL_TUCSEN | \
264 RCTRL_PRSDEP_INIT)
265#define RCTRL_EXTHASH (RCTRL_GHTX)
266#define RCTRL_VLAN (RCTRL_PRSDEP_INIT)
267#define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK)
268
269
270#define RSTAT_CLEAR_RHALT 0x00800000
271#define RSTAT_CLEAR_RXF0 0x00000080
272#define RSTAT_RXF_MASK 0x000000ff
273
274#define TCTRL_IPCSEN 0x00004000
275#define TCTRL_TUCSEN 0x00002000
276#define TCTRL_VLINS 0x00001000
277#define TCTRL_THDF 0x00000800
278#define TCTRL_RFCPAUSE 0x00000010
279#define TCTRL_TFCPAUSE 0x00000008
280#define TCTRL_TXSCHED_MASK 0x00000006
281#define TCTRL_TXSCHED_INIT 0x00000000
282
283#define TCTRL_TXSCHED_PRIO 0x00000002
284
285#define TCTRL_TXSCHED_WRRS 0x00000004
286
287
288
289
290#define DEFAULT_WRRS_WEIGHT 0x18181818
291
292#define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN)
293
294#define IEVENT_INIT_CLEAR 0xffffffff
295#define IEVENT_BABR 0x80000000
296#define IEVENT_RXC 0x40000000
297#define IEVENT_BSY 0x20000000
298#define IEVENT_EBERR 0x10000000
299#define IEVENT_MSRO 0x04000000
300#define IEVENT_GTSC 0x02000000
301#define IEVENT_BABT 0x01000000
302#define IEVENT_TXC 0x00800000
303#define IEVENT_TXE 0x00400000
304#define IEVENT_TXB 0x00200000
305#define IEVENT_TXF 0x00100000
306#define IEVENT_LC 0x00040000
307#define IEVENT_CRL 0x00020000
308#define IEVENT_XFUN 0x00010000
309#define IEVENT_RXB0 0x00008000
310#define IEVENT_MAG 0x00000800
311#define IEVENT_GRSC 0x00000100
312#define IEVENT_RXF0 0x00000080
313#define IEVENT_FGPI 0x00000010
314#define IEVENT_FIR 0x00000008
315#define IEVENT_FIQ 0x00000004
316#define IEVENT_DPE 0x00000002
317#define IEVENT_PERR 0x00000001
318#define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0 | IEVENT_BSY)
319#define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF)
320#define IEVENT_RTX_MASK (IEVENT_RX_MASK | IEVENT_TX_MASK)
321#define IEVENT_ERR_MASK \
322(IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
323 IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
324 | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \
325 | IEVENT_MAG | IEVENT_BABR)
326
327#define IMASK_INIT_CLEAR 0x00000000
328#define IMASK_BABR 0x80000000
329#define IMASK_RXC 0x40000000
330#define IMASK_BSY 0x20000000
331#define IMASK_EBERR 0x10000000
332#define IMASK_MSRO 0x04000000
333#define IMASK_GTSC 0x02000000
334#define IMASK_BABT 0x01000000
335#define IMASK_TXC 0x00800000
336#define IMASK_TXEEN 0x00400000
337#define IMASK_TXBEN 0x00200000
338#define IMASK_TXFEN 0x00100000
339#define IMASK_LC 0x00040000
340#define IMASK_CRL 0x00020000
341#define IMASK_XFUN 0x00010000
342#define IMASK_RXB0 0x00008000
343#define IMASK_MAG 0x00000800
344#define IMASK_GRSC 0x00000100
345#define IMASK_RXFEN0 0x00000080
346#define IMASK_FGPI 0x00000010
347#define IMASK_FIR 0x00000008
348#define IMASK_FIQ 0x00000004
349#define IMASK_DPE 0x00000002
350#define IMASK_PERR 0x00000001
351#define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \
352 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \
353 IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \
354 | IMASK_PERR)
355#define IMASK_RX_DEFAULT (IMASK_RXFEN0 | IMASK_BSY)
356#define IMASK_TX_DEFAULT (IMASK_TXFEN | IMASK_TXBEN)
357
358#define IMASK_RX_DISABLED ((~(IMASK_RX_DEFAULT)) & IMASK_DEFAULT)
359#define IMASK_TX_DISABLED ((~(IMASK_TX_DEFAULT)) & IMASK_DEFAULT)
360
361
362
363
364#define ATTR_BDSTASH 0x00000800
365
366#define ATTR_BUFSTASH 0x00004000
367
368#define ATTR_SNOOPING 0x000000c0
369#define ATTR_INIT_SETTINGS ATTR_SNOOPING
370
371#define ATTRELI_INIT_SETTINGS 0x0
372#define ATTRELI_EL_MASK 0x3fff0000
373#define ATTRELI_EL(x) (x << 16)
374#define ATTRELI_EI_MASK 0x00003fff
375#define ATTRELI_EI(x) (x)
376
377#define BD_LFLAG(flags) ((flags) << 16)
378#define BD_LENGTH_MASK 0x0000ffff
379
380#define FPR_FILER_MASK 0xFFFFFFFF
381#define MAX_FILER_IDX 0xFF
382
383
384
385#define DEFAULT_8RXQ_RIR0 0x05397700
386
387#define DEFAULT_2RXQ_RIR0 0x04104100
388
389
390#define RQFCR_GPI 0x80000000
391#define RQFCR_HASHTBL_Q 0x00000000
392#define RQFCR_HASHTBL_0 0x00020000
393#define RQFCR_HASHTBL_1 0x00040000
394#define RQFCR_HASHTBL_2 0x00060000
395#define RQFCR_HASHTBL_3 0x00080000
396#define RQFCR_HASH 0x00010000
397#define RQFCR_QUEUE 0x0000FC00
398#define RQFCR_CLE 0x00000200
399#define RQFCR_RJE 0x00000100
400#define RQFCR_AND 0x00000080
401#define RQFCR_CMP_EXACT 0x00000000
402#define RQFCR_CMP_MATCH 0x00000020
403#define RQFCR_CMP_NOEXACT 0x00000040
404#define RQFCR_CMP_NOMATCH 0x00000060
405
406
407#define RQFCR_PID_MASK 0x00000000
408#define RQFCR_PID_PARSE 0x00000001
409#define RQFCR_PID_ARB 0x00000002
410#define RQFCR_PID_DAH 0x00000003
411#define RQFCR_PID_DAL 0x00000004
412#define RQFCR_PID_SAH 0x00000005
413#define RQFCR_PID_SAL 0x00000006
414#define RQFCR_PID_ETY 0x00000007
415#define RQFCR_PID_VID 0x00000008
416#define RQFCR_PID_PRI 0x00000009
417#define RQFCR_PID_TOS 0x0000000A
418#define RQFCR_PID_L4P 0x0000000B
419#define RQFCR_PID_DIA 0x0000000C
420#define RQFCR_PID_SIA 0x0000000D
421#define RQFCR_PID_DPT 0x0000000E
422#define RQFCR_PID_SPT 0x0000000F
423
424
425#define RQFPR_HDR_GE_512 0x00200000
426#define RQFPR_LERR 0x00100000
427#define RQFPR_RAR 0x00080000
428#define RQFPR_RARQ 0x00040000
429#define RQFPR_AR 0x00020000
430#define RQFPR_ARQ 0x00010000
431#define RQFPR_EBC 0x00008000
432#define RQFPR_VLN 0x00004000
433#define RQFPR_CFI 0x00002000
434#define RQFPR_JUM 0x00001000
435#define RQFPR_IPF 0x00000800
436#define RQFPR_FIF 0x00000400
437#define RQFPR_IPV4 0x00000200
438#define RQFPR_IPV6 0x00000100
439#define RQFPR_ICC 0x00000080
440#define RQFPR_ICV 0x00000040
441#define RQFPR_TCP 0x00000020
442#define RQFPR_UDP 0x00000010
443#define RQFPR_TUC 0x00000008
444#define RQFPR_TUV 0x00000004
445#define RQFPR_PER 0x00000002
446#define RQFPR_EER 0x00000001
447
448
449#define TXBD_READY 0x8000
450#define TXBD_PADCRC 0x4000
451#define TXBD_WRAP 0x2000
452#define TXBD_INTERRUPT 0x1000
453#define TXBD_LAST 0x0800
454#define TXBD_CRC 0x0400
455#define TXBD_DEF 0x0200
456#define TXBD_HUGEFRAME 0x0080
457#define TXBD_LATECOLLISION 0x0080
458#define TXBD_RETRYLIMIT 0x0040
459#define TXBD_RETRYCOUNTMASK 0x003c
460#define TXBD_UNDERRUN 0x0002
461#define TXBD_TOE 0x0002
462
463
464#define TXFCB_VLN 0x80
465#define TXFCB_IP 0x40
466#define TXFCB_IP6 0x20
467#define TXFCB_TUP 0x10
468#define TXFCB_UDP 0x08
469#define TXFCB_CIP 0x04
470#define TXFCB_CTU 0x02
471#define TXFCB_NPH 0x01
472#define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH)
473
474
475#define RXBD_EMPTY 0x8000
476#define RXBD_RO1 0x4000
477#define RXBD_WRAP 0x2000
478#define RXBD_INTERRUPT 0x1000
479#define RXBD_LAST 0x0800
480#define RXBD_FIRST 0x0400
481#define RXBD_MISS 0x0100
482#define RXBD_BROADCAST 0x0080
483#define RXBD_MULTICAST 0x0040
484#define RXBD_LARGE 0x0020
485#define RXBD_NONOCTET 0x0010
486#define RXBD_SHORT 0x0008
487#define RXBD_CRCERR 0x0004
488#define RXBD_OVERRUN 0x0002
489#define RXBD_TRUNCATED 0x0001
490#define RXBD_STATS 0x01ff
491#define RXBD_ERR (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET \
492 | RXBD_CRCERR | RXBD_OVERRUN \
493 | RXBD_TRUNCATED)
494
495
496#define RXFCB_VLN 0x8000
497#define RXFCB_IP 0x4000
498#define RXFCB_IP6 0x2000
499#define RXFCB_TUP 0x1000
500#define RXFCB_CIP 0x0800
501#define RXFCB_CTU 0x0400
502#define RXFCB_EIP 0x0200
503#define RXFCB_ETU 0x0100
504#define RXFCB_CSUM_MASK 0x0f00
505#define RXFCB_PERR_MASK 0x000c
506#define RXFCB_PERR_BADL3 0x0008
507
508#define GFAR_INT_NAME_MAX (IFNAMSIZ + 6)
509
510#define GFAR_WOL_MAGIC 0x00000001
511#define GFAR_WOL_FILER_UCAST 0x00000002
512
513struct txbd8
514{
515 union {
516 struct {
517 __be16 status;
518 __be16 length;
519 };
520 __be32 lstatus;
521 };
522 __be32 bufPtr;
523};
524
525struct txfcb {
526 u8 flags;
527 u8 ptp;
528 u8 l4os;
529 u8 l3os;
530 __be16 phcs;
531 __be16 vlctl;
532};
533
534struct rxbd8
535{
536 union {
537 struct {
538 __be16 status;
539 __be16 length;
540 };
541 __be32 lstatus;
542 };
543 __be32 bufPtr;
544};
545
546struct rxfcb {
547 __be16 flags;
548 u8 rq;
549 u8 pro;
550 u16 reserved;
551 __be16 vlctl;
552};
553
554struct gianfar_skb_cb {
555 unsigned int bytes_sent;
556};
557
558#define GFAR_CB(skb) ((struct gianfar_skb_cb *)((skb)->cb))
559
560struct rmon_mib
561{
562 u32 tr64;
563 u32 tr127;
564 u32 tr255;
565 u32 tr511;
566 u32 tr1k;
567 u32 trmax;
568 u32 trmgv;
569 u32 rbyt;
570 u32 rpkt;
571 u32 rfcs;
572 u32 rmca;
573 u32 rbca;
574 u32 rxcf;
575 u32 rxpf;
576 u32 rxuo;
577 u32 raln;
578 u32 rflr;
579 u32 rcde;
580 u32 rcse;
581 u32 rund;
582 u32 rovr;
583 u32 rfrg;
584 u32 rjbr;
585 u32 rdrp;
586 u32 tbyt;
587 u32 tpkt;
588 u32 tmca;
589 u32 tbca;
590 u32 txpf;
591 u32 tdfr;
592 u32 tedf;
593 u32 tscl;
594 u32 tmcl;
595 u32 tlcl;
596 u32 txcl;
597 u32 tncl;
598 u8 res1[4];
599 u32 tdrp;
600 u32 tjbr;
601 u32 tfcs;
602 u32 txcf;
603 u32 tovr;
604 u32 tund;
605 u32 tfrg;
606 u32 car1;
607 u32 car2;
608 u32 cam1;
609 u32 cam2;
610};
611
612struct gfar_extra_stats {
613 atomic64_t rx_alloc_err;
614 atomic64_t rx_large;
615 atomic64_t rx_short;
616 atomic64_t rx_nonoctet;
617 atomic64_t rx_crcerr;
618 atomic64_t rx_overrun;
619 atomic64_t rx_bsy;
620 atomic64_t rx_babr;
621 atomic64_t rx_trunc;
622 atomic64_t eberr;
623 atomic64_t tx_babt;
624 atomic64_t tx_underrun;
625 atomic64_t tx_timeout;
626};
627
628#define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32))
629#define GFAR_EXTRA_STATS_LEN \
630 (sizeof(struct gfar_extra_stats)/sizeof(atomic64_t))
631
632
633#define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN)
634
635struct gfar {
636 u32 tsec_id;
637 u32 tsec_id2;
638 u8 res1[8];
639 u32 ievent;
640 u32 imask;
641 u32 edis;
642 u32 emapg;
643 u32 ecntrl;
644 u32 minflr;
645 u32 ptv;
646 u32 dmactrl;
647 u32 tbipa;
648 u8 res2[28];
649 u32 fifo_rx_pause;
650
651 u32 fifo_rx_pause_shutoff;
652
653 u32 fifo_rx_alarm;
654
655 u32 fifo_rx_alarm_shutoff;
656
657 u8 res3[44];
658 u32 fifo_tx_thr;
659 u8 res4[8];
660 u32 fifo_tx_starve;
661 u32 fifo_tx_starve_shutoff;
662 u8 res5[96];
663 u32 tctrl;
664 u32 tstat;
665 u32 dfvlan;
666 u32 tbdlen;
667 u32 txic;
668 u32 tqueue;
669 u8 res7[40];
670 u32 tr03wt;
671 u32 tr47wt;
672 u8 res8[52];
673 u32 tbdbph;
674 u8 res9a[4];
675 u32 tbptr0;
676 u8 res9b[4];
677 u32 tbptr1;
678 u8 res9c[4];
679 u32 tbptr2;
680 u8 res9d[4];
681 u32 tbptr3;
682 u8 res9e[4];
683 u32 tbptr4;
684 u8 res9f[4];
685 u32 tbptr5;
686 u8 res9g[4];
687 u32 tbptr6;
688 u8 res9h[4];
689 u32 tbptr7;
690 u8 res9[64];
691 u32 tbaseh;
692 u32 tbase0;
693 u8 res10a[4];
694 u32 tbase1;
695 u8 res10b[4];
696 u32 tbase2;
697 u8 res10c[4];
698 u32 tbase3;
699 u8 res10d[4];
700 u32 tbase4;
701 u8 res10e[4];
702 u32 tbase5;
703 u8 res10f[4];
704 u32 tbase6;
705 u8 res10g[4];
706 u32 tbase7;
707 u8 res10[192];
708 u32 rctrl;
709 u32 rstat;
710 u8 res12[8];
711 u32 rxic;
712 u32 rqueue;
713 u32 rir0;
714 u32 rir1;
715 u32 rir2;
716 u32 rir3;
717 u8 res13[8];
718 u32 rbifx;
719 u32 rqfar;
720 u32 rqfcr;
721 u32 rqfpr;
722 u32 mrblr;
723 u8 res14[56];
724 u32 rbdbph;
725 u8 res15a[4];
726 u32 rbptr0;
727 u8 res15b[4];
728 u32 rbptr1;
729 u8 res15c[4];
730 u32 rbptr2;
731 u8 res15d[4];
732 u32 rbptr3;
733 u8 res15e[4];
734 u32 rbptr4;
735 u8 res15f[4];
736 u32 rbptr5;
737 u8 res15g[4];
738 u32 rbptr6;
739 u8 res15h[4];
740 u32 rbptr7;
741 u8 res16[64];
742 u32 rbaseh;
743 u32 rbase0;
744 u8 res17a[4];
745 u32 rbase1;
746 u8 res17b[4];
747 u32 rbase2;
748 u8 res17c[4];
749 u32 rbase3;
750 u8 res17d[4];
751 u32 rbase4;
752 u8 res17e[4];
753 u32 rbase5;
754 u8 res17f[4];
755 u32 rbase6;
756 u8 res17g[4];
757 u32 rbase7;
758 u8 res17[192];
759 u32 maccfg1;
760 u32 maccfg2;
761 u32 ipgifg;
762 u32 hafdup;
763 u32 maxfrm;
764 u8 res18[12];
765 u8 gfar_mii_regs[24];
766 u32 ifctrl;
767 u32 ifstat;
768 u32 macstnaddr1;
769 u32 macstnaddr2;
770 u32 mac01addr1;
771 u32 mac01addr2;
772 u32 mac02addr1;
773 u32 mac02addr2;
774 u32 mac03addr1;
775 u32 mac03addr2;
776 u32 mac04addr1;
777 u32 mac04addr2;
778 u32 mac05addr1;
779 u32 mac05addr2;
780 u32 mac06addr1;
781 u32 mac06addr2;
782 u32 mac07addr1;
783 u32 mac07addr2;
784 u32 mac08addr1;
785 u32 mac08addr2;
786 u32 mac09addr1;
787 u32 mac09addr2;
788 u32 mac10addr1;
789 u32 mac10addr2;
790 u32 mac11addr1;
791 u32 mac11addr2;
792 u32 mac12addr1;
793 u32 mac12addr2;
794 u32 mac13addr1;
795 u32 mac13addr2;
796 u32 mac14addr1;
797 u32 mac14addr2;
798 u32 mac15addr1;
799 u32 mac15addr2;
800 u8 res20[192];
801 struct rmon_mib rmon;
802 u32 rrej;
803 u8 res21[188];
804 u32 igaddr0;
805 u32 igaddr1;
806 u32 igaddr2;
807 u32 igaddr3;
808 u32 igaddr4;
809 u32 igaddr5;
810 u32 igaddr6;
811 u32 igaddr7;
812 u8 res22[96];
813 u32 gaddr0;
814 u32 gaddr1;
815 u32 gaddr2;
816 u32 gaddr3;
817 u32 gaddr4;
818 u32 gaddr5;
819 u32 gaddr6;
820 u32 gaddr7;
821 u8 res23a[352];
822 u32 fifocfg;
823 u8 res23b[252];
824 u8 res23c[248];
825 u32 attr;
826 u32 attreli;
827 u32 rqprm0;
828 u32 rqprm1;
829 u32 rqprm2;
830 u32 rqprm3;
831 u32 rqprm4;
832 u32 rqprm5;
833 u32 rqprm6;
834 u32 rqprm7;
835 u8 res24[36];
836 u32 rfbptr0;
837 u8 res24a[4];
838 u32 rfbptr1;
839 u8 res24b[4];
840 u32 rfbptr2;
841 u8 res24c[4];
842 u32 rfbptr3;
843 u8 res24d[4];
844 u32 rfbptr4;
845 u8 res24e[4];
846 u32 rfbptr5;
847 u8 res24f[4];
848 u32 rfbptr6;
849 u8 res24g[4];
850 u32 rfbptr7;
851 u8 res24h[4];
852 u8 res24x[556];
853 u32 isrg0;
854 u32 isrg1;
855 u32 isrg2;
856 u32 isrg3;
857 u8 res25[16];
858 u32 rxic0;
859 u32 rxic1;
860 u32 rxic2;
861 u32 rxic3;
862 u32 rxic4;
863 u32 rxic5;
864 u32 rxic6;
865 u32 rxic7;
866 u8 res26[32];
867 u32 txic0;
868 u32 txic1;
869 u32 txic2;
870 u32 txic3;
871 u32 txic4;
872 u32 txic5;
873 u32 txic6;
874 u32 txic7;
875 u8 res27[208];
876};
877
878
879#define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001
880#define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002
881#define FSL_GIANFAR_DEV_HAS_RMON 0x00000004
882#define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008
883#define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010
884#define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020
885#define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040
886#define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET 0x00000100
887#define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200
888#define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400
889#define FSL_GIANFAR_DEV_HAS_TIMER 0x00000800
890#define FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER 0x00001000
891#define FSL_GIANFAR_DEV_HAS_RX_FILER 0x00002000
892
893#if (MAXGROUPS == 2)
894#define DEFAULT_MAPPING 0xAA
895#else
896#define DEFAULT_MAPPING 0xFF
897#endif
898
899#define ISRG_RR0 0x80000000
900#define ISRG_TR0 0x00800000
901
902
903
904
905
906
907enum {
908 SQ_SG_MODE = 0,
909 MQ_MG_MODE
910};
911
912
913
914
915
916
917
918
919
920
921
922
923enum gfar_poll_mode {
924 GFAR_SQ_POLLING = 0,
925 GFAR_MQ_POLLING
926};
927
928
929
930
931struct tx_q_stats {
932 unsigned long tx_packets;
933 unsigned long tx_bytes;
934};
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956struct gfar_priv_tx_q {
957
958 spinlock_t txlock __attribute__ ((aligned (SMP_CACHE_BYTES)));
959 struct txbd8 *tx_bd_base;
960 struct txbd8 *cur_tx;
961 unsigned int num_txbdfree;
962 unsigned short skb_curtx;
963 unsigned short tx_ring_size;
964 struct tx_q_stats stats;
965 struct gfar_priv_grp *grp;
966
967 struct net_device *dev;
968 struct sk_buff **tx_skbuff;
969 struct txbd8 *dirty_tx;
970 unsigned short skb_dirtytx;
971 unsigned short qindex;
972
973 unsigned int txcoalescing;
974 unsigned long txic;
975 dma_addr_t tx_bd_dma_base;
976};
977
978
979
980
981struct rx_q_stats {
982 unsigned long rx_packets;
983 unsigned long rx_bytes;
984 unsigned long rx_dropped;
985};
986
987struct gfar_rx_buff {
988 dma_addr_t dma;
989 struct page *page;
990 unsigned int page_offset;
991};
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006struct gfar_priv_rx_q {
1007 struct gfar_rx_buff *rx_buff __aligned(SMP_CACHE_BYTES);
1008 struct rxbd8 *rx_bd_base;
1009 struct net_device *ndev;
1010 struct device *dev;
1011 u16 rx_ring_size;
1012 u16 qindex;
1013 struct gfar_priv_grp *grp;
1014 u16 next_to_clean;
1015 u16 next_to_use;
1016 u16 next_to_alloc;
1017 struct sk_buff *skb;
1018 struct rx_q_stats stats;
1019 u32 __iomem *rfbptr;
1020 unsigned char rxcoalescing;
1021 unsigned long rxic;
1022 dma_addr_t rx_bd_dma_base;
1023};
1024
1025enum gfar_irqinfo_id {
1026 GFAR_TX = 0,
1027 GFAR_RX = 1,
1028 GFAR_ER = 2,
1029 GFAR_NUM_IRQS = 3
1030};
1031
1032struct gfar_irqinfo {
1033 unsigned int irq;
1034 char name[GFAR_INT_NAME_MAX];
1035};
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045struct gfar_priv_grp {
1046 spinlock_t grplock __aligned(SMP_CACHE_BYTES);
1047 struct napi_struct napi_rx;
1048 struct napi_struct napi_tx;
1049 struct gfar __iomem *regs;
1050 struct gfar_priv_tx_q *tx_queue;
1051 struct gfar_priv_rx_q *rx_queue;
1052 unsigned int tstat;
1053 unsigned int rstat;
1054
1055 struct gfar_private *priv;
1056 unsigned long num_tx_queues;
1057 unsigned long tx_bit_map;
1058 unsigned long num_rx_queues;
1059 unsigned long rx_bit_map;
1060
1061 struct gfar_irqinfo *irqinfo[GFAR_NUM_IRQS];
1062};
1063
1064#define gfar_irq(grp, ID) \
1065 ((grp)->irqinfo[GFAR_##ID])
1066
1067enum gfar_errata {
1068 GFAR_ERRATA_74 = 0x01,
1069 GFAR_ERRATA_76 = 0x02,
1070 GFAR_ERRATA_A002 = 0x04,
1071 GFAR_ERRATA_12 = 0x08,
1072};
1073
1074enum gfar_dev_state {
1075 GFAR_DOWN = 1,
1076 GFAR_RESETTING
1077};
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088struct gfar_private {
1089 struct device *dev;
1090 struct net_device *ndev;
1091 enum gfar_errata errata;
1092
1093 u16 uses_rxfcb;
1094 u16 padding;
1095 u32 device_flags;
1096
1097
1098 int hwts_rx_en;
1099 int hwts_tx_en;
1100
1101 struct gfar_priv_tx_q *tx_queue[MAX_TX_QS];
1102 struct gfar_priv_rx_q *rx_queue[MAX_RX_QS];
1103 struct gfar_priv_grp gfargrp[MAXGROUPS];
1104
1105 unsigned long state;
1106
1107 unsigned short mode;
1108 unsigned short poll_mode;
1109 unsigned int num_tx_queues;
1110 unsigned int num_rx_queues;
1111 unsigned int num_grps;
1112 int tx_actual_en;
1113
1114
1115 struct gfar_extra_stats extra_stats;
1116
1117
1118 phy_interface_t interface;
1119 struct device_node *phy_node;
1120 struct device_node *tbi_node;
1121 struct mii_bus *mii_bus;
1122 int oldspeed;
1123 int oldduplex;
1124 int oldlink;
1125
1126 uint32_t msg_enable;
1127
1128 struct work_struct reset_task;
1129
1130 struct platform_device *ofdev;
1131 unsigned char
1132 extended_hash:1,
1133 bd_stash_en:1,
1134 rx_filer_enable:1,
1135
1136 prio_sched_en:1,
1137
1138 pause_aneg_en:1,
1139 tx_pause_en:1,
1140 rx_pause_en:1;
1141
1142
1143 unsigned int total_tx_ring_size;
1144 unsigned int total_rx_ring_size;
1145
1146 u32 rqueue;
1147 u32 tqueue;
1148
1149
1150 unsigned int rx_stash_size;
1151 unsigned int rx_stash_index;
1152
1153 u32 cur_filer_idx;
1154
1155
1156 struct ethtool_rx_list rx_list;
1157 struct mutex rx_queue_access;
1158
1159
1160 u32 __iomem *hash_regs[16];
1161 int hash_width;
1162
1163
1164 u16 wol_opts;
1165 u16 wol_supported;
1166
1167
1168 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
1169 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
1170};
1171
1172
1173static inline int gfar_has_errata(struct gfar_private *priv,
1174 enum gfar_errata err)
1175{
1176 return priv->errata & err;
1177}
1178
1179static inline u32 gfar_read(unsigned __iomem *addr)
1180{
1181 u32 val;
1182 val = ioread32be(addr);
1183 return val;
1184}
1185
1186static inline void gfar_write(unsigned __iomem *addr, u32 val)
1187{
1188 iowrite32be(val, addr);
1189}
1190
1191static inline void gfar_write_filer(struct gfar_private *priv,
1192 unsigned int far, unsigned int fcr, unsigned int fpr)
1193{
1194 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1195
1196 gfar_write(®s->rqfar, far);
1197 gfar_write(®s->rqfcr, fcr);
1198 gfar_write(®s->rqfpr, fpr);
1199}
1200
1201static inline void gfar_read_filer(struct gfar_private *priv,
1202 unsigned int far, unsigned int *fcr, unsigned int *fpr)
1203{
1204 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1205
1206 gfar_write(®s->rqfar, far);
1207 *fcr = gfar_read(®s->rqfcr);
1208 *fpr = gfar_read(®s->rqfpr);
1209}
1210
1211static inline void gfar_write_isrg(struct gfar_private *priv)
1212{
1213 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1214 u32 __iomem *baddr = ®s->isrg0;
1215 u32 isrg = 0;
1216 int grp_idx, i;
1217
1218 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1219 struct gfar_priv_grp *grp = &priv->gfargrp[grp_idx];
1220
1221 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
1222 isrg |= (ISRG_RR0 >> i);
1223 }
1224
1225 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
1226 isrg |= (ISRG_TR0 >> i);
1227 }
1228
1229 gfar_write(baddr, isrg);
1230
1231 baddr++;
1232 isrg = 0;
1233 }
1234}
1235
1236static inline int gfar_is_dma_stopped(struct gfar_private *priv)
1237{
1238 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1239
1240 return ((gfar_read(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC)) ==
1241 (IEVENT_GRSC | IEVENT_GTSC));
1242}
1243
1244static inline int gfar_is_rx_dma_stopped(struct gfar_private *priv)
1245{
1246 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1247
1248 return gfar_read(®s->ievent) & IEVENT_GRSC;
1249}
1250
1251static inline void gfar_wmb(void)
1252{
1253#if defined(CONFIG_PPC)
1254
1255
1256
1257
1258
1259
1260
1261 eieio();
1262#else
1263 wmb();
1264#endif
1265}
1266
1267static inline void gfar_clear_txbd_status(struct txbd8 *bdp)
1268{
1269 u32 lstatus = be32_to_cpu(bdp->lstatus);
1270
1271 lstatus &= BD_LFLAG(TXBD_WRAP);
1272 bdp->lstatus = cpu_to_be32(lstatus);
1273}
1274
1275static inline int gfar_rxbd_unused(struct gfar_priv_rx_q *rxq)
1276{
1277 if (rxq->next_to_clean > rxq->next_to_use)
1278 return rxq->next_to_clean - rxq->next_to_use - 1;
1279
1280 return rxq->rx_ring_size + rxq->next_to_clean - rxq->next_to_use - 1;
1281}
1282
1283static inline u32 gfar_rxbd_dma_lastfree(struct gfar_priv_rx_q *rxq)
1284{
1285 struct rxbd8 *bdp;
1286 u32 bdp_dma;
1287 int i;
1288
1289 i = rxq->next_to_use ? rxq->next_to_use - 1 : rxq->rx_ring_size - 1;
1290 bdp = &rxq->rx_bd_base[i];
1291 bdp_dma = lower_32_bits(rxq->rx_bd_dma_base);
1292 bdp_dma += (uintptr_t)bdp - (uintptr_t)rxq->rx_bd_base;
1293
1294 return bdp_dma;
1295}
1296
1297int startup_gfar(struct net_device *dev);
1298void stop_gfar(struct net_device *dev);
1299void gfar_mac_reset(struct gfar_private *priv);
1300int gfar_set_features(struct net_device *dev, netdev_features_t features);
1301
1302extern const struct ethtool_ops gfar_ethtool_ops;
1303
1304#define MAX_FILER_CACHE_IDX (2*(MAX_FILER_IDX))
1305
1306#define RQFCR_PID_PRI_MASK 0xFFFFFFF8
1307#define RQFCR_PID_L4P_MASK 0xFFFFFF00
1308#define RQFCR_PID_VID_MASK 0xFFFFF000
1309#define RQFCR_PID_PORT_MASK 0xFFFF0000
1310#define RQFCR_PID_MAC_MASK 0xFF000000
1311
1312
1313struct gfar_filer_entry {
1314 u32 ctrl;
1315 u32 prop;
1316};
1317
1318
1319
1320struct filer_table {
1321 u32 index;
1322 struct gfar_filer_entry fe[MAX_FILER_CACHE_IDX + 20];
1323};
1324
1325#endif
1326