1
2
3
4
5
6
7#include <linux/etherdevice.h>
8#include <linux/pci.h>
9#include "gve.h"
10#include "gve_adminq.h"
11#include "gve_register.h"
12
13#define GVE_MAX_ADMINQ_RELEASE_CHECK 500
14#define GVE_ADMINQ_SLEEP_LEN 20
15#define GVE_MAX_ADMINQ_EVENT_COUNTER_CHECK 100
16
17int gve_adminq_alloc(struct device *dev, struct gve_priv *priv)
18{
19 priv->adminq = dma_alloc_coherent(dev, PAGE_SIZE,
20 &priv->adminq_bus_addr, GFP_KERNEL);
21 if (unlikely(!priv->adminq))
22 return -ENOMEM;
23
24 priv->adminq_mask = (PAGE_SIZE / sizeof(union gve_adminq_command)) - 1;
25 priv->adminq_prod_cnt = 0;
26 priv->adminq_cmd_fail = 0;
27 priv->adminq_timeouts = 0;
28 priv->adminq_describe_device_cnt = 0;
29 priv->adminq_cfg_device_resources_cnt = 0;
30 priv->adminq_register_page_list_cnt = 0;
31 priv->adminq_unregister_page_list_cnt = 0;
32 priv->adminq_create_tx_queue_cnt = 0;
33 priv->adminq_create_rx_queue_cnt = 0;
34 priv->adminq_destroy_tx_queue_cnt = 0;
35 priv->adminq_destroy_rx_queue_cnt = 0;
36 priv->adminq_dcfg_device_resources_cnt = 0;
37 priv->adminq_set_driver_parameter_cnt = 0;
38 priv->adminq_report_stats_cnt = 0;
39 priv->adminq_report_link_speed_cnt = 0;
40
41
42 iowrite32be(priv->adminq_bus_addr / PAGE_SIZE,
43 &priv->reg_bar0->adminq_pfn);
44
45 gve_set_admin_queue_ok(priv);
46 return 0;
47}
48
49void gve_adminq_release(struct gve_priv *priv)
50{
51 int i = 0;
52
53
54 iowrite32be(0x0, &priv->reg_bar0->adminq_pfn);
55 while (ioread32be(&priv->reg_bar0->adminq_pfn)) {
56
57
58
59
60 if (i == GVE_MAX_ADMINQ_RELEASE_CHECK)
61 WARN(1, "Unrecoverable platform error!");
62 i++;
63 msleep(GVE_ADMINQ_SLEEP_LEN);
64 }
65 gve_clear_device_rings_ok(priv);
66 gve_clear_device_resources_ok(priv);
67 gve_clear_admin_queue_ok(priv);
68}
69
70void gve_adminq_free(struct device *dev, struct gve_priv *priv)
71{
72 if (!gve_get_admin_queue_ok(priv))
73 return;
74 gve_adminq_release(priv);
75 dma_free_coherent(dev, PAGE_SIZE, priv->adminq, priv->adminq_bus_addr);
76 gve_clear_admin_queue_ok(priv);
77}
78
79static void gve_adminq_kick_cmd(struct gve_priv *priv, u32 prod_cnt)
80{
81 iowrite32be(prod_cnt, &priv->reg_bar0->adminq_doorbell);
82}
83
84static bool gve_adminq_wait_for_cmd(struct gve_priv *priv, u32 prod_cnt)
85{
86 int i;
87
88 for (i = 0; i < GVE_MAX_ADMINQ_EVENT_COUNTER_CHECK; i++) {
89 if (ioread32be(&priv->reg_bar0->adminq_event_counter)
90 == prod_cnt)
91 return true;
92 msleep(GVE_ADMINQ_SLEEP_LEN);
93 }
94
95 return false;
96}
97
98static int gve_adminq_parse_err(struct gve_priv *priv, u32 status)
99{
100 if (status != GVE_ADMINQ_COMMAND_PASSED &&
101 status != GVE_ADMINQ_COMMAND_UNSET) {
102 dev_err(&priv->pdev->dev, "AQ command failed with status %d\n", status);
103 priv->adminq_cmd_fail++;
104 }
105 switch (status) {
106 case GVE_ADMINQ_COMMAND_PASSED:
107 return 0;
108 case GVE_ADMINQ_COMMAND_UNSET:
109 dev_err(&priv->pdev->dev, "parse_aq_err: err and status both unset, this should not be possible.\n");
110 return -EINVAL;
111 case GVE_ADMINQ_COMMAND_ERROR_ABORTED:
112 case GVE_ADMINQ_COMMAND_ERROR_CANCELLED:
113 case GVE_ADMINQ_COMMAND_ERROR_DATALOSS:
114 case GVE_ADMINQ_COMMAND_ERROR_FAILED_PRECONDITION:
115 case GVE_ADMINQ_COMMAND_ERROR_UNAVAILABLE:
116 return -EAGAIN;
117 case GVE_ADMINQ_COMMAND_ERROR_ALREADY_EXISTS:
118 case GVE_ADMINQ_COMMAND_ERROR_INTERNAL_ERROR:
119 case GVE_ADMINQ_COMMAND_ERROR_INVALID_ARGUMENT:
120 case GVE_ADMINQ_COMMAND_ERROR_NOT_FOUND:
121 case GVE_ADMINQ_COMMAND_ERROR_OUT_OF_RANGE:
122 case GVE_ADMINQ_COMMAND_ERROR_UNKNOWN_ERROR:
123 return -EINVAL;
124 case GVE_ADMINQ_COMMAND_ERROR_DEADLINE_EXCEEDED:
125 return -ETIME;
126 case GVE_ADMINQ_COMMAND_ERROR_PERMISSION_DENIED:
127 case GVE_ADMINQ_COMMAND_ERROR_UNAUTHENTICATED:
128 return -EACCES;
129 case GVE_ADMINQ_COMMAND_ERROR_RESOURCE_EXHAUSTED:
130 return -ENOMEM;
131 case GVE_ADMINQ_COMMAND_ERROR_UNIMPLEMENTED:
132 return -ENOTSUPP;
133 default:
134 dev_err(&priv->pdev->dev, "parse_aq_err: unknown status code %d\n", status);
135 return -EINVAL;
136 }
137}
138
139
140
141
142static int gve_adminq_kick_and_wait(struct gve_priv *priv)
143{
144 u32 tail, head;
145 int i;
146
147 tail = ioread32be(&priv->reg_bar0->adminq_event_counter);
148 head = priv->adminq_prod_cnt;
149
150 gve_adminq_kick_cmd(priv, head);
151 if (!gve_adminq_wait_for_cmd(priv, head)) {
152 dev_err(&priv->pdev->dev, "AQ commands timed out, need to reset AQ\n");
153 priv->adminq_timeouts++;
154 return -ENOTRECOVERABLE;
155 }
156
157 for (i = tail; i < head; i++) {
158 union gve_adminq_command *cmd;
159 u32 status, err;
160
161 cmd = &priv->adminq[i & priv->adminq_mask];
162 status = be32_to_cpu(READ_ONCE(cmd->status));
163 err = gve_adminq_parse_err(priv, status);
164 if (err)
165
166 return err;
167 }
168
169 return 0;
170}
171
172
173
174
175static int gve_adminq_issue_cmd(struct gve_priv *priv,
176 union gve_adminq_command *cmd_orig)
177{
178 union gve_adminq_command *cmd;
179 u32 opcode;
180 u32 tail;
181
182 tail = ioread32be(&priv->reg_bar0->adminq_event_counter);
183
184
185 if (((priv->adminq_prod_cnt + 1) & priv->adminq_mask) == tail) {
186 int err;
187
188
189 err = gve_adminq_kick_and_wait(priv);
190 if (err)
191 return err;
192
193
194 tail = ioread32be(&priv->reg_bar0->adminq_event_counter);
195 if (((priv->adminq_prod_cnt + 1) & priv->adminq_mask) == tail) {
196
197
198 return -ENOMEM;
199 }
200 }
201
202 cmd = &priv->adminq[priv->adminq_prod_cnt & priv->adminq_mask];
203 priv->adminq_prod_cnt++;
204
205 memcpy(cmd, cmd_orig, sizeof(*cmd_orig));
206 opcode = be32_to_cpu(READ_ONCE(cmd->opcode));
207
208 switch (opcode) {
209 case GVE_ADMINQ_DESCRIBE_DEVICE:
210 priv->adminq_describe_device_cnt++;
211 break;
212 case GVE_ADMINQ_CONFIGURE_DEVICE_RESOURCES:
213 priv->adminq_cfg_device_resources_cnt++;
214 break;
215 case GVE_ADMINQ_REGISTER_PAGE_LIST:
216 priv->adminq_register_page_list_cnt++;
217 break;
218 case GVE_ADMINQ_UNREGISTER_PAGE_LIST:
219 priv->adminq_unregister_page_list_cnt++;
220 break;
221 case GVE_ADMINQ_CREATE_TX_QUEUE:
222 priv->adminq_create_tx_queue_cnt++;
223 break;
224 case GVE_ADMINQ_CREATE_RX_QUEUE:
225 priv->adminq_create_rx_queue_cnt++;
226 break;
227 case GVE_ADMINQ_DESTROY_TX_QUEUE:
228 priv->adminq_destroy_tx_queue_cnt++;
229 break;
230 case GVE_ADMINQ_DESTROY_RX_QUEUE:
231 priv->adminq_destroy_rx_queue_cnt++;
232 break;
233 case GVE_ADMINQ_DECONFIGURE_DEVICE_RESOURCES:
234 priv->adminq_dcfg_device_resources_cnt++;
235 break;
236 case GVE_ADMINQ_SET_DRIVER_PARAMETER:
237 priv->adminq_set_driver_parameter_cnt++;
238 break;
239 case GVE_ADMINQ_REPORT_STATS:
240 priv->adminq_report_stats_cnt++;
241 break;
242 case GVE_ADMINQ_REPORT_LINK_SPEED:
243 priv->adminq_report_link_speed_cnt++;
244 break;
245 default:
246 dev_err(&priv->pdev->dev, "unknown AQ command opcode %d\n", opcode);
247 }
248
249 return 0;
250}
251
252
253
254
255
256
257static int gve_adminq_execute_cmd(struct gve_priv *priv, union gve_adminq_command *cmd_orig)
258{
259 u32 tail, head;
260 int err;
261
262 tail = ioread32be(&priv->reg_bar0->adminq_event_counter);
263 head = priv->adminq_prod_cnt;
264 if (tail != head)
265
266 return -EINVAL;
267
268 err = gve_adminq_issue_cmd(priv, cmd_orig);
269 if (err)
270 return err;
271
272 return gve_adminq_kick_and_wait(priv);
273}
274
275
276
277
278
279
280
281
282#define GVE_NTFY_BLK_BASE_MSIX_IDX 0
283int gve_adminq_configure_device_resources(struct gve_priv *priv,
284 dma_addr_t counter_array_bus_addr,
285 u32 num_counters,
286 dma_addr_t db_array_bus_addr,
287 u32 num_ntfy_blks)
288{
289 union gve_adminq_command cmd;
290
291 memset(&cmd, 0, sizeof(cmd));
292 cmd.opcode = cpu_to_be32(GVE_ADMINQ_CONFIGURE_DEVICE_RESOURCES);
293 cmd.configure_device_resources =
294 (struct gve_adminq_configure_device_resources) {
295 .counter_array = cpu_to_be64(counter_array_bus_addr),
296 .num_counters = cpu_to_be32(num_counters),
297 .irq_db_addr = cpu_to_be64(db_array_bus_addr),
298 .num_irq_dbs = cpu_to_be32(num_ntfy_blks),
299 .irq_db_stride = cpu_to_be32(sizeof(priv->ntfy_blocks[0])),
300 .ntfy_blk_msix_base_idx =
301 cpu_to_be32(GVE_NTFY_BLK_BASE_MSIX_IDX),
302 };
303
304 return gve_adminq_execute_cmd(priv, &cmd);
305}
306
307int gve_adminq_deconfigure_device_resources(struct gve_priv *priv)
308{
309 union gve_adminq_command cmd;
310
311 memset(&cmd, 0, sizeof(cmd));
312 cmd.opcode = cpu_to_be32(GVE_ADMINQ_DECONFIGURE_DEVICE_RESOURCES);
313
314 return gve_adminq_execute_cmd(priv, &cmd);
315}
316
317static int gve_adminq_create_tx_queue(struct gve_priv *priv, u32 queue_index)
318{
319 struct gve_tx_ring *tx = &priv->tx[queue_index];
320 union gve_adminq_command cmd;
321 int err;
322
323 memset(&cmd, 0, sizeof(cmd));
324 cmd.opcode = cpu_to_be32(GVE_ADMINQ_CREATE_TX_QUEUE);
325 cmd.create_tx_queue = (struct gve_adminq_create_tx_queue) {
326 .queue_id = cpu_to_be32(queue_index),
327 .reserved = 0,
328 .queue_resources_addr =
329 cpu_to_be64(tx->q_resources_bus),
330 .tx_ring_addr = cpu_to_be64(tx->bus),
331 .queue_page_list_id = cpu_to_be32(tx->tx_fifo.qpl->id),
332 .ntfy_id = cpu_to_be32(tx->ntfy_id),
333 };
334
335 err = gve_adminq_issue_cmd(priv, &cmd);
336 if (err)
337 return err;
338
339 return 0;
340}
341
342int gve_adminq_create_tx_queues(struct gve_priv *priv, u32 num_queues)
343{
344 int err;
345 int i;
346
347 for (i = 0; i < num_queues; i++) {
348 err = gve_adminq_create_tx_queue(priv, i);
349 if (err)
350 return err;
351 }
352
353 return gve_adminq_kick_and_wait(priv);
354}
355
356static int gve_adminq_create_rx_queue(struct gve_priv *priv, u32 queue_index)
357{
358 struct gve_rx_ring *rx = &priv->rx[queue_index];
359 union gve_adminq_command cmd;
360 int err;
361
362 memset(&cmd, 0, sizeof(cmd));
363 cmd.opcode = cpu_to_be32(GVE_ADMINQ_CREATE_RX_QUEUE);
364 cmd.create_rx_queue = (struct gve_adminq_create_rx_queue) {
365 .queue_id = cpu_to_be32(queue_index),
366 .index = cpu_to_be32(queue_index),
367 .reserved = 0,
368 .ntfy_id = cpu_to_be32(rx->ntfy_id),
369 .queue_resources_addr = cpu_to_be64(rx->q_resources_bus),
370 .rx_desc_ring_addr = cpu_to_be64(rx->desc.bus),
371 .rx_data_ring_addr = cpu_to_be64(rx->data.data_bus),
372 .queue_page_list_id = cpu_to_be32(rx->data.qpl->id),
373 };
374
375 err = gve_adminq_issue_cmd(priv, &cmd);
376 if (err)
377 return err;
378
379 return 0;
380}
381
382int gve_adminq_create_rx_queues(struct gve_priv *priv, u32 num_queues)
383{
384 int err;
385 int i;
386
387 for (i = 0; i < num_queues; i++) {
388 err = gve_adminq_create_rx_queue(priv, i);
389 if (err)
390 return err;
391 }
392
393 return gve_adminq_kick_and_wait(priv);
394}
395
396static int gve_adminq_destroy_tx_queue(struct gve_priv *priv, u32 queue_index)
397{
398 union gve_adminq_command cmd;
399 int err;
400
401 memset(&cmd, 0, sizeof(cmd));
402 cmd.opcode = cpu_to_be32(GVE_ADMINQ_DESTROY_TX_QUEUE);
403 cmd.destroy_tx_queue = (struct gve_adminq_destroy_tx_queue) {
404 .queue_id = cpu_to_be32(queue_index),
405 };
406
407 err = gve_adminq_issue_cmd(priv, &cmd);
408 if (err)
409 return err;
410
411 return 0;
412}
413
414int gve_adminq_destroy_tx_queues(struct gve_priv *priv, u32 num_queues)
415{
416 int err;
417 int i;
418
419 for (i = 0; i < num_queues; i++) {
420 err = gve_adminq_destroy_tx_queue(priv, i);
421 if (err)
422 return err;
423 }
424
425 return gve_adminq_kick_and_wait(priv);
426}
427
428static int gve_adminq_destroy_rx_queue(struct gve_priv *priv, u32 queue_index)
429{
430 union gve_adminq_command cmd;
431 int err;
432
433 memset(&cmd, 0, sizeof(cmd));
434 cmd.opcode = cpu_to_be32(GVE_ADMINQ_DESTROY_RX_QUEUE);
435 cmd.destroy_rx_queue = (struct gve_adminq_destroy_rx_queue) {
436 .queue_id = cpu_to_be32(queue_index),
437 };
438
439 err = gve_adminq_issue_cmd(priv, &cmd);
440 if (err)
441 return err;
442
443 return 0;
444}
445
446int gve_adminq_destroy_rx_queues(struct gve_priv *priv, u32 num_queues)
447{
448 int err;
449 int i;
450
451 for (i = 0; i < num_queues; i++) {
452 err = gve_adminq_destroy_rx_queue(priv, i);
453 if (err)
454 return err;
455 }
456
457 return gve_adminq_kick_and_wait(priv);
458}
459
460int gve_adminq_describe_device(struct gve_priv *priv)
461{
462 struct gve_device_descriptor *descriptor;
463 union gve_adminq_command cmd;
464 dma_addr_t descriptor_bus;
465 int err = 0;
466 u8 *mac;
467 u16 mtu;
468
469 memset(&cmd, 0, sizeof(cmd));
470 descriptor = dma_alloc_coherent(&priv->pdev->dev, PAGE_SIZE,
471 &descriptor_bus, GFP_KERNEL);
472 if (!descriptor)
473 return -ENOMEM;
474 cmd.opcode = cpu_to_be32(GVE_ADMINQ_DESCRIBE_DEVICE);
475 cmd.describe_device.device_descriptor_addr =
476 cpu_to_be64(descriptor_bus);
477 cmd.describe_device.device_descriptor_version =
478 cpu_to_be32(GVE_ADMINQ_DEVICE_DESCRIPTOR_VERSION);
479 cmd.describe_device.available_length = cpu_to_be32(PAGE_SIZE);
480
481 err = gve_adminq_execute_cmd(priv, &cmd);
482 if (err)
483 goto free_device_descriptor;
484
485 priv->tx_desc_cnt = be16_to_cpu(descriptor->tx_queue_entries);
486 if (priv->tx_desc_cnt * sizeof(priv->tx->desc[0]) < PAGE_SIZE) {
487 dev_err(&priv->pdev->dev, "Tx desc count %d too low\n", priv->tx_desc_cnt);
488 err = -EINVAL;
489 goto free_device_descriptor;
490 }
491 priv->rx_desc_cnt = be16_to_cpu(descriptor->rx_queue_entries);
492 if (priv->rx_desc_cnt * sizeof(priv->rx->desc.desc_ring[0])
493 < PAGE_SIZE ||
494 priv->rx_desc_cnt * sizeof(priv->rx->data.data_ring[0])
495 < PAGE_SIZE) {
496 dev_err(&priv->pdev->dev, "Rx desc count %d too low\n", priv->rx_desc_cnt);
497 err = -EINVAL;
498 goto free_device_descriptor;
499 }
500 priv->max_registered_pages =
501 be64_to_cpu(descriptor->max_registered_pages);
502 mtu = be16_to_cpu(descriptor->mtu);
503 if (mtu < ETH_MIN_MTU) {
504 dev_err(&priv->pdev->dev, "MTU %d below minimum MTU\n", mtu);
505 err = -EINVAL;
506 goto free_device_descriptor;
507 }
508 priv->dev->max_mtu = mtu;
509 priv->num_event_counters = be16_to_cpu(descriptor->counters);
510 ether_addr_copy(priv->dev->dev_addr, descriptor->mac);
511 mac = descriptor->mac;
512 dev_info(&priv->pdev->dev, "MAC addr: %pM\n", mac);
513 priv->tx_pages_per_qpl = be16_to_cpu(descriptor->tx_pages_per_qpl);
514 priv->rx_pages_per_qpl = be16_to_cpu(descriptor->rx_pages_per_qpl);
515 if (priv->rx_pages_per_qpl < priv->rx_desc_cnt) {
516 dev_err(&priv->pdev->dev, "rx_pages_per_qpl cannot be smaller than rx_desc_cnt, setting rx_desc_cnt down to %d.\n",
517 priv->rx_pages_per_qpl);
518 priv->rx_desc_cnt = priv->rx_pages_per_qpl;
519 }
520 priv->default_num_queues = be16_to_cpu(descriptor->default_num_queues);
521
522free_device_descriptor:
523 dma_free_coherent(&priv->pdev->dev, sizeof(*descriptor), descriptor,
524 descriptor_bus);
525 return err;
526}
527
528int gve_adminq_register_page_list(struct gve_priv *priv,
529 struct gve_queue_page_list *qpl)
530{
531 struct device *hdev = &priv->pdev->dev;
532 u32 num_entries = qpl->num_entries;
533 u32 size = num_entries * sizeof(qpl->page_buses[0]);
534 union gve_adminq_command cmd;
535 dma_addr_t page_list_bus;
536 __be64 *page_list;
537 int err;
538 int i;
539
540 memset(&cmd, 0, sizeof(cmd));
541 page_list = dma_alloc_coherent(hdev, size, &page_list_bus, GFP_KERNEL);
542 if (!page_list)
543 return -ENOMEM;
544
545 for (i = 0; i < num_entries; i++)
546 page_list[i] = cpu_to_be64(qpl->page_buses[i]);
547
548 cmd.opcode = cpu_to_be32(GVE_ADMINQ_REGISTER_PAGE_LIST);
549 cmd.reg_page_list = (struct gve_adminq_register_page_list) {
550 .page_list_id = cpu_to_be32(qpl->id),
551 .num_pages = cpu_to_be32(num_entries),
552 .page_address_list_addr = cpu_to_be64(page_list_bus),
553 };
554
555 err = gve_adminq_execute_cmd(priv, &cmd);
556 dma_free_coherent(hdev, size, page_list, page_list_bus);
557 return err;
558}
559
560int gve_adminq_unregister_page_list(struct gve_priv *priv, u32 page_list_id)
561{
562 union gve_adminq_command cmd;
563
564 memset(&cmd, 0, sizeof(cmd));
565 cmd.opcode = cpu_to_be32(GVE_ADMINQ_UNREGISTER_PAGE_LIST);
566 cmd.unreg_page_list = (struct gve_adminq_unregister_page_list) {
567 .page_list_id = cpu_to_be32(page_list_id),
568 };
569
570 return gve_adminq_execute_cmd(priv, &cmd);
571}
572
573int gve_adminq_set_mtu(struct gve_priv *priv, u64 mtu)
574{
575 union gve_adminq_command cmd;
576
577 memset(&cmd, 0, sizeof(cmd));
578 cmd.opcode = cpu_to_be32(GVE_ADMINQ_SET_DRIVER_PARAMETER);
579 cmd.set_driver_param = (struct gve_adminq_set_driver_parameter) {
580 .parameter_type = cpu_to_be32(GVE_SET_PARAM_MTU),
581 .parameter_value = cpu_to_be64(mtu),
582 };
583
584 return gve_adminq_execute_cmd(priv, &cmd);
585}
586
587int gve_adminq_report_stats(struct gve_priv *priv, u64 stats_report_len,
588 dma_addr_t stats_report_addr, u64 interval)
589{
590 union gve_adminq_command cmd;
591
592 memset(&cmd, 0, sizeof(cmd));
593 cmd.opcode = cpu_to_be32(GVE_ADMINQ_REPORT_STATS);
594 cmd.report_stats = (struct gve_adminq_report_stats) {
595 .stats_report_len = cpu_to_be64(stats_report_len),
596 .stats_report_addr = cpu_to_be64(stats_report_addr),
597 .interval = cpu_to_be64(interval),
598 };
599
600 return gve_adminq_execute_cmd(priv, &cmd);
601}
602
603int gve_adminq_report_link_speed(struct gve_priv *priv)
604{
605 union gve_adminq_command gvnic_cmd;
606 dma_addr_t link_speed_region_bus;
607 __be64 *link_speed_region;
608 int err;
609
610 link_speed_region =
611 dma_alloc_coherent(&priv->pdev->dev, sizeof(*link_speed_region),
612 &link_speed_region_bus, GFP_KERNEL);
613
614 if (!link_speed_region)
615 return -ENOMEM;
616
617 memset(&gvnic_cmd, 0, sizeof(gvnic_cmd));
618 gvnic_cmd.opcode = cpu_to_be32(GVE_ADMINQ_REPORT_LINK_SPEED);
619 gvnic_cmd.report_link_speed.link_speed_address =
620 cpu_to_be64(link_speed_region_bus);
621
622 err = gve_adminq_execute_cmd(priv, &gvnic_cmd);
623
624 priv->link_speed = be64_to_cpu(*link_speed_region);
625 dma_free_coherent(&priv->pdev->dev, sizeof(*link_speed_region), link_speed_region,
626 link_speed_region_bus);
627 return err;
628}
629
